diff options
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/natsemi.c | 2 | ||||
| -rw-r--r-- | drivers/net/ns8382x.c | 2 | ||||
| -rw-r--r-- | drivers/net/rtl8139.c | 2 | ||||
| -rw-r--r-- | drivers/net/tigon3.c | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c index ff8d2d7c0..ce12c3b62 100644 --- a/drivers/net/natsemi.c +++ b/drivers/net/natsemi.c @@ -409,7 +409,7 @@ natsemi_initialize(bd_t * bis) The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses. */ /* Delay between EEPROM clock transitions. - No extra delay is needed with 33Mhz PCI, but future 66Mhz + No extra delay is needed with 33MHz PCI, but future 66MHz access may need a delay. */ #define eeprom_delay(ee_addr) INL(dev, ee_addr) diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c index a2d61afec..198f73dee 100644 --- a/drivers/net/ns8382x.c +++ b/drivers/net/ns8382x.c @@ -445,7 +445,7 @@ ns8382x_initialize(bd_t * bis) Read and write MII registers using software-generated serial MDIO protocol. See the MII specifications or DP83840A data sheet for details. - The maximum data clock rate is 2.5 Mhz. To meet minimum timing we + The maximum data clock rate is 2.5 MHz. To meet minimum timing we must flush writes to the PCI bus with a PCI read. */ #define mdio_delay(mdio_addr) INL(dev, mdio_addr) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index d378ce39b..db8a727c8 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -287,7 +287,7 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis) /* Delay between EEPROM clock transitions. - No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. + No extra delay is needed with 33MHz PCI, but 66MHz may change this. */ #define eeprom_delay() inl(ee_addr) diff --git a/drivers/net/tigon3.c b/drivers/net/tigon3.c index ab448b0f8..e4e004eed 100644 --- a/drivers/net/tigon3.c +++ b/drivers/net/tigon3.c @@ -2247,7 +2247,7 @@ LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice) REG_WR (pDevice, Grc.Mode, Value32); /* Setup the timer prescalar register. */ - REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */ + REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66MHz. */ /* Set up the MBUF pool base address and size. */ REG_WR (pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase); |