diff options
Diffstat (limited to 'drivers/net')
40 files changed, 1336 insertions, 1343 deletions
diff --git a/drivers/net/3c589.c b/drivers/net/3c589.c index 080b686e2..3f1e770ef 100644 --- a/drivers/net/3c589.c +++ b/drivers/net/3c589.c @@ -99,7 +99,7 @@ typedef unsigned long int dword; }) #define insw(args...) mmio_insw(args) -#define mmio_insw(r,b,l) ({ int __i ; \ +#define mmio_insw(r,b,l) ({ int __i ; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ @@ -154,8 +154,8 @@ enum RxFilter { /* Register window 1 offsets, the window used in normal operation. */ #define TX_FIFO 0x00 #define RX_FIFO 0x00 -#define RX_STATUS 0x08 -#define TX_STATUS 0x0B +#define RX_STATUS 0x08 +#define TX_STATUS 0x0B #define TX_FREE 0x0C /* Remaining free bytes in Tx buffer. */ diff --git a/drivers/net/3c589.h b/drivers/net/3c589.h index 6735bf9f6..8f8cf5be1 100644 --- a/drivers/net/3c589.h +++ b/drivers/net/3c589.h @@ -64,7 +64,7 @@ /* * some macros to acces long named fields */ -#define BASE (EL_BASE_ADDR) +#define BASE (EL_BASE_ADDR) /* * Commands to read/write EEPROM trough EEPROM command register (Window 0, diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 4131aad98..5b031c9af 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -23,7 +23,7 @@ include $(TOPDIR)/config.mk -LIB := $(obj)libnet.a +LIB := $(obj)libnet.a COBJS-y += 3c589.o COBJS-y += bcm570x.o bcm570x_autoneg.o 5701rls.o @@ -68,8 +68,8 @@ COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o COBJS := $(COBJS-y) -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) all: $(LIB) diff --git a/drivers/net/bcm570x.c b/drivers/net/bcm570x.c index c8f406422..5ad31d1fd 100644 --- a/drivers/net/bcm570x.c +++ b/drivers/net/bcm570x.c @@ -27,7 +27,7 @@ /* * PCI memory base for Ethernet device as well as device Interrupt. */ -#define BCM570X_MBAR 0x80100000 +#define BCM570X_MBAR 0x80100000 #define BCM570X_ILINE 1 #define SECOND_USEC 1000000 diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index afe122a33..fe5694998 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -35,7 +35,7 @@ #define TXBUF_BASE_ADDR 0xFF800000 #define TX_BUF_CNT 1 -#define TOUT_LOOP 1000000 +#define TOUT_LOOP 1000000 ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT]; ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX]; diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 723892261..1d728d8b3 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -212,14 +212,14 @@ static struct pci_device_id supported[] = { int dc21x4x_initialize(bd_t *bis) { - int idx=0; - int card_number = 0; - unsigned int cfrv; - unsigned char timer; + int idx=0; + int card_number = 0; + unsigned int cfrv; + unsigned char timer; pci_dev_t devbusfn; unsigned int iobase; unsigned short status; - struct eth_device* dev; + struct eth_device* dev; while(1) { devbusfn = pci_find_devices(supported, idx++); @@ -490,7 +490,7 @@ static void send_setup_frame(struct eth_device* dev, bd_t *bis) { int i; char setup_frame[SETUP_FRAME_LEN]; - char *pa = &setup_frame[0]; + char *pa = &setup_frame[0]; memset(pa, 0xff, SETUP_FRAME_LEN); @@ -738,22 +738,22 @@ static void update_srom(struct eth_device *dev, bd_t *bis) { int i; static unsigned short eeprom[0x40] = { - 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */ - 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */ - 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */ - 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */ - 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */ - 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */ - 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */ - 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */ - 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */ - 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */ - 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */ - 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */ - 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ - 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */ - 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */ - 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */ + 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */ + 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */ + 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */ + 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */ + 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */ + 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */ + 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */ }; /* Ethernet Addr... */ @@ -761,8 +761,7 @@ static void update_srom(struct eth_device *dev, bd_t *bis) eeprom[0x0b] = ((bis->bi_enetaddr[3] & 0xff) << 8) | (bis->bi_enetaddr[2] & 0xff); eeprom[0x0c] = ((bis->bi_enetaddr[5] & 0xff) << 8) | (bis->bi_enetaddr[4] & 0xff); - for (i=0; i<0x40; i++) - { + for (i=0; i<0x40; i++) { write_srom(dev, DE4X5_APROM, i, eeprom[i]); } } diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index 6131b5c35..01e2f14a9 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -17,17 +17,17 @@ (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match - 06/22/2001 Support DM9801 progrmming - E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000 - E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200 - R17 = (R17 & 0xfff0) | NF + 3 - E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200 - R17 = (R17 & 0xfff0) | NF + 06/22/2001 Support DM9801 progrmming + E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000 + E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200 + R17 = (R17 & 0xfff0) | NF + 3 + E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200 + R17 = (R17 & 0xfff0) | NF -v1.00 modify by simon 2001.9.5 +v1.00 modify by simon 2001.9.5 change for kernel 2.4.x -v1.1 11/09/2001 fix force mode bug +v1.1 11/09/2001 fix force mode bug v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>: Fixed phy reset. diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index 822afc566..851467d81 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -15,7 +15,7 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 - Temple Place - Suite 330, Boston, MA 02111-1307, USA. + Temple Place - Suite 330, Boston, MA 02111-1307, USA. The full GNU General Public License is included in this distribution in the file called LICENSE. @@ -44,7 +44,7 @@ #ifdef E1000_DEBUG #define E1000_DBG(args...) printf("e1000: " args) #define DEBUGOUT(fmt,args...) printf(fmt ,##args) -#define DEBUGFUNC() printf("%s\n", __FUNCTION__); +#define DEBUGFUNC() printf("%s\n", __FUNCTION__); #else #define E1000_DBG(args...) #define DEBUGFUNC() @@ -193,35 +193,35 @@ struct e1000_phy_stats { }; /* Error Codes */ -#define E1000_SUCCESS 0 -#define E1000_ERR_EEPROM 1 -#define E1000_ERR_PHY 2 -#define E1000_ERR_CONFIG 3 -#define E1000_ERR_PARAM 4 -#define E1000_ERR_MAC_TYPE 5 -#define E1000_ERR_PHY_TYPE 6 -#define E1000_ERR_NOLINK 7 -#define E1000_ERR_TIMEOUT 8 -#define E1000_ERR_RESET 9 -#define E1000_ERR_MASTER_REQUESTS_PENDING 10 -#define E1000_ERR_HOST_INTERFACE_COMMAND 11 -#define E1000_BLK_PHY_RESET 12 +#define E1000_SUCCESS 0 +#define E1000_ERR_EEPROM 1 +#define E1000_ERR_PHY 2 +#define E1000_ERR_CONFIG 3 +#define E1000_ERR_PARAM 4 +#define E1000_ERR_MAC_TYPE 5 +#define E1000_ERR_PHY_TYPE 6 +#define E1000_ERR_NOLINK 7 +#define E1000_ERR_TIMEOUT 8 +#define E1000_ERR_RESET 9 +#define E1000_ERR_MASTER_REQUESTS_PENDING 10 +#define E1000_ERR_HOST_INTERFACE_COMMAND 11 +#define E1000_BLK_PHY_RESET 12 /* PCI Device IDs */ -#define E1000_DEV_ID_82542 0x1000 +#define E1000_DEV_ID_82542 0x1000 #define E1000_DEV_ID_82543GC_FIBER 0x1001 #define E1000_DEV_ID_82543GC_COPPER 0x1004 #define E1000_DEV_ID_82544EI_COPPER 0x1008 #define E1000_DEV_ID_82544EI_FIBER 0x1009 #define E1000_DEV_ID_82544GC_COPPER 0x100C #define E1000_DEV_ID_82544GC_LOM 0x100D -#define E1000_DEV_ID_82540EM 0x100E +#define E1000_DEV_ID_82540EM 0x100E #define E1000_DEV_ID_82540EM_LOM 0x1015 #define E1000_DEV_ID_82545EM_COPPER 0x100F #define E1000_DEV_ID_82545EM_FIBER 0x1011 #define E1000_DEV_ID_82546EB_COPPER 0x1010 #define E1000_DEV_ID_82546EB_FIBER 0x1012 -#define E1000_DEV_ID_82541ER 0x1078 +#define E1000_DEV_ID_82541ER 0x1078 #define NUM_DEV_IDS 14 #define NODE_ADDRESS_SIZE 6 @@ -240,24 +240,24 @@ struct e1000_phy_stats { #define FULL_DUPLEX 2 /* The sizes (in bytes) of a ethernet packet */ -#define ENET_HEADER_SIZE 14 +#define ENET_HEADER_SIZE 14 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ -#define ETHERNET_FCS_SIZE 4 +#define ETHERNET_FCS_SIZE 4 #define MAXIMUM_ETHERNET_PACKET_SIZE \ (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) #define MINIMUM_ETHERNET_PACKET_SIZE \ (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) -#define CRC_LENGTH ETHERNET_FCS_SIZE -#define MAX_JUMBO_FRAME_SIZE 0x3F00 +#define CRC_LENGTH ETHERNET_FCS_SIZE +#define MAX_JUMBO_FRAME_SIZE 0x3F00 /* 802.1q VLAN Packet Sizes */ -#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ +#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ /* Ethertype field values */ #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ -#define ETHERNET_IP_TYPE 0x0800 /* IP packets */ -#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ +#define ETHERNET_IP_TYPE 0x0800 /* IP packets */ +#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ /* Packet Header defines */ #define IP_PROTOCOL_TCP 6 @@ -269,7 +269,7 @@ struct e1000_phy_stats { * o RXSEQ = Receive Sequence Error */ #define POLL_IMS_ENABLE_MASK ( \ - E1000_IMS_RXDMT0 | \ + E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ) /* This defines the bits that are set in the Interrupt Mask @@ -281,10 +281,10 @@ struct e1000_phy_stats { * o LSC = Link Status Change */ #define IMS_ENABLE_MASK ( \ - E1000_IMS_RXT0 | \ - E1000_IMS_TXDW | \ - E1000_IMS_RXDMT0 | \ - E1000_IMS_RXSEQ | \ + E1000_IMS_RXT0 | \ + E1000_IMS_TXDW | \ + E1000_IMS_RXDMT0 | \ + E1000_IMS_RXSEQ | \ E1000_IMS_LSC) /* The number of high/low register pairs in the RAR. The RAR (Receive Address @@ -308,32 +308,32 @@ struct e1000_rx_desc { }; /* Receive Decriptor bit definitions */ -#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ -#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ -#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ -#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ -#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ -#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ -#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ -#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ -#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ -#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ -#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ -#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ -#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ -#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ +#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ +#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ +#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ +#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ +#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ +#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ +#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ +#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ +#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ +#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ +#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ +#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ +#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ +#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ -#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ +#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ #define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ -#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ +#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ #define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */ /* mask to determine if packets should be dropped due to frame errors */ #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ - E1000_RXD_ERR_CE | \ - E1000_RXD_ERR_SE | \ - E1000_RXD_ERR_SEQ | \ - E1000_RXD_ERR_CXE | \ + E1000_RXD_ERR_CE | \ + E1000_RXD_ERR_SE | \ + E1000_RXD_ERR_SEQ | \ + E1000_RXD_ERR_CXE | \ E1000_RXD_ERR_RXE) /* Transmit Descriptor */ @@ -430,8 +430,8 @@ struct e1000_data_desc { }; /* Filters */ -#define E1000_NUM_UNICAST 16 /* Unicast filter entries */ -#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ +#define E1000_NUM_UNICAST 16 /* Unicast filter entries */ +#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ /* Receive Address Register */ @@ -451,8 +451,8 @@ struct e1000_ipv4_at_entry { /* Four wakeup IP addresses are supported */ #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 -#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX -#define E1000_IP6AT_SIZE 1 +#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX +#define E1000_IP6AT_SIZE 1 /* IPv6 Address Table Entry */ struct e1000_ipv6_at_entry { @@ -481,7 +481,7 @@ struct e1000_ffvt_entry { #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 /* Each Flexible Filter is at most 128 (0x80) bytes in length */ -#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 +#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX @@ -636,7 +636,7 @@ struct e1000_ffvt_entry { #define E1000_82542_FCAH E1000_FCAH #define E1000_82542_FCT E1000_FCT #define E1000_82542_VET E1000_VET -#define E1000_82542_RA 0x00040 +#define E1000_82542_RA 0x00040 #define E1000_82542_ICR E1000_ICR #define E1000_82542_ITR E1000_ITR #define E1000_82542_ICS E1000_ICS @@ -685,7 +685,7 @@ struct e1000_ffvt_entry { #define E1000_82542_MCC E1000_MCC #define E1000_82542_LATECOL E1000_LATECOL #define E1000_82542_COLC E1000_COLC -#define E1000_82542_DC E1000_DC +#define E1000_82542_DC E1000_DC #define E1000_82542_TNCRS E1000_TNCRS #define E1000_82542_SEC E1000_SEC #define E1000_82542_CEXTERR E1000_CEXTERR @@ -886,14 +886,14 @@ struct e1000_hw { /* Register Bit Masks */ /* Device Control */ -#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ -#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ +#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ +#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ -#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ -#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ +#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ +#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ -#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ +#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ @@ -910,30 +910,30 @@ struct e1000_hw { #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ -#define E1000_CTRL_RST 0x04000000 /* Global reset */ +#define E1000_CTRL_RST 0x04000000 /* Global reset */ #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ -#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ -#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ +#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ +#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ /* Device Status */ -#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ -#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ -#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ -#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ -#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ -#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ -#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ +#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ +#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ +#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ +#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ +#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ +#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ +#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ #define E1000_STATUS_SPEED_MASK 0x000000C0 -#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ -#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ +#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ +#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ -#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ -#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ -#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ -#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ -#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ +#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ +#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ +#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ +#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ +#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ /* Constants used to intrepret the masked PCI-X bus speed. */ @@ -942,17 +942,17 @@ struct e1000_hw { #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ /* EEPROM/Flash Control */ -#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ -#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ -#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ -#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ +#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ +#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ +#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ +#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ #define E1000_EECD_FWE_MASK 0x00000030 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ #define E1000_EECD_FWE_SHIFT 4 #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ -#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ -#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ +#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ +#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ /* EEPROM Read */ @@ -964,27 +964,27 @@ struct e1000_hw { #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ /* Extended Device Control */ -#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ -#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ +#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ +#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN -#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ -#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ +#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ +#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ -#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA +#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ -#define E1000_CTRL_EXT_SWDPIN6 0x00000040 /* SWDPIN 6 value */ +#define E1000_CTRL_EXT_SWDPIN6 0x00000040 /* SWDPIN 6 value */ #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ -#define E1000_CTRL_EXT_SWDPIN7 0x00000080 /* SWDPIN 7 value */ +#define E1000_CTRL_EXT_SWDPIN7 0x00000080 /* SWDPIN 7 value */ #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ -#define E1000_CTRL_EXT_SWDPIO6 0x00000400 /* SWDPIN 6 Input or output */ +#define E1000_CTRL_EXT_SWDPIO6 0x00000400 /* SWDPIN 6 Input or output */ #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ -#define E1000_CTRL_EXT_SWDPIO7 0x00000800 /* SWDPIN 7 Input or output */ -#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ -#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ -#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ +#define E1000_CTRL_EXT_SWDPIO7 0x00000800 /* SWDPIN 7 Input or output */ +#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ +#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ +#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 @@ -1010,152 +1010,152 @@ struct e1000_hw { /* LED Control */ #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F #define E1000_LEDCTL_LED0_MODE_SHIFT 0 -#define E1000_LEDCTL_LED0_IVRT 0x00000040 +#define E1000_LEDCTL_LED0_IVRT 0x00000040 #define E1000_LEDCTL_LED0_BLINK 0x00000080 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 #define E1000_LEDCTL_LED1_MODE_SHIFT 8 -#define E1000_LEDCTL_LED1_IVRT 0x00004000 +#define E1000_LEDCTL_LED1_IVRT 0x00004000 #define E1000_LEDCTL_LED1_BLINK 0x00008000 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 #define E1000_LEDCTL_LED2_MODE_SHIFT 16 -#define E1000_LEDCTL_LED2_IVRT 0x00400000 +#define E1000_LEDCTL_LED2_IVRT 0x00400000 #define E1000_LEDCTL_LED2_BLINK 0x00800000 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 #define E1000_LEDCTL_LED3_MODE_SHIFT 24 -#define E1000_LEDCTL_LED3_IVRT 0x40000000 +#define E1000_LEDCTL_LED3_IVRT 0x40000000 #define E1000_LEDCTL_LED3_BLINK 0x80000000 -#define E1000_LEDCTL_MODE_LINK_10_1000 0x0 +#define E1000_LEDCTL_MODE_LINK_10_1000 0x0 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1 -#define E1000_LEDCTL_MODE_LINK_UP 0x2 -#define E1000_LEDCTL_MODE_ACTIVITY 0x3 +#define E1000_LEDCTL_MODE_LINK_UP 0x2 +#define E1000_LEDCTL_MODE_ACTIVITY 0x3 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 -#define E1000_LEDCTL_MODE_LINK_10 0x5 -#define E1000_LEDCTL_MODE_LINK_100 0x6 -#define E1000_LEDCTL_MODE_LINK_1000 0x7 -#define E1000_LEDCTL_MODE_PCIX_MODE 0x8 -#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 -#define E1000_LEDCTL_MODE_COLLISION 0xA -#define E1000_LEDCTL_MODE_BUS_SPEED 0xB -#define E1000_LEDCTL_MODE_BUS_SIZE 0xC -#define E1000_LEDCTL_MODE_PAUSED 0xD -#define E1000_LEDCTL_MODE_LED_ON 0xE -#define E1000_LEDCTL_MODE_LED_OFF 0xF +#define E1000_LEDCTL_MODE_LINK_10 0x5 +#define E1000_LEDCTL_MODE_LINK_100 0x6 +#define E1000_LEDCTL_MODE_LINK_1000 0x7 +#define E1000_LEDCTL_MODE_PCIX_MODE 0x8 +#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 +#define E1000_LEDCTL_MODE_COLLISION 0xA +#define E1000_LEDCTL_MODE_BUS_SPEED 0xB +#define E1000_LEDCTL_MODE_BUS_SIZE 0xC +#define E1000_LEDCTL_MODE_PAUSED 0xD +#define E1000_LEDCTL_MODE_LED_ON 0xE +#define E1000_LEDCTL_MODE_LED_OFF 0xF /* Receive Address */ #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ /* Interrupt Cause Read */ -#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ -#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ -#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ +#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ +#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ +#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ -#define E1000_ICR_RXO 0x00000040 /* rx overrun */ -#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ -#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ +#define E1000_ICR_RXO 0x00000040 /* rx overrun */ +#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ +#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ #define E1000_ICR_TXD_LOW 0x00008000 -#define E1000_ICR_SRPD 0x00010000 +#define E1000_ICR_SRPD 0x00010000 /* Interrupt Cause Set */ -#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ -#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ -#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ +#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ -#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ -#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ -#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ +#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ +#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW -#define E1000_ICS_SRPD E1000_ICR_SRPD +#define E1000_ICS_SRPD E1000_ICR_SRPD /* Interrupt Mask Set */ -#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ -#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ -#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ +#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ -#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ -#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ -#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ +#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ +#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW -#define E1000_IMS_SRPD E1000_ICR_SRPD +#define E1000_IMS_SRPD E1000_ICR_SRPD /* Interrupt Mask Clear */ -#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ -#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ -#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ +#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ +#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ +#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ -#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ -#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ -#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ +#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ +#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ +#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW -#define E1000_IMC_SRPD E1000_ICR_SRPD +#define E1000_IMC_SRPD E1000_ICR_SRPD /* Receive Control */ -#define E1000_RCTL_RST 0x00000001 /* Software reset */ -#define E1000_RCTL_EN 0x00000002 /* enable */ -#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ -#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ -#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ -#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ -#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ -#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ -#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ -#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ -#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ -#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ -#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ -#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ -#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ -#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ -#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ -#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ -#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ -#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ +#define E1000_RCTL_RST 0x00000001 /* Software reset */ +#define E1000_RCTL_EN 0x00000002 /* enable */ +#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ +#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ +#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ +#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ +#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ +#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ +#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ +#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ +#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ +#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ +#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ +#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ +#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ +#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ +#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ +#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ +#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ -#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ -#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ -#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ -#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ +#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ +#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ +#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ +#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ -#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ -#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ -#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ -#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ -#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ -#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ -#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ -#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ -#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ +#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ +#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ +#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ +#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ +#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ +#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ +#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ +#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ +#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ /* Receive Descriptor */ #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ -#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ +#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ -#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ -#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ +#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ +#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ /* Flow Control */ #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ @@ -1178,35 +1178,35 @@ struct e1000_hw { #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ /* Transmit Configuration Word */ -#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ -#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ +#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ +#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ -#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ -#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ -#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ -#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ -#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ +#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ +#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ +#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ +#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ +#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ /* Receive Configuration Word */ -#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ -#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ -#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ -#define E1000_RXCW_CC 0x10000000 /* Receive config change */ -#define E1000_RXCW_C 0x20000000 /* Receive config */ +#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ +#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ +#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ +#define E1000_RXCW_CC 0x10000000 /* Receive config change */ +#define E1000_RXCW_C 0x20000000 /* Receive config */ #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ -#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ +#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ /* Transmit Control */ -#define E1000_TCTL_RST 0x00000001 /* software reset */ -#define E1000_TCTL_EN 0x00000002 /* enable tx */ -#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ -#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ -#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ +#define E1000_TCTL_RST 0x00000001 /* software reset */ +#define E1000_TCTL_EN 0x00000002 /* enable tx */ +#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ +#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ +#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ -#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ +#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ @@ -1218,18 +1218,18 @@ struct e1000_hw { /* Definitions for power management and wakeup registers */ /* Wake Up Control */ -#define E1000_WUC_APME 0x00000001 /* APM Enable */ +#define E1000_WUC_APME 0x00000001 /* APM Enable */ #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ /* Wake Up Filter Control */ #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ -#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ -#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ -#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ -#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ -#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ +#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ +#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ +#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ +#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ +#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ @@ -1256,26 +1256,26 @@ struct e1000_hw { #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ /* Management Control */ -#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ -#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ -#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ -#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ -#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ -#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ -#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ -#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ -#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ -#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery +#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ +#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ +#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ +#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ +#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ +#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ +#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ +#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ +#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ +#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery * Filtering */ -#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ -#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ +#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ +#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ -#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ -#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ -#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ -#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ +#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ +#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ +#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ +#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ -#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ +#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ @@ -1283,7 +1283,7 @@ struct e1000_hw { /* Wake Up Packet Length */ #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ -#define E1000_MDALIGN 4096 +#define E1000_MDALIGN 4096 /* EEPROM Commands */ #define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */ @@ -1293,17 +1293,17 @@ struct e1000_hw { #define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */ /* EEPROM Word Offsets */ -#define EEPROM_COMPAT 0x0003 -#define EEPROM_ID_LED_SETTINGS 0x0004 +#define EEPROM_COMPAT 0x0003 +#define EEPROM_ID_LED_SETTINGS 0x0004 #define EEPROM_INIT_CONTROL1_REG 0x000A #define EEPROM_INIT_CONTROL2_REG 0x000F -#define EEPROM_FLASH_VERSION 0x0032 -#define EEPROM_CHECKSUM_REG 0x003F +#define EEPROM_FLASH_VERSION 0x0032 +#define EEPROM_CHECKSUM_REG 0x003F /* Word definitions for ID LED Settings */ #define ID_LED_RESERVED_0000 0x0000 #define ID_LED_RESERVED_FFFF 0xFFFF -#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ +#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ (ID_LED_OFF1_OFF2 << 8) | \ (ID_LED_DEF1_DEF2 << 4) | \ (ID_LED_DEF1_DEF2)) @@ -1311,7 +1311,7 @@ struct e1000_hw { #define ID_LED_DEF1_ON2 0x2 #define ID_LED_DEF1_OFF2 0x3 #define ID_LED_ON1_DEF2 0x4 -#define ID_LED_ON1_ON2 0x5 +#define ID_LED_ON1_ON2 0x5 #define ID_LED_ON1_OFF2 0x6 #define ID_LED_OFF1_DEF2 0x7 #define ID_LED_OFF1_ON2 0x8 @@ -1330,9 +1330,9 @@ struct e1000_hw { /* Mask bits for fields in Word 0x0f of the EEPROM */ #define EEPROM_WORD0F_PAUSE_MASK 0x3000 -#define EEPROM_WORD0F_PAUSE 0x1000 -#define EEPROM_WORD0F_ASM_DIR 0x2000 -#define EEPROM_WORD0F_ANE 0x0800 +#define EEPROM_WORD0F_PAUSE 0x1000 +#define EEPROM_WORD0F_ASM_DIR 0x2000 +#define EEPROM_WORD0F_ANE 0x0800 #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ @@ -1340,19 +1340,19 @@ struct e1000_hw { /* EEPROM Map defines (WORD OFFSETS)*/ #define EEPROM_NODE_ADDRESS_BYTE_0 0 -#define EEPROM_PBA_BYTE_1 8 +#define EEPROM_PBA_BYTE_1 8 /* EEPROM Map Sizes (Byte Counts) */ #define PBA_SIZE 4 /* Collision related configuration parameters */ -#define E1000_COLLISION_THRESHOLD 16 -#define E1000_CT_SHIFT 4 -#define E1000_COLLISION_DISTANCE 64 -#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE -#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE +#define E1000_COLLISION_THRESHOLD 16 +#define E1000_CT_SHIFT 4 +#define E1000_COLLISION_DISTANCE 64 +#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE +#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE #define E1000_GB_HDX_COLLISION_DISTANCE 512 -#define E1000_COLD_SHIFT 12 +#define E1000_COLD_SHIFT 12 /* The number of Transmit and Receive Descriptors must be a multiple of 8 */ #define REQ_TX_DESCRIPTOR_MULTIPLE 8 @@ -1369,11 +1369,11 @@ struct e1000_hw { #define DEFAULT_82542_TIPG_IPGR1 2 #define DEFAULT_82543_TIPG_IPGR1 8 -#define E1000_TIPG_IPGR1_SHIFT 10 +#define E1000_TIPG_IPGR1_SHIFT 10 #define DEFAULT_82542_TIPG_IPGR2 10 #define DEFAULT_82543_TIPG_IPGR2 6 -#define E1000_TIPG_IPGR2_SHIFT 20 +#define E1000_TIPG_IPGR2_SHIFT 20 #define E1000_TXDMAC_DPP 0x00000001 @@ -1384,11 +1384,11 @@ struct e1000_hw { #define TX_THRESHOLD_STOP 190 #define TX_THRESHOLD_DISABLE 0 #define TX_THRESHOLD_TIMER_MS 10000 -#define MIN_NUM_XMITS 1000 -#define IFS_MAX 80 -#define IFS_STEP 10 -#define IFS_MIN 40 -#define IFS_RATIO 4 +#define MIN_NUM_XMITS 1000 +#define IFS_MAX 80 +#define IFS_STEP 10 +#define IFS_MIN 40 +#define IFS_RATIO 4 /* PBA constants */ #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ @@ -1399,12 +1399,12 @@ struct e1000_hw { /* Flow Control Constants */ #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 -#define FLOW_CONTROL_TYPE 0x8808 +#define FLOW_CONTROL_TYPE 0x8808 /* The historical defaults for the flow control values are given below. */ -#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ -#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ -#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ +#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ +#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ +#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ /* Flow Control High-Watermark: 43464 bytes */ #define E1000_FC_HIGH_THRESH 0xA9C8 @@ -1414,7 +1414,7 @@ struct e1000_hw { #define E1000_FC_PAUSE_TIME 0x0680 /* PCIX Config space */ -#define PCIX_COMMAND_REGISTER 0xE6 +#define PCIX_COMMAND_REGISTER 0xE6 #define PCIX_STATUS_REGISTER_LO 0xE8 #define PCIX_STATUS_REGISTER_HI 0xEA @@ -1453,7 +1453,7 @@ struct e1000_hw { #define RECEIVE_BUFFER_ALIGN_SIZE (256) /* The number of milliseconds we wait for auto-negotiation to complete */ -#define LINK_UP_TIMEOUT 500 +#define LINK_UP_TIMEOUT 500 #define E1000_TX_BUFFER_SIZE ((uint32_t)1514) @@ -1463,14 +1463,14 @@ struct e1000_hw { /* TBI_ACCEPT macro definition: * * This macro requires: - * adapter = a pointer to struct e1000_hw - * status = the 8 bit status field of the RX descriptor with EOP set - * error = the 8 bit error field of the RX descriptor with EOP set - * length = the sum of all the length fields of the RX descriptors that - * make up the current frame - * last_byte = the last byte of the frame DMAed by the hardware - * max_frame_length = the maximum frame length we want to accept. - * min_frame_length = the minimum frame length we want to accept. + * adapter = a pointer to struct e1000_hw + * status = the 8 bit status field of the RX descriptor with EOP set + * error = the 8 bit error field of the RX descriptor with EOP set + * length = the sum of all the length fields of the RX descriptors that + * make up the current frame + * last_byte = the last byte of the frame DMAed by the hardware + * max_frame_length = the maximum frame length we want to accept. + * min_frame_length = the minimum frame length we want to accept. * * This macro is a conditional that should be used in the interrupt * handler's Rx processing routine when RxErrors have been detected. @@ -1478,11 +1478,11 @@ struct e1000_hw { * Typical use: * ... * if (TBI_ACCEPT) { - * accept_frame = TRUE; - * e1000_tbi_adjust_stats(adapter, MacAddress); - * frame_length--; + * accept_frame = TRUE; + * e1000_tbi_adjust_stats(adapter, MacAddress); + * frame_length--; * } else { - * accept_frame = FALSE; + * accept_frame = FALSE; * } * ... */ @@ -1502,237 +1502,237 @@ struct e1000_hw { /* Bit definitions for the Management Data IO (MDIO) and Management Data * Clock (MDC) pins in the Device Control Register. */ -#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 -#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 -#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 -#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 -#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 -#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 -#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR -#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA +#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 +#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 +#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 +#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 +#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 +#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 +#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR +#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA /* PHY 1000 MII Register/Bit Definitions */ /* PHY Registers defined by IEEE */ -#define PHY_CTRL 0x00 /* Control Register */ -#define PHY_STATUS 0x01 /* Status Regiser */ -#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ -#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ -#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ -#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ -#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ -#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ -#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ -#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ -#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ -#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ +#define PHY_CTRL 0x00 /* Control Register */ +#define PHY_STATUS 0x01 /* Status Regiser */ +#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ +#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ +#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ +#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ +#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ +#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ +#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ +#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ +#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ +#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ /* M88E1000 Specific Registers */ -#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ -#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ -#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ -#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ -#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ -#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ +#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ +#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ +#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ +#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ +#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ +#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ -#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ +#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ /* IGP01E1000 specifics */ -#define IGP01E1000_IEEE_REGS_PAGE 0x0000 +#define IGP01E1000_IEEE_REGS_PAGE 0x0000 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 -#define IGP01E1000_IEEE_FORCE_GIGA 0x0140 +#define IGP01E1000_IEEE_FORCE_GIGA 0x0140 /* IGP01E1000 Specific Registers */ -#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ -#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ -#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ -#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ -#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ -#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ -#define IGP02E1000_PHY_POWER_MGMT 0x19 -#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ +#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ +#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ +#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ +#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ +#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ +#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ +#define IGP02E1000_PHY_POWER_MGMT 0x19 +#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ /* PHY Control Register */ -#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ -#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ -#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ -#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ -#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ -#define MII_CR_POWER_DOWN 0x0800 /* Power down */ -#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ -#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ -#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ -#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ +#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ +#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ +#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ +#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ +#define MII_CR_POWER_DOWN 0x0800 /* Power down */ +#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ +#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ +#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ +#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ /* PHY Status Register */ -#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ -#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ -#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ -#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ -#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ -#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ -#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ -#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ -#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ -#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ -#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ -#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ -#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ -#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ -#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ +#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ +#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ +#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ +#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ +#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ +#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ +#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ +#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ +#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ +#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ +#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ +#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ +#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ +#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ +#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ /* Autoneg Advertisement Register */ -#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ -#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ -#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ -#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ -#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ -#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ -#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ -#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ -#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ -#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ +#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ +#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ +#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ +#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ +#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ +#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ +#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ +#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ +#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ +#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ /* Link Partner Ability Register (Base Page) */ -#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ -#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ -#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ -#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ -#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ -#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ -#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ -#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ -#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ -#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ -#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ +#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ +#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ +#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ +#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ +#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ +#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ +#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ +#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ +#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ +#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ +#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ /* Autoneg Expansion Register */ -#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ -#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ -#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ -#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ -#define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */ +#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ +#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ +#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ +#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ +#define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */ /* Next Page TX Register */ -#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ -#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges - * of different NP - */ -#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg - * 0 = cannot comply with msg - */ -#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ -#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow - * 0 = sending last NP - */ +#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ +#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges + * of different NP + */ +#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg + * 0 = cannot comply with msg + */ +#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ +#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow + * 0 = sending last NP + */ /* Link Partner Next Page Register */ -#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ -#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges - * of different NP - */ -#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg - * 0 = cannot comply with msg - */ -#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ -#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ -#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow - * 0 = sending last NP - */ +#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ +#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges + * of different NP + */ +#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg + * 0 = cannot comply with msg + */ +#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ +#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ +#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow + * 0 = sending last NP + */ /* 1000BASE-T Control Register */ -#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ -#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ -#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ -#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ - /* 0=DTE device */ -#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ - /* 0=Configure PHY as Slave */ -#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ - /* 0=Automatic Master/Slave config */ -#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ -#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ -#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ -#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ -#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ +#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ +#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ +#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ +#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ + /* 0=DTE device */ +#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ + /* 0=Configure PHY as Slave */ +#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ + /* 0=Automatic Master/Slave config */ +#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ +#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ +#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ +#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ +#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ /* 1000BASE-T Status Register */ -#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ -#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ -#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ -#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ -#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ -#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ -#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ -#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ +#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ +#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ +#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ +#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ +#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ +#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ +#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ +#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 -#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 +#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 /* Extended Status Register */ -#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ -#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ -#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ -#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ +#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ +#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ +#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ +#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ -#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ -#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ +#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ +#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ -#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ - /* (0=enable, 1=disable) */ +#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ + /* (0=enable, 1=disable) */ /* M88E1000 PHY Specific Control Register */ -#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ +#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ -#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ -#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, +#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ +#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, * 0=CLK125 toggling */ -#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ - /* Manual MDI configuration */ -#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ -#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, +#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ + /* Manual MDI configuration */ +#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ +#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, * 100BASE-TX/10BASE-T: * MDI Mode */ -#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled +#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled * all speeds. */ #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 - /* 1=Enable Extended 10BASE-T distance - * (Lower 10BASE-T RX Threshold) - * 0=Normal 10BASE-T RX Threshold */ -#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 - /* 1=5-Bit interface in 100BASE-TX - * 0=MII interface in 100BASE-TX */ -#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ -#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ -#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ + /* 1=Enable Extended 10BASE-T distance + * (Lower 10BASE-T RX Threshold) + * 0=Normal 10BASE-T RX Threshold */ +#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 + /* 1=5-Bit interface in 100BASE-TX + * 0=MII interface in 100BASE-TX */ +#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ +#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ +#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ -#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 -#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 +#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 +#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 /* M88E1000 PHY Specific Status Register */ -#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ -#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ -#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ -#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; - * 3=110-140M;4=>140M */ -#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ -#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ -#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ -#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ -#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ -#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ -#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ -#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ +#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ +#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ +#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ +#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; + * 3=110-140M;4=>140M */ +#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ +#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ +#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ +#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ +#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ +#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ +#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ +#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ #define M88E1000_PSSR_REV_POLARITY_SHIFT 1 -#define M88E1000_PSSR_MDIX_SHIFT 6 +#define M88E1000_PSSR_MDIX_SHIFT 6 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 /* M88E1000 Extended PHY Specific Control Register */ -#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ -#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. +#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ +#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. * Will assert lost lock and bring * link down if idle not seen * within 1ms in 1000BASE-T @@ -1751,41 +1751,41 @@ struct e1000_hw { #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 -#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ -#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ -#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ +#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ +#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ +#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ /* Bit definitions for valid PHY IDs. */ -#define M88E1000_E_PHY_ID 0x01410C50 -#define M88E1000_I_PHY_ID 0x01410C30 -#define M88E1011_I_PHY_ID 0x01410C20 -#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID -#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID -#define IGP01E1000_I_PHY_ID 0x02A80380 +#define M88E1000_E_PHY_ID 0x01410C50 +#define M88E1000_I_PHY_ID 0x01410C30 +#define M88E1011_I_PHY_ID 0x01410C20 +#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID +#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID +#define IGP01E1000_I_PHY_ID 0x02A80380 /* Miscellaneous PHY bit definitions. */ -#define PHY_PREAMBLE 0xFFFFFFFF -#define PHY_SOF 0x01 -#define PHY_OP_READ 0x02 -#define PHY_OP_WRITE 0x01 -#define PHY_TURNAROUND 0x02 -#define PHY_PREAMBLE_SIZE 32 -#define MII_CR_SPEED_1000 0x0040 -#define MII_CR_SPEED_100 0x2000 -#define MII_CR_SPEED_10 0x0000 -#define E1000_PHY_ADDRESS 0x01 -#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ -#define PHY_FORCE_TIME 20 /* 2.0 Seconds */ -#define PHY_REVISION_MASK 0xFFFFFFF0 -#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ -#define REG4_SPEED_MASK 0x01E0 -#define REG9_SPEED_MASK 0x0300 -#define ADVERTISE_10_HALF 0x0001 -#define ADVERTISE_10_FULL 0x0002 -#define ADVERTISE_100_HALF 0x0004 -#define ADVERTISE_100_FULL 0x0008 -#define ADVERTISE_1000_HALF 0x0010 -#define ADVERTISE_1000_FULL 0x0020 +#define PHY_PREAMBLE 0xFFFFFFFF +#define PHY_SOF 0x01 +#define PHY_OP_READ 0x02 +#define PHY_OP_WRITE 0x01 +#define PHY_TURNAROUND 0x02 +#define PHY_PREAMBLE_SIZE 32 +#define MII_CR_SPEED_1000 0x0040 +#define MII_CR_SPEED_100 0x2000 +#define MII_CR_SPEED_10 0x0000 +#define E1000_PHY_ADDRESS 0x01 +#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ +#define PHY_FORCE_TIME 20 /* 2.0 Seconds */ +#define PHY_REVISION_MASK 0xFFFFFFF0 +#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ +#define REG4_SPEED_MASK 0x01E0 +#define REG9_SPEED_MASK 0x0300 +#define ADVERTISE_10_HALF 0x0001 +#define ADVERTISE_10_FULL 0x0002 +#define ADVERTISE_100_HALF 0x0004 +#define ADVERTISE_100_FULL 0x0008 +#define ADVERTISE_1000_HALF 0x0010 +#define ADVERTISE_1000_FULL 0x0020 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ -#endif /* _E1000_HW_H_ */ +#endif /* _E1000_HW_H_ */ diff --git a/drivers/net/lan91c96.h b/drivers/net/lan91c96.h index 7d33a821f..5beddda04 100644 --- a/drivers/net/lan91c96.h +++ b/drivers/net/lan91c96.h @@ -31,7 +31,7 @@ * information under www.smsc.com. * * Authors - * Erik Stahlman ( erik@vt.edu ) + * Erik Stahlman ( erik@vt.edu ) * Daris A Nevil ( dnevil@snmc.com ) * * History @@ -58,7 +58,7 @@ void smc_set_mac_addr(const unsigned char *addr); typedef unsigned char byte; typedef unsigned short word; -typedef unsigned long int dword; +typedef unsigned long int dword; /* * DEBUGGING LEVELS @@ -88,8 +88,8 @@ typedef unsigned long int dword; #define SMCREG(r) (SMC_BASE_ADDRESS+((r)<<SMC_IO_SHIFT)) -#define SMC_inl(r) (*((volatile dword *)SMCREG(r))) -#define SMC_inw(r) (*((volatile word *)SMCREG(r))) +#define SMC_inl(r) (*((volatile dword *)SMCREG(r))) +#define SMC_inw(r) (*((volatile word *)SMCREG(r))) #define SMC_inb(p) ({ \ unsigned int __p = p; \ unsigned int __v = SMC_inw(__p & ~1); \ @@ -122,7 +122,7 @@ typedef unsigned long int dword; } \ }) -#define SMC_insl(r,b,l) ({ int __i ; \ +#define SMC_insl(r,b,l) ({ int __i ; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ @@ -131,7 +131,7 @@ typedef unsigned long int dword; }; \ }) -#define SMC_insw(r,b,l) ({ int __i ; \ +#define SMC_insw(r,b,l) ({ int __i ; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ @@ -140,7 +140,7 @@ typedef unsigned long int dword; }; \ }) -#define SMC_insb(r,b,l) ({ int __i ; \ +#define SMC_insb(r,b,l) ({ int __i ; \ byte *__b2; \ __b2 = (byte *) b; \ for (__i = 0; __i < l; __i++) { \ @@ -155,7 +155,7 @@ typedef unsigned long int dword; * We have only 16 Bit PCMCIA access on Socket 0 */ -#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) #define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF) #define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) @@ -178,9 +178,9 @@ typedef unsigned long int dword; #endif #if 0 -#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) +#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) #else -#define SMC_insw(r,b,l) ({ int __i ; \ +#define SMC_insw(r,b,l) ({ int __i ; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 71d19608e..5ab4726ff 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -208,7 +208,7 @@ int fec_recv(struct eth_device *dev) for (;;) { #ifdef CFG_UNIFY_CACHE - icache_invalid(); + icache_invalid(); #endif /* section 16.9.23.2 */ if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c index 075d6c52c..a52395981 100644 --- a/drivers/net/natsemi.c +++ b/drivers/net/natsemi.c @@ -62,58 +62,58 @@ /* defines */ #define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/ -#define DSIZE 0x00000FFF +#define DSIZE 0x00000FFF #define ETH_ALEN 6 -#define CRC_SIZE 4 -#define TOUT_LOOP 500000 -#define TX_BUF_SIZE 1536 -#define RX_BUF_SIZE 1536 -#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */ +#define CRC_SIZE 4 +#define TOUT_LOOP 500000 +#define TX_BUF_SIZE 1536 +#define RX_BUF_SIZE 1536 +#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */ /* Offsets to the device registers. Unlike software-only systems, device drivers interact with complex hardware. It's not useful to define symbolic names for every register bit in the device. */ enum register_offsets { - ChipCmd = 0x00, - ChipConfig = 0x04, - EECtrl = 0x08, - IntrMask = 0x14, - IntrEnable = 0x18, - TxRingPtr = 0x20, - TxConfig = 0x24, - RxRingPtr = 0x30, - RxConfig = 0x34, - ClkRun = 0x3C, - RxFilterAddr = 0x48, - RxFilterData = 0x4C, - SiliconRev = 0x58, - PCIPM = 0x44, + ChipCmd = 0x00, + ChipConfig = 0x04, + EECtrl = 0x08, + IntrMask = 0x14, + IntrEnable = 0x18, + TxRingPtr = 0x20, + TxConfig = 0x24, + RxRingPtr = 0x30, + RxConfig = 0x34, + ClkRun = 0x3C, + RxFilterAddr = 0x48, + RxFilterData = 0x4C, + SiliconRev = 0x58, + PCIPM = 0x44, BasicControl = 0x80, BasicStatus = 0x84, /* These are from the spec, around page 78... on a separate table. */ - PGSEL = 0xCC, - PMDCSR = 0xE4, - TSTDAT = 0xFC, - DSPCFG = 0xF4, - SDCFG = 0x8C + PGSEL = 0xCC, + PMDCSR = 0xE4, + TSTDAT = 0xFC, + DSPCFG = 0xF4, + SDCFG = 0x8C }; /* Bit in ChipCmd. */ enum ChipCmdBits { - ChipReset = 0x100, - RxReset = 0x20, - TxReset = 0x10, - RxOff = 0x08, - RxOn = 0x04, - TxOff = 0x02, - TxOn = 0x01 + ChipReset = 0x100, + RxReset = 0x20, + TxReset = 0x10, + RxOff = 0x08, + RxOn = 0x04, + TxOff = 0x02, + TxOn = 0x01 }; enum ChipConfigBits { - LinkSts = 0x80000000, - HundSpeed = 0x40000000, - FullDuplex = 0x20000000, + LinkSts = 0x80000000, + HundSpeed = 0x40000000, + FullDuplex = 0x20000000, TenPolarity = 0x10000000, AnegDone = 0x08000000, AnegEnBothBoth = 0x0000E000, @@ -127,58 +127,58 @@ enum ChipConfigBits { SpeedMask = 0x00004000, AnegMask = 0x00002000, AnegDis10Half = 0x00000000, - ExtPhy = 0x00001000, - PhyRst = 0x00000400, - PhyDis = 0x00000200, + ExtPhy = 0x00001000, + PhyRst = 0x00000400, + PhyDis = 0x00000200, BootRomDisable = 0x00000004, - BEMode = 0x00000001, + BEMode = 0x00000001, }; enum TxConfig_bits { - TxDrthMask = 0x3f, - TxFlthMask = 0x3f00, + TxDrthMask = 0x3f, + TxFlthMask = 0x3f00, TxMxdmaMask = 0x700000, - TxMxdma_512 = 0x0, - TxMxdma_4 = 0x100000, - TxMxdma_8 = 0x200000, - TxMxdma_16 = 0x300000, - TxMxdma_32 = 0x400000, - TxMxdma_64 = 0x500000, - TxMxdma_128 = 0x600000, - TxMxdma_256 = 0x700000, - TxCollRetry = 0x800000, - TxAutoPad = 0x10000000, - TxMacLoop = 0x20000000, - TxHeartIgn = 0x40000000, - TxCarrierIgn = 0x80000000 + TxMxdma_512 = 0x0, + TxMxdma_4 = 0x100000, + TxMxdma_8 = 0x200000, + TxMxdma_16 = 0x300000, + TxMxdma_32 = 0x400000, + TxMxdma_64 = 0x500000, + TxMxdma_128 = 0x600000, + TxMxdma_256 = 0x700000, + TxCollRetry = 0x800000, + TxAutoPad = 0x10000000, + TxMacLoop = 0x20000000, + TxHeartIgn = 0x40000000, + TxCarrierIgn = 0x80000000 }; enum RxConfig_bits { - RxDrthMask = 0x3e, - RxMxdmaMask = 0x700000, - RxMxdma_512 = 0x0, - RxMxdma_4 = 0x100000, - RxMxdma_8 = 0x200000, - RxMxdma_16 = 0x300000, - RxMxdma_32 = 0x400000, - RxMxdma_64 = 0x500000, - RxMxdma_128 = 0x600000, - RxMxdma_256 = 0x700000, - RxAcceptLong = 0x8000000, - RxAcceptTx = 0x10000000, - RxAcceptRunt = 0x40000000, - RxAcceptErr = 0x80000000 + RxDrthMask = 0x3e, + RxMxdmaMask = 0x700000, + RxMxdma_512 = 0x0, + RxMxdma_4 = 0x100000, + RxMxdma_8 = 0x200000, + RxMxdma_16 = 0x300000, + RxMxdma_32 = 0x400000, + RxMxdma_64 = 0x500000, + RxMxdma_128 = 0x600000, + RxMxdma_256 = 0x700000, + RxAcceptLong = 0x8000000, + RxAcceptTx = 0x10000000, + RxAcceptRunt = 0x40000000, + RxAcceptErr = 0x80000000 }; /* Bits in the RxMode register. */ enum rx_mode_bits { - AcceptErr = 0x20, - AcceptRunt = 0x10, - AcceptBroadcast = 0xC0000000, - AcceptMulticast = 0x00200000, - AcceptAllMulticast = 0x20000000, - AcceptAllPhys = 0x10000000, - AcceptMyPhys = 0x08000000 + AcceptErr = 0x20, + AcceptRunt = 0x10, + AcceptBroadcast = 0xC0000000, + AcceptMulticast = 0x00200000, + AcceptAllMulticast = 0x20000000, + AcceptAllPhys = 0x10000000, + AcceptMyPhys = 0x08000000 }; typedef struct _BufferDesc { @@ -377,7 +377,7 @@ natsemi_initialize(bd_t * bis) chip_config = INL(dev, ChipConfig); #ifdef NATSEMI_DEBUG printf("%s: Transceiver status %#08X advertising %#08X\n", - dev->name, (int) INL(dev, BasicStatus), advertising); + dev->name, (int) INL(dev, BasicStatus), advertising); printf("%s: Transceiver default autoneg. %s 10%s %s duplex.\n", dev->name, chip_config & AnegMask ? "enabled, advertise" : "disabled, force", chip_config & SpeedMask ? "0" : "", @@ -550,7 +550,7 @@ mdio_read(struct eth_device *dev, int phy_id, int location) * * Arguments: struct eth_device *dev: NIC data structure * - * returns: int. + * returns: int. */ static int @@ -693,8 +693,8 @@ natsemi_init_rxd(struct eth_device *dev) #ifdef NATSEMI_DEBUG printf ("natsemi_init_rxd: rxd[%d]=%p link=%X cmdsts=%lX bufptr=%X\n", - i, &rxd[i], le32_to_cpu(rxd[i].link), - rxd[i].cmdsts, rxd[i].bufptr); + i, &rxd[i], le32_to_cpu(rxd[i].link), + rxd[i].cmdsts, rxd[i].bufptr); #endif } diff --git a/drivers/net/nicext.h b/drivers/net/nicext.h index 4074972c0..ff422e773 100644 --- a/drivers/net/nicext.h +++ b/drivers/net/nicext.h @@ -30,7 +30,7 @@ /* * ioctl for NICE */ -#define SIOCNICE SIOCDEVPRIVATE+7 +#define SIOCNICE SIOCDEVPRIVATE+7 /* * SIOCNICE: diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c index f8b143a01..c807dd4c7 100644 --- a/drivers/net/ns8382x.c +++ b/drivers/net/ns8382x.c @@ -42,11 +42,11 @@ /* Revision History * October 2002 mar 1.0 * Initial U-Boot Release. - * Tested with Netgear GA622T (83820) - * and SMC9452TX (83821) - * NOTE: custom boards with these chips may (likely) require - * a programmed EEPROM device (if present) in order to work - * correctly. + * Tested with Netgear GA622T (83820) + * and SMC9452TX (83821) + * NOTE: custom boards with these chips may (likely) require + * a programmed EEPROM device (if present) in order to work + * correctly. */ /* Includes */ @@ -115,50 +115,50 @@ enum ChipConfigBits { #define SpeedStatus_Polarity ( GigSpeed | HundSpeed | FullDuplex) enum TxConfig_bits { - TxDrthMask = 0x000000ff, - TxFlthMask = 0x0000ff00, + TxDrthMask = 0x000000ff, + TxFlthMask = 0x0000ff00, TxMxdmaMask = 0x00700000, - TxMxdma_8 = 0x00100000, - TxMxdma_16 = 0x00200000, - TxMxdma_32 = 0x00300000, - TxMxdma_64 = 0x00400000, - TxMxdma_128 = 0x00500000, - TxMxdma_256 = 0x00600000, - TxMxdma_512 = 0x00700000, - TxMxdma_1024 = 0x00000000, - TxCollRetry = 0x00800000, - TxAutoPad = 0x10000000, - TxMacLoop = 0x20000000, - TxHeartIgn = 0x40000000, - TxCarrierIgn = 0x80000000 + TxMxdma_8 = 0x00100000, + TxMxdma_16 = 0x00200000, + TxMxdma_32 = 0x00300000, + TxMxdma_64 = 0x00400000, + TxMxdma_128 = 0x00500000, + TxMxdma_256 = 0x00600000, + TxMxdma_512 = 0x00700000, + TxMxdma_1024 = 0x00000000, + TxCollRetry = 0x00800000, + TxAutoPad = 0x10000000, + TxMacLoop = 0x20000000, + TxHeartIgn = 0x40000000, + TxCarrierIgn = 0x80000000 }; enum RxConfig_bits { - RxDrthMask = 0x0000003e, - RxMxdmaMask = 0x00700000, - RxMxdma_8 = 0x00100000, - RxMxdma_16 = 0x00200000, - RxMxdma_32 = 0x00300000, - RxMxdma_64 = 0x00400000, - RxMxdma_128 = 0x00500000, - RxMxdma_256 = 0x00600000, - RxMxdma_512 = 0x00700000, - RxMxdma_1024 = 0x00000000, - RxAcceptLenErr = 0x04000000, - RxAcceptLong = 0x08000000, - RxAcceptTx = 0x10000000, - RxStripCRC = 0x20000000, - RxAcceptRunt = 0x40000000, - RxAcceptErr = 0x80000000, + RxDrthMask = 0x0000003e, + RxMxdmaMask = 0x00700000, + RxMxdma_8 = 0x00100000, + RxMxdma_16 = 0x00200000, + RxMxdma_32 = 0x00300000, + RxMxdma_64 = 0x00400000, + RxMxdma_128 = 0x00500000, + RxMxdma_256 = 0x00600000, + RxMxdma_512 = 0x00700000, + RxMxdma_1024 = 0x00000000, + RxAcceptLenErr = 0x04000000, + RxAcceptLong = 0x08000000, + RxAcceptTx = 0x10000000, + RxStripCRC = 0x20000000, + RxAcceptRunt = 0x40000000, + RxAcceptErr = 0x80000000, }; /* Bits in the RxMode register. */ enum rx_mode_bits { - RxFilterEnable = 0x80000000, - AcceptAllBroadcast = 0x40000000, - AcceptAllMulticast = 0x20000000, - AcceptAllUnicast = 0x10000000, - AcceptPerfectMatch = 0x08000000, + RxFilterEnable = 0x80000000, + AcceptAllBroadcast = 0x40000000, + AcceptAllMulticast = 0x20000000, + AcceptAllUnicast = 0x10000000, + AcceptPerfectMatch = 0x08000000, }; typedef struct _BufferDesc { @@ -527,7 +527,7 @@ mdio_write(struct eth_device *dev, int phy_id, int addr, int value) * Description: resets the ethernet controller chip and configures * registers and data structures required for sending and receiving packets. * Arguments: struct eth_device *dev: NIC data structure - * returns: int. + * returns: int. */ static int diff --git a/drivers/net/plb2800_eth.c b/drivers/net/plb2800_eth.c index 0ae5d808a..b8cc57aa7 100644 --- a/drivers/net/plb2800_eth.c +++ b/drivers/net/plb2800_eth.c @@ -333,7 +333,7 @@ static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr) DA_LOOKUP = temp; /* Set MA_LEARN register */ - temp = 50 << MA_DEST_SHF; /* static entry */ + temp = 50 << MA_DEST_SHF; /* static entry */ MA_LEARN = temp; /* set destination address */ diff --git a/drivers/net/rtl8019.h b/drivers/net/rtl8019.h index 38116ad84..ae5163c43 100644 --- a/drivers/net/rtl8019.h +++ b/drivers/net/rtl8019.h @@ -30,88 +30,85 @@ #include <asm/types.h> #include <config.h> - #ifdef CONFIG_DRIVER_RTL8019 -#define RTL8019_REG_00 (RTL8019_BASE + 0x00) -#define RTL8019_REG_01 (RTL8019_BASE + 0x01) -#define RTL8019_REG_02 (RTL8019_BASE + 0x02) -#define RTL8019_REG_03 (RTL8019_BASE + 0x03) -#define RTL8019_REG_04 (RTL8019_BASE + 0x04) -#define RTL8019_REG_05 (RTL8019_BASE + 0x05) -#define RTL8019_REG_06 (RTL8019_BASE + 0x06) -#define RTL8019_REG_07 (RTL8019_BASE + 0x07) -#define RTL8019_REG_08 (RTL8019_BASE + 0x08) -#define RTL8019_REG_09 (RTL8019_BASE + 0x09) -#define RTL8019_REG_0a (RTL8019_BASE + 0x0a) -#define RTL8019_REG_0b (RTL8019_BASE + 0x0b) -#define RTL8019_REG_0c (RTL8019_BASE + 0x0c) -#define RTL8019_REG_0d (RTL8019_BASE + 0x0d) -#define RTL8019_REG_0e (RTL8019_BASE + 0x0e) -#define RTL8019_REG_0f (RTL8019_BASE + 0x0f) -#define RTL8019_REG_10 (RTL8019_BASE + 0x10) -#define RTL8019_REG_1f (RTL8019_BASE + 0x1f) - -#define RTL8019_COMMAND RTL8019_REG_00 -#define RTL8019_PAGESTART RTL8019_REG_01 -#define RTL8019_PAGESTOP RTL8019_REG_02 -#define RTL8019_BOUNDARY RTL8019_REG_03 -#define RTL8019_TRANSMITSTATUS RTL8019_REG_04 -#define RTL8019_TRANSMITPAGE RTL8019_REG_04 -#define RTL8019_TRANSMITBYTECOUNT0 RTL8019_REG_05 -#define RTL8019_NCR RTL8019_REG_05 -#define RTL8019_TRANSMITBYTECOUNT1 RTL8019_REG_06 -#define RTL8019_INTERRUPTSTATUS RTL8019_REG_07 -#define RTL8019_CURRENT RTL8019_REG_07 -#define RTL8019_REMOTESTARTADDRESS0 RTL8019_REG_08 -#define RTL8019_CRDMA0 RTL8019_REG_08 -#define RTL8019_REMOTESTARTADDRESS1 RTL8019_REG_09 -#define RTL8019_CRDMA1 RTL8019_REG_09 -#define RTL8019_REMOTEBYTECOUNT0 RTL8019_REG_0a -#define RTL8019_REMOTEBYTECOUNT1 RTL8019_REG_0b -#define RTL8019_RECEIVESTATUS RTL8019_REG_0c -#define RTL8019_RECEIVECONFIGURATION RTL8019_REG_0c -#define RTL8019_TRANSMITCONFIGURATION RTL8019_REG_0d -#define RTL8019_FAE_TALLY RTL8019_REG_0d -#define RTL8019_DATACONFIGURATION RTL8019_REG_0e -#define RTL8019_CRC_TALLY RTL8019_REG_0e -#define RTL8019_INTERRUPTMASK RTL8019_REG_0f -#define RTL8019_MISS_PKT_TALLY RTL8019_REG_0f -#define RTL8019_PHYSICALADDRESS0 RTL8019_REG_01 -#define RTL8019_PHYSICALADDRESS1 RTL8019_REG_02 -#define RTL8019_PHYSICALADDRESS2 RTL8019_REG_03 -#define RTL8019_PHYSICALADDRESS3 RTL8019_REG_04 -#define RTL8019_PHYSICALADDRESS4 RTL8019_REG_05 -#define RTL8019_PHYSICALADDRESS5 RTL8019_REG_06 -#define RTL8019_MULTIADDRESS0 RTL8019_REG_08 -#define RTL8019_MULTIADDRESS1 RTL8019_REG_09 -#define RTL8019_MULTIADDRESS2 RTL8019_REG_0a -#define RTL8019_MULTIADDRESS3 RTL8019_REG_0b -#define RTL8019_MULTIADDRESS4 RTL8019_REG_0c -#define RTL8019_MULTIADDRESS5 RTL8019_REG_0d -#define RTL8019_MULTIADDRESS6 RTL8019_REG_0e -#define RTL8019_MULTIADDRESS7 RTL8019_REG_0f -#define RTL8019_DMA_DATA RTL8019_REG_10 -#define RTL8019_RESET RTL8019_REG_1f - +#define RTL8019_REG_00 (RTL8019_BASE + 0x00) +#define RTL8019_REG_01 (RTL8019_BASE + 0x01) +#define RTL8019_REG_02 (RTL8019_BASE + 0x02) +#define RTL8019_REG_03 (RTL8019_BASE + 0x03) +#define RTL8019_REG_04 (RTL8019_BASE + 0x04) +#define RTL8019_REG_05 (RTL8019_BASE + 0x05) +#define RTL8019_REG_06 (RTL8019_BASE + 0x06) +#define RTL8019_REG_07 (RTL8019_BASE + 0x07) +#define RTL8019_REG_08 (RTL8019_BASE + 0x08) +#define RTL8019_REG_09 (RTL8019_BASE + 0x09) +#define RTL8019_REG_0a (RTL8019_BASE + 0x0a) +#define RTL8019_REG_0b (RTL8019_BASE + 0x0b) +#define RTL8019_REG_0c (RTL8019_BASE + 0x0c) +#define RTL8019_REG_0d (RTL8019_BASE + 0x0d) +#define RTL8019_REG_0e (RTL8019_BASE + 0x0e) +#define RTL8019_REG_0f (RTL8019_BASE + 0x0f) +#define RTL8019_REG_10 (RTL8019_BASE + 0x10) +#define RTL8019_REG_1f (RTL8019_BASE + 0x1f) -#define RTL8019_PAGE0 0x22 -#define RTL8019_PAGE1 0x62 -#define RTL8019_PAGE0DMAWRITE 0x12 -#define RTL8019_PAGE2DMAWRITE 0x92 -#define RTL8019_REMOTEDMAWR 0x12 -#define RTL8019_REMOTEDMARD 0x0A -#define RTL8019_ABORTDMAWR 0x32 -#define RTL8019_ABORTDMARD 0x2A -#define RTL8019_PAGE0STOP 0x21 -#define RTL8019_PAGE1STOP 0x61 -#define RTL8019_TRANSMIT 0x26 -#define RTL8019_TXINPROGRESS 0x04 -#define RTL8019_SEND 0x1A +#define RTL8019_COMMAND RTL8019_REG_00 +#define RTL8019_PAGESTART RTL8019_REG_01 +#define RTL8019_PAGESTOP RTL8019_REG_02 +#define RTL8019_BOUNDARY RTL8019_REG_03 +#define RTL8019_TRANSMITSTATUS RTL8019_REG_04 +#define RTL8019_TRANSMITPAGE RTL8019_REG_04 +#define RTL8019_TRANSMITBYTECOUNT0 RTL8019_REG_05 +#define RTL8019_NCR RTL8019_REG_05 +#define RTL8019_TRANSMITBYTECOUNT1 RTL8019_REG_06 +#define RTL8019_INTERRUPTSTATUS RTL8019_REG_07 +#define RTL8019_CURRENT RTL8019_REG_07 +#define RTL8019_REMOTESTARTADDRESS0 RTL8019_REG_08 +#define RTL8019_CRDMA0 RTL8019_REG_08 +#define RTL8019_REMOTESTARTADDRESS1 RTL8019_REG_09 +#define RTL8019_CRDMA1 RTL8019_REG_09 +#define RTL8019_REMOTEBYTECOUNT0 RTL8019_REG_0a +#define RTL8019_REMOTEBYTECOUNT1 RTL8019_REG_0b +#define RTL8019_RECEIVESTATUS RTL8019_REG_0c +#define RTL8019_RECEIVECONFIGURATION RTL8019_REG_0c +#define RTL8019_TRANSMITCONFIGURATION RTL8019_REG_0d +#define RTL8019_FAE_TALLY RTL8019_REG_0d +#define RTL8019_DATACONFIGURATION RTL8019_REG_0e +#define RTL8019_CRC_TALLY RTL8019_REG_0e +#define RTL8019_INTERRUPTMASK RTL8019_REG_0f +#define RTL8019_MISS_PKT_TALLY RTL8019_REG_0f +#define RTL8019_PHYSICALADDRESS0 RTL8019_REG_01 +#define RTL8019_PHYSICALADDRESS1 RTL8019_REG_02 +#define RTL8019_PHYSICALADDRESS2 RTL8019_REG_03 +#define RTL8019_PHYSICALADDRESS3 RTL8019_REG_04 +#define RTL8019_PHYSICALADDRESS4 RTL8019_REG_05 +#define RTL8019_PHYSICALADDRESS5 RTL8019_REG_06 +#define RTL8019_MULTIADDRESS0 RTL8019_REG_08 +#define RTL8019_MULTIADDRESS1 RTL8019_REG_09 +#define RTL8019_MULTIADDRESS2 RTL8019_REG_0a +#define RTL8019_MULTIADDRESS3 RTL8019_REG_0b +#define RTL8019_MULTIADDRESS4 RTL8019_REG_0c +#define RTL8019_MULTIADDRESS5 RTL8019_REG_0d +#define RTL8019_MULTIADDRESS6 RTL8019_REG_0e +#define RTL8019_MULTIADDRESS7 RTL8019_REG_0f +#define RTL8019_DMA_DATA RTL8019_REG_10 +#define RTL8019_RESET RTL8019_REG_1f -#define RTL8019_PSTART 0x4c -#define RTL8019_PSTOP 0x80 -#define RTL8019_TPSTART 0x40 +#define RTL8019_PAGE0 0x22 +#define RTL8019_PAGE1 0x62 +#define RTL8019_PAGE0DMAWRITE 0x12 +#define RTL8019_PAGE2DMAWRITE 0x92 +#define RTL8019_REMOTEDMAWR 0x12 +#define RTL8019_REMOTEDMARD 0x0A +#define RTL8019_ABORTDMAWR 0x32 +#define RTL8019_ABORTDMARD 0x2A +#define RTL8019_PAGE0STOP 0x21 +#define RTL8019_PAGE1STOP 0x61 +#define RTL8019_TRANSMIT 0x26 +#define RTL8019_TXINPROGRESS 0x04 +#define RTL8019_SEND 0x1A +#define RTL8019_PSTART 0x4c +#define RTL8019_PSTOP 0x80 +#define RTL8019_TPSTART 0x40 #endif /*end of CONFIG_DRIVER_RTL8019*/ diff --git a/drivers/net/sk98lin/h/skdebug.h b/drivers/net/sk98lin/h/skdebug.h index cf5b5ad33..5feda92e3 100644 --- a/drivers/net/sk98lin/h/skdebug.h +++ b/drivers/net/sk98lin/h/skdebug.h @@ -73,8 +73,8 @@ #ifdef DEBUG #ifndef SK_DBG_MSG #define SK_DBG_MSG(pAC,comp,cat,arg) \ - if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \ - ((cat) & SK_DBG_CHKCAT(pAC)) ) { \ + if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \ + ((cat) & SK_DBG_CHKCAT(pAC)) ) { \ SK_DBG_PRINTF arg ; \ } #endif diff --git a/drivers/net/sk98lin/h/skdrv2nd.h b/drivers/net/sk98lin/h/skdrv2nd.h index a311827aa..a55005fc1 100644 --- a/drivers/net/sk98lin/h/skdrv2nd.h +++ b/drivers/net/sk98lin/h/skdrv2nd.h @@ -283,7 +283,7 @@ struct s_TxD { /* definition of flags in descriptor control field */ -#define RX_CTRL_OWN_BMU UINT32_C(0x80000000) +#define RX_CTRL_OWN_BMU UINT32_C(0x80000000) #define RX_CTRL_STF UINT32_C(0x40000000) #define RX_CTRL_EOF UINT32_C(0x20000000) #define RX_CTRL_EOB_IRQ UINT32_C(0x10000000) @@ -295,7 +295,7 @@ struct s_TxD { #define RX_CTRL_CHECK_CSUM UINT32_C(0x00560000) #define RX_CTRL_LEN_MASK UINT32_C(0x0000FFFF) -#define TX_CTRL_OWN_BMU UINT32_C(0x80000000) +#define TX_CTRL_OWN_BMU UINT32_C(0x80000000) #define TX_CTRL_STF UINT32_C(0x40000000) #define TX_CTRL_EOF UINT32_C(0x20000000) #define TX_CTRL_EOB_IRQ UINT32_C(0x10000000) diff --git a/drivers/net/sk98lin/h/skgedrv.h b/drivers/net/sk98lin/h/skgedrv.h index 72ba9ce19..9810b39d4 100644 --- a/drivers/net/sk98lin/h/skgedrv.h +++ b/drivers/net/sk98lin/h/skgedrv.h @@ -58,15 +58,15 @@ * Usually the events are defined by the destination module. * In case of the driver we put the definition of the events here. */ -#define SK_DRV_PORT_RESET 1 /* The port needs to be reset */ -#define SK_DRV_NET_UP 2 /* The net is operational */ -#define SK_DRV_NET_DOWN 3 /* The net is down */ -#define SK_DRV_SWITCH_SOFT 4 /* Ports switch with both links connected */ -#define SK_DRV_SWITCH_HARD 5 /* Port switch due to link failure */ -#define SK_DRV_RLMT_SEND 6 /* Send a RLMT packet */ -#define SK_DRV_ADAP_FAIL 7 /* The whole adapter fails */ -#define SK_DRV_PORT_FAIL 8 /* One port fails */ +#define SK_DRV_PORT_RESET 1 /* The port needs to be reset */ +#define SK_DRV_NET_UP 2 /* The net is operational */ +#define SK_DRV_NET_DOWN 3 /* The net is down */ +#define SK_DRV_SWITCH_SOFT 4 /* Ports switch with both links connected */ +#define SK_DRV_SWITCH_HARD 5 /* Port switch due to link failure */ +#define SK_DRV_RLMT_SEND 6 /* Send a RLMT packet */ +#define SK_DRV_ADAP_FAIL 7 /* The whole adapter fails */ +#define SK_DRV_PORT_FAIL 8 /* One port fails */ #define SK_DRV_SWITCH_INTERN 9 /* Port switch by the driver itself */ -#define SK_DRV_POWER_DOWN 10 /* Power down mode */ +#define SK_DRV_POWER_DOWN 10 /* Power down mode */ #endif /* __INC_SKGEDRV_H_ */ diff --git a/drivers/net/sk98lin/h/skgehw.h b/drivers/net/sk98lin/h/skgehw.h index 2c9842767..52dc83f8b 100644 --- a/drivers/net/sk98lin/h/skgehw.h +++ b/drivers/net/sk98lin/h/skgehw.h @@ -110,10 +110,10 @@ * * Revision 1.29 1999/01/26 08:55:48 malthoff * Bugfix: The 16 bit field relations inside the descriptor are - * endianess dependend if the descriptor reversal feature - * (PCI_REV_DESC bit in PCI_OUR_REG_2) is enabled. - * Drivers which use this feature has to set the define - * SK_USE_REV_DESC. + * endianess dependend if the descriptor reversal feature + * (PCI_REV_DESC bit in PCI_OUR_REG_2) is enabled. + * Drivers which use this feature has to set the define + * SK_USE_REV_DESC. * * Revision 1.28 1998/12/10 11:10:22 malthoff * bug fix: IS_IRQ_STAT and IS_IRQ_MST_ERR has been twisted. @@ -274,7 +274,7 @@ extern "C" { #define BIT_10S (1 << 10) #define BIT_9S (1 << 9) #define BIT_8S (1 << 8) -#define BIT_7S (1 << 7) +#define BIT_7S (1 << 7) #define BIT_6S (1 << 6) #define BIT_5S (1 << 5) #define BIT_4S (1 << 4) @@ -340,27 +340,27 @@ extern "C" { #define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */ #define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */ #define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */ -#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Ptr */ +#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Ptr */ /* Byte 35..3b: reserved */ #define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */ #define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */ #define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */ #define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */ /* Device Dependent Region */ -#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */ -#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ +#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */ +#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ /* Power Management Region */ -#define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */ -#define PCI_PM_NITEM 0x49 /* 8 bit Next Item Ptr */ -#define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */ -#define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */ +#define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */ +#define PCI_PM_NITEM 0x49 /* 8 bit Next Item Ptr */ +#define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */ +#define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */ /* Byte 0x4e: reserved */ -#define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */ +#define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */ /* VPD Region */ -#define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */ -#define PCI_VPD_NITEM 0x51 /* 8 bit Next Item Ptr */ -#define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */ -#define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */ +#define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */ +#define PCI_VPD_NITEM 0x51 /* 8 bit Next Item Ptr */ +#define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */ +#define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */ /* Byte 0x58..0xff: reserved */ /* @@ -530,7 +530,7 @@ extern "C" { #define PCI_PM_STATE_D0 0 /* D0: Operational (default) */ #define PCI_PM_STATE_D1 1 /* D1: (YUKON only) */ #define PCI_PM_STATE_D2 2 /* D2: (YUKON only) */ -#define PCI_PM_STATE_D3 3 /* D3: HOT, Power Down and Reset */ +#define PCI_PM_STATE_D3 3 /* D3: HOT, Power Down and Reset */ /* VPD Region */ /* PCI_VPD_ADR_REG 16 bit VPD Address Register */ @@ -602,7 +602,7 @@ extern "C" { #define B2_CONN_TYP 0x0118 /* 8 bit Connector type */ #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */ #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */ -#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ +#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ /* Eprom registers are currently of no use */ #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */ #define B2_E_1 0x011d /* 8 bit EPROM Byte 1 (PHY type) */ @@ -623,7 +623,7 @@ extern "C" { #define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */ #define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */ #define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */ -#define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */ +#define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */ #define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */ /* 0x0154 - 0x0157: reserved */ #define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */ @@ -805,7 +805,7 @@ extern "C" { * use MR_ADDR() to access */ #define RX_MFF_EA 0x0c00 /* 32 bit Receive MAC FIFO End Address */ -#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer */ +#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer */ /* 0x0c08 - 0x0c0b: reserved */ #define RX_MFF_RP 0x0c0c /* 32 bit Receive MAC FIFO Read Pointer */ #define RX_MFF_PC 0x0c10 /* 32 bit Receive MAC FIFO Packet Cnt */ @@ -837,13 +837,13 @@ extern "C" { #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ /* 0x0c54 - 0x0c5f: reserved */ -#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ +#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ /* 0x0c64 - 0x0c67: reserved */ -#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ +#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ /* 0x0c6c - 0x0c6f: reserved */ -#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */ +#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */ /* 0x0c74 - 0x0c77: reserved */ -#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */ +#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */ /* 0x0c7c - 0x0c7f: reserved */ /* @@ -860,7 +860,7 @@ extern "C" { * use MR_ADDR() to access */ #define TX_MFF_EA 0x0d00 /* 32 bit Transmit MAC FIFO End Address */ -#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */ +#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */ #define TX_MFF_WSP 0x0d08 /* 32 bit Transmit MAC FIFO WR Shadow Ptr */ #define TX_MFF_RP 0x0d0c /* 32 bit Transmit MAC FIFO RD Pointer */ #define TX_MFF_PC 0x0d10 /* 32 bit Transmit MAC FIFO Packet Cnt */ @@ -883,13 +883,13 @@ extern "C" { #define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */ /* 0x0d4c - 0x0d5f: reserved */ -#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ -#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Ptr. */ -#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ +#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ +#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Ptr. */ +#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ /* 0x0d6c - 0x0d6f: reserved */ -#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */ -#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */ -#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */ +#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */ +#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */ +#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */ /* 0x0d7c - 0x0d7f: reserved */ /* @@ -1039,8 +1039,8 @@ extern "C" { /* B0_ISRC 32 bit Interrupt Source Register */ /* B0_IMSK 32 bit Interrupt Mask Register */ /* B0_SP_ISRC 32 bit Special Interrupt Source Reg */ -/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ -#define IS_ALL_MSK 0xbfffffffL /* All Interrupt bits */ +/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ +#define IS_ALL_MSK 0xbfffffffL /* All Interrupt bits */ #define IS_HW_ERR BIT_31 /* Interrupt HW Error */ /* Bit 30: reserved */ #define IS_PA_TO_RX1 BIT_29 /* Packet Arb Timeout Rx1 */ @@ -1085,7 +1085,7 @@ extern "C" { /* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */ /* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */ /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ -#define IS_ERR_MSK 0x00000fffL /* All Error bits */ +#define IS_ERR_MSK 0x00000fffL /* All Error bits */ /* Bit 31..14: reserved */ #define IS_IRQ_TIST_OV BIT_13 /* Time Stamp Timer Overflow (YUKON only) */ #define IS_IRQ_SENSOR BIT_12 /* IRQ from Sensor (YUKON only) */ @@ -1112,7 +1112,7 @@ extern "C" { #define CFG_DIS_M2_CLK BIT_1S /* Disable Clock for 2nd MAC */ #define CFG_SNG_MAC BIT_0S /* MAC Config: 0=2 MACs / 1=1 MAC*/ -/* B2_CHIP_ID 8 bit Chip Identification Number */ +/* B2_CHIP_ID 8 bit Chip Identification Number */ #define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ #define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */ @@ -1157,7 +1157,7 @@ extern "C" { #define DPT_START BIT_1S /* Start Descriptor Poll Timer */ #define DPT_STOP BIT_0S /* Stop Descriptor Poll Timer */ -/* B2_E_3 8 bit lower 4 bits used for HW self test result */ +/* B2_E_3 8 bit lower 4 bits used for HW self test result */ #define B2_E3_RES_MASK 0x0f /* B2_TST_CTRL1 8 bit Test Control Register 1 */ @@ -1210,7 +1210,7 @@ extern "C" { #define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */ #define I2C_DEV_SIZE (7L<<1) /* Bit 3.. 1: I2C Device Size */ #define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smal. */ -#define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */ +#define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */ #define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */ #define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */ #define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */ @@ -1417,7 +1417,7 @@ extern "C" { #define F_WM_REACHED BIT_25 /* Watermark reached */ /* reserved */ #define F_FIFO_LEVEL (0x1fL<<16) /* Bit 23..16: # of Qwords in FIFO */ - /* Bit 15..11: reserved */ + /* Bit 15..11: reserved */ #define F_WATER_MARK 0x0007ffL /* Bit 10.. 0: Watermark */ /* Q_T1 32 bit Test Register 1 */ @@ -1501,12 +1501,12 @@ extern "C" { /* Receive and Transmit MAC FIFO Registers (GENESIS only) */ /* RX_MFF_EA 32 bit Receive MAC FIFO End Address */ -/* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */ +/* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */ /* RX_MFF_RP 32 bit Receive MAC FIFO Read Pointer */ /* RX_MFF_PC 32 bit Receive MAC FIFO Packet Counter */ /* RX_MFF_LEV 32 bit Receive MAC FIFO Level */ /* TX_MFF_EA 32 bit Transmit MAC FIFO End Address */ -/* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer */ +/* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer */ /* TX_MFF_WSP 32 bit Transmit MAC FIFO WR Shadow Pointer */ /* TX_MFF_RP 32 bit Transmit MAC FIFO Read Pointer */ /* TX_MFF_PC 32 bit Transmit MAC FIFO Packet Cnt */ @@ -1553,8 +1553,8 @@ extern "C" { #define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH) -/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */ -/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */ +/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */ +/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */ /* Bit 7: reserved */ #define MFF_WSP_T_ON BIT_6S /* Tx: Write Shadow Ptr TestOn */ #define MFF_WSP_T_OFF BIT_5S /* Tx: Write Shadow Ptr TstOff */ @@ -1564,8 +1564,8 @@ extern "C" { #define MFF_PC_T_OFF BIT_1S /* Packet Counter Test Off */ #define MFF_PC_INC BIT_0S /* Packet Counter Increment */ -/* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */ -/* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */ +/* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */ +/* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */ /* Bit 7: reserved */ #define MFF_WP_T_ON BIT_6S /* Write Pointer Test On */ #define MFF_WP_T_OFF BIT_5S /* Write Pointer Test Off */ @@ -1593,7 +1593,7 @@ extern "C" { #define LED_START BIT_2S /* Start Timer */ #define LED_STOP BIT_1S /* Stop Timer */ #define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED on */ -#define LED_CLR_IRQ BIT_0S /* Lnk: Clear Link IRQ */ +#define LED_CLR_IRQ BIT_0S /* Lnk: Clear Link IRQ */ /* RX_LED_TST 8 bit Receive LED Cnt Test Register */ /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */ @@ -1603,7 +1603,7 @@ extern "C" { #define LED_T_OFF BIT_1S /* LED Counter Test mode Off */ #define LED_T_STEP BIT_0S /* LED Counter Step */ -/* LNK_LED_REG 8 bit Link LED Register */ +/* LNK_LED_REG 8 bit Link LED Register */ /* Bit 7.. 6: reserved */ #define LED_BLK_ON BIT_5S /* Link LED Blinking On */ #define LED_BLK_OFF BIT_4S /* Link LED Blinking Off */ @@ -1616,18 +1616,18 @@ extern "C" { /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */ /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */ -/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */ -/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */ -/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */ -/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */ +/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */ +/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */ +/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */ +/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */ /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */ /* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ -/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */ -/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Ptr. */ -/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */ -/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */ -/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */ -/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */ +/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */ +/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Ptr. */ +/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */ +/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */ +/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */ +/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */ /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ /* Bits 31..15: reserved */ @@ -2211,11 +2211,11 @@ typedef struct s_HwRxd { * PHY_WRITE() write a 16 bit value to the PHY * * para: - * IoC I/O context needed for SK I/O macros - * pPort Pointer to port struct for PhyAddr - * Mac XMAC to access values: MAC_1 or MAC_2 - * PhyReg PHY Register to read or write - * (p)Val Value or pointer to the value which should be read or + * IoC I/O context needed for SK I/O macros + * pPort Pointer to port struct for PhyAddr + * Mac XMAC to access values: MAC_1 or MAC_2 + * PhyReg PHY Register to read or write + * (p)Val Value or pointer to the value which should be read or * written. * * usage: PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value); @@ -2224,26 +2224,26 @@ typedef struct s_HwRxd { */ #ifndef DEBUG #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \ - SK_U16 Mmu; \ + SK_U16 Mmu; \ \ XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \ XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ if ((pPort)->PhyType != SK_PHY_XMAC) { \ - do { \ + do { \ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ } while ((Mmu & XM_MMU_PHY_RDY) == 0); \ XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ - } \ + } \ } #else #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \ - SK_U16 Mmu; \ + SK_U16 Mmu; \ int __i = 0; \ \ XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \ XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ if ((pPort)->PhyType != SK_PHY_XMAC) { \ - do { \ + do { \ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ __i++; \ if (__i > 100000) { \ @@ -2254,7 +2254,7 @@ typedef struct s_HwRxd { } \ } while ((Mmu & XM_MMU_PHY_RDY) == 0); \ XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \ - } \ + } \ } #endif /* DEBUG */ @@ -2262,17 +2262,17 @@ typedef struct s_HwRxd { SK_U16 Mmu; \ \ if ((pPort)->PhyType != SK_PHY_XMAC) { \ - do { \ + do { \ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \ - } \ + } \ XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \ XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val)); \ if ((pPort)->PhyType != SK_PHY_XMAC) { \ - do { \ + do { \ XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \ } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \ - } \ + } \ } /* diff --git a/drivers/net/sk98lin/h/skgei2c.h b/drivers/net/sk98lin/h/skgei2c.h index e639f733c..78c25f863 100644 --- a/drivers/net/sk98lin/h/skgei2c.h +++ b/drivers/net/sk98lin/h/skgei2c.h @@ -186,7 +186,7 @@ * To watch the statemachine (JS) use the timer in two ways instead of one as hitherto */ #define SK_TIMER_WATCH_STATEMACHINE 0 /* Watch the statemachine to finish in a specific time */ -#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */ +#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */ /* @@ -200,7 +200,7 @@ #define SK_SEN_TEMP_LOW_ERR 0 /* Temperature Low Err Threshold */ /* VCC which should be 5 V */ -#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */ +#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */ #define SK_SEN_PCI_5V_HIGH_WARN 5346 /* Voltage PCI High Warn Threshold */ #define SK_SEN_PCI_5V_LOW_WARN 4664 /* Voltage PCI Low Warn Threshold */ #define SK_SEN_PCI_5V_LOW_ERR 4422 /* Voltage PCI Low Err Threshold */ @@ -270,10 +270,10 @@ /* * ASIC Core 1V5 voltage (YUKON only) */ -#define SK_SEN_CORE_1V5_HIGH_ERR 1650 /* Voltage ASIC Core High Err Threshold */ +#define SK_SEN_CORE_1V5_HIGH_ERR 1650 /* Voltage ASIC Core High Err Threshold */ #define SK_SEN_CORE_1V5_HIGH_WARN 1575 /* Voltage ASIC Core High Warn Threshold */ #define SK_SEN_CORE_1V5_LOW_WARN 1425 /* Voltage ASIC Core Low Warn Threshold */ -#define SK_SEN_CORE_1V5_LOW_ERR 1350 /* Voltage ASIC Core Low Err Threshold */ +#define SK_SEN_CORE_1V5_LOW_ERR 1350 /* Voltage ASIC Core Low Err Threshold */ /* * FAN 1 speed @@ -285,7 +285,7 @@ */ #define SK_SEN_FAN_HIGH_ERR 20000 /* FAN Speed High Err Threshold */ #define SK_SEN_FAN_HIGH_WARN 20000 /* FAN Speed High Warn Threshold */ -#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */ +#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */ #define SK_SEN_FAN_LOW_ERR 4550 /* FAN Speed Low Err Threshold */ /* diff --git a/drivers/net/sk98lin/h/skgeinit.h b/drivers/net/sk98lin/h/skgeinit.h index cdddef92b..ef101d79e 100644 --- a/drivers/net/sk98lin/h/skgeinit.h +++ b/drivers/net/sk98lin/h/skgeinit.h @@ -486,7 +486,7 @@ extern "C" { /* Link Speed Current State */ #define SK_LSPEED_STAT_UNKNOWN 1 #define SK_LSPEED_STAT_10MBPS 2 -#define SK_LSPEED_STAT_100MBPS 3 +#define SK_LSPEED_STAT_100MBPS 3 #define SK_LSPEED_STAT_1000MBPS 4 #define SK_LSPEED_STAT_INDETERMINATED 5 diff --git a/drivers/net/sk98lin/h/skgepnm2.h b/drivers/net/sk98lin/h/skgepnm2.h index 5c44f4771..e812f28b9 100644 --- a/drivers/net/sk98lin/h/skgepnm2.h +++ b/drivers/net/sk98lin/h/skgepnm2.h @@ -248,7 +248,7 @@ typedef struct s_OidTabEntry { enum SK_MACSTATS { SK_PNMI_HTX = 0, SK_PNMI_HTX_OCTET, - SK_PNMI_HTX_OCTETHIGH = SK_PNMI_HTX_OCTET, + SK_PNMI_HTX_OCTETHIGH = SK_PNMI_HTX_OCTET, SK_PNMI_HTX_OCTETLOW, SK_PNMI_HTX_BROADCAST, SK_PNMI_HTX_MULTICAST, diff --git a/drivers/net/sk98lin/h/skgepnmi.h b/drivers/net/sk98lin/h/skgepnmi.h index 7532313ba..c93e99cb2 100644 --- a/drivers/net/sk98lin/h/skgepnmi.h +++ b/drivers/net/sk98lin/h/skgepnmi.h @@ -67,7 +67,7 @@ * Changed macro PHYS2INST. Added pAC to Interface * * Revision 1.47 2001/02/07 08:28:23 mkunz - * - Added Oids: OID_SKGE_DIAG_ACTION + * - Added Oids: OID_SKGE_DIAG_ACTION * OID_SKGE_DIAG_RESULT * OID_SKGE_MULTICAST_LIST * OID_SKGE_CURRENT_PACKET_FILTER @@ -253,22 +253,22 @@ /* * Event definitions */ -#define SK_PNMI_EVT_SIRQ_OVERFLOW 1 /* Counter overflow */ -#define SK_PNMI_EVT_SEN_WAR_LOW 2 /* Lower war thres exceeded */ -#define SK_PNMI_EVT_SEN_WAR_UPP 3 /* Upper war thres exceeded */ -#define SK_PNMI_EVT_SEN_ERR_LOW 4 /* Lower err thres exceeded */ -#define SK_PNMI_EVT_SEN_ERR_UPP 5 /* Upper err thres exceeded */ -#define SK_PNMI_EVT_CHG_EST_TIMER 6 /* Timer event for RLMT Chg */ +#define SK_PNMI_EVT_SIRQ_OVERFLOW 1 /* Counter overflow */ +#define SK_PNMI_EVT_SEN_WAR_LOW 2 /* Lower war thres exceeded */ +#define SK_PNMI_EVT_SEN_WAR_UPP 3 /* Upper war thres exceeded */ +#define SK_PNMI_EVT_SEN_ERR_LOW 4 /* Lower err thres exceeded */ +#define SK_PNMI_EVT_SEN_ERR_UPP 5 /* Upper err thres exceeded */ +#define SK_PNMI_EVT_CHG_EST_TIMER 6 /* Timer event for RLMT Chg */ #define SK_PNMI_EVT_UTILIZATION_TIMER 7 /* Timer event for Utiliza. */ -#define SK_PNMI_EVT_CLEAR_COUNTER 8 /* Clear statistic counters */ -#define SK_PNMI_EVT_XMAC_RESET 9 /* XMAC will be reset */ +#define SK_PNMI_EVT_CLEAR_COUNTER 8 /* Clear statistic counters */ +#define SK_PNMI_EVT_XMAC_RESET 9 /* XMAC will be reset */ -#define SK_PNMI_EVT_RLMT_PORT_UP 10 /* Port came logically up */ -#define SK_PNMI_EVT_RLMT_PORT_DOWN 11 /* Port went logically down */ +#define SK_PNMI_EVT_RLMT_PORT_UP 10 /* Port came logically up */ +#define SK_PNMI_EVT_RLMT_PORT_DOWN 11 /* Port went logically down */ #define SK_PNMI_EVT_RLMT_SEGMENTATION 13 /* Two SP root bridges found */ #define SK_PNMI_EVT_RLMT_ACTIVE_DOWN 14 /* Port went logically down */ -#define SK_PNMI_EVT_RLMT_ACTIVE_UP 15 /* Port came logically up */ -#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* 1. Parameter is number of nets +#define SK_PNMI_EVT_RLMT_ACTIVE_UP 15 /* Port came logically up */ +#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* 1. Parameter is number of nets 1 = single net; 2 = dual net */ #define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */ @@ -276,14 +276,14 @@ /* * Return values */ -#define SK_PNMI_ERR_OK 0 -#define SK_PNMI_ERR_GENERAL 1 +#define SK_PNMI_ERR_OK 0 +#define SK_PNMI_ERR_GENERAL 1 #define SK_PNMI_ERR_TOO_SHORT 2 #define SK_PNMI_ERR_BAD_VALUE 3 #define SK_PNMI_ERR_READ_ONLY 4 #define SK_PNMI_ERR_UNKNOWN_OID 5 #define SK_PNMI_ERR_UNKNOWN_INST 6 -#define SK_PNMI_ERR_UNKNOWN_NET 7 +#define SK_PNMI_ERR_UNKNOWN_NET 7 /* @@ -329,11 +329,11 @@ */ #ifndef _NDIS_ /* Check, whether NDIS already included OIDs */ -#define OID_GEN_XMIT_OK 0x00020101 -#define OID_GEN_RCV_OK 0x00020102 -#define OID_GEN_XMIT_ERROR 0x00020103 -#define OID_GEN_RCV_ERROR 0x00020104 -#define OID_GEN_RCV_NO_BUFFER 0x00020105 +#define OID_GEN_XMIT_OK 0x00020101 +#define OID_GEN_RCV_OK 0x00020102 +#define OID_GEN_XMIT_ERROR 0x00020103 +#define OID_GEN_RCV_ERROR 0x00020104 +#define OID_GEN_RCV_NO_BUFFER 0x00020105 /* #define OID_GEN_DIRECTED_BYTES_XMIT 0x00020201 */ #define OID_GEN_DIRECTED_FRAMES_XMIT 0x00020202 @@ -342,27 +342,27 @@ /* #define OID_GEN_BROADCAST_BYTES_XMIT 0x00020205 */ #define OID_GEN_BROADCAST_FRAMES_XMIT 0x00020206 /* #define OID_GEN_DIRECTED_BYTES_RCV 0x00020207 */ -#define OID_GEN_DIRECTED_FRAMES_RCV 0x00020208 +#define OID_GEN_DIRECTED_FRAMES_RCV 0x00020208 /* #define OID_GEN_MULTICAST_BYTES_RCV 0x00020209 */ #define OID_GEN_MULTICAST_FRAMES_RCV 0x0002020A /* #define OID_GEN_BROADCAST_BYTES_RCV 0x0002020B */ #define OID_GEN_BROADCAST_FRAMES_RCV 0x0002020C -#define OID_GEN_RCV_CRC_ERROR 0x0002020D +#define OID_GEN_RCV_CRC_ERROR 0x0002020D #define OID_GEN_TRANSMIT_QUEUE_LENGTH 0x0002020E -#define OID_802_3_PERMANENT_ADDRESS 0x01010101 -#define OID_802_3_CURRENT_ADDRESS 0x01010102 -/* #define OID_802_3_MULTICAST_LIST 0x01010103 */ +#define OID_802_3_PERMANENT_ADDRESS 0x01010101 +#define OID_802_3_CURRENT_ADDRESS 0x01010102 +/* #define OID_802_3_MULTICAST_LIST 0x01010103 */ /* #define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104 */ -/* #define OID_802_3_MAC_OPTIONS 0x01010105 */ +/* #define OID_802_3_MAC_OPTIONS 0x01010105 */ #define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101 #define OID_802_3_XMIT_ONE_COLLISION 0x01020102 #define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103 -#define OID_802_3_XMIT_DEFERRED 0x01020201 +#define OID_802_3_XMIT_DEFERRED 0x01020201 #define OID_802_3_XMIT_MAX_COLLISIONS 0x01020202 -#define OID_802_3_RCV_OVERRUN 0x01020203 -#define OID_802_3_XMIT_UNDERRUN 0x01020204 +#define OID_802_3_RCV_OVERRUN 0x01020203 +#define OID_802_3_XMIT_UNDERRUN 0x01020204 #define OID_802_3_XMIT_TIMES_CRS_LOST 0x01020206 #define OID_802_3_XMIT_LATE_COLLISIONS 0x01020207 @@ -370,193 +370,193 @@ * PnP and PM OIDs */ #ifdef SK_POWER_MGMT -#define OID_PNP_CAPABILITIES 0xFD010100 -#define OID_PNP_SET_POWER 0xFD010101 -#define OID_PNP_QUERY_POWER 0xFD010102 -#define OID_PNP_ADD_WAKE_UP_PATTERN 0xFD010103 +#define OID_PNP_CAPABILITIES 0xFD010100 +#define OID_PNP_SET_POWER 0xFD010101 +#define OID_PNP_QUERY_POWER 0xFD010102 +#define OID_PNP_ADD_WAKE_UP_PATTERN 0xFD010103 #define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xFD010104 -#define OID_PNP_ENABLE_WAKE_UP 0xFD010106 +#define OID_PNP_ENABLE_WAKE_UP 0xFD010106 #endif /* SK_POWER_MGMT */ #endif /* _NDIS_ */ -#define OID_SKGE_MDB_VERSION 0xFF010100 -#define OID_SKGE_SUPPORTED_LIST 0xFF010101 -#define OID_SKGE_VPD_FREE_BYTES 0xFF010102 -#define OID_SKGE_VPD_ENTRIES_LIST 0xFF010103 -#define OID_SKGE_VPD_ENTRIES_NUMBER 0xFF010104 -#define OID_SKGE_VPD_KEY 0xFF010105 -#define OID_SKGE_VPD_VALUE 0xFF010106 -#define OID_SKGE_VPD_ACCESS 0xFF010107 -#define OID_SKGE_VPD_ACTION 0xFF010108 +#define OID_SKGE_MDB_VERSION 0xFF010100 +#define OID_SKGE_SUPPORTED_LIST 0xFF010101 +#define OID_SKGE_VPD_FREE_BYTES 0xFF010102 +#define OID_SKGE_VPD_ENTRIES_LIST 0xFF010103 +#define OID_SKGE_VPD_ENTRIES_NUMBER 0xFF010104 +#define OID_SKGE_VPD_KEY 0xFF010105 +#define OID_SKGE_VPD_VALUE 0xFF010106 +#define OID_SKGE_VPD_ACCESS 0xFF010107 +#define OID_SKGE_VPD_ACTION 0xFF010108 -#define OID_SKGE_PORT_NUMBER 0xFF010110 -#define OID_SKGE_DEVICE_TYPE 0xFF010111 -#define OID_SKGE_DRIVER_DESCR 0xFF010112 -#define OID_SKGE_DRIVER_VERSION 0xFF010113 -#define OID_SKGE_HW_DESCR 0xFF010114 -#define OID_SKGE_HW_VERSION 0xFF010115 -#define OID_SKGE_CHIPSET 0xFF010116 -#define OID_SKGE_ACTION 0xFF010117 -#define OID_SKGE_RESULT 0xFF010118 -#define OID_SKGE_BUS_TYPE 0xFF010119 -#define OID_SKGE_BUS_SPEED 0xFF01011A -#define OID_SKGE_BUS_WIDTH 0xFF01011B +#define OID_SKGE_PORT_NUMBER 0xFF010110 +#define OID_SKGE_DEVICE_TYPE 0xFF010111 +#define OID_SKGE_DRIVER_DESCR 0xFF010112 +#define OID_SKGE_DRIVER_VERSION 0xFF010113 +#define OID_SKGE_HW_DESCR 0xFF010114 +#define OID_SKGE_HW_VERSION 0xFF010115 +#define OID_SKGE_CHIPSET 0xFF010116 +#define OID_SKGE_ACTION 0xFF010117 +#define OID_SKGE_RESULT 0xFF010118 +#define OID_SKGE_BUS_TYPE 0xFF010119 +#define OID_SKGE_BUS_SPEED 0xFF01011A +#define OID_SKGE_BUS_WIDTH 0xFF01011B /* 0xFF01011C unused */ -#define OID_SKGE_DIAG_ACTION 0xFF01011D -#define OID_SKGE_DIAG_RESULT 0xFF01011E -#define OID_SKGE_MTU 0xFF01011F -#define OID_SKGE_PHYS_CUR_ADDR 0xFF010120 -#define OID_SKGE_PHYS_FAC_ADDR 0xFF010121 -#define OID_SKGE_PMD 0xFF010122 -#define OID_SKGE_CONNECTOR 0xFF010123 -#define OID_SKGE_LINK_CAP 0xFF010124 -#define OID_SKGE_LINK_MODE 0xFF010125 -#define OID_SKGE_LINK_MODE_STATUS 0xFF010126 -#define OID_SKGE_LINK_STATUS 0xFF010127 -#define OID_SKGE_FLOWCTRL_CAP 0xFF010128 -#define OID_SKGE_FLOWCTRL_MODE 0xFF010129 -#define OID_SKGE_FLOWCTRL_STATUS 0xFF01012A -#define OID_SKGE_PHY_OPERATION_CAP 0xFF01012B -#define OID_SKGE_PHY_OPERATION_MODE 0xFF01012C +#define OID_SKGE_DIAG_ACTION 0xFF01011D +#define OID_SKGE_DIAG_RESULT 0xFF01011E +#define OID_SKGE_MTU 0xFF01011F +#define OID_SKGE_PHYS_CUR_ADDR 0xFF010120 +#define OID_SKGE_PHYS_FAC_ADDR 0xFF010121 +#define OID_SKGE_PMD 0xFF010122 +#define OID_SKGE_CONNECTOR 0xFF010123 +#define OID_SKGE_LINK_CAP 0xFF010124 +#define OID_SKGE_LINK_MODE 0xFF010125 +#define OID_SKGE_LINK_MODE_STATUS 0xFF010126 +#define OID_SKGE_LINK_STATUS 0xFF010127 +#define OID_SKGE_FLOWCTRL_CAP 0xFF010128 +#define OID_SKGE_FLOWCTRL_MODE 0xFF010129 +#define OID_SKGE_FLOWCTRL_STATUS 0xFF01012A +#define OID_SKGE_PHY_OPERATION_CAP 0xFF01012B +#define OID_SKGE_PHY_OPERATION_MODE 0xFF01012C #define OID_SKGE_PHY_OPERATION_STATUS 0xFF01012D -#define OID_SKGE_MULTICAST_LIST 0xFF01012E +#define OID_SKGE_MULTICAST_LIST 0xFF01012E #define OID_SKGE_CURRENT_PACKET_FILTER 0xFF01012F -#define OID_SKGE_TRAP 0xFF010130 -#define OID_SKGE_TRAP_NUMBER 0xFF010131 +#define OID_SKGE_TRAP 0xFF010130 +#define OID_SKGE_TRAP_NUMBER 0xFF010131 -#define OID_SKGE_RLMT_MODE 0xFF010140 -#define OID_SKGE_RLMT_PORT_NUMBER 0xFF010141 -#define OID_SKGE_RLMT_PORT_ACTIVE 0xFF010142 +#define OID_SKGE_RLMT_MODE 0xFF010140 +#define OID_SKGE_RLMT_PORT_NUMBER 0xFF010141 +#define OID_SKGE_RLMT_PORT_ACTIVE 0xFF010142 #define OID_SKGE_RLMT_PORT_PREFERRED 0xFF010143 #define OID_SKGE_INTERMEDIATE_SUPPORT 0xFF010160 -#define OID_SKGE_SPEED_CAP 0xFF010170 -#define OID_SKGE_SPEED_MODE 0xFF010171 -#define OID_SKGE_SPEED_STATUS 0xFF010172 +#define OID_SKGE_SPEED_CAP 0xFF010170 +#define OID_SKGE_SPEED_MODE 0xFF010171 +#define OID_SKGE_SPEED_STATUS 0xFF010172 -#define OID_SKGE_SENSOR_NUMBER 0xFF020100 -#define OID_SKGE_SENSOR_INDEX 0xFF020101 -#define OID_SKGE_SENSOR_DESCR 0xFF020102 -#define OID_SKGE_SENSOR_TYPE 0xFF020103 -#define OID_SKGE_SENSOR_VALUE 0xFF020104 +#define OID_SKGE_SENSOR_NUMBER 0xFF020100 +#define OID_SKGE_SENSOR_INDEX 0xFF020101 +#define OID_SKGE_SENSOR_DESCR 0xFF020102 +#define OID_SKGE_SENSOR_TYPE 0xFF020103 +#define OID_SKGE_SENSOR_VALUE 0xFF020104 #define OID_SKGE_SENSOR_WAR_THRES_LOW 0xFF020105 #define OID_SKGE_SENSOR_WAR_THRES_UPP 0xFF020106 #define OID_SKGE_SENSOR_ERR_THRES_LOW 0xFF020107 #define OID_SKGE_SENSOR_ERR_THRES_UPP 0xFF020108 -#define OID_SKGE_SENSOR_STATUS 0xFF020109 -#define OID_SKGE_SENSOR_WAR_CTS 0xFF02010A -#define OID_SKGE_SENSOR_ERR_CTS 0xFF02010B -#define OID_SKGE_SENSOR_WAR_TIME 0xFF02010C -#define OID_SKGE_SENSOR_ERR_TIME 0xFF02010D +#define OID_SKGE_SENSOR_STATUS 0xFF020109 +#define OID_SKGE_SENSOR_WAR_CTS 0xFF02010A +#define OID_SKGE_SENSOR_ERR_CTS 0xFF02010B +#define OID_SKGE_SENSOR_WAR_TIME 0xFF02010C +#define OID_SKGE_SENSOR_ERR_TIME 0xFF02010D -#define OID_SKGE_CHKSM_NUMBER 0xFF020110 -#define OID_SKGE_CHKSM_RX_OK_CTS 0xFF020111 +#define OID_SKGE_CHKSM_NUMBER 0xFF020110 +#define OID_SKGE_CHKSM_RX_OK_CTS 0xFF020111 #define OID_SKGE_CHKSM_RX_UNABLE_CTS 0xFF020112 -#define OID_SKGE_CHKSM_RX_ERR_CTS 0xFF020113 -#define OID_SKGE_CHKSM_TX_OK_CTS 0xFF020114 +#define OID_SKGE_CHKSM_RX_ERR_CTS 0xFF020113 +#define OID_SKGE_CHKSM_TX_OK_CTS 0xFF020114 #define OID_SKGE_CHKSM_TX_UNABLE_CTS 0xFF020115 -#define OID_SKGE_STAT_TX 0xFF020120 -#define OID_SKGE_STAT_TX_OCTETS 0xFF020121 -#define OID_SKGE_STAT_TX_BROADCAST 0xFF020122 -#define OID_SKGE_STAT_TX_MULTICAST 0xFF020123 -#define OID_SKGE_STAT_TX_UNICAST 0xFF020124 -#define OID_SKGE_STAT_TX_LONGFRAMES 0xFF020125 -#define OID_SKGE_STAT_TX_BURST 0xFF020126 -#define OID_SKGE_STAT_TX_PFLOWC 0xFF020127 -#define OID_SKGE_STAT_TX_FLOWC 0xFF020128 -#define OID_SKGE_STAT_TX_SINGLE_COL 0xFF020129 -#define OID_SKGE_STAT_TX_MULTI_COL 0xFF02012A -#define OID_SKGE_STAT_TX_EXCESS_COL 0xFF02012B -#define OID_SKGE_STAT_TX_LATE_COL 0xFF02012C -#define OID_SKGE_STAT_TX_DEFFERAL 0xFF02012D -#define OID_SKGE_STAT_TX_EXCESS_DEF 0xFF02012E -#define OID_SKGE_STAT_TX_UNDERRUN 0xFF02012F -#define OID_SKGE_STAT_TX_CARRIER 0xFF020130 -/* #define OID_SKGE_STAT_TX_UTIL 0xFF020131 */ -#define OID_SKGE_STAT_TX_64 0xFF020132 -#define OID_SKGE_STAT_TX_127 0xFF020133 -#define OID_SKGE_STAT_TX_255 0xFF020134 -#define OID_SKGE_STAT_TX_511 0xFF020135 -#define OID_SKGE_STAT_TX_1023 0xFF020136 -#define OID_SKGE_STAT_TX_MAX 0xFF020137 -#define OID_SKGE_STAT_TX_SYNC 0xFF020138 +#define OID_SKGE_STAT_TX 0xFF020120 +#define OID_SKGE_STAT_TX_OCTETS 0xFF020121 +#define OID_SKGE_STAT_TX_BROADCAST 0xFF020122 +#define OID_SKGE_STAT_TX_MULTICAST 0xFF020123 +#define OID_SKGE_STAT_TX_UNICAST 0xFF020124 +#define OID_SKGE_STAT_TX_LONGFRAMES 0xFF020125 +#define OID_SKGE_STAT_TX_BURST 0xFF020126 +#define OID_SKGE_STAT_TX_PFLOWC 0xFF020127 +#define OID_SKGE_STAT_TX_FLOWC 0xFF020128 +#define OID_SKGE_STAT_TX_SINGLE_COL 0xFF020129 +#define OID_SKGE_STAT_TX_MULTI_COL 0xFF02012A +#define OID_SKGE_STAT_TX_EXCESS_COL 0xFF02012B +#define OID_SKGE_STAT_TX_LATE_COL 0xFF02012C +#define OID_SKGE_STAT_TX_DEFFERAL 0xFF02012D +#define OID_SKGE_STAT_TX_EXCESS_DEF 0xFF02012E +#define OID_SKGE_STAT_TX_UNDERRUN 0xFF02012F +#define OID_SKGE_STAT_TX_CARRIER 0xFF020130 +/* #define OID_SKGE_STAT_TX_UTIL 0xFF020131 */ +#define OID_SKGE_STAT_TX_64 0xFF020132 +#define OID_SKGE_STAT_TX_127 0xFF020133 +#define OID_SKGE_STAT_TX_255 0xFF020134 +#define OID_SKGE_STAT_TX_511 0xFF020135 +#define OID_SKGE_STAT_TX_1023 0xFF020136 +#define OID_SKGE_STAT_TX_MAX 0xFF020137 +#define OID_SKGE_STAT_TX_SYNC 0xFF020138 #define OID_SKGE_STAT_TX_SYNC_OCTETS 0xFF020139 -#define OID_SKGE_STAT_RX 0xFF02013A -#define OID_SKGE_STAT_RX_OCTETS 0xFF02013B -#define OID_SKGE_STAT_RX_BROADCAST 0xFF02013C -#define OID_SKGE_STAT_RX_MULTICAST 0xFF02013D -#define OID_SKGE_STAT_RX_UNICAST 0xFF02013E -#define OID_SKGE_STAT_RX_PFLOWC 0xFF02013F -#define OID_SKGE_STAT_RX_FLOWC 0xFF020140 -#define OID_SKGE_STAT_RX_PFLOWC_ERR 0xFF020141 +#define OID_SKGE_STAT_RX 0xFF02013A +#define OID_SKGE_STAT_RX_OCTETS 0xFF02013B +#define OID_SKGE_STAT_RX_BROADCAST 0xFF02013C +#define OID_SKGE_STAT_RX_MULTICAST 0xFF02013D +#define OID_SKGE_STAT_RX_UNICAST 0xFF02013E +#define OID_SKGE_STAT_RX_PFLOWC 0xFF02013F +#define OID_SKGE_STAT_RX_FLOWC 0xFF020140 +#define OID_SKGE_STAT_RX_PFLOWC_ERR 0xFF020141 #define OID_SKGE_STAT_RX_FLOWC_UNKWN 0xFF020142 -#define OID_SKGE_STAT_RX_BURST 0xFF020143 -#define OID_SKGE_STAT_RX_MISSED 0xFF020144 -#define OID_SKGE_STAT_RX_FRAMING 0xFF020145 -#define OID_SKGE_STAT_RX_OVERFLOW 0xFF020146 -#define OID_SKGE_STAT_RX_JABBER 0xFF020147 -#define OID_SKGE_STAT_RX_CARRIER 0xFF020148 -#define OID_SKGE_STAT_RX_IR_LENGTH 0xFF020149 -#define OID_SKGE_STAT_RX_SYMBOL 0xFF02014A -#define OID_SKGE_STAT_RX_SHORTS 0xFF02014B -#define OID_SKGE_STAT_RX_RUNT 0xFF02014C -#define OID_SKGE_STAT_RX_CEXT 0xFF02014D -#define OID_SKGE_STAT_RX_TOO_LONG 0xFF02014E -#define OID_SKGE_STAT_RX_FCS 0xFF02014F -/* #define OID_SKGE_STAT_RX_UTIL 0xFF020150 */ -#define OID_SKGE_STAT_RX_64 0xFF020151 -#define OID_SKGE_STAT_RX_127 0xFF020152 -#define OID_SKGE_STAT_RX_255 0xFF020153 -#define OID_SKGE_STAT_RX_511 0xFF020154 -#define OID_SKGE_STAT_RX_1023 0xFF020155 -#define OID_SKGE_STAT_RX_MAX 0xFF020156 -#define OID_SKGE_STAT_RX_LONGFRAMES 0xFF020157 +#define OID_SKGE_STAT_RX_BURST 0xFF020143 +#define OID_SKGE_STAT_RX_MISSED 0xFF020144 +#define OID_SKGE_STAT_RX_FRAMING 0xFF020145 +#define OID_SKGE_STAT_RX_OVERFLOW 0xFF020146 +#define OID_SKGE_STAT_RX_JABBER 0xFF020147 +#define OID_SKGE_STAT_RX_CARRIER 0xFF020148 +#define OID_SKGE_STAT_RX_IR_LENGTH 0xFF020149 +#define OID_SKGE_STAT_RX_SYMBOL 0xFF02014A +#define OID_SKGE_STAT_RX_SHORTS 0xFF02014B +#define OID_SKGE_STAT_RX_RUNT 0xFF02014C +#define OID_SKGE_STAT_RX_CEXT 0xFF02014D +#define OID_SKGE_STAT_RX_TOO_LONG 0xFF02014E +#define OID_SKGE_STAT_RX_FCS 0xFF02014F +/* #define OID_SKGE_STAT_RX_UTIL 0xFF020150 */ +#define OID_SKGE_STAT_RX_64 0xFF020151 +#define OID_SKGE_STAT_RX_127 0xFF020152 +#define OID_SKGE_STAT_RX_255 0xFF020153 +#define OID_SKGE_STAT_RX_511 0xFF020154 +#define OID_SKGE_STAT_RX_1023 0xFF020155 +#define OID_SKGE_STAT_RX_MAX 0xFF020156 +#define OID_SKGE_STAT_RX_LONGFRAMES 0xFF020157 -#define OID_SKGE_RLMT_CHANGE_CTS 0xFF020160 -#define OID_SKGE_RLMT_CHANGE_TIME 0xFF020161 -#define OID_SKGE_RLMT_CHANGE_ESTIM 0xFF020162 -#define OID_SKGE_RLMT_CHANGE_THRES 0xFF020163 +#define OID_SKGE_RLMT_CHANGE_CTS 0xFF020160 +#define OID_SKGE_RLMT_CHANGE_TIME 0xFF020161 +#define OID_SKGE_RLMT_CHANGE_ESTIM 0xFF020162 +#define OID_SKGE_RLMT_CHANGE_THRES 0xFF020163 -#define OID_SKGE_RLMT_PORT_INDEX 0xFF020164 -#define OID_SKGE_RLMT_STATUS 0xFF020165 -#define OID_SKGE_RLMT_TX_HELLO_CTS 0xFF020166 -#define OID_SKGE_RLMT_RX_HELLO_CTS 0xFF020167 -#define OID_SKGE_RLMT_TX_SP_REQ_CTS 0xFF020168 -#define OID_SKGE_RLMT_RX_SP_CTS 0xFF020169 +#define OID_SKGE_RLMT_PORT_INDEX 0xFF020164 +#define OID_SKGE_RLMT_STATUS 0xFF020165 +#define OID_SKGE_RLMT_TX_HELLO_CTS 0xFF020166 +#define OID_SKGE_RLMT_RX_HELLO_CTS 0xFF020167 +#define OID_SKGE_RLMT_TX_SP_REQ_CTS 0xFF020168 +#define OID_SKGE_RLMT_RX_SP_CTS 0xFF020169 #define OID_SKGE_RLMT_MONITOR_NUMBER 0xFF010150 -#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151 -#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152 -#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153 +#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151 +#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152 +#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153 #define OID_SKGE_RLMT_MONITOR_TIMESTAMP 0xFF010154 -#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155 +#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155 -#define OID_SKGE_TX_SW_QUEUE_LEN 0xFF020170 -#define OID_SKGE_TX_SW_QUEUE_MAX 0xFF020171 -#define OID_SKGE_TX_RETRY 0xFF020172 -#define OID_SKGE_RX_INTR_CTS 0xFF020173 -#define OID_SKGE_TX_INTR_CTS 0xFF020174 -#define OID_SKGE_RX_NO_BUF_CTS 0xFF020175 -#define OID_SKGE_TX_NO_BUF_CTS 0xFF020176 -#define OID_SKGE_TX_USED_DESCR_NO 0xFF020177 -#define OID_SKGE_RX_DELIVERED_CTS 0xFF020178 +#define OID_SKGE_TX_SW_QUEUE_LEN 0xFF020170 +#define OID_SKGE_TX_SW_QUEUE_MAX 0xFF020171 +#define OID_SKGE_TX_RETRY 0xFF020172 +#define OID_SKGE_RX_INTR_CTS 0xFF020173 +#define OID_SKGE_TX_INTR_CTS 0xFF020174 +#define OID_SKGE_RX_NO_BUF_CTS 0xFF020175 +#define OID_SKGE_TX_NO_BUF_CTS 0xFF020176 +#define OID_SKGE_TX_USED_DESCR_NO 0xFF020177 +#define OID_SKGE_RX_DELIVERED_CTS 0xFF020178 #define OID_SKGE_RX_OCTETS_DELIV_CTS 0xFF020179 -#define OID_SKGE_RX_HW_ERROR_CTS 0xFF02017A -#define OID_SKGE_TX_HW_ERROR_CTS 0xFF02017B -#define OID_SKGE_IN_ERRORS_CTS 0xFF02017C -#define OID_SKGE_OUT_ERROR_CTS 0xFF02017D -#define OID_SKGE_ERR_RECOVERY_CTS 0xFF02017E -#define OID_SKGE_SYSUPTIME 0xFF02017F +#define OID_SKGE_RX_HW_ERROR_CTS 0xFF02017A +#define OID_SKGE_TX_HW_ERROR_CTS 0xFF02017B +#define OID_SKGE_IN_ERRORS_CTS 0xFF02017C +#define OID_SKGE_OUT_ERROR_CTS 0xFF02017D +#define OID_SKGE_ERR_RECOVERY_CTS 0xFF02017E +#define OID_SKGE_SYSUPTIME 0xFF02017F -#define OID_SKGE_ALL_DATA 0xFF020190 +#define OID_SKGE_ALL_DATA 0xFF020190 /* Defines for VCT. */ -#define OID_SKGE_VCT_GET 0xFF020200 -#define OID_SKGE_VCT_SET 0xFF020201 -#define OID_SKGE_VCT_STATUS 0xFF020202 +#define OID_SKGE_VCT_GET 0xFF020200 +#define OID_SKGE_VCT_SET 0xFF020201 +#define OID_SKGE_VCT_STATUS 0xFF020202 /* VCT struct to store a backup copy of VCT data after a port reset. */ @@ -578,20 +578,20 @@ typedef struct s_PnmiVct { /* VCT cable test status. */ -#define SK_PNMI_VCT_NORMAL_CABLE 0 -#define SK_PNMI_VCT_SHORT_CABLE 1 -#define SK_PNMI_VCT_OPEN_CABLE 2 -#define SK_PNMI_VCT_TEST_FAIL 3 -#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4 +#define SK_PNMI_VCT_NORMAL_CABLE 0 +#define SK_PNMI_VCT_SHORT_CABLE 1 +#define SK_PNMI_VCT_OPEN_CABLE 2 +#define SK_PNMI_VCT_TEST_FAIL 3 +#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4 -#define OID_SKGE_TRAP_SEN_WAR_LOW 500 -#define OID_SKGE_TRAP_SEN_WAR_UPP 501 -#define OID_SKGE_TRAP_SEN_ERR_LOW 502 -#define OID_SKGE_TRAP_SEN_ERR_UPP 503 +#define OID_SKGE_TRAP_SEN_WAR_LOW 500 +#define OID_SKGE_TRAP_SEN_WAR_UPP 501 +#define OID_SKGE_TRAP_SEN_ERR_LOW 502 +#define OID_SKGE_TRAP_SEN_ERR_UPP 503 #define OID_SKGE_TRAP_RLMT_CHANGE_THRES 520 #define OID_SKGE_TRAP_RLMT_CHANGE_PORT 521 #define OID_SKGE_TRAP_RLMT_PORT_DOWN 522 -#define OID_SKGE_TRAP_RLMT_PORT_UP 523 +#define OID_SKGE_TRAP_RLMT_PORT_UP 523 #define OID_SKGE_TRAP_RLMT_SEGMENTATION 524 @@ -775,7 +775,7 @@ typedef struct s_PnmiVct { /* * Structure definition for SkPnmiGetStruct and SkPnmiSetStruct */ -#define SK_PNMI_VPD_KEY_SIZE 5 +#define SK_PNMI_VPD_KEY_SIZE 5 #define SK_PNMI_VPD_BUFSIZE (VPD_SIZE) #define SK_PNMI_VPD_ENTRIES (VPD_SIZE / 4) #define SK_PNMI_VPD_DATALEN 128 /* Number of data bytes */ @@ -783,12 +783,12 @@ typedef struct s_PnmiVct { #define SK_PNMI_MULTICAST_LISTLEN 64 #define SK_PNMI_SENSOR_ENTRIES (SK_MAX_SENSORS) #define SK_PNMI_CHECKSUM_ENTRIES 3 -#define SK_PNMI_MAC_ENTRIES (SK_MAX_MACS + 1) +#define SK_PNMI_MAC_ENTRIES (SK_MAX_MACS + 1) #define SK_PNMI_MONITOR_ENTRIES 20 #define SK_PNMI_TRAP_ENTRIES 10 -#define SK_PNMI_TRAPLEN 128 -#define SK_PNMI_STRINGLEN1 80 -#define SK_PNMI_STRINGLEN2 25 +#define SK_PNMI_TRAPLEN 128 +#define SK_PNMI_STRINGLEN1 80 +#define SK_PNMI_STRINGLEN2 25 #define SK_PNMI_TRAP_QUEUE_LEN 512 typedef struct s_PnmiVpd { @@ -992,12 +992,12 @@ typedef struct s_PnmiStrucData { /* * Various definitions */ -#define SK_PNMI_MAX_PROTOS 3 +#define SK_PNMI_MAX_PROTOS 3 -#define SK_PNMI_CNT_NO 66 /* Must have the value of the enum - * SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK - * for check while init phase 1 - */ +#define SK_PNMI_CNT_NO 66 /* Must have the value of the enum + * SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK + * for check while init phase 1 + */ /* * Estimate data structure @@ -1091,7 +1091,6 @@ typedef struct s_PnmiData { SK_PNMI_VCT_TIMER VctTimeout[SK_MAX_MACS]; } SK_PNMI; - /* * Function prototypes */ diff --git a/drivers/net/sk98lin/h/skvpd.h b/drivers/net/sk98lin/h/skvpd.h index 1be34c5a9..3159e27c2 100644 --- a/drivers/net/sk98lin/h/skvpd.h +++ b/drivers/net/sk98lin/h/skvpd.h @@ -126,7 +126,7 @@ * Define READ and WRITE Constants. */ -#define VPD_DEV_ID_GENESIS 0x4300 +#define VPD_DEV_ID_GENESIS 0x4300 #define VPD_SIZE_YUKON 256 #define VPD_SIZE_GENESIS 512 @@ -223,19 +223,19 @@ typedef struct s_vpd_key { if ((pAC)->DgT.DgUseCfgCycle) \ SkPciWriteCfgDWord(pAC,Addr,Val); \ else \ - SK_OUT32(pAC,PCI_C(Addr),Val); \ + SK_OUT32(pAC,PCI_C(Addr),Val); \ } #define VPD_IN8(pAC,Ioc,Addr,pVal) { \ - if ((pAC)->DgT.DgUseCfgCycle) \ + if ((pAC)->DgT.DgUseCfgCycle) \ SkPciReadCfgByte(pAC,Addr,pVal); \ else \ - SK_IN8(pAC,PCI_C(Addr),pVal); \ + SK_IN8(pAC,PCI_C(Addr),pVal); \ } #define VPD_IN16(pAC,Ioc,Addr,pVal) { \ - if ((pAC)->DgT.DgUseCfgCycle) \ + if ((pAC)->DgT.DgUseCfgCycle) \ SkPciReadCfgWord(pAC,Addr,pVal); \ else \ - SK_IN16(pAC,PCI_C(Addr),pVal); \ + SK_IN16(pAC,PCI_C(Addr),pVal); \ } #define VPD_IN32(pAC,Ioc,Addr,pVal) { \ if ((pAC)->DgT.DgUseCfgCycle) \ diff --git a/drivers/net/sk98lin/h/xmac_ii.h b/drivers/net/sk98lin/h/xmac_ii.h index 2ef903a87..09e21d68a 100644 --- a/drivers/net/sk98lin/h/xmac_ii.h +++ b/drivers/net/sk98lin/h/xmac_ii.h @@ -237,7 +237,7 @@ extern "C" { #define XM_RX_CMD 0x0030 /* 16 bit r/w Receive Command Register */ #define XM_PHY_ADDR 0x0034 /* 16 bit r/w PHY Address Register */ #define XM_PHY_DATA 0x0038 /* 16 bit r/w PHY Data Register */ - /* 0x003c: reserved */ + /* 0x003c: reserved */ #define XM_GP_PORT 0x0040 /* 32 bit r/w General Purpose Port Register */ #define XM_IMSK 0x0044 /* 16 bit r/w Interrupt Mask Register */ #define XM_ISRC 0x0048 /* 16 bit r/o Interrupt Status Register */ @@ -248,14 +248,14 @@ extern "C" { #define XM_TX_THR 0x0064 /* 16 bit r/w Tx Request Threshold */ #define XM_HT_THR 0x0066 /* 16 bit r/w Host Request Threshold */ #define XM_PAUSE_DA 0x0068 /* NA reg r/w Pause Destination Address */ - /* 0x006e: reserved */ + /* 0x006e: reserved */ #define XM_CTL_PARA 0x0070 /* 32 bit r/w Control Parameter Register */ #define XM_MAC_OPCODE 0x0074 /* 16 bit r/w Opcode for MAC control frames */ #define XM_MAC_PTIME 0x0076 /* 16 bit r/w Pause time for MAC ctrl frames*/ #define XM_TX_STAT 0x0078 /* 32 bit r/o Tx Status LIFO Register */ /* 0x0080 - 0x00fc: 16 NA reg r/w Exact Match Address Registers */ - /* use the XM_EXM() macro to address */ + /* use the XM_EXM() macro to address */ #define XM_EXM_START 0x0080 /* r/w Start Address of the EXM Regs */ /* @@ -413,7 +413,7 @@ extern "C" { #define XM_RX_IPG_CAP (1<<6) /* Bit 6 repl. type field with IPG */ #define XM_RX_TP_MD (1<<5) /* Bit 5: Enable transparent Mode */ #define XM_RX_STRIP_FCS (1<<4) /* Bit 4: Enable FCS Stripping */ -#define XM_RX_SELF_RX (1<<3) /* Bit 3: Enable Rx of own packets */ +#define XM_RX_SELF_RX (1<<3) /* Bit 3: Enable Rx of own packets */ #define XM_RX_SAM_LINE (1<<2) /* Bit 2: (sc) Start utilization calculation */ #define XM_RX_STRIP_PAD (1<<1) /* Bit 1: Strip pad bytes of Rx frames */ #define XM_RX_DIS_CEXT (1<<0) /* Bit 0: Disable carrier ext. check */ @@ -510,7 +510,7 @@ extern "C" { /* Bit 31..27: reserved */ #define XM_MD_ENA_REJ (1L<<26) /* Bit 26: Enable Frame Reject */ #define XM_MD_SPOE_E (1L<<25) /* Bit 25: Send Pause on Edge */ - /* extern generated */ + /* extern generated */ #define XM_MD_TX_REP (1L<<24) /* Bit 24: Transmit Repeater Mode */ #define XM_MD_SPOFF_I (1L<<23) /* Bit 23: Send Pause on FIFO full */ /* intern generated */ @@ -548,7 +548,7 @@ extern "C" { /* Bit 16..6: reserved */ #define XM_SC_SNP_RXC (1<<5) /* Bit 5: (sc) Snap Rx Counters */ #define XM_SC_SNP_TXC (1<<4) /* Bit 4: (sc) Snap Tx Counters */ -#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */ +#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */ #define XM_SC_CP_TXC (1<<2) /* Bit 2: Copy Tx Counters Continuously */ #define XM_SC_CLR_RXC (1<<1) /* Bit 1: (sc) Clear Rx Counters */ #define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */ @@ -1316,7 +1316,7 @@ extern "C" { #define PHY_M_PC_DIS_JABBER (1<<0) /* Bit 0: Disable Jabber */ #define PHY_M_PC_MDI_XMODE(x) SHIFT5(x) -#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ +#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ #define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */ #define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */ diff --git a/drivers/net/sk98lin/skge.c b/drivers/net/sk98lin/skge.c index 61a609423..e1d7e8720 100644 --- a/drivers/net/sk98lin/skge.c +++ b/drivers/net/sk98lin/skge.c @@ -3,7 +3,7 @@ * Name: skge.c * Project: GEnesis, PCI Gigabit Ethernet Adapter * Version: $Revision: 1.46 $ - * Date: $Date: 2003/02/25 14:16:36 $ + * Date: $Date: 2003/02/25 14:16:36 $ * Purpose: The main driver source module * ******************************************************************************/ @@ -348,7 +348,7 @@ #if 0 #include <linux/module.h> #include <linux/init.h> -#include <linux/proc_fs.h> +#include <linux/proc_fs.h> #endif #include "h/skdrv1st.h" #include "h/skdrv2nd.h" @@ -501,7 +501,7 @@ static struct pci_device_id supported[] = { /***************************************************************************** * - * skge_probe - find all SK-98xx adapters + * skge_probe - find all SK-98xx adapters * * Description: * This function scans the PCI bus for SK-98xx adapters. Resources for @@ -646,7 +646,7 @@ int skge_probe (struct eth_device ** ret_dev) dev->set_mac_address = &SkGeSetMacAddr; dev->do_ioctl = &SkGeIoctl; dev->change_mtu = &SkGeChangeMtu; - dev->flags &= ~IFF_RUNNING; + dev->flags &= ~IFF_RUNNING; #endif #ifdef SK_ZEROCOPY @@ -793,7 +793,7 @@ int skge_probe (struct eth_device ** ret_dev) dev->set_mac_address = &SkGeSetMacAddr; dev->do_ioctl = &SkGeIoctl; dev->change_mtu = &SkGeChangeMtu; - dev->flags &= ~IFF_RUNNING; + dev->flags &= ~IFF_RUNNING; #endif #ifdef SK_ZEROCOPY @@ -857,7 +857,7 @@ int skge_probe (struct eth_device ** ret_dev) /***************************************************************************** * - * FreeResources - release resources allocated for adapter + * FreeResources - release resources allocated for adapter * * Description: * This function releases the IRQ, unmaps the IO and @@ -992,7 +992,7 @@ static int options[SK_MAX_CARD_PARAM] = {0, }; /* not used */ /***************************************************************************** * - * skge_init_module - module initialization function + * skge_init_module - module initialization function * * Description: * Very simple, only call skge_probe and return approriate result. @@ -1020,7 +1020,7 @@ static int __init skge_init_module(void) /***************************************************************************** * - * skge_cleanup_module - module unload function + * skge_cleanup_module - module unload function * * Description: * Disable adapter if it is still running, free resources, @@ -1098,7 +1098,7 @@ module_exit(skge_cleanup_module); /***************************************************************************** * - * SkGeBoardInit - do level 0 and 1 initialization + * SkGeBoardInit - do level 0 and 1 initialization * * Description: * This function prepares the board hardware for running. The desriptor @@ -1262,7 +1262,7 @@ SK_BOOL DualNet; /***************************************************************************** * - * BoardAllocMem - allocate the memory for the descriptor rings + * BoardAllocMem - allocate the memory for the descriptor rings * * Description: * This function allocates the memory for all descriptor rings. @@ -1360,7 +1360,7 @@ size_t AllocLength; /* length of complete descriptor area */ /***************************************************************************** * - * BoardInitMem - initiate the descriptor rings + * BoardInitMem - initiate the descriptor rings * * Description: * This function sets the descriptor rings up in memory. @@ -1408,7 +1408,7 @@ int TxDescrSize; /* the size of a tx descriptor rounded up to alignment*/ /***************************************************************************** * - * SetupRing - create one descriptor ring + * SetupRing - create one descriptor ring * * Description: * This function creates one descriptor ring in the given memory area. @@ -1477,7 +1477,7 @@ uintptr_t VNextDescr; /* the virtual bus address of the next descriptor */ /***************************************************************************** * - * PortReInitBmu - re-initiate the descriptor rings for one port + * PortReInitBmu - re-initiate the descriptor rings for one port * * Description: * This function reinitializes the descriptor rings of one port @@ -1998,7 +1998,7 @@ struct SK_NET_DEVICE *dev) /***************************************************************************** * - * SkGeXmit - Linux frame transmit function + * SkGeXmit - Linux frame transmit function * * Description: * The system calls this function to send frames onto the wire. @@ -2078,7 +2078,7 @@ int Rc; /* return code of XmitFrame */ /***************************************************************************** * - * XmitFrame - fill one socket buffer into the transmit ring + * XmitFrame - fill one socket buffer into the transmit ring * * Description: * This function puts a message into the transmit descriptor ring @@ -2099,7 +2099,7 @@ int Rc; /* return code of XmitFrame */ * < 0 - on failure: other problems ( -> return failure to upper layers) */ static int XmitFrame( -SK_AC *pAC, /* pointer to adapter context */ +SK_AC *pAC, /* pointer to adapter context */ TX_PORT *pTxPort, /* pointer to struct of port to send to */ struct sk_buff *pMessage) /* pointer to send-message */ { @@ -2186,7 +2186,7 @@ int BytesSend; /***************************************************************************** * - * XmitFrameSG - fill one socket buffer into the transmit ring + * XmitFrameSG - fill one socket buffer into the transmit ring * (use SG and TCP/UDP hardware checksumming) * * Description: @@ -2201,12 +2201,12 @@ int BytesSend; */ #if 0 static int XmitFrameSG( -SK_AC *pAC, /* pointer to adapter context */ +SK_AC *pAC, /* pointer to adapter context */ TX_PORT *pTxPort, /* pointer to struct of port to send to */ struct sk_buff *pMessage) /* pointer to send-message */ { - int i; + int i; int BytesSend; int hlength; int protocol; @@ -2374,7 +2374,7 @@ void dump_frag( SK_U8 *data, int length) /***************************************************************************** * - * FreeTxDescriptors - release descriptors from the descriptor ring + * FreeTxDescriptors - release descriptors from the descriptor ring * * Description: * This function releases descriptors from a transmit ring if they @@ -2444,7 +2444,7 @@ SK_U64 PhysAddr; /* address of DMA mapping */ /***************************************************************************** * - * FillRxRing - fill the receive ring with valid descriptors + * FillRxRing - fill the receive ring with valid descriptors * * Description: * This function fills the receive ring descriptors with data @@ -2476,7 +2476,7 @@ unsigned long Flags; /***************************************************************************** * - * FillRxDescriptor - fill one buffer into the receive ring + * FillRxDescriptor - fill one buffer into the receive ring * * Description: * The function allocates a new receive buffer and @@ -2532,7 +2532,7 @@ SK_U64 PhysAddr; /* physical address of a rx buffer */ /***************************************************************************** * - * ReQueueRxBuffer - fill one buffer back into the receive ring + * ReQueueRxBuffer - fill one buffer back into the receive ring * * Description: * Fill a given buffer back into the rx ring. The buffer @@ -2566,7 +2566,7 @@ SK_U16 Length; /* data fragment length */ /***************************************************************************** * - * ReceiveIrq - handle a receive IRQ + * ReceiveIrq - handle a receive IRQ * * Description: * This function is called when a receive IRQ is set. @@ -2598,7 +2598,7 @@ unsigned int NumBytes; unsigned int ForRlmt; SK_BOOL IsBc; SK_BOOL IsMc; -SK_BOOL IsBadFrame; /* Bad frame */ +SK_BOOL IsBadFrame; /* Bad frame */ SK_U32 FrameStat; unsigned short Csum1; @@ -2935,7 +2935,7 @@ rx_failed: /***************************************************************************** * - * ClearAndStartRx - give a start receive command to BMU, clear IRQ + * ClearAndStartRx - give a start receive command to BMU, clear IRQ * * Description: * This function sends a start command and a clear interrupt @@ -2955,7 +2955,7 @@ int PortIndex) /* index of the receive port (XMAC) */ /***************************************************************************** * - * ClearTxIrq - give a clear transmit IRQ command to BMU + * ClearTxIrq - give a clear transmit IRQ command to BMU * * Description: * This function sends a clear tx IRQ command for one @@ -2975,7 +2975,7 @@ int Prio) /* priority or normal queue */ /***************************************************************************** * - * ClearRxRing - remove all buffers from the receive ring + * ClearRxRing - remove all buffers from the receive ring * * Description: * This function removes all receive buffers from the ring. @@ -3052,7 +3052,7 @@ unsigned long Flags; #if 0 /***************************************************************************** * - * SetQueueSizes - configure the sizes of rx and tx queues + * SetQueueSizes - configure the sizes of rx and tx queues * * Description: * This function assigns the sizes for active and passive port @@ -3145,7 +3145,7 @@ if (pAC->RlmtNets == 1) { /***************************************************************************** * - * SkGeSetMacAddr - Set the hardware MAC address + * SkGeSetMacAddr - Set the hardware MAC address * * Description: * This function sets the MAC address used by the adapter. @@ -3188,7 +3188,7 @@ unsigned long Flags; /***************************************************************************** * - * SkGeSetRxMode - set receive mode + * SkGeSetRxMode - set receive mode * * Description: * This function sets the receive mode of an adapter. The adapter @@ -3264,7 +3264,7 @@ unsigned long Flags; /***************************************************************************** * - * SkGeChangeMtu - set the MTU to another value + * SkGeChangeMtu - set the MTU to another value * * Description: * This function sets is called whenever the MTU size is changed @@ -3282,7 +3282,7 @@ DEV_NET *pOtherNet; SK_AC *pAC; unsigned long Flags; int i; -SK_EVPARA EvPara; +SK_EVPARA EvPara; SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY, ("SkGeChangeMtu starts now...\n")); @@ -3487,7 +3487,7 @@ SK_EVPARA EvPara; /***************************************************************************** * - * SkGeStats - return ethernet device statistics + * SkGeStats - return ethernet device statistics * * Description: * This function return statistic data about the ethernet device @@ -3560,7 +3560,7 @@ unsigned long Flags; /* for spin lock */ /***************************************************************************** * - * SkGeIoctl - IO-control function + * SkGeIoctl - IO-control function * * Description: * This function is called if an ioctl is issued on the device. @@ -3619,7 +3619,7 @@ int Size; /***************************************************************************** * - * SkGeIocMib - handle a GetMib, SetMib- or PresetMib-ioctl message + * SkGeIocMib - handle a GetMib, SetMib- or PresetMib-ioctl message * * Description: * This function reads/writes the MIB data using PNMI (Private Network @@ -3673,7 +3673,7 @@ SK_AC *pAC; /***************************************************************************** * - * GetConfiguration - read configuration information + * GetConfiguration - read configuration information * * Description: * This function reads per-adapter configuration information from @@ -3717,7 +3717,7 @@ int Capabilities[3][3] = /* settings for port A */ /* settings link speed */ - LinkSpeed = SK_LSPEED_AUTO; /* default: do auto select */ + LinkSpeed = SK_LSPEED_AUTO; /* default: do auto select */ if (Speed_A != NULL && pAC->Index<SK_MAX_CARD_PARAM && Speed_A[pAC->Index] != NULL) { if (strcmp(Speed_A[pAC->Index],"")==0) { @@ -3876,7 +3876,7 @@ int Capabilities[3][3] = /* settings for port B */ /* settings link speed */ - LinkSpeed = SK_LSPEED_AUTO; /* default: do auto select */ + LinkSpeed = SK_LSPEED_AUTO; /* default: do auto select */ if (Speed_B != NULL && pAC->Index<SK_MAX_CARD_PARAM && Speed_B[pAC->Index] != NULL) { if (strcmp(Speed_B[pAC->Index],"")==0) { @@ -4100,7 +4100,7 @@ int Capabilities[3][3] = /***************************************************************************** * - * ProductStr - return a adapter identification string from vpd + * ProductStr - return a adapter identification string from vpd * * Description: * This function reads the product name string from the vpd area diff --git a/drivers/net/sk98lin/skgeinit.c b/drivers/net/sk98lin/skgeinit.c index a18dc0a48..e49685bb9 100644 --- a/drivers/net/sk98lin/skgeinit.c +++ b/drivers/net/sk98lin/skgeinit.c @@ -585,7 +585,7 @@ int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */ * 1: configuration error */ static int DoCalcAddr( -SK_AC *pAC, /* adapter context */ +SK_AC *pAC, /* adapter context */ SK_GEPORT *pPrt, /* port index */ int QuSize, /* size of the queue to configure in kB */ SK_U32 *StartVal, /* start value for address calculation */ @@ -1263,9 +1263,8 @@ int Port) /* Port Index (MAC_1 + n) */ pPrt = &pAC->GIni.GP[Port]; if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) { - RxQType = SK_RX_SRAM_Q; /* small Rx Queue */ - } - else { + RxQType = SK_RX_SRAM_Q; /* small Rx Queue */ + } else { RxQType = SK_RX_BRAM_Q; /* big Rx Queue */ } @@ -1354,7 +1353,7 @@ int Port) /* Port Index (MAC_1 + n) */ /* * Tx Queue: Release all local resets if the queue is used ! - * set watermark + * set watermark */ if (pPrt->PXSQSize != 0) { SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET); @@ -1416,7 +1415,7 @@ int QuIoOffs) /* Queue IO Address Offset */ * It is possible to stop the receive and transmit path separate or * both together. * - * Dir = SK_STOP_TX Stops the transmit path only and resets the MAC. + * Dir = SK_STOP_TX Stops the transmit path only and resets the MAC. * The receive queue is still active and * the pending Rx frames may be still transferred * into the RxD. diff --git a/drivers/net/sk98lin/skgepnmi.c b/drivers/net/sk98lin/skgepnmi.c index b5d32b04c..16fa3523a 100644 --- a/drivers/net/sk98lin/skgepnmi.c +++ b/drivers/net/sk98lin/skgepnmi.c @@ -537,70 +537,70 @@ PNMI_STATIC void CheckVctStatus(SK_AC *, SK_IOC, char *, SK_U32, SK_U32); * mask returned by the pFnMacOverflow function */ PNMI_STATIC const SK_U16 StatOvrflwBit[][SK_PNMI_MAC_TYPES] = { -/* Bit0 */ { SK_PNMI_HTX, SK_PNMI_HTX_UNICAST}, -/* Bit1 */ { SK_PNMI_HTX_OCTETHIGH, SK_PNMI_HTX_BROADCAST}, -/* Bit2 */ { SK_PNMI_HTX_OCTETLOW, SK_PNMI_HTX_PMACC}, -/* Bit3 */ { SK_PNMI_HTX_BROADCAST, SK_PNMI_HTX_MULTICAST}, -/* Bit4 */ { SK_PNMI_HTX_MULTICAST, SK_PNMI_HTX_OCTETLOW}, -/* Bit5 */ { SK_PNMI_HTX_UNICAST, SK_PNMI_HTX_OCTETHIGH}, -/* Bit6 */ { SK_PNMI_HTX_LONGFRAMES, SK_PNMI_HTX_64}, -/* Bit7 */ { SK_PNMI_HTX_BURST, SK_PNMI_HTX_127}, -/* Bit8 */ { SK_PNMI_HTX_PMACC, SK_PNMI_HTX_255}, -/* Bit9 */ { SK_PNMI_HTX_MACC, SK_PNMI_HTX_511}, -/* Bit10 */ { SK_PNMI_HTX_SINGLE_COL, SK_PNMI_HTX_1023}, -/* Bit11 */ { SK_PNMI_HTX_MULTI_COL, SK_PNMI_HTX_MAX}, -/* Bit12 */ { SK_PNMI_HTX_EXCESS_COL, SK_PNMI_HTX_LONGFRAMES}, -/* Bit13 */ { SK_PNMI_HTX_LATE_COL, SK_PNMI_HTX_RESERVED}, -/* Bit14 */ { SK_PNMI_HTX_DEFFERAL, SK_PNMI_HTX_COL}, -/* Bit15 */ { SK_PNMI_HTX_EXCESS_DEF, SK_PNMI_HTX_LATE_COL}, -/* Bit16 */ { SK_PNMI_HTX_UNDERRUN, SK_PNMI_HTX_EXCESS_COL}, -/* Bit17 */ { SK_PNMI_HTX_CARRIER, SK_PNMI_HTX_MULTI_COL}, -/* Bit18 */ { SK_PNMI_HTX_UTILUNDER, SK_PNMI_HTX_SINGLE_COL}, -/* Bit19 */ { SK_PNMI_HTX_UTILOVER, SK_PNMI_HTX_UNDERRUN}, -/* Bit20 */ { SK_PNMI_HTX_64, SK_PNMI_HTX_RESERVED}, -/* Bit21 */ { SK_PNMI_HTX_127, SK_PNMI_HTX_RESERVED}, -/* Bit22 */ { SK_PNMI_HTX_255, SK_PNMI_HTX_RESERVED}, -/* Bit23 */ { SK_PNMI_HTX_511, SK_PNMI_HTX_RESERVED}, -/* Bit24 */ { SK_PNMI_HTX_1023, SK_PNMI_HTX_RESERVED}, -/* Bit25 */ { SK_PNMI_HTX_MAX, SK_PNMI_HTX_RESERVED}, -/* Bit26 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, -/* Bit27 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, -/* Bit28 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, -/* Bit29 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, -/* Bit30 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, -/* Bit31 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, -/* Bit32 */ { SK_PNMI_HRX, SK_PNMI_HRX_UNICAST}, -/* Bit33 */ { SK_PNMI_HRX_OCTETHIGH, SK_PNMI_HRX_BROADCAST}, -/* Bit34 */ { SK_PNMI_HRX_OCTETLOW, SK_PNMI_HRX_PMACC}, -/* Bit35 */ { SK_PNMI_HRX_BROADCAST, SK_PNMI_HRX_MULTICAST}, -/* Bit36 */ { SK_PNMI_HRX_MULTICAST, SK_PNMI_HRX_FCS}, -/* Bit37 */ { SK_PNMI_HRX_UNICAST, SK_PNMI_HRX_RESERVED}, -/* Bit38 */ { SK_PNMI_HRX_PMACC, SK_PNMI_HRX_OCTETLOW}, -/* Bit39 */ { SK_PNMI_HRX_MACC, SK_PNMI_HRX_OCTETHIGH}, -/* Bit40 */ { SK_PNMI_HRX_PMACC_ERR, SK_PNMI_HRX_BADOCTETLOW}, +/* Bit0 */ { SK_PNMI_HTX, SK_PNMI_HTX_UNICAST}, +/* Bit1 */ { SK_PNMI_HTX_OCTETHIGH, SK_PNMI_HTX_BROADCAST}, +/* Bit2 */ { SK_PNMI_HTX_OCTETLOW, SK_PNMI_HTX_PMACC}, +/* Bit3 */ { SK_PNMI_HTX_BROADCAST, SK_PNMI_HTX_MULTICAST}, +/* Bit4 */ { SK_PNMI_HTX_MULTICAST, SK_PNMI_HTX_OCTETLOW}, +/* Bit5 */ { SK_PNMI_HTX_UNICAST, SK_PNMI_HTX_OCTETHIGH}, +/* Bit6 */ { SK_PNMI_HTX_LONGFRAMES, SK_PNMI_HTX_64}, +/* Bit7 */ { SK_PNMI_HTX_BURST, SK_PNMI_HTX_127}, +/* Bit8 */ { SK_PNMI_HTX_PMACC, SK_PNMI_HTX_255}, +/* Bit9 */ { SK_PNMI_HTX_MACC, SK_PNMI_HTX_511}, +/* Bit10 */ { SK_PNMI_HTX_SINGLE_COL, SK_PNMI_HTX_1023}, +/* Bit11 */ { SK_PNMI_HTX_MULTI_COL, SK_PNMI_HTX_MAX}, +/* Bit12 */ { SK_PNMI_HTX_EXCESS_COL, SK_PNMI_HTX_LONGFRAMES}, +/* Bit13 */ { SK_PNMI_HTX_LATE_COL, SK_PNMI_HTX_RESERVED}, +/* Bit14 */ { SK_PNMI_HTX_DEFFERAL, SK_PNMI_HTX_COL}, +/* Bit15 */ { SK_PNMI_HTX_EXCESS_DEF, SK_PNMI_HTX_LATE_COL}, +/* Bit16 */ { SK_PNMI_HTX_UNDERRUN, SK_PNMI_HTX_EXCESS_COL}, +/* Bit17 */ { SK_PNMI_HTX_CARRIER, SK_PNMI_HTX_MULTI_COL}, +/* Bit18 */ { SK_PNMI_HTX_UTILUNDER, SK_PNMI_HTX_SINGLE_COL}, +/* Bit19 */ { SK_PNMI_HTX_UTILOVER, SK_PNMI_HTX_UNDERRUN}, +/* Bit20 */ { SK_PNMI_HTX_64, SK_PNMI_HTX_RESERVED}, +/* Bit21 */ { SK_PNMI_HTX_127, SK_PNMI_HTX_RESERVED}, +/* Bit22 */ { SK_PNMI_HTX_255, SK_PNMI_HTX_RESERVED}, +/* Bit23 */ { SK_PNMI_HTX_511, SK_PNMI_HTX_RESERVED}, +/* Bit24 */ { SK_PNMI_HTX_1023, SK_PNMI_HTX_RESERVED}, +/* Bit25 */ { SK_PNMI_HTX_MAX, SK_PNMI_HTX_RESERVED}, +/* Bit26 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit27 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit28 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit29 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit30 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit31 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED}, +/* Bit32 */ { SK_PNMI_HRX, SK_PNMI_HRX_UNICAST}, +/* Bit33 */ { SK_PNMI_HRX_OCTETHIGH, SK_PNMI_HRX_BROADCAST}, +/* Bit34 */ { SK_PNMI_HRX_OCTETLOW, SK_PNMI_HRX_PMACC}, +/* Bit35 */ { SK_PNMI_HRX_BROADCAST, SK_PNMI_HRX_MULTICAST}, +/* Bit36 */ { SK_PNMI_HRX_MULTICAST, SK_PNMI_HRX_FCS}, +/* Bit37 */ { SK_PNMI_HRX_UNICAST, SK_PNMI_HRX_RESERVED}, +/* Bit38 */ { SK_PNMI_HRX_PMACC, SK_PNMI_HRX_OCTETLOW}, +/* Bit39 */ { SK_PNMI_HRX_MACC, SK_PNMI_HRX_OCTETHIGH}, +/* Bit40 */ { SK_PNMI_HRX_PMACC_ERR, SK_PNMI_HRX_BADOCTETLOW}, /* Bit41 */ { SK_PNMI_HRX_MACC_UNKWN, SK_PNMI_HRX_BADOCTETHIGH}, -/* Bit42 */ { SK_PNMI_HRX_BURST, SK_PNMI_HRX_UNDERSIZE}, -/* Bit43 */ { SK_PNMI_HRX_MISSED, SK_PNMI_HRX_RUNT}, -/* Bit44 */ { SK_PNMI_HRX_FRAMING, SK_PNMI_HRX_64}, -/* Bit45 */ { SK_PNMI_HRX_OVERFLOW, SK_PNMI_HRX_127}, -/* Bit46 */ { SK_PNMI_HRX_JABBER, SK_PNMI_HRX_255}, -/* Bit47 */ { SK_PNMI_HRX_CARRIER, SK_PNMI_HRX_511}, -/* Bit48 */ { SK_PNMI_HRX_IRLENGTH, SK_PNMI_HRX_1023}, -/* Bit49 */ { SK_PNMI_HRX_SYMBOL, SK_PNMI_HRX_MAX}, -/* Bit50 */ { SK_PNMI_HRX_SHORTS, SK_PNMI_HRX_LONGFRAMES}, -/* Bit51 */ { SK_PNMI_HRX_RUNT, SK_PNMI_HRX_TOO_LONG}, -/* Bit52 */ { SK_PNMI_HRX_TOO_LONG, SK_PNMI_HRX_JABBER}, -/* Bit53 */ { SK_PNMI_HRX_FCS, SK_PNMI_HRX_RESERVED}, -/* Bit54 */ { SK_PNMI_HRX_RESERVED, SK_PNMI_HRX_OVERFLOW}, -/* Bit55 */ { SK_PNMI_HRX_CEXT, SK_PNMI_HRX_RESERVED}, -/* Bit56 */ { SK_PNMI_HRX_UTILUNDER, SK_PNMI_HRX_RESERVED}, -/* Bit57 */ { SK_PNMI_HRX_UTILOVER, SK_PNMI_HRX_RESERVED}, -/* Bit58 */ { SK_PNMI_HRX_64, SK_PNMI_HRX_RESERVED}, -/* Bit59 */ { SK_PNMI_HRX_127, SK_PNMI_HRX_RESERVED}, -/* Bit60 */ { SK_PNMI_HRX_255, SK_PNMI_HRX_RESERVED}, -/* Bit61 */ { SK_PNMI_HRX_511, SK_PNMI_HRX_RESERVED}, -/* Bit62 */ { SK_PNMI_HRX_1023, SK_PNMI_HRX_RESERVED}, -/* Bit63 */ { SK_PNMI_HRX_MAX, SK_PNMI_HRX_RESERVED} +/* Bit42 */ { SK_PNMI_HRX_BURST, SK_PNMI_HRX_UNDERSIZE}, +/* Bit43 */ { SK_PNMI_HRX_MISSED, SK_PNMI_HRX_RUNT}, +/* Bit44 */ { SK_PNMI_HRX_FRAMING, SK_PNMI_HRX_64}, +/* Bit45 */ { SK_PNMI_HRX_OVERFLOW, SK_PNMI_HRX_127}, +/* Bit46 */ { SK_PNMI_HRX_JABBER, SK_PNMI_HRX_255}, +/* Bit47 */ { SK_PNMI_HRX_CARRIER, SK_PNMI_HRX_511}, +/* Bit48 */ { SK_PNMI_HRX_IRLENGTH, SK_PNMI_HRX_1023}, +/* Bit49 */ { SK_PNMI_HRX_SYMBOL, SK_PNMI_HRX_MAX}, +/* Bit50 */ { SK_PNMI_HRX_SHORTS, SK_PNMI_HRX_LONGFRAMES}, +/* Bit51 */ { SK_PNMI_HRX_RUNT, SK_PNMI_HRX_TOO_LONG}, +/* Bit52 */ { SK_PNMI_HRX_TOO_LONG, SK_PNMI_HRX_JABBER}, +/* Bit53 */ { SK_PNMI_HRX_FCS, SK_PNMI_HRX_RESERVED}, +/* Bit54 */ { SK_PNMI_HRX_RESERVED, SK_PNMI_HRX_OVERFLOW}, +/* Bit55 */ { SK_PNMI_HRX_CEXT, SK_PNMI_HRX_RESERVED}, +/* Bit56 */ { SK_PNMI_HRX_UTILUNDER, SK_PNMI_HRX_RESERVED}, +/* Bit57 */ { SK_PNMI_HRX_UTILOVER, SK_PNMI_HRX_RESERVED}, +/* Bit58 */ { SK_PNMI_HRX_64, SK_PNMI_HRX_RESERVED}, +/* Bit59 */ { SK_PNMI_HRX_127, SK_PNMI_HRX_RESERVED}, +/* Bit60 */ { SK_PNMI_HRX_255, SK_PNMI_HRX_RESERVED}, +/* Bit61 */ { SK_PNMI_HRX_511, SK_PNMI_HRX_RESERVED}, +/* Bit62 */ { SK_PNMI_HRX_1023, SK_PNMI_HRX_RESERVED}, +/* Bit63 */ { SK_PNMI_HRX_MAX, SK_PNMI_HRX_RESERVED} }; /* @@ -8253,7 +8253,7 @@ char *pBuf, SK_U32 Offset, SK_U32 PhysPortIndex) { - SK_GEPORT *pPrt; + SK_GEPORT *pPrt; SK_PNMI_VCT *pVctData; SK_U32 RetCode; SK_U8 LinkSpeedUsed; diff --git a/drivers/net/sk98lin/skgesirq.c b/drivers/net/sk98lin/skgesirq.c index e5a4f7ec1..c9763e740 100644 --- a/drivers/net/sk98lin/skgesirq.c +++ b/drivers/net/sk98lin/skgesirq.c @@ -830,10 +830,10 @@ SK_U32 Istatus) /* Interrupt status word */ SK_EVPARA Para; SK_U32 RegVal32; /* Read register value */ SK_GEPORT *pPrt; /* GIni Port struct pointer */ - unsigned Len; + unsigned Len; SK_U64 Octets; - SK_U16 PhyInt; - SK_U16 PhyIMsk; + SK_U16 PhyInt; + SK_U16 PhyIMsk; int i; if ((Istatus & IS_HW_ERR) != 0) { diff --git a/drivers/net/sk98lin/ski2c.c b/drivers/net/sk98lin/ski2c.c index 2ab635a22..0c5d9b407 100644 --- a/drivers/net/sk98lin/ski2c.c +++ b/drivers/net/sk98lin/ski2c.c @@ -281,7 +281,7 @@ static const char SysKonnectFileId[] = . +-----------------+ . | Temperature and | . | Voltage Sensor | -. | LM80 | +. | LM80 | . +-----------------+ . | . | @@ -323,7 +323,7 @@ intro() */ #ifndef I2C_SLOW_TIMING #define T_CLK_LOW 1300L /* clock low time in ns */ -#define T_CLK_HIGH 600L /* clock high time in ns */ +#define T_CLK_HIGH 600L /* clock high time in ns */ #define T_DATA_IN_SETUP 100L /* data in Set-up Time */ #define T_START_HOLD 600L /* start condition hold time */ #define T_START_SETUP 600L /* start condition Set-up time */ diff --git a/drivers/net/sk98lin/sklm80.c b/drivers/net/sk98lin/sklm80.c index 687572b1d..0229877b5 100644 --- a/drivers/net/sk98lin/sklm80.c +++ b/drivers/net/sk98lin/sklm80.c @@ -122,7 +122,7 @@ static const char SysKonnectFileId[] = /* * read the register 'Reg' from the device 'Dev' * - * return read error -1 + * return read error -1 * success the read value */ int SkLm80RcvReg( diff --git a/drivers/net/sk98lin/skproc.c b/drivers/net/sk98lin/skproc.c index 4e340730e..94a6a564a 100644 --- a/drivers/net/sk98lin/skproc.c +++ b/drivers/net/sk98lin/skproc.c @@ -86,21 +86,20 @@ #define SPECIALX 32 /* 0x */ #define LARGE 64 -extern SK_AC *pACList; -extern struct net_device *SkGeRootDev; +extern SK_AC *pACList; +extern struct net_device *SkGeRootDev; -extern char * SkNumber( - char * str, - long long num, - int base, - int size, - int precision, - int type); +extern char *SkNumber (char *str, + long long num, + int base, + int size, + int precision, + int type); /***************************************************************************** * - * proc_read - print "summaries" entry + * proc_read - print "summaries" entry * * Description: * This function fills the proc entry with statistic data about @@ -120,16 +119,16 @@ void *data) int len = 0; int t; int i; - DEV_NET *pNet; - SK_AC *pAC; - char test_buf[100]; - char sens_msg[50]; - unsigned long Flags; - unsigned int Size; - struct SK_NET_DEVICE *next; - struct SK_NET_DEVICE *SkgeProcDev = SkGeRootDev; + DEV_NET *pNet; + SK_AC *pAC; + char test_buf[100]; + char sens_msg[50]; + unsigned long Flags; + unsigned int Size; + struct SK_NET_DEVICE *next; + struct SK_NET_DEVICE *SkgeProcDev = SkGeRootDev; - SK_PNMI_STRUCT_DATA *pPnmiStruct; + SK_PNMI_STRUCT_DATA *pPnmiStruct; SK_PNMI_STAT *pPnmiStat; struct proc_dir_entry *file = (struct proc_dir_entry*) data; @@ -393,31 +392,31 @@ void *data) */ static long SkDoDiv (long long Dividend, int Divisor, long long *pErg) { - long Rest; - long long Ergebnis; - long Akku; + long Rest; + long long Ergebnis; + long Akku; - Akku = Dividend >> 32; + Akku = Dividend >> 32; - Ergebnis = ((long long) (Akku / Divisor)) << 32; - Rest = Akku % Divisor ; + Ergebnis = ((long long) (Akku / Divisor)) << 32; + Rest = Akku % Divisor; - Akku = Rest << 16; - Akku |= ((Dividend & 0xFFFF0000) >> 16); + Akku = Rest << 16; + Akku |= ((Dividend & 0xFFFF0000) >> 16); - Ergebnis += ((long long) (Akku / Divisor)) << 16; - Rest = Akku % Divisor ; + Ergebnis += ((long long) (Akku / Divisor)) << 16; + Rest = Akku % Divisor; - Akku = Rest << 16; - Akku |= (Dividend & 0xFFFF); + Akku = Rest << 16; + Akku |= (Dividend & 0xFFFF); - Ergebnis += (Akku / Divisor); - Rest = Akku % Divisor ; + Ergebnis += (Akku / Divisor); + Rest = Akku % Divisor; - *pErg = Ergebnis; - return (Rest); + *pErg = Ergebnis; + return (Rest); } diff --git a/drivers/net/sk98lin/skrlmt.c b/drivers/net/sk98lin/skrlmt.c index f8a3b41f0..14a6f40d8 100644 --- a/drivers/net/sk98lin/skrlmt.c +++ b/drivers/net/sk98lin/skrlmt.c @@ -350,7 +350,7 @@ extern "C" { /* ----- Private RLMT defaults ----- */ #define SK_RLMT_DEF_PREF_PORT 0 /* "Lower" port. */ -#define SK_RLMT_DEF_MODE SK_RLMT_CHECK_LINK /* Default RLMT Mode. */ +#define SK_RLMT_DEF_MODE SK_RLMT_CHECK_LINK /* Default RLMT Mode. */ /* ----- Private RLMT checking states ----- */ @@ -530,7 +530,7 @@ typedef struct s_SpTreeRlmtPacket { SK_MAC_ADDR SkRlmtMcAddr = {{0x01, 0x00, 0x5A, 0x52, 0x4C, 0x4D}}; SK_MAC_ADDR BridgeMcAddr = {{0x01, 0x80, 0xC2, 0x00, 0x00, 0x00}}; -SK_MAC_ADDR BcAddr = {{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}}; +SK_MAC_ADDR BcAddr = {{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}}; /* local variables ************************************************************/ diff --git a/drivers/net/sk98lin/skvpd.c b/drivers/net/sk98lin/skvpd.c index 3b81e67df..429da8256 100644 --- a/drivers/net/sk98lin/skvpd.c +++ b/drivers/net/sk98lin/skvpd.c @@ -288,10 +288,10 @@ int addr) /* VPD address */ . write 1.8 ms 3.6 ms . internal write cyles 0.7 ms 7.0 ms . ------------------------------------------------------------------- -. over all program time 2.5 ms 10.6 ms +. over all program time 2.5 ms 10.6 ms . read 1.3 ms 2.6 ms . ------------------------------------------------------------------- -. over all 3.8 ms 13.2 ms +. over all 3.8 ms 13.2 ms . diff --git a/drivers/net/sk98lin/skxmac2.c b/drivers/net/sk98lin/skxmac2.c index e6b5a95d4..794600054 100644 --- a/drivers/net/sk98lin/skxmac2.c +++ b/drivers/net/sk98lin/skxmac2.c @@ -1247,7 +1247,7 @@ int Port) /* Port Index (MAC_1 + n) */ * (Timing requirements: Broadcom: 400ns, Level One: none, National: 80ns). * * ATTENTION: - * It is absolutely necessary to reset the SW_RST Bit first + * It is absolutely necessary to reset the SW_RST Bit first * before calling this function. * * Returns: @@ -1351,7 +1351,7 @@ int Port) /* Port Index (MAC_1 + n) */ * Description: * * ATTENTION: - * It is absolutely necessary to reset the SW_RST Bit first + * It is absolutely necessary to reset the SW_RST Bit first * before calling this function. * * Returns: @@ -1919,7 +1919,7 @@ int Port) /* Port Index (MAC_1 + n) */ /* Configuration Actions for Half Duplex Mode */ /* * XM_BURST = default value. We are probable not quick - * enough at the 'XMAC' bus to burst 8kB. + * enough at the 'XMAC' bus to burst 8kB. * The XMAC stops bursting if no transmit frames * are available or the burst limit is exceeded. */ @@ -2879,8 +2879,8 @@ SK_U16 PhyStat) /* PHY Status word to analyse */ * * Returns: * SK_AND_OK o.k. - * SK_AND_DUP_CAP Duplex capability error happened - * SK_AND_OTHER Other error happened + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened */ static int SkXmAutoNegDoneXmac( SK_AC *pAC, /* adapter context */ @@ -2962,8 +2962,8 @@ int Port) /* Port Index (MAC_1 + n) */ * * Returns: * SK_AND_OK o.k. - * SK_AND_DUP_CAP Duplex capability error happened - * SK_AND_OTHER Other error happened + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened */ static int SkXmAutoNegDoneBcom( SK_AC *pAC, /* adapter context */ @@ -3063,8 +3063,8 @@ int Port) /* Port Index (MAC_1 + n) */ * * Returns: * SK_AND_OK o.k. - * SK_AND_DUP_CAP Duplex capability error happened - * SK_AND_OTHER Other error happened + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened */ static int SkGmAutoNegDoneMarv( SK_AC *pAC, /* adapter context */ @@ -3168,8 +3168,8 @@ int Port) /* Port Index (MAC_1 + n) */ * * Returns: * SK_AND_OK o.k. - * SK_AND_DUP_CAP Duplex capability error happened - * SK_AND_OTHER Other error happened + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened */ static int SkXmAutoNegDoneLone( SK_AC *pAC, /* adapter context */ @@ -3273,8 +3273,8 @@ int Port) /* Port Index (MAC_1 + n) */ * * Returns: * SK_AND_OK o.k. - * SK_AND_DUP_CAP Duplex capability error happened - * SK_AND_OTHER Other error happened + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened */ static int SkXmAutoNegDoneNat( SK_AC *pAC, /* adapter context */ @@ -3295,8 +3295,8 @@ int Port) /* Port Index (MAC_1 + n) */ * * Returns: * SK_AND_OK o.k. - * SK_AND_DUP_CAP Duplex capability error happened - * SK_AND_OTHER Other error happened + * SK_AND_DUP_CAP Duplex capability error happened + * SK_AND_OTHER Other error happened */ int SkMacAutoNegDone( SK_AC *pAC, /* adapter context */ @@ -4323,7 +4323,7 @@ SK_U64 *pStatus) /* ptr for return overflow status value */ */ int SkGmCableDiagStatus( SK_AC *pAC, /* adapter context */ -SK_IOC IoC, /* IO context */ +SK_IOC IoC, /* IO context */ int Port, /* Port Index (MAC_1 + n) */ SK_BOOL StartTest) /* flag for start / get result */ { diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index 96ff04d36..967adddd7 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -31,7 +31,7 @@ . information under www.smsc.com. . . Authors - . Erik Stahlman ( erik@vt.edu ) + . Erik Stahlman ( erik@vt.edu ) . Daris A Nevil ( dnevil@snmc.com ) . . History @@ -56,7 +56,7 @@ void smc_set_mac_addr (const unsigned char *addr); typedef unsigned char byte; typedef unsigned short word; -typedef unsigned long int dword; +typedef unsigned long int dword; /* . DEBUGGING LEVELS @@ -77,8 +77,8 @@ typedef unsigned long int dword; #ifdef CONFIG_PXA250 #ifdef CONFIG_XSENGINE -#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) -#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1)))) +#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1)))) #define SMC_inb(p) ({ \ unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \ unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \ @@ -99,8 +99,8 @@ typedef unsigned long int dword; else ___v &= 0xff; \ ___v; }) #else -#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) -#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) #define SMC_inb(p) ({ \ unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \ unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \ @@ -149,28 +149,28 @@ typedef unsigned long int dword; } \ }) -#define SMC_insl(r,b,l) ({ int __i ; \ +#define SMC_insl(r,b,l) ({ int __i ; \ dword *__b2; \ - __b2 = (dword *) b; \ - for (__i = 0; __i < l; __i++) { \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ *(__b2 + __i) = SMC_inl(r); \ SMC_inl(0); \ }; \ }) -#define SMC_insw(r,b,l) ({ int __i ; \ +#define SMC_insw(r,b,l) ({ int __i ; \ word *__b2; \ - __b2 = (word *) b; \ - for (__i = 0; __i < l; __i++) { \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ *(__b2 + __i) = SMC_inw(r); \ SMC_inw(0); \ }; \ }) -#define SMC_insb(r,b,l) ({ int __i ; \ +#define SMC_insb(r,b,l) ({ int __i ; \ byte *__b2; \ - __b2 = (byte *) b; \ - for (__i = 0; __i < l; __i++) { \ + __b2 = (byte *) b; \ + for (__i = 0; __i < l; __i++) { \ *(__b2 + __i) = SMC_inb(r); \ SMC_inb(0); \ }; \ @@ -187,10 +187,10 @@ typedef unsigned long int dword; ((0x00FF0000UL & _x) >> 8) | \ (_x >> 24)); }) -#define SMC_inl(r) (SMC_LEON_SWAP32((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))))) -#define SMC_inl_nosw(r) ((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0)))) -#define SMC_inw(r) (SMC_LEON_SWAP16((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))))) -#define SMC_inw_nosw(r) ((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0)))) +#define SMC_inl(r) (SMC_LEON_SWAP32((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))))) +#define SMC_inl_nosw(r) ((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0)))) +#define SMC_inw(r) (SMC_LEON_SWAP16((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))))) +#define SMC_inw_nosw(r) ((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0)))) #define SMC_inb(p) ({ \ word ___v = SMC_inw((p) & ~1); \ if ((p) & 1) ___v >>= 8; \ @@ -221,7 +221,7 @@ typedef unsigned long int dword; SMC_outw_nosw( *(__b2 + __i), r); \ } \ }while(0) -#define SMC_insl(r,b,l) do{ int __i ; \ +#define SMC_insl(r,b,l) do{ int __i ; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ @@ -229,7 +229,7 @@ typedef unsigned long int dword; }; \ }while(0) -#define SMC_insw(r,b,l) do{ int __i ; \ +#define SMC_insw(r,b,l) do{ int __i ; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ @@ -237,7 +237,7 @@ typedef unsigned long int dword; }; \ }while(0) -#define SMC_insb(r,b,l) do{ int __i ; \ +#define SMC_insb(r,b,l) do{ int __i ; \ byte *__b2; \ __b2 = (byte *) b; \ for (__i = 0; __i < l; __i++) { \ @@ -253,11 +253,11 @@ typedef unsigned long int dword; */ #ifdef CONFIG_ADNPESC1 -#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1)))) +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1)))) #elif CONFIG_BLACKFIN -#define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); SSYNC(); __v;}) +#define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); SSYNC(); __v;}) #else -#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) #endif #define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF) @@ -287,12 +287,12 @@ typedef unsigned long int dword; #endif #if 0 -#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) +#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) #else -#define SMC_insw(r,b,l) ({ int __i ; \ +#define SMC_insw(r,b,l) ({ int __i ; \ word *__b2; \ - __b2 = (word *) b; \ - for (__i = 0; __i < l; __i++) { \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ *(__b2 + __i) = SMC_inw(r); \ SMC_inw(0); \ }; \ @@ -304,15 +304,15 @@ typedef unsigned long int dword; #if defined(CONFIG_SMC_USE_32_BIT) #ifdef CONFIG_XSENGINE -#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) +#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) #else -#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) #endif -#define SMC_insl(r,b,l) ({ int __i ; \ +#define SMC_insl(r,b,l) ({ int __i ; \ dword *__b2; \ - __b2 = (dword *) b; \ - for (__i = 0; __i < l; __i++) { \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ *(__b2 + __i) = SMC_inl(r); \ SMC_inl(0); \ }; \ @@ -352,21 +352,21 @@ typedef unsigned long int dword; . Bank Select Register: . . yyyy yyyy 0000 00xx - . xx = bank number + . xx = bank number . yyyy yyyy = 0x33, for identification purposes. */ #define BANK_SELECT 14 /* Transmit Control Register */ /* BANK 0 */ -#define TCR_REG 0x0000 /* transmit control register */ +#define TCR_REG 0x0000 /* transmit control register */ #define TCR_ENABLE 0x0001 /* When 1 we can transmit */ #define TCR_LOOP 0x0002 /* Controls output pin LBK */ #define TCR_FORCOL 0x0004 /* When 1 will force a collision */ #define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */ #define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */ #define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */ -#define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ +#define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ #define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */ #define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */ #define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */ @@ -374,7 +374,7 @@ typedef unsigned long int dword; #define TCR_CLEAR 0 /* do NOTHING */ /* the default settings for the TCR register : */ /* QUESTION: do I want to enable padding of short packets ? */ -#define TCR_DEFAULT TCR_ENABLE +#define TCR_DEFAULT TCR_ENABLE /* EPH Status Register */ @@ -406,7 +406,7 @@ typedef unsigned long int dword; #define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */ #define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */ #define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */ -#define RCR_SOFTRST 0x8000 /* resets the chip */ +#define RCR_SOFTRST 0x8000 /* resets the chip */ /* the normal settings for the RCR register : */ #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) @@ -507,11 +507,11 @@ typedef unsigned long int dword; #define MMU_CMD_REG 0x0000 #define MC_BUSY 1 /* When 1 the last release has not completed */ #define MC_NOP (0<<5) /* No Op */ -#define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ +#define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ #define MC_RESET (2<<5) /* Reset MMU to initial state */ -#define MC_REMOVE (3<<5) /* Remove the current rx packet */ -#define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ -#define MC_FREEPKT (5<<5) /* Release packet in PNR register */ +#define MC_REMOVE (3<<5) /* Remove the current rx packet */ +#define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ +#define MC_FREEPKT (5<<5) /* Release packet in PNR register */ #define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */ #define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */ @@ -543,7 +543,7 @@ typedef unsigned long int dword; /* BANK 2 */ #define PTR_REG 0x0006 #define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */ -#define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ +#define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ #define PTR_READ 0x2000 /* When 1 the operation is a read */ #define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */ diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index c17dcf437..5302cb522 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -79,7 +79,7 @@ static inline void reg_write(u32 addr, u32 val) #define RX_STS_MII_ERR 0x00000008 #define RX_STS_DRIBBLING 0x00000004 #define RX_STS_CRC_ERR 0x00000002 -#define RX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x44) +#define RX_STATUS_FIFO_PEEK (CONFIG_DRIVER_SMC911X_BASE + 0x44) #define TX_STATUS_FIFO (CONFIG_DRIVER_SMC911X_BASE + 0x48) #define TX_STS_TAG 0xFFFF0000 #define TX_STS_ES 0x00008000 @@ -196,9 +196,9 @@ static inline void reg_write(u32 addr, u32 val) #define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */ #define HW_CFG_TR 0x00003000 /* R/W */ #define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */ -#define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */ -#define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */ -#define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */ +#define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */ +#define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */ +#define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */ #define HW_CFG_SMI_SEL 0x00000010 /* R/W */ #define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */ #define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */ diff --git a/drivers/net/tigon3.h b/drivers/net/tigon3.h index c03347fdc..551107bc7 100644 --- a/drivers/net/tigon3.h +++ b/drivers/net/tigon3.h @@ -3238,7 +3238,7 @@ LM_VOID LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, #define REG_WR_OFFSET(pDevice, Offset, Value32) \ (((Offset >=0x200 ) && (Offset < 0x400)) || \ - ((pDevice)->EnablePciXFix == FALSE)) ? \ + ((pDevice)->EnablePciXFix == FALSE)) ? \ (void) writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset)) : \ LM_RegWrInd(pDevice, Offset, Value32) diff --git a/drivers/net/tsec.h b/drivers/net/tsec.h index 597ea1d3c..6a2338b46 100644 --- a/drivers/net/tsec.h +++ b/drivers/net/tsec.h @@ -36,9 +36,9 @@ #define MAC_ADDR_LEN 6 -/* #define TSEC_TIMEOUT 1000000 */ +/* #define TSEC_TIMEOUT 1000000 */ #define TSEC_TIMEOUT 1000 -#define TOUT_LOOP 1000000 +#define TOUT_LOOP 1000000 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */ @@ -58,12 +58,12 @@ #define MACCFG2_INIT_SETTINGS 0x00007205 #define MACCFG2_FULL_DUPLEX 0x00000001 -#define MACCFG2_IF 0x00000300 +#define MACCFG2_IF 0x00000300 #define MACCFG2_GMII 0x00000200 -#define MACCFG2_MII 0x00000100 +#define MACCFG2_MII 0x00000100 #define ECNTRL_INIT_SETTINGS 0x00001000 -#define ECNTRL_TBI_MODE 0x00000020 +#define ECNTRL_TBI_MODE 0x00000020 #define ECNTRL_R100 0x00000008 #define ECNTRL_SGMII_MODE 0x00000002 @@ -76,21 +76,21 @@ #define MIIMCFG_INIT_VALUE 0x00000003 #define MIIMCFG_RESET 0x80000000 -#define MIIMIND_BUSY 0x00000001 -#define MIIMIND_NOTVALID 0x00000004 +#define MIIMIND_BUSY 0x00000001 +#define MIIMIND_NOTVALID 0x00000004 -#define MIIM_CONTROL 0x00 +#define MIIM_CONTROL 0x00 #define MIIM_CONTROL_RESET 0x00009140 -#define MIIM_CONTROL_INIT 0x00001140 -#define MIIM_CONTROL_RESTART 0x00001340 -#define MIIM_ANEN 0x00001000 +#define MIIM_CONTROL_INIT 0x00001140 +#define MIIM_CONTROL_RESTART 0x00001340 +#define MIIM_ANEN 0x00001000 -#define MIIM_CR 0x00 +#define MIIM_CR 0x00 #define MIIM_CR_RST 0x00008000 -#define MIIM_CR_INIT 0x00001000 +#define MIIM_CR_INIT 0x00001000 #define MIIM_STATUS 0x1 -#define MIIM_STATUS_AN_DONE 0x00000020 +#define MIIM_STATUS_AN_DONE 0x00000020 #define MIIM_STATUS_LINK 0x0004 #define PHY_BMSR_AUTN_ABLE 0x0008 #define PHY_BMSR_AUTN_COMP 0x0020 @@ -120,16 +120,16 @@ #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8 /* Cicada Auxiliary Control/Status Register */ -#define MIIM_CIS8201_AUX_CONSTAT 0x1c -#define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004 -#define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020 -#define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018 -#define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010 -#define MIIM_CIS8201_AUXCONSTAT_100 0x0008 +#define MIIM_CIS8201_AUX_CONSTAT 0x1c +#define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004 +#define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020 +#define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018 +#define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010 +#define MIIM_CIS8201_AUXCONSTAT_100 0x0008 /* Cicada Extended Control Register 1 */ -#define MIIM_CIS8201_EXT_CON1 0x17 -#define MIIM_CIS8201_EXTCON1_INIT 0x0000 +#define MIIM_CIS8201_EXT_CON1 0x17 +#define MIIM_CIS8201_EXTCON1_INIT 0x0000 /* Cicada 8204 Extended PHY Control Register 1 */ #define MIIM_CIS8204_EPHY_CON 0x17 @@ -145,21 +145,21 @@ /* Entry for Vitesse VSC8244 regs starts here */ /* Vitesse VSC8244 Auxiliary Control/Status Register */ -#define MIIM_VSC8244_AUX_CONSTAT 0x1c -#define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000 -#define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020 -#define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018 -#define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010 -#define MIIM_VSC8244_AUXCONSTAT_100 0x0008 -#define MIIM_CONTROL_INIT_LOOPBACK 0x4000 +#define MIIM_VSC8244_AUX_CONSTAT 0x1c +#define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000 +#define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020 +#define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018 +#define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010 +#define MIIM_VSC8244_AUXCONSTAT_100 0x0008 +#define MIIM_CONTROL_INIT_LOOPBACK 0x4000 /* Vitesse VSC8244 Extended PHY Control Register 1 */ -#define MIIM_VSC8244_EPHY_CON 0x17 -#define MIIM_VSC8244_EPHYCON_INIT 0x0006 +#define MIIM_VSC8244_EPHY_CON 0x17 +#define MIIM_VSC8244_EPHYCON_INIT 0x0006 /* Vitesse VSC8244 Serial LED Control Register */ -#define MIIM_VSC8244_LED_CON 0x1b -#define MIIM_VSC8244_LEDCON_INIT 0xF011 +#define MIIM_VSC8244_LED_CON 0x1b +#define MIIM_VSC8244_LEDCON_INIT 0xF011 /* Entry for Vitesse VSC8601 regs starts here (Not complete) */ /* Vitesse VSC8601 Extended PHY Control Register 1 */ @@ -168,11 +168,11 @@ #define MIIM_VSC8601_SKEW_CTRL 0x1c /* 88E1011 PHY Status Register */ -#define MIIM_88E1011_PHY_STATUS 0x11 -#define MIIM_88E1011_PHYSTAT_SPEED 0xc000 -#define MIIM_88E1011_PHYSTAT_GBIT 0x8000 -#define MIIM_88E1011_PHYSTAT_100 0x4000 -#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 +#define MIIM_88E1011_PHY_STATUS 0x11 +#define MIIM_88E1011_PHYSTAT_SPEED 0xc000 +#define MIIM_88E1011_PHYSTAT_GBIT 0x8000 +#define MIIM_88E1011_PHYSTAT_100 0x4000 +#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 #define MIIM_88E1011_PHYSTAT_LINK 0x0400 @@ -189,7 +189,7 @@ #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 -#define MIIM_88E1145_PHY_PAGE 29 +#define MIIM_88E1145_PHY_PAGE 29 #define MIIM_88E1145_PHY_CAL_OV 30 /* RTL8211B PHY Status Register */ @@ -220,12 +220,12 @@ #define MIIM_DM9161_10BTCSR_INIT 0x7800 /* LXT971 Status 2 registers */ -#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */ +#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */ #define MIIM_LXT971_SR2_SPEED_MASK 0x4200 -#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */ -#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */ -#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ -#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ +#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */ +#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ /* DP83865 Control register values */ #define MIIM_DP83865_CR_INIT 0x9200 @@ -237,18 +237,18 @@ #define MIIM_DP83865_SPD_100 0x0008 #define MIIM_DP83865_DPX_FULL 0x0002 -#define MIIM_READ_COMMAND 0x00000001 +#define MIIM_READ_COMMAND 0x00000001 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN #define MINFLR_INIT_SETTINGS 0x00000040 -#define DMACTRL_INIT_SETTINGS 0x000000c3 -#define DMACTRL_GRS 0x00000010 -#define DMACTRL_GTS 0x00000008 +#define DMACTRL_INIT_SETTINGS 0x000000c3 +#define DMACTRL_GRS 0x00000010 +#define DMACTRL_GTS 0x00000008 -#define TSTAT_CLEAR_THALT 0x80000000 -#define RSTAT_CLEAR_RHALT 0x00800000 +#define TSTAT_CLEAR_THALT 0x80000000 +#define RSTAT_CLEAR_RHALT 0x00800000 #define IEVENT_INIT_CLEAR 0xffffffff @@ -274,7 +274,7 @@ #define IMASK_INIT_CLEAR 0x00000000 #define IMASK_TXEEN 0x00400000 #define IMASK_TXBEN 0x00200000 -#define IMASK_TXFEN 0x00100000 +#define IMASK_TXFEN 0x00100000 #define IMASK_RXFEN0 0x00000080 @@ -296,7 +296,7 @@ #define TXBD_RETRYLIMIT 0x0040 #define TXBD_RETRYCOUNTMASK 0x003c #define TXBD_UNDERRUN 0x0002 -#define TXBD_STATS 0x03ff +#define TXBD_STATS 0x03ff /* RxBD status field bits */ #define RXBD_EMPTY 0x8000 @@ -318,16 +318,16 @@ typedef struct txbd8 { - ushort status; /* Status Fields */ - ushort length; /* Buffer length */ - uint bufPtr; /* Buffer Pointer */ + ushort status; /* Status Fields */ + ushort length; /* Buffer length */ + uint bufPtr; /* Buffer Pointer */ } txbd8_t; typedef struct rxbd8 { - ushort status; /* Status Fields */ - ushort length; /* Buffer Length */ - uint bufPtr; /* Buffer Pointer */ + ushort status; /* Status Fields */ + ushort length; /* Buffer Length */ + uint bufPtr; /* Buffer Pointer */ } rxbd8_t; typedef struct rmon_mib @@ -431,21 +431,21 @@ typedef struct tsec /* Transmit Control and Status Registers (0x2_n100) */ uint tctrl; /* Transmit Control */ - uint tstat; /* Transmit Status */ + uint tstat; /* Transmit Status */ uint res108; uint tbdlen; /* Tx BD Data Length */ uint res110[5]; - uint ctbptr; /* Current TxBD Pointer */ + uint ctbptr; /* Current TxBD Pointer */ uint res128[23]; uint tbptr; /* TxBD Pointer */ uint res188[30]; /* (0x2_n200) */ - uint res200; + uint res200; uint tbase; /* TxBD Base Address */ uint res208[42]; uint ostbd; /* Out of Sequence TxBD */ uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */ - uint res2b8[18]; + uint res2b8[18]; /* Receive Control and Status Registers (0x2_n300) */ uint rctrl; /* Receive Control */ @@ -453,17 +453,17 @@ typedef struct tsec uint res308; uint rbdlen; /* RxBD Data Length */ uint res310[4]; - uint res320; - uint crbptr; /* Current Receive Buffer Pointer */ + uint res320; + uint crbptr; /* Current Receive Buffer Pointer */ uint res328[6]; - uint mrblr; /* Maximum Receive Buffer Length */ + uint mrblr; /* Maximum Receive Buffer Length */ uint res344[16]; - uint rbptr; /* RxBD Pointer */ - uint res388[30]; + uint rbptr; /* RxBD Pointer */ + uint res388[30]; /* (0x2_n400) */ - uint res400; - uint rbase; /* RxBD Base Address */ - uint res408[62]; + uint res400; + uint rbase; /* RxBD Base Address */ + uint res408[62]; /* MAC Registers (0x2_n500) */ uint maccfg1; /* MAC Configuration #1 */ @@ -500,12 +500,12 @@ typedef struct tsec /* Hash Function Registers (0x2_n800) */ tsec_hash_t hash; - uint res900[128]; + uint res900[128]; /* Pattern Registers (0x2_nb00) */ - uint resb00[62]; - uint attr; /* Default Attribute Register */ - uint attreli; /* Default Attribute Extract Length and Index */ + uint resb00[62]; + uint attr; /* Default Attribute Register */ + uint attreli; /* Default Attribute Extract Length and Index */ /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */ uint resc00[256]; @@ -535,18 +535,18 @@ struct tsec_private { * mii_reg: The register to read or write * * mii_data: For writes, the value to put in the register. - * A value of -1 indicates this is a read. + * A value of -1 indicates this is a read. * * funct: A function pointer which is invoked for each command. - * For reads, this function will be passed the value read + * For reads, this function will be passed the value read * from the PHY, and process it. * For writes, the result of this function will be written * to the PHY register */ struct phy_cmd { - uint mii_reg; - uint mii_data; - uint (*funct) (uint mii_reg, struct tsec_private* priv); + uint mii_reg; + uint mii_data; + uint (*funct) (uint mii_reg, struct tsec_private * priv); }; /* struct phy_info: a structure which defines attributes for a PHY @@ -562,18 +562,18 @@ struct phy_cmd { * commands which tell the driver what to do to the PHY. */ struct phy_info { - uint id; - char *name; - uint shift; - /* Called to configure the PHY, and modify the controller - * based on the results */ - struct phy_cmd *config; + uint id; + char *name; + uint shift; + /* Called to configure the PHY, and modify the controller + * based on the results */ + struct phy_cmd *config; - /* Called when starting up the controller */ - struct phy_cmd *startup; + /* Called when starting up the controller */ + struct phy_cmd *startup; - /* Called when bringing down the controller */ - struct phy_cmd *shutdown; + /* Called when bringing down the controller */ + struct phy_cmd *shutdown; }; #endif /* __TSEC_H */ diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c index d64845fec..79d29ae82 100644 --- a/drivers/net/uli526x.c +++ b/drivers/net/uli526x.c @@ -412,7 +412,7 @@ static void uli526x_init(struct eth_device *dev) } /* Media Mode Process */ if (!(db->media_mode & ULI526X_AUTO)) - db->op_mode = db->media_mode; /* Force Mode */ + db->op_mode = db->media_mode; /* Force Mode */ /* Initialize Transmit/Receive decriptor and CR3/4 */ uli526x_descriptor_init(db, db->ioaddr); |