diff options
Diffstat (limited to 'drivers/i2c')
| -rw-r--r-- | drivers/i2c/Makefile | 2 | ||||
| -rw-r--r-- | drivers/i2c/davinci_i2c.c | 4 | ||||
| -rw-r--r-- | drivers/i2c/fsl_i2c.c | 2 | ||||
| -rw-r--r-- | drivers/i2c/mxs_i2c.c | 246 | ||||
| -rw-r--r-- | drivers/i2c/sh_i2c.c | 292 |
5 files changed, 542 insertions, 4 deletions
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index a48047a4f..504db03c7 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -31,6 +31,7 @@ COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o COBJS-$(CONFIG_I2C_MV) += mv_i2c.o COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o +COBJS-$(CONFIG_I2C_MXS) += mxs_i2c.o COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o @@ -42,6 +43,7 @@ COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o +COBJS-$(CONFIG_SH_I2C) += sh_i2c.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c index 5e3406dc8..2abddfb6f 100644 --- a/drivers/i2c/davinci_i2c.c +++ b/drivers/i2c/davinci_i2c.c @@ -78,13 +78,11 @@ static int poll_i2c_irq(int mask) void flush_rx(void) { - int dummy; - while (1) { if (!(REG(I2C_STAT) & I2C_STAT_RRDY)) break; - dummy = REG(I2C_DRR); + REG(I2C_DRR); REG(I2C_STAT) = I2C_STAT_RRDY; udelay(1000); } diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 258be0a90..5b017a910 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -225,7 +225,7 @@ unsigned int get_i2c_clock(int bus) void i2c_init(int speed, int slaveadd) { - struct fsl_i2c *dev; + const struct fsl_i2c *dev; unsigned int temp; int bus_num, i; diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c new file mode 100644 index 000000000..c8fea3235 --- /dev/null +++ b/drivers/i2c/mxs_i2c.c @@ -0,0 +1,246 @@ +/* + * Freescale i.MX28 I2C Driver + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Partly based on Linux kernel i2c-mxs.c driver: + * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K. + * + * Which was based on a (non-working) driver which was: + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> +#include <malloc.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +#define MXS_I2C_MAX_TIMEOUT 1000000 + +void mxs_i2c_reset(void) +{ + struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE; + int ret; + + ret = mx28_reset_block(&i2c_regs->hw_i2c_ctrl0_reg); + if (ret) { + debug("MXS I2C: Block reset timeout\n"); + return; + } + + writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ | + I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ | + I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ, + &i2c_regs->hw_i2c_ctrl1_clr); + + writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set); +} + +void mxs_i2c_setup_read(uint8_t chip, int len) +{ + struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE; + + writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START | + I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION | + (1 << I2C_QUEUECMD_XFER_COUNT_OFFSET), + &i2c_regs->hw_i2c_queuecmd); + + writel((chip << 1) | 1, &i2c_regs->hw_i2c_data); + + writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE | + (len << I2C_QUEUECMD_XFER_COUNT_OFFSET) | + I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd); + + writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); +} + +void mxs_i2c_write(uchar chip, uint addr, int alen, + uchar *buf, int blen, int stop) +{ + struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE; + uint32_t data; + int i, remain, off; + + if ((alen > 4) || (alen == 0)) { + debug("MXS I2C: Invalid address length\n"); + return; + } + + if (stop) + stop = I2C_QUEUECMD_POST_SEND_STOP; + + writel(I2C_QUEUECMD_PRE_SEND_START | + I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION | + ((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop, + &i2c_regs->hw_i2c_queuecmd); + + data = (chip << 1) << 24; + + for (i = 0; i < alen; i++) { + data >>= 8; + data |= ((char *)&addr)[i] << 24; + if ((i & 3) == 2) + writel(data, &i2c_regs->hw_i2c_data); + } + + off = i; + for (; i < off + blen; i++) { + data >>= 8; + data |= buf[i - off] << 24; + if ((i & 3) == 2) + writel(data, &i2c_regs->hw_i2c_data); + } + + remain = 24 - ((i & 3) * 8); + if (remain) + writel(data >> remain, &i2c_regs->hw_i2c_data); + + writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); +} + +int mxs_i2c_wait_for_ack(void) +{ + struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE; + uint32_t tmp; + int timeout = MXS_I2C_MAX_TIMEOUT; + + for (;;) { + tmp = readl(&i2c_regs->hw_i2c_ctrl1); + if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) { + debug("MXS I2C: No slave ACK\n"); + goto err; + } + + if (tmp & ( + I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ | + I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) { + debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp); + goto err; + } + + if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ) + break; + + if (!timeout--) { + debug("MXS I2C: Operation timed out\n"); + goto err; + } + + udelay(1); + } + + return 0; + +err: + mxs_i2c_reset(); + return 1; +} + +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE; + uint32_t tmp = 0; + int ret; + int i; + + mxs_i2c_write(chip, addr, alen, NULL, 0, 0); + ret = mxs_i2c_wait_for_ack(); + if (ret) { + debug("MXS I2C: Failed writing address\n"); + return ret; + } + + mxs_i2c_setup_read(chip, len); + ret = mxs_i2c_wait_for_ack(); + if (ret) { + debug("MXS I2C: Failed reading address\n"); + return ret; + } + + for (i = 0; i < len; i++) { + if (!(i & 3)) { + while (readl(&i2c_regs->hw_i2c_queuestat) & + I2C_QUEUESTAT_RD_QUEUE_EMPTY) + ; + tmp = readl(&i2c_regs->hw_i2c_queuedata); + } + buffer[i] = tmp & 0xff; + tmp >>= 8; + } + + return 0; +} + +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int ret; + mxs_i2c_write(chip, addr, alen, buffer, len, 1); + ret = mxs_i2c_wait_for_ack(); + if (ret) + debug("MXS I2C: Failed writing address\n"); + + return ret; +} + +int i2c_probe(uchar chip) +{ + int ret; + mxs_i2c_write(chip, 0, 1, NULL, 0, 1); + ret = mxs_i2c_wait_for_ack(); + mxs_i2c_reset(); + return ret; +} + +void i2c_init(int speed, int slaveadd) +{ + struct mx28_i2c_regs *i2c_regs = (struct mx28_i2c_regs *)MXS_I2C0_BASE; + + mxs_i2c_reset(); + + switch (speed) { + case 100000: + writel((0x0078 << I2C_TIMING0_HIGH_COUNT_OFFSET) | + (0x0030 << I2C_TIMING0_RCV_COUNT_OFFSET), + &i2c_regs->hw_i2c_timing0); + writel((0x0080 << I2C_TIMING1_LOW_COUNT_OFFSET) | + (0x0030 << I2C_TIMING1_XMIT_COUNT_OFFSET), + &i2c_regs->hw_i2c_timing1); + break; + case 400000: + writel((0x000f << I2C_TIMING0_HIGH_COUNT_OFFSET) | + (0x0007 << I2C_TIMING0_RCV_COUNT_OFFSET), + &i2c_regs->hw_i2c_timing0); + writel((0x001f << I2C_TIMING1_LOW_COUNT_OFFSET) | + (0x000f << I2C_TIMING1_XMIT_COUNT_OFFSET), + &i2c_regs->hw_i2c_timing1); + break; + default: + printf("MXS I2C: Invalid speed selected (%d Hz)\n", speed); + return; + } + + writel((0x0015 << I2C_TIMING2_BUS_FREE_OFFSET) | + (0x000d << I2C_TIMING2_LEADIN_COUNT_OFFSET), + &i2c_regs->hw_i2c_timing2); + + return; +} diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c new file mode 100644 index 000000000..fd8cb9285 --- /dev/null +++ b/drivers/i2c/sh_i2c.c @@ -0,0 +1,292 @@ +/* + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> + +/* Every register is 32bit aligned, but only 8bits in size */ +#define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1; +struct sh_i2c { + ureg(icdr); + ureg(iccr); + ureg(icsr); + ureg(icic); + ureg(iccl); + ureg(icch); +}; +#undef ureg + +static struct sh_i2c *base; + +/* ICCR */ +#define SH_I2C_ICCR_ICE (1 << 7) +#define SH_I2C_ICCR_RACK (1 << 6) +#define SH_I2C_ICCR_RTS (1 << 4) +#define SH_I2C_ICCR_BUSY (1 << 2) +#define SH_I2C_ICCR_SCP (1 << 0) + +/* ICSR / ICIC */ +#define SH_IC_BUSY (1 << 3) +#define SH_IC_TACK (1 << 2) +#define SH_IC_WAIT (1 << 1) +#define SH_IC_DTE (1 << 0) + +static u8 iccl, icch; + +#define IRQ_WAIT 1000 + +static void irq_wait(struct sh_i2c *base) +{ + int i; + u8 status; + + for (i = 0 ; i < IRQ_WAIT ; i++) { + status = readb(&base->icsr); + if (SH_IC_WAIT & status) + break; + + udelay(10); + } + + writeb(status & ~SH_IC_WAIT, &base->icsr); +} + +static void irq_dte(struct sh_i2c *base) +{ + int i; + + for (i = 0 ; i < IRQ_WAIT ; i++) { + if (SH_IC_DTE & readb(&base->icsr)) + break; + udelay(10); + } +} + +static void irq_busy(struct sh_i2c *base) +{ + int i; + + for (i = 0 ; i < IRQ_WAIT ; i++) { + if (!(SH_IC_BUSY & readb(&base->icsr))) + break; + udelay(10); + } +} + +static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) +{ + writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); + writeb(readb(&base->iccr) | SH_I2C_ICCR_ICE, &base->iccr); + + writeb(iccl, &base->iccl); + writeb(icch, &base->icch); + writeb(0, &base->icic); + + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); + irq_dte(base); + + writeb(id << 1, &base->icdr); + irq_dte(base); + + writeb(reg, &base->icdr); + if (stop) + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr); + + irq_dte(base); +} + +static void i2c_finish(struct sh_i2c *base) +{ + writeb(0, &base->icsr); + writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); +} + +static void i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val) +{ + i2c_set_addr(base, id, reg, 0); + udelay(10); + + writeb(val, &base->icdr); + irq_dte(base); + + writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr); + irq_dte(base); + irq_busy(base); + + i2c_finish(base); +} + +static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) +{ + u8 ret; + + i2c_set_addr(base, id, reg, 1); + udelay(100); + + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); + irq_dte(base); + + writeb(id << 1 | 0x01, &base->icdr); + irq_dte(base); + + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr); + irq_dte(base); + + ret = readb(&base->icdr); + + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr); + readb(&base->icdr); /* Dummy read */ + irq_busy(base); + + i2c_finish(base); + + return ret; +} + +#ifdef CONFIG_I2C_MULTI_BUS +static unsigned int current_bus; + +/** + * i2c_set_bus_num - change active I2C bus + * @bus: bus index, zero based + * @returns: 0 on success, non-0 on failure + */ +int i2c_set_bus_num(unsigned int bus) +{ + if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) { + printf("Bad bus: %d\n", bus); + return -1; + } + + switch (bus) { + case 0: + base = (void *)CONFIG_SH_I2C_BASE0; + break; + case 1: + base = (void *)CONFIG_SH_I2C_BASE1; + break; + default: + return -1; + } + current_bus = bus; + + return 0; +} + +/** + * i2c_get_bus_num - returns index of active I2C bus + */ +unsigned int i2c_get_bus_num(void) +{ + return current_bus; +} +#endif + +#define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \ + ((clk / rate) * (t_low / t_low + t_high)) +#define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \ + ((clk / rate) * (t_high / t_low + t_high)) + +void i2c_init(int speed, int slaveaddr) +{ + int num, denom, tmp; + +#ifdef CONFIG_I2C_MULTI_BUS + current_bus = 0; +#endif + base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0; + + /* + * Calculate the value for iccl. From the data sheet: + * iccl = (p-clock / transfer-rate) * (L / (L + H)) + * where L and H are the SCL low and high ratio. + */ + num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW; + denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW); + tmp = num * 10 / denom; + if (tmp % 10 >= 5) + iccl = (u8)((num/denom) + 1); + else + iccl = (u8)(num/denom); + + /* Calculate the value for icch. From the data sheet: + icch = (p clock / transfer rate) * (H / (L + H)) */ + num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH; + tmp = num * 10 / denom; + if (tmp % 10 >= 5) + icch = (u8)((num/denom) + 1); + else + icch = (u8)(num/denom); +} + +/* + * i2c_read: - Read multiple bytes from an i2c device + * + * The higher level routines take into account that this function is only + * called with len < page length of the device (see configuration file) + * + * @chip: address of the chip which is to be read + * @addr: i2c data address within the chip + * @alen: length of the i2c data address (1..2 bytes) + * @buffer: where to write the data + * @len: how much byte do we want to read + * @return: 0 in case of success + */ +int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len) +{ + int i = 0; + for (i = 0 ; i < len ; i++) + buffer[i] = i2c_raw_read(base, chip, addr + i); + + return 0; +} + +/* + * i2c_write: - Write multiple bytes to an i2c device + * + * The higher level routines take into account that this function is only + * called with len < page length of the device (see configuration file) + * + * @chip: address of the chip which is to be written + * @addr: i2c data address within the chip + * @alen: length of the i2c data address (1..2 bytes) + * @buffer: where to find the data to be written + * @len: how much byte do we want to read + * @return: 0 in case of success + */ +int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) +{ + int i = 0; + for (i = 0; i < len ; i++) + i2c_raw_write(base, chip, addr + i, buffer[i]); + + return 0; +} + +/* + * i2c_probe: - Test if a chip answers for a given i2c address + * + * @chip: address of the chip which is searched for + * @return: 0 if a chip was found, -1 otherwhise + */ +int i2c_probe(u8 chip) +{ + return 0; +} |