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Diffstat (limited to 'drivers/fsl_i2c.c')
-rw-r--r--drivers/fsl_i2c.c122
1 files changed, 87 insertions, 35 deletions
diff --git a/drivers/fsl_i2c.c b/drivers/fsl_i2c.c
index 65c27439e..c92909608 100644
--- a/drivers/fsl_i2c.c
+++ b/drivers/fsl_i2c.c
@@ -28,29 +28,52 @@
#include <asm/fsl_i2c.h> /* HW definitions */
#define I2C_TIMEOUT (CFG_HZ / 4)
-#define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET))
+#define I2C_READ_BIT 1
+#define I2C_WRITE_BIT 0
+
+/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
+ * Default is bus 0. This is necessary because the DDR initialization
+ * runs from ROM, and we can't switch buses because we can't modify
+ * the global variables.
+ */
+#ifdef CFG_SPD_BUS_NUM
+static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
+#else
+static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
+#endif
+
+static volatile struct fsl_i2c *i2c_dev[2] = {
+ (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET),
+#ifdef CFG_I2C2_OFFSET
+ (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET)
+#endif
+};
void
i2c_init(int speed, int slaveadd)
{
- /* stop I2C controller */
- writeb(0x0, &I2C->cr);
+ volatile struct fsl_i2c *dev;
- /* set clock */
- writeb(0x3f, &I2C->fdr);
+ dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET);
- /* set default filter */
- writeb(0x10, &I2C->dfsrr);
+ writeb(0, &dev->cr); /* stop I2C controller */
+ writeb(0x3F, &dev->fdr); /* set bus speed */
+ writeb(0x3F, &dev->dfsrr); /* set default filter */
+ writeb(slaveadd << 1, &dev->adr); /* write slave address */
+ writeb(0x0, &dev->sr); /* clear status register */
+ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
- /* write slave address */
- writeb(slaveadd, &I2C->adr);
+#ifdef CFG_I2C2_OFFSET
+ dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET);
- /* clear status register */
- writeb(0x0, &I2C->sr);
-
- /* start I2C controller */
- writeb(I2C_CR_MEN, &I2C->cr);
+ writeb(0, &dev->cr); /* stop I2C controller */
+ writeb(0x3F, &dev->fdr); /* set bus speed */
+ writeb(0x3F, &dev->dfsrr); /* set default filter */
+ writeb(slaveadd, &dev->adr); /* write slave address */
+ writeb(0x0, &dev->sr); /* clear status register */
+ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
+#endif /* CFG_I2C2_OFFSET */
}
static __inline__ int
@@ -58,7 +81,7 @@ i2c_wait4bus(void)
{
ulong timeval = get_timer(0);
- while (readb(&I2C->sr) & I2C_SR_MBB) {
+ while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
if (get_timer(timeval) > I2C_TIMEOUT) {
return -1;
}
@@ -74,11 +97,11 @@ i2c_wait(int write)
ulong timeval = get_timer(0);
do {
- csr = readb(&I2C->sr);
+ csr = readb(&i2c_dev[i2c_bus_num]->sr);
if (!(csr & I2C_SR_MIF))
continue;
- writeb(0x0, &I2C->sr);
+ writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
if (csr & I2C_SR_MAL) {
debug("i2c_wait: MAL\n");
@@ -90,7 +113,7 @@ i2c_wait(int write)
return -1;
}
- if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) {
+ if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
debug("i2c_wait: No RXACK\n");
return -1;
}
@@ -107,11 +130,11 @@ i2c_write_addr (u8 dev, u8 dir, int rsta)
{
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
| (rsta ? I2C_CR_RSTA : 0),
- &I2C->cr);
+ &i2c_dev[i2c_bus_num]->cr);
- writeb((dev << 1) | dir, &I2C->dr);
+ writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
- if (i2c_wait(I2C_WRITE) < 0)
+ if (i2c_wait(I2C_WRITE_BIT) < 0)
return 0;
return 1;
@@ -123,12 +146,12 @@ __i2c_write(u8 *data, int length)
int i;
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
- &I2C->cr);
+ &i2c_dev[i2c_bus_num]->cr);
for (i = 0; i < length; i++) {
- writeb(data[i], &I2C->dr);
+ writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
- if (i2c_wait(I2C_WRITE) < 0)
+ if (i2c_wait(I2C_WRITE_BIT) < 0)
break;
}
@@ -141,25 +164,25 @@ __i2c_read(u8 *data, int length)
int i;
writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
- &I2C->cr);
+ &i2c_dev[i2c_bus_num]->cr);
/* dummy read */
- readb(&I2C->dr);
+ readb(&i2c_dev[i2c_bus_num]->dr);
for (i = 0; i < length; i++) {
- if (i2c_wait(I2C_READ) < 0)
+ if (i2c_wait(I2C_READ_BIT) < 0)
break;
/* Generate ack on last next to last byte */
if (i == length - 2)
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
- &I2C->cr);
+ &i2c_dev[i2c_bus_num]->cr);
/* Generate stop on last byte */
if (i == length - 1)
- writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr);
+ writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr);
- data[i] = readb(&I2C->dr);
+ data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
}
return i;
@@ -172,13 +195,13 @@ i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
u8 *a = (u8*)&addr;
if (i2c_wait4bus() >= 0
- && i2c_write_addr(dev, I2C_WRITE, 0) != 0
+ && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
&& __i2c_write(&a[4 - alen], alen) == alen
- && i2c_write_addr(dev, I2C_READ, 1) != 0) {
+ && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) {
i = __i2c_read(data, length);
}
- writeb(I2C_CR_MEN, &I2C->cr);
+ writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
if (i == length)
return 0;
@@ -193,12 +216,12 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
u8 *a = (u8*)&addr;
if (i2c_wait4bus() >= 0
- && i2c_write_addr(dev, I2C_WRITE, 0) != 0
+ && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
&& __i2c_write(&a[4 - alen], alen) == alen) {
i = __i2c_write(data, length);
}
- writeb(I2C_CR_MEN, &I2C->cr);
+ writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
if (i == length)
return 0;
@@ -237,5 +260,34 @@ i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
i2c_write(i2c_addr, reg, 1, &val, 1);
}
+int i2c_set_bus_num(unsigned int bus)
+{
+#ifdef CFG_I2C2_OFFSET
+ if (bus > 1) {
+#else
+ if (bus > 0) {
+#endif
+ return -1;
+ }
+
+ i2c_bus_num = bus;
+
+ return 0;
+}
+
+int i2c_set_bus_speed(unsigned int speed)
+{
+ return -1;
+}
+
+unsigned int i2c_get_bus_num(void)
+{
+ return i2c_bus_num;
+}
+
+unsigned int i2c_get_bus_speed(void)
+{
+ return 0;
+}
#endif /* CONFIG_HARD_I2C */
#endif /* CONFIG_FSL_I2C */
generated by cgit v1.2.3-70-g09d2 (git 2.51.2) at 2025-10-31 11:10:07 +0000