diff options
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.SPL | 62 | ||||
| -rw-r--r-- | doc/README.m68k | 4 | ||||
| -rw-r--r-- | doc/README.p2041rdb | 123 | ||||
| -rw-r--r-- | doc/README.qemu_mips | 2 | ||||
| -rw-r--r-- | doc/README.ublimage | 141 | ||||
| -rw-r--r-- | doc/README.update | 5 |
6 files changed, 334 insertions, 3 deletions
diff --git a/doc/README.SPL b/doc/README.SPL new file mode 100644 index 000000000..ce8e19fb7 --- /dev/null +++ b/doc/README.SPL @@ -0,0 +1,62 @@ +Generic SPL framework +===================== + +Overview +-------- + +To unify all existing implementations for a secondary program loader (SPL) +and to allow simply adding of new implementations this generic SPL framework +has been created. With this framework almost all source files for a board +can be reused. No code duplication or symlinking is necessary anymore. + + +How it works +------------ + +There is a new directory TOPDIR/spl which contains only a Makefile. +The object files are built separately for SPL and placed in this directory. +The final binaries which are generated are u-boot-spl, u-boot-spl.bin and +u-boot-spl.map. + +During the SPL build a variable named CONFIG_SPL_BUILD is exported +in the make environment and also appended to CPPFLAGS with -DCONFIG_SPL_BUILD. +Source files can therefore be compiled for SPL with different settings. +ARM-based boards have previously used the option CONFIG_PRELOADER for it. + +For example: + +ifeq ($(CONFIG_SPL_BUILD),y) +COBJS-y += board_spl.o +else +COBJS-y += board.o +endif + +COBJS-$(CONFIG_SPL_BUILD) += foo.o + +#ifdef CONFIG_SPL_BUILD + foo(); +#endif + + +The building of SPL images can be with: + +#define CONFIG_SPL + +Because SPL images normally have a different text base, one have to be +configured by defining CONFIG_SPL_TEXT_BASE. The linker script have to be +defined with CONFIG_SPL_LDSCRIPT. + +To support generic U-Boot libraries and drivers in the SPL binary one can +optionally define CONFIG_SPL_XXX_SUPPORT. Currently following options +are supported: + +CONFIG_SPL_LIBCOMMON_SUPPORT (common/libcommon.o) +CONFIG_SPL_LIBDISK_SUPPORT (disk/libdisk.o) +CONFIG_SPL_I2C_SUPPORT (drivers/i2c/libi2c.o) +CONFIG_SPL_GPIO_SUPPORT (drivers/gpio/libgpio.o) +CONFIG_SPL_MMC_SUPPORT (drivers/mmc/libmmc.o) +CONFIG_SPL_SERIAL_SUPPORT (drivers/serial/libserial.o) +CONFIG_SPL_SPI_FLASH_SUPPORT (drivers/mtd/spi/libspi_flash.o) +CONFIG_SPL_SPI_SUPPORT (drivers/spi/libspi.o) +CONFIG_SPL_FAT_SUPPORT (fs/fat/libfat.o) +CONFIG_SPL_LIBGENERIC_SUPPORT (lib/libgeneric.o) diff --git a/doc/README.m68k b/doc/README.m68k index 3766b33bd..c85febc1f 100644 --- a/doc/README.m68k +++ b/doc/README.m68k @@ -111,7 +111,7 @@ CONFIG_SYS_MBAR -- defines the base address of the MCF5272 configuration registe CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5272 internal SRAM CONFIG_SYS_ENET_BD_BASE - -- defines the base addres of the FEC buffer descriptors + -- defines the base address of the FEC buffer descriptors CONFIG_SYS_SCR -- defines the contents of the System Configuration Register CONFIG_SYS_SPR -- defines the contents of the System Protection Register @@ -138,7 +138,7 @@ CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_INT_FLASH_BASE -- defines the base address of the MCF5282 internal Flash memory CONFIG_SYS_ENET_BD_BASE - -- defines the base addres of the FEC buffer descriptors + -- defines the base address of the FEC buffer descriptors CONFIG_SYS_MFD -- defines the PLL Multiplication Factor Devider diff --git a/doc/README.p2041rdb b/doc/README.p2041rdb new file mode 100644 index 000000000..292d0d39c --- /dev/null +++ b/doc/README.p2041rdb @@ -0,0 +1,123 @@ +Overview +========= +The P2041 Processor combines four Power Architecture processor cores +with high-performance datapath acceleration architecture(DPAA), CoreNet +fabric infrastructure, as well as network and peripheral bus interfaces +required for networking, telecom/datacom, wireless infrastructure, and +military/aerospace applications. + +P2041RDB board is a quad core platform supporting the P2041 processor +of QorIQ DPAA series. + +Boot from NOR flash +=================== +1. Build image + make P2041RDB_config + make all + +2. Program image + => tftp 1000000 u-boot.bin + => protect off all + => erase eff80000 efffffff + => cp.b 1000000 eff80000 80000 + +3. Program RCW + => tftp 1000000 rcw.bin + => protect off all + => erase e8000000 e801ffff + => cp.b 1000000 e8000000 50 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => protect off all + => erase ef000000 ef0fffff + => cp.b 1000000 ef000000 2000 + +5. Change DIP-switch + SW1[1-5] = 10110 + Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SDCard +=================== +1. Build image + make P2041RDB_SDCARD_config + make all + +2. Generate PBL imge + Use PE tool to produce a image used to be programed to + SDCard which contains RCW and U-Boot image. + +3. Program the PBL image to SDCard + => tftp 1000000 pbl_sd.bin + => mmcinfo + => mmc write 1000000 8 441 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => mmc write 1000000 46a 10 + +5. Change DIP-switch + SW1[1-5] = 01100 + Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SPI flash +=================== +1. Build image + make P2041RDB_SPIFLASH_config + make all + +2. Generate PBL imge + Use PE tool to produce a image used to be programed to + SPI flash which contains RCW and U-Boot image. + +3. Program the PBL image to SPI flash + => tftp 1000000 pbl_spi.bin + => spi probe 0 + => sf erase 0 100000 + => sf write 1000000 0 $filesize + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => sf erase 110000 10000 + => sf write 1000000 110000 $filesize + +5. Change DIP-switch + SW1[1-5] = 10100 + Note: 1 stands for 'on', 0 stands for 'off' + +CPLD command +============ +The CPLD is used to control the power sequence and some serdes lane +mux function. + +cpld reset - hard reset to default bank +cpld reset altbank - reset to alternate bank +cpld lane_mux <lane> <mux_value> - set multiplexed lane pin + lane 6: 0 -> slot1 (Default) + 1 -> SGMII + lane a: 0 -> slot2 (Default) + 1 -> AURORA + lane c: 0 -> slot2 (Default) + 1 -> SATA0 + lane d: 0 -> slot2 (Default) + 1 -> SATA1 + +Using the Device Tree Source File +================================= +To create the DTB (Device Tree Binary) image file, use a command +similar to this: + dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb + +Or use the following command: + {linux-2.6}/make p2041rdb.dtb ARCH=powerpc + +then the dtb file will be generated under the following directory: + {linux-2.6}/arch/powerpc/boot/p2041rdb.dtb + +Booting Linux +============= +Place a linux uImage in the TFTP disk area. + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp 3000000 p2041rdb.dtb + bootm 1000000 2000000 3000000 diff --git a/doc/README.qemu_mips b/doc/README.qemu_mips index 398526424..e6a385573 100644 --- a/doc/README.qemu_mips +++ b/doc/README.qemu_mips @@ -24,7 +24,7 @@ you can downland #config to build the kernel qemu_mips_defconfig -#patch to fix mips interupt init on 2.6.24.y kernel +#patch to fix mips interrupt init on 2.6.24.y kernel qemu_mips_kernel.patch initrd.gz vmlinux diff --git a/doc/README.ublimage b/doc/README.ublimage new file mode 100644 index 000000000..add24d649 --- /dev/null +++ b/doc/README.ublimage @@ -0,0 +1,141 @@ +--------------------------------------------- +UBL image Boot Image generation using mkimage +--------------------------------------------- + +This document describes how to set up an U-Boot image that can be directly +booted by a DaVinci processor via NAND boot mode, using an UBL header, +but without need for UBL. + +For more details see section 11.2 "ARM ROM Boot Modes" of +http://focus.ti.com/lit/ug/sprufg5a/sprufg5a.pdf + +Command syntax: +-------------- +./tools/mkimage -l <u-boot_file> + to list the UBL image file details + +./tools/mkimage -T ublimage \ + -n <board specific configuration file> \ + -d <u-boot binary> <output image file> + +For example, for the davinci dm365evm board: +./tools/mkimage -n ./board/davinci/dm365evm/ublimage.cfg \ + -T ublimage \ + -d u-boot-nand.bin u-boot.ubl + +You can generate the image directly when you compile u-boot with: + +$ make u-boot.ubl + +The output image can be flashed into the NAND. + +Please check the DaVinci documentation for further details. + +Board specific configuration file specifications: +------------------------------------------------- +1. This file must present in the $(BOARDDIR) and the name should be + ublimage.cfg (since this is used in Makefile). +2. This file can have empty lines and lines starting with "#" as first + character to put comments. +3. This file can have configuration command lines as mentioned below, + any other information in this file is treated as invalid. + +Configuration command line syntax: +--------------------------------- +1. Each command line must have two strings, first one command or address + and second one data string +2. Following are the valid command strings and associated data strings:- + Command string data string + -------------- ----------- + MODE UBL special mode, on of: + safe + Example: + MODE safe + + ENTRY Entry point address for the user + bootloader (absolute address) = TEXT_BASE + nand_spl loader. + Example: + ENTRY 0x00000020 + + PAGES Number of pages (size of user bootloader + in number of pages) + Example: + PAGES 27 + + START_BLOCK Block number where user bootloader is present + Example: + START_BLOCK 5 + + START_PAGE Page number where user bootloader is present + (for RBL always 0) + Example: + START_PAGE 0 + +------------------------------------------------ + +Structure of the u-boot.ubl binary: + +compile steps: + +1) nand_spl code compile, with pad_to = (TEXT_BASE + + (CONFIG_SYS_NROF_PAGES_NAND_SPL * pagesize)) + Example: cam_enc_4xx pad_to = 0x20 + (6 * 0x800) = 0x3020 = 12320 + -> u-boot-spl-16k.bin + + !! TEXT_BASE = 0x20, as the RBL starts at 0x20 + +2) compile u-boot.bin ("normal" u-boot) + -> u-boot.bin + +3) create u-boot-nand.bin = u-boot-spl-16k.bin + u-boot.bin + +4) create u-boot.ubl, size = 1 page size NAND + create UBL header and paste it before u-boot.bin + +This steps are done automagically if you do a "make all" + +-> You get an u-boot.ubl binary, which you can flash + into your NAND. + +Structure of this binary (Example for the cam_enc_4xx board with a NAND +page size = 0x800): + +offset : 0x00000 | 0x800 | 0x3800 +content: UBL | nand_spl | u-boot code + Header | code | + +The NAND layout looks for example like this: + +(Example for the cam_enc_4xx board with a NAND page size = 0x800, block +size = 0x20000 and CONFIG_SYS_NROF_UBL_HEADER 5): + +offset : 0x80000 | 0xa0000 | 0xa3000 +content: UBL | nand_spl | u-boot code + Header | code | + ^ ^ + ^ 0xa0000 = CONFIG_SYS_NROF_UBL_HEADER * 0x20000 + ^ + 0x80000 = Block 4 * 0x20000 + +If the cpu starts in NAND boot mode, it checks the UBL descriptor +starting with block 1 (page 0). When a valid UBL signature is found, +the corresponding block number (from 1 to 24) is written to the last 32 +bits of ARM internal memory (0x7ffc-0x8000). This feature is provided +as a basic debug mechanism. If not found, it continues with block 2 +... last possible block is 24 + +If a valid UBL descriptor is found, the UBL descriptor is read and +processed. The descriptor gives the information required for loading +and control transfer to the nand_spl code. The nand_spl code is then +read and processed. + +Once the user-specified start-up conditions are set, the RBL copies the +nand_spl into ARM internal RAM, starting at address 0x0000: 0020. + ^^^^ + +The nand_spl code itself now does necessary intializations, and at least, +copies the u-boot code from NAND into RAM, and jumps to it ... + +------------------------------------------------ +Author: Heiko Schocher <hs@denx.de> diff --git a/doc/README.update b/doc/README.update index 48f03b780..a7f4d9ebe 100644 --- a/doc/README.update +++ b/doc/README.update @@ -51,6 +51,11 @@ the mkimage tool. dtc tool with support for binary includes, e.g. in version to be prepared. Refer to the doc/uImage.FIT/ directory for more details on FIT images. +This mechanism can be also triggered by the commmand "fitupd". +If an optional, non-zero address is provided as argument, the TFTP transfer +is skipped and the image at this address is used. +The fitupd command is enabled by CONFIG_CMD_FITUPD. + Example .its files ------------------ |