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Diffstat (limited to 'doc/README.fsl-ddr')
| -rw-r--r-- | doc/README.fsl-ddr | 39 |
1 files changed, 28 insertions, 11 deletions
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 9c2224fea..e108a0d50 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -27,43 +27,60 @@ Table of interleaving modes supported in cpu/8xxx/ddr/ from each controller. {CS2+CS3} on each controller are only rank interleaved on that controller. + For memory controller interleaving, identical DIMMs are suggested. Software + doesn't check the size or organization of interleaved DIMMs. + The ways to configure the ddr interleaving mode ============================================== 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting under "CONFIG_EXTRA_ENV_SETTINGS", like: #define CONFIG_EXTRA_ENV_SETTINGS \ - "memctl_intlv_ctl=2\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=bank" \ ...... 2. Run u-boot "setenv" command to configure the memory interleaving mode. Either numerical or string value is accepted. # disable memory controller interleaving - setenv memctl_intlv_ctl + setenv hwconfig "fsl_ddr:ctlr_intlv=null" # cacheline interleaving - setenv memctl_intlv_ctl 0 or setenv memctl_intlv_ctl cacheline + setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline" # page interleaving - setenv memctl_intlv_ctl 1 or setenv memctl_intlv_ctl page + setenv hwconfig "fsl_ddr:ctlr_intlv=page" # bank interleaving - setenv memctl_intlv_ctl 2 or setenv memctl_intlv_ctl bank + setenv hwconfig "fsl_ddr:ctlr_intlv=bank" # superbank - setenv memctl_intlv_ctl 3 or setenv memctl_intlv_ctl superbank + setenv hwconfig "fsl_ddr:ctlr_intlv=superbank" # disable bank (chip-select) interleaving - setenv ba_intlv_ctl + setenv hwconfig "fsl_ddr:bank_intlv=null" # bank(chip-select) interleaving cs0+cs1 - setenv ba_intlv_ctl 0x40 or setenv ba_intlv_ctl cs0_cs1 + setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1" # bank(chip-select) interleaving cs2+cs3 - setenv ba_intlv_ctl 0x20 or setenv ba_intlv_ctl cs2_cs3 + setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3" # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2) - setenv ba_intlv_ctl 0x60 or setenv ba_intlv_ctl cs0_cs1_and_cs2_cs3 + setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3" # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1) - setenv ba_intlv_ctl 0x04 or setenv ba_intlv_ctl cs0_cs1_cs2_cs3 + setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3" + +Memory controller address hashing +================================== +If the DDR controller supports address hashing, it can be enabled by hwconfig. + +Syntax is: +hwconfig=fsl_ddr:addr_hash=true + +Combination of hwconfig +======================= +Hwconfig can be combined with multiple parameters, for example, on a supported +platform + +hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3 |