diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/i386/sc520.c | 2 | ||||
| -rw-r--r-- | cpu/i386/sc520_asm.S | 12 | ||||
| -rw-r--r-- | cpu/mcf52x2/fec.c | 1 | ||||
| -rw-r--r-- | cpu/mcf52x2/start.S | 2 | ||||
| -rw-r--r-- | cpu/mpc5xxx/interrupts.c | 292 | ||||
| -rw-r--r-- | cpu/mpc5xxx/serial.c | 56 | ||||
| -rw-r--r-- | cpu/ppc4xx/440spe_pcie.c | 416 | ||||
| -rw-r--r-- | cpu/ppc4xx/440spe_pcie.h | 11 |
8 files changed, 746 insertions, 46 deletions
diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c index 1c4370b08..d0a734188 100644 --- a/cpu/i386/sc520.c +++ b/cpu/i386/sc520.c @@ -149,7 +149,7 @@ unsigned long init_sc520_dram(void) /* these memory control registers are set up in the assember part, * in sc520_asm.S, during 'mem_init'. If we muck with them here, * after we are running a stack in RAM, we have troubles. Besides, - * these refresh and delay values are better ? simply specified + * these refresh and delay values are better ? simply specified * outright in the include/configs/{cfg} file since the HW designer * simply dictates it. */ diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S index e1fa37a4a..8fc713d93 100644 --- a/cpu/i386/sc520_asm.S +++ b/cpu/i386/sc520_asm.S @@ -462,7 +462,7 @@ emptybank: #if defined CFG_SDRAM_DRCTMCTL /* just have your hardware desinger _GIVE_ you what you need here! */ - movl $DRCTMCTL, %edi + movl $DRCTMCTL, %edi movb $CFG_SDRAM_DRCTMCTL,%al movb (%edi), %al #else @@ -477,7 +477,7 @@ emptybank: #ifdef CFG_SDRAM_CAS_LATENCY_3T orb $0x10, %al #endif - movb %al, (%edi) + movb %al, (%edi) #endif #endif movl $DRCCTL, %edi /* DRAM Control register */ @@ -537,7 +537,7 @@ bank0: movl (%edi), %eax movl %eax, %ebx -done: +done: movl %ebx, %eax #if CFG_SDRAM_ECC_ENABLE @@ -547,7 +547,7 @@ done: movl $0x1, %edi memtest0: movb $0xa5, (%edi) - cmpb $0xa5, (%edi) + cmpb $0xa5, (%edi) jne out shrl $1, %ecx andl %ecx,%ecx @@ -571,11 +571,11 @@ set_ecc: /* enable NMI mapping for ECC */ movl $ECCINT, %edi mov $0x10, %al - movb %al, (%edi) + movb %al, (%edi) /* Turn on ECC */ movl $ECCCTL, %edi mov $0x05, %al - movb %al, (%edi) + movb %al, (%edi) #endif out: movl %ebx, %eax diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c index 6db621472..b6540b55a 100644 --- a/cpu/mcf52x2/fec.c +++ b/cpu/mcf52x2/fec.c @@ -267,6 +267,7 @@ int eth_init (bd_t * bd) fecp->fec_hash_table_high = 0; fecp->fec_hash_table_low = 0; #endif +#endif /* Set maximum receive buffer size. */ diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S index 8a83ca5ef..f1f4077eb 100644 --- a/cpu/mcf52x2/start.S +++ b/cpu/mcf52x2/start.S @@ -140,6 +140,7 @@ _start: move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ move.l %d0, 0x40000000 +#if defined(CONFIG_M5282) /* Initialize RAMBAR1: locate SRAM and validate it */ move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 movec %d0, %RAMBAR1 @@ -171,6 +172,7 @@ _after_flashbar_copy: #endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */ #endif +#endif /* if we come from a pre-loader we have no exception table and * therefore no VBR to set */ diff --git a/cpu/mpc5xxx/interrupts.c b/cpu/mpc5xxx/interrupts.c index 7bacecd59..7b5cb8be4 100644 --- a/cpu/mpc5xxx/interrupts.c +++ b/cpu/mpc5xxx/interrupts.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2006 + * Detlev Zundel, DENX Software Engineering, dzu@denx.de + * * (C) Copyright -2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -24,18 +27,212 @@ * MA 02111-1307 USA */ -/* - * interrupts.c - just enough support for the decrementer/timer +/* this section was ripped out of arch/ppc/syslib/mpc52xx_pic.c in the + * Linux 2.6 source with the following copyright. + * + * Based on (well, mostly copied from) the code from the 2.4 kernel by + * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg. + * + * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com> + * Copyright (C) 2003 Montavista Software, Inc */ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <command.h> -int interrupt_init_cpu (ulong *decrementer_count) +struct irq_action { + interrupt_handler_t *handler; + void *arg; + ulong count; +}; + +static struct irq_action irq_handlers[NR_IRQS]; + +static struct mpc5xxx_intr *intr; +static struct mpc5xxx_sdma *sdma; + +static void mpc5xxx_ic_disable(unsigned int irq) +{ + u32 val; + + if (irq == MPC5XXX_IRQ0) { + val = in_be32(&intr->ctrl); + val &= ~(1 << 11); + out_be32(&intr->ctrl, val); + } else if (irq < MPC5XXX_IRQ1) { + BUG(); + } else if (irq <= MPC5XXX_IRQ3) { + val = in_be32(&intr->ctrl); + val &= ~(1 << (10 - (irq - MPC5XXX_IRQ1))); + out_be32(&intr->ctrl, val); + } else if (irq < MPC5XXX_SDMA_IRQ_BASE) { + val = in_be32(&intr->main_mask); + val |= 1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE)); + out_be32(&intr->main_mask, val); + } else if (irq < MPC5XXX_PERP_IRQ_BASE) { + val = in_be32(&sdma->IntMask); + val |= 1 << (irq - MPC5XXX_SDMA_IRQ_BASE); + out_be32(&sdma->IntMask, val); + } else { + val = in_be32(&intr->per_mask); + val |= 1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE)); + out_be32(&intr->per_mask, val); + } +} + +static void mpc5xxx_ic_enable(unsigned int irq) +{ + u32 val; + + if (irq == MPC5XXX_IRQ0) { + val = in_be32(&intr->ctrl); + val |= 1 << 11; + out_be32(&intr->ctrl, val); + } else if (irq < MPC5XXX_IRQ1) { + BUG(); + } else if (irq <= MPC5XXX_IRQ3) { + val = in_be32(&intr->ctrl); + val |= 1 << (10 - (irq - MPC5XXX_IRQ1)); + out_be32(&intr->ctrl, val); + } else if (irq < MPC5XXX_SDMA_IRQ_BASE) { + val = in_be32(&intr->main_mask); + val &= ~(1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE))); + out_be32(&intr->main_mask, val); + } else if (irq < MPC5XXX_PERP_IRQ_BASE) { + val = in_be32(&sdma->IntMask); + val &= ~(1 << (irq - MPC5XXX_SDMA_IRQ_BASE)); + out_be32(&sdma->IntMask, val); + } else { + val = in_be32(&intr->per_mask); + val &= ~(1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE))); + out_be32(&intr->per_mask, val); + } +} + +static void mpc5xxx_ic_ack(unsigned int irq) +{ + u32 val; + + /* + * Only some irqs are reset here, others in interrupting hardware. + */ + + switch (irq) { + case MPC5XXX_IRQ0: + val = in_be32(&intr->ctrl); + val |= 0x08000000; + out_be32(&intr->ctrl, val); + break; + case MPC5XXX_CCS_IRQ: + val = in_be32(&intr->enc_status); + val |= 0x00000400; + out_be32(&intr->enc_status, val); + break; + case MPC5XXX_IRQ1: + val = in_be32(&intr->ctrl); + val |= 0x04000000; + out_be32(&intr->ctrl, val); + break; + case MPC5XXX_IRQ2: + val = in_be32(&intr->ctrl); + val |= 0x02000000; + out_be32(&intr->ctrl, val); + break; + case MPC5XXX_IRQ3: + val = in_be32(&intr->ctrl); + val |= 0x01000000; + out_be32(&intr->ctrl, val); + break; + default: + if (irq >= MPC5XXX_SDMA_IRQ_BASE + && irq < (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)) { + out_be32(&sdma->IntPend, + 1 << (irq - MPC5XXX_SDMA_IRQ_BASE)); + } + break; + } +} + +static void mpc5xxx_ic_disable_and_ack(unsigned int irq) +{ + mpc5xxx_ic_disable(irq); + mpc5xxx_ic_ack(irq); +} + +static void mpc5xxx_ic_end(unsigned int irq) +{ + mpc5xxx_ic_enable(irq); +} + +void mpc5xxx_init_irq(void) +{ + u32 intr_ctrl; + + /* Remap the necessary zones */ + intr = (struct mpc5xxx_intr *)(MPC5XXX_ICTL); + sdma = (struct mpc5xxx_sdma *)(MPC5XXX_SDMA); + + /* Disable all interrupt sources. */ + out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */ + out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */ + out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */ + out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */ + intr_ctrl = in_be32(&intr->ctrl); + intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */ + 0x00ff0000 | /* IRQ 0-3 level sensitive low active */ + 0x00001000 | /* MEE master external enable */ + 0x00000000 | /* 0 means disable IRQ 0-3 */ + 0x00000001; /* CEb route critical normally */ + out_be32(&intr->ctrl, intr_ctrl); + + /* Zero a bunch of the priority settings. */ + out_be32(&intr->per_pri1, 0); + out_be32(&intr->per_pri2, 0); + out_be32(&intr->per_pri3, 0); + out_be32(&intr->main_pri1, 0); + out_be32(&intr->main_pri2, 0); +} + +int mpc5xxx_get_irq(struct pt_regs *regs) +{ + u32 status; + int irq = -1; + + status = in_be32(&intr->enc_status); + + if (status & 0x00000400) { /* critical */ + irq = (status >> 8) & 0x3; + if (irq == 2) /* high priority peripheral */ + goto peripheral; + irq += MPC5XXX_CRIT_IRQ_BASE; + } else if (status & 0x00200000) { /* main */ + irq = (status >> 16) & 0x1f; + if (irq == 4) /* low priority peripheral */ + goto peripheral; + irq += MPC5XXX_MAIN_IRQ_BASE; + } else if (status & 0x20000000) { /* peripheral */ + peripheral: + irq = (status >> 24) & 0x1f; + if (irq == 0) { /* bestcomm */ + status = in_be32(&sdma->IntPend); + irq = ffs(status) + MPC5XXX_SDMA_IRQ_BASE - 1; + } else + irq += MPC5XXX_PERP_IRQ_BASE; + } + + return irq; +} + +/****************************************************************************/ + +int interrupt_init_cpu(ulong * decrementer_count) { *decrementer_count = get_tbclk() / CFG_HZ; + mpc5xxx_init_irq(); + return (0); } @@ -44,14 +241,32 @@ int interrupt_init_cpu (ulong *decrementer_count) /* * Handle external interrupts */ -void -external_interrupt(struct pt_regs *regs) +void external_interrupt(struct pt_regs *regs) { - puts("external_interrupt (oops!)\n"); + int irq, unmask = 1; + + irq = mpc5xxx_get_irq(regs); + + mpc5xxx_ic_disable_and_ack(irq); + + enable_interrupts(); + + if (irq_handlers[irq].handler != NULL) + (*irq_handlers[irq].handler) (irq_handlers[irq].arg); + else { + printf("\nBogus External Interrupt IRQ %d\n", irq); + /* + * turn off the bogus interrupt, otherwise it + * might repeat forever + */ + unmask = 0; + } + + if (unmask) + mpc5xxx_ic_end(irq); } -void -timer_interrupt_cpu (struct pt_regs *regs) +void timer_interrupt_cpu(struct pt_regs *regs) { /* nothing to do here */ return; @@ -63,22 +278,69 @@ timer_interrupt_cpu (struct pt_regs *regs) * Install and free a interrupt handler. */ -void -irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) +void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg) { + if (irq < 0 || irq >= NR_IRQS) { + printf("irq_install_handler: bad irq number %d\n", irq); + return; + } + if (irq_handlers[irq].handler != NULL) + printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n", + (ulong) handler, (ulong) irq_handlers[irq].handler); + + irq_handlers[irq].handler = handler; + irq_handlers[irq].arg = arg; + + mpc5xxx_ic_enable(irq); } -void -irq_free_handler(int vec) +void irq_free_handler(int irq) { + if (irq < 0 || irq >= NR_IRQS) { + printf("irq_free_handler: bad irq number %d\n", irq); + return; + } + + mpc5xxx_ic_disable(irq); + irq_handlers[irq].handler = NULL; + irq_handlers[irq].arg = NULL; } /****************************************************************************/ -void -do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) +#if (CONFIG_COMMANDS & CFG_CMD_IRQ) +void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) { - puts("IRQ related functions are unimplemented currently.\n"); + int irq, re_enable; + u32 intr_ctrl; + char *irq_config[] = { "level sensitive, active high", + "edge sensitive, rising active edge", + "edge sensitive, falling active edge", + "level sensitive, active low" + }; + + re_enable = disable_interrupts(); + + intr_ctrl = in_be32(&intr->ctrl); + printf("Interrupt configuration:\n"); + + for (irq = 0; irq <= 3; irq++) { + printf("IRQ%d: %s\n", irq, + irq_config[(intr_ctrl >> (22 - 2 * irq)) & 0x3]); + } + + puts("\nInterrupt-Information:\n" "Nr Routine Arg Count\n"); + + for (irq = 0; irq < NR_IRQS; irq++) + if (irq_handlers[irq].handler != NULL) + printf("%02d %08lx %08lx %ld\n", irq, + (ulong) irq_handlers[irq].handler, + (ulong) irq_handlers[irq].arg, + irq_handlers[irq].count); + + if (re_enable) + enable_interrupts(); } +#endif diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c index 6cb523d3c..430d63f74 100644 --- a/cpu/mpc5xxx/serial.c +++ b/cpu/mpc5xxx/serial.c @@ -166,6 +166,25 @@ void serial_putc(const char c) } #if defined(CONFIG_SERIAL_MULTI) +void serial_putc_raw_dev(unsigned long dev_base, const char c) +#else +void serial_putc_raw(const char c) +#endif +{ +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + /* Wait for last character to go. */ + while (!(psc->psc_status & PSC_SR_TXEMP)) + ; + + psc->psc_buffer_8 = c; +} + + +#if defined(CONFIG_SERIAL_MULTI) void serial_puts_dev (unsigned long dev_base, const char *s) #else void serial_puts (const char *s) @@ -240,6 +259,43 @@ void serial_setbrg(void) } #if defined(CONFIG_SERIAL_MULTI) +void serial_setrts_dev (unsigned long dev_base, int s) +#else +void serial_setrts(int s) +#endif +{ +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + + if (s) { + /* Assert RTS (become LOW) */ + psc->op1 = 0x1; + } + else { + /* Negate RTS (become HIGH) */ + psc->op0 = 0x1; + } +} + +#if defined(CONFIG_SERIAL_MULTI) +int serial_getcts_dev (unsigned long dev_base) +#else +int serial_getcts(void) +#endif +{ +#if defined(CONFIG_SERIAL_MULTI) + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; +#else + volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; +#endif + + return (psc->ip & 0x1) ? 0 : 1; +} + +#if defined(CONFIG_SERIAL_MULTI) int serial0_init(void) { return (serial_init_dev(PSC_BASE)); diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c index 2e920aadf..6130cd283 100644 --- a/cpu/ppc4xx/440spe_pcie.c +++ b/cpu/ppc4xx/440spe_pcie.c @@ -169,7 +169,7 @@ static void ppc440spe_setup_utl(u32 port) { break; } utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port); - + /* * Set buffer allocations and then assert VRB and TXE. */ @@ -270,7 +270,7 @@ int ppc440spe_init_pcie(void) SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); udelay(3); - while(time_out) { + while (time_out) { if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { time_out--; udelay(1); @@ -284,6 +284,40 @@ int ppc440spe_init_pcie(void) return 0; } +/* + * Yucca board as End point and root point setup + * and + * testing inbound and out bound windows + * + * YUCCA board can be plugged into another yucca board or you can get PCI-E + * cable which can be used to setup loop back from one port to another port. + * Please rememeber that unless there is a endpoint plugged in to root port it + * will not initialize. It is the same in case of endpoint , unless there is + * root port attached it will not initialize. + * + * In this release of software all the PCI-E ports are configured as either + * endpoint or rootpoint.In future we will have support for selective ports + * setup as endpoint and root point in single board. + * + * Once your board came up as root point , you can verify by reading + * /proc/bus/pci/devices. Where you can see the configuration registers + * of end point device attached to the port. + * + * Enpoint cofiguration can be verified by connecting Yucca board to any + * host or another yucca board. Then try to scan the device. In case of + * linux use "lspci" or appripriate os command. + * + * How do I verify the inbound and out bound windows ?(yucca to yucca) + * in this configuration inbound and outbound windows are setup to access + * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address + * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000, + * This is waere your POM(PLB out bound memory window) mapped. then + * read the data from other yucca board's u-boot prompt at address + * 0x9000 0000(SRAM). Data should match. + * In case of inbound , write data to u-boot command prompt at 0xb000 0000 + * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check + * data at 0x9000 0000(SRAM).Data should match. + */ int ppc440spe_init_pcie_rootport(int port) { static int core_init; @@ -326,7 +360,7 @@ int ppc440spe_init_pcie_rootport(int port) SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); SDR_WRITE(PESDR0_RCSSET, - (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); break; case 1: @@ -339,7 +373,7 @@ int ppc440spe_init_pcie_rootport(int port) SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); SDR_WRITE(PESDR1_RCSSET, - (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); break; case 2: @@ -352,6 +386,225 @@ int ppc440spe_init_pcie_rootport(int port) SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); SDR_WRITE(PESDR2_RCSSET, + (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + } + /* + * Notice: the following delay has critical impact on device + * initialization - if too short (<50ms) the link doesn't get up. + */ + mdelay(100); + + switch (port) { + case 0: + val = SDR_READ(PESDR0_RCSSTS); + break; + case 1: + val = SDR_READ(PESDR1_RCSSTS); + break; + case 2: + val = SDR_READ(PESDR2_RCSSTS); + break; + } + + if (val & (1 << 20)) { + printf("PCIE%d: PGRST failed %08x\n", port, val); + return -1; + } + + /* + * Verify link is up + */ + val = 0; + switch (port) { + case 0: + val = SDR_READ(PESDR0_LOOP); + break; + case 1: + val = SDR_READ(PESDR1_LOOP); + break; + case 2: + val = SDR_READ(PESDR2_LOOP); + break; + } + if (!(val & 0x00001000)) { + printf("PCIE%d: link is not up.\n", port); + return -1; + } + + /* + * Setup UTL registers - but only on revA! + * We use default settings for revB chip. + */ + if (!ppc440spe_revB()) + ppc440spe_setup_utl(port); + + /* + * We map PCI Express configuration access into the 512MB regions + * + * NOTICE: revB is very strict about PLB real addressess and ranges to + * be mapped for config space; it seems to only work with d_nnnn_nnnn + * range (hangs the core upon config transaction attempts when set + * otherwise) while revA uses c_nnnn_nnnn. + * + * For revA: + * PCIE0: 0xc_4000_0000 + * PCIE1: 0xc_8000_0000 + * PCIE2: 0xc_c000_0000 + * + * For revB: + * PCIE0: 0xd_0000_0000 + * PCIE1: 0xd_2000_0000 + * PCIE2: 0xd_4000_0000 + */ + + switch (port) { + case 0: + if (ppc440spe_revB()) { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000); + } else { + /* revA */ + mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000); + } + mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ + break; + + case 1: + if (ppc440spe_revB()) { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000); + } else { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000); + } + mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ + break; + + case 2: + if (ppc440spe_revB()) { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000); + } else { + mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000); + } + mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ + break; + } + + /* + * Check for VC0 active and assert RDY. + */ + attempts = 10; + switch (port) { + case 0: + while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE0: VC0 not active\n"); + return -1; + } + mdelay(1000); + } + SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20); + break; + case 1: + while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE1: VC0 not active\n"); + return -1; + } + mdelay(1000); + } + + SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20); + break; + case 2: + while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE2: VC0 not active\n"); + return -1; + } + mdelay(1000); + } + + SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20); + break; + } + mdelay(100); + + return 0; +} + +int ppc440spe_init_pcie_endport(int port) +{ + static int core_init; + volatile u32 val = 0; + int attempts; + + if (!core_init) { + ++core_init; + if (ppc440spe_init_pcie()) + return -1; + } + + /* + * Initialize various parts of the PCI Express core for our port: + * + * - Set as a end port and enable max width + * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). + * - Set up UTL configuration. + * - Increase SERDES drive strength to levels suggested by AMCC. + * - De-assert RSTPYN, RSTDL and RSTGU. + * + * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with + * default setting 0x11310000. The register has new fields, + * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core + * hang. + */ + switch (port) { + case 0: + SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X8 << 12); + + SDR_WRITE(PESDR0_UTLSET1, 0x20222222); + if (!ppc440spe_revB()) + SDR_WRITE(PESDR0_UTLSET2, 0x11000000); + SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); + SDR_WRITE(PESDR0_RCSSET, + (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + + case 1: + SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12); + SDR_WRITE(PESDR1_UTLSET1, 0x20222222); + if (!ppc440spe_revB()) + SDR_WRITE(PESDR1_UTLSET2, 0x11000000); + SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR1_RCSSET, + (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + + case 2: + SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12); + SDR_WRITE(PESDR2_UTLSET1, 0x20222222); + if (!ppc440spe_revB()) + SDR_WRITE(PESDR2_UTLSET2, 0x11000000); + SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR2_RCSSET, (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); break; } @@ -418,7 +671,6 @@ int ppc440spe_init_pcie_rootport(int port) * PCIE1: 0xd_2000_0000 * PCIE2: 0xd_4000_0000 */ - switch (port) { case 0: if (ppc440spe_revB()) { @@ -498,29 +750,33 @@ int ppc440spe_init_pcie_rootport(int port) return 0; } -void ppc440spe_setup_pcie(struct pci_controller *hose, int port) +void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) { volatile void *mbase = NULL; + volatile void *rmbase = NULL; pci_set_ops(hose, - pcie_read_config_byte, - pcie_read_config_word, - pcie_read_config_dword, - pcie_write_config_byte, - pcie_write_config_word, - pcie_write_config_dword); + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); - switch(port) { + switch (port) { case 0: mbase = (u32 *)CFG_PCIE0_XCFGBASE; + rmbase = (u32 *)CFG_PCIE0_CFGBASE; hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; break; case 1: mbase = (u32 *)CFG_PCIE1_XCFGBASE; + rmbase = (u32 *)CFG_PCIE1_CFGBASE; hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; break; case 2: mbase = (u32 *)CFG_PCIE2_XCFGBASE; + rmbase = (u32 *)CFG_PCIE2_CFGBASE; hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; break; } @@ -528,14 +784,9 @@ void ppc440spe_setup_pcie(struct pci_controller *hose, int port) /* * Set bus numbers on our root port */ - if (ppc440spe_revB()) { - out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); - out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); - out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); - } else { - out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); - out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0); - } + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); + out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); /* * Set up outbound translation to hose->mem_space from PLB @@ -544,8 +795,7 @@ void ppc440spe_setup_pcie(struct pci_controller *hose, int port) * subregions and to enable the outbound translation. */ out_le32(mbase + PECFG_POM0LAH, 0x00000000); - out_le32(mbase + PECFG_POM0LAL, (CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE)); + out_le32(mbase + PECFG_POM0LAL, 0x00000000); switch (port) { case 0: @@ -579,14 +829,134 @@ void ppc440spe_setup_pcie(struct pci_controller *hose, int port) out_le32(mbase + PCI_BASE_ADDRESS_1, 0); out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); out_le32(mbase + PECFG_BAR0LMPA, 0); + + out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); + out_le32(mbase + PECFG_PIM01SAL, 0x00000000); out_le32(mbase + PECFG_PIM0LAL, 0); out_le32(mbase + PECFG_PIM0LAH, 0); + out_le32(mbase + PECFG_PIM1LAL, 0x00000000); + out_le32(mbase + PECFG_PIM1LAH, 0x00000004); + out_le32(mbase + PECFG_PIMEN, 0x1); + + /* Enable I/O, Mem, and Busmaster cycles */ + out_le16((u16 *)(mbase + PCI_COMMAND), + in_le16((u16 *)(mbase + PCI_COMMAND)) | + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + printf("PCIE:%d successfully set as rootpoint\n",port); +} + +int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port) +{ + volatile void *mbase = NULL; + int attempts = 0; + + pci_set_ops(hose, + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); + + switch (port) { + case 0: + mbase = (u32 *)CFG_PCIE0_XCFGBASE; + hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; + break; + case 1: + mbase = (u32 *)CFG_PCIE1_XCFGBASE; + hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; + break; + case 2: + mbase = (u32 *)CFG_PCIE2_XCFGBASE; + hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; + break; + } + + /* + * Set up outbound translation to hose->mem_space from PLB + * addresses at an offset of 0xd_0000_0000. We set the low + * bits of the mask to 11 to turn off splitting into 8 + * subregions and to enable the outbound translation. + */ + out_le32(mbase + PECFG_POM0LAH, 0x00001ff8); + out_le32(mbase + PECFG_POM0LAL, 0x00001000); + + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), + ~(CFG_PCIE_MEMSIZE - 1) | 3); + break; + case 1: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), + ~(CFG_PCIE_MEMSIZE - 1) | 3); + break; + case 2: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), + ~(CFG_PCIE_MEMSIZE - 1) | 3); + break; + } + + /* Set up 16GB inbound memory window at 0 */ + out_le32(mbase + PCI_BASE_ADDRESS_0, 0); + out_le32(mbase + PCI_BASE_ADDRESS_1, 0); + out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); + out_le32(mbase + PECFG_BAR0LMPA, 0); + out_le32(mbase + PECFG_PIM0LAL, 0x00000000); + out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */ out_le32(mbase + PECFG_PIMEN, 0x1); /* Enable I/O, Mem, and Busmaster cycles */ out_le16((u16 *)(mbase + PCI_COMMAND), in_le16((u16 *)(mbase + PCI_COMMAND)) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */ + out_le16(mbase + 0x202,0xfeed); /* Setting device ID */ + attempts = 10; + switch (port) { + case 0: + while (!(SDR_READ(PESDR0_RCSSTS) & (1 << 8))) { + if (!(attempts--)) { + printf("PCIE0: BMEN is not active\n"); + return -1; + } + mdelay(1000); + } + break; + case 1: + while (!(SDR_READ(PESDR1_RCSSTS) & (1 << 8))) { + if (!(attempts--)) { + printf("PCIE1: BMEN is not active\n"); + return -1; + } + mdelay(1000); + } + break; + case 2: + while (!(SDR_READ(PESDR2_RCSSTS) & (1 << 8))) { + if (!(attempts--)) { + printf("PCIE2: BMEN is not active\n"); + return -1; + } + mdelay(1000); + } + break; + } + printf("PCIE:%d successfully set as endpoint\n",port); + + return 0; } #endif /* CONFIG_PCI */ #endif /* CONFIG_440SPE */ diff --git a/cpu/ppc4xx/440spe_pcie.h b/cpu/ppc4xx/440spe_pcie.h index 47df7620a..2becc7772 100644 --- a/cpu/ppc4xx/440spe_pcie.h +++ b/cpu/ppc4xx/440spe_pcie.h @@ -139,9 +139,17 @@ */ #define PECFG_BAR0LMPA 0x210 #define PECFG_BAR0HMPA 0x214 +#define PECFG_BAR1MPA 0x218 +#define PECFG_BAR2MPA 0x220 + #define PECFG_PIMEN 0x33c #define PECFG_PIM0LAL 0x340 #define PECFG_PIM0LAH 0x344 +#define PECFG_PIM1LAL 0x348 +#define PECFG_PIM1LAH 0x34c +#define PECFG_PIM01SAL 0x350 +#define PECFG_PIM01SAH 0x354 + #define PECFG_POM0LAL 0x380 #define PECFG_POM0LAH 0x384 @@ -156,7 +164,8 @@ int ppc440spe_init_pcie(void); int ppc440spe_init_pcie_rootport(int port); void yucca_setup_pcie_fpga_rootpoint(int port); -void ppc440spe_setup_pcie(struct pci_controller *hose, int port); +void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port); +int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port); int yucca_pcie_card_present(int port); int pcie_hose_scan(struct pci_controller *hose, int bus); #endif /* __440SPE_PCIE_H */ |