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-rw-r--r--cpu/mpc83xx/cpu_init.c261
-rw-r--r--cpu/ppc4xx/40x_spd_sdram.c27
-rw-r--r--cpu/ppc4xx/44x_spd_ddr.c44
-rw-r--r--cpu/ppc4xx/sdram.c60
-rw-r--r--cpu/ppc4xx/uic.c28
5 files changed, 233 insertions, 187 deletions
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 5c930d388..031e8d574 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -23,8 +23,8 @@
#include <common.h>
#include <mpc83xx.h>
#include <ioports.h>
-#ifdef CONFIG_USB_EHCI_FSL
#include <asm/io.h>
+#ifdef CONFIG_USB_EHCI_FSL
#include <usb/ehci-fsl.h>
#endif
@@ -63,149 +63,163 @@ static void config_qe_ioports(void)
*/
void cpu_init_f (volatile immap_t * im)
{
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
- /* Clear initial global data */
- memset ((void *) gd, 0, sizeof (gd_t));
-
- /* system performance tweaking */
-
-#ifdef CONFIG_SYS_ACR_PIPE_DEP
- /* Arbiter pipeline depth */
- im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
- (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+ __be32 acr_mask =
+#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
+ (ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_ACR_RPTCNT
- /* Arbiter repeat count */
- im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
- (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
+#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
+ (ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
#endif
-
+ 0;
+ __be32 acr_val =
+#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
+ (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
+ (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
+#endif
+ 0;
+ __be32 spcr_mask =
+#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
+ (SPCR_OPT << SPCR_OPT_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
+ (SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
+ (SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
+ (SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
+#endif
+ 0;
+ __be32 spcr_val =
#ifdef CONFIG_SYS_SPCR_OPT
- /* Optimize transactions between CSB and other devices */
- im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
- (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
+ (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SPCR_TSECEP
- /* all eTSEC's Emergency priority */
- im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
- (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
+#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
+ (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SPCR_TSEC1EP
- /* TSEC1 Emergency priority */
- im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) |
- (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
+#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
+ (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SPCR_TSEC2EP
- /* TSEC2 Emergency priority */
- im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) |
- (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
+#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
+ (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_ENCCM
- /* Encryption clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) |
- (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT);
+ 0;
+ __be32 sccr_mask =
+#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
+ (SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_PCICM
- /* PCI & DMA clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) |
- (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT);
+#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
+ (SCCR_PCICM << SCCR_PCICM_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_TSECCM
- /* all TSEC's clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) |
- (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
+#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
+ (SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_TSEC1CM
- /* TSEC1 clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) |
- (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
+#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
+ (SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_TSEC2CM
- /* TSEC2 clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) |
- (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
+#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
+ (SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_TSEC1ON
- /* TSEC1 clock switch */
- im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) |
- (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
+#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
+ (SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_TSEC2ON
- /* TSEC2 clock switch */
- im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) |
- (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
+#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
+ (SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_USBMPHCM
- /* USB MPH clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) |
- (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
+#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
+ (SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_USBDRCM
- /* USB DR clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) |
- (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
+#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
+ (SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
#endif
-
-#ifdef CONFIG_SYS_SCCR_SATACM
- /* SATA controller clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) |
- (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT);
+#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
+ (SCCR_SATACM << SCCR_SATACM_SHIFT) |
+#endif
+ 0;
+ __be32 sccr_val =
+#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
+ (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
#endif
+#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
+ (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
+ (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
+ (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
+ (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
+ (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
+ (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
+ (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
+ (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
+ (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
+#endif
+ 0;
+
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+ /* Clear initial global data */
+ memset ((void *) gd, 0, sizeof (gd_t));
+
+ /* system performance tweaking */
+ clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
+
+ clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
+
+ clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
/* RSR - Reset Status Register - clear all status (4.6.1.3) */
- gd->reset_status = im->reset.rsr;
- im->reset.rsr = ~(RSR_RES);
+ gd->reset_status = __raw_readl(&im->reset.rsr);
+ __raw_writel(~(RSR_RES), &im->reset.rsr);
/* AER - Arbiter Event Register - store status */
- gd->arbiter_event_attributes = im->arbiter.aeatr;
- gd->arbiter_event_address = im->arbiter.aeadr;
+ gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
+ gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
/*
* RMR - Reset Mode Register
* contains checkstop reset enable (4.6.1.4)
*/
- im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
-
- /* LCRR - Clock Ratio Register (10.3.1.16) */
- im->lbus.lcrr = CONFIG_SYS_LCRR;
+ __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
- /* Enable Time Base & Decrimenter ( so we will have udelay() )*/
- im->sysconf.spcr |= SPCR_TBEN;
+ /* Enable Time Base & Decrementer ( so we will have udelay() )*/
+ setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
/* System General Purpose Register */
#ifdef CONFIG_SYS_SICRH
#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
- im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH;
+ __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
+ &im->sysconf.sicrh);
#else
- im->sysconf.sicrh = CONFIG_SYS_SICRH;
+ __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
#endif
#endif
#ifdef CONFIG_SYS_SICRL
- im->sysconf.sicrl = CONFIG_SYS_SICRL;
+ __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
#endif
- /* DDR control driver register */
-#ifdef CONFIG_SYS_DDRCDR
- im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
+#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
+ __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
#endif
- /* Output buffer impedance register */
-#ifdef CONFIG_SYS_OBIR
- im->sysconf.obir = CONFIG_SYS_OBIR;
+#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
+ __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
#endif
#ifdef CONFIG_QE
@@ -308,7 +322,7 @@ void cpu_init_f (volatile immap_t * im)
/* Wait for clock to stabilize */
do {
- temp = in_be32(&ehci->control);
+ temp = __raw_readl(&ehci->control);
udelay(1000);
} while (!(temp & PHY_CLK_VALID));
#endif
@@ -317,8 +331,41 @@ void cpu_init_f (volatile immap_t * im)
int cpu_init_r (void)
{
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
#ifdef CONFIG_QE
uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
+#endif
+ __be32 lcrr_mask =
+#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
+ LCRR_DBYP |
+#endif
+#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
+ LCRR_EADC |
+#endif
+#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
+ LCRR_CLKDIV |
+#endif
+ 0;
+ __be32 lcrr_val =
+#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
+ CONFIG_SYS_LCRR_DBYP |
+#endif
+#ifdef CONFIG_SYS_LCRR_EADC
+ CONFIG_SYS_LCRR_EADC |
+#endif
+#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
+ CONFIG_SYS_LCRR_CLKDIV |
+#endif
+ 0;
+
+ /* LCRR - Clock Ratio Register (10.3.1.16)
+ * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
+ */
+ clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
+ __raw_readl(&im->lbus.lcrr);
+ isync();
+
+#ifdef CONFIG_QE
qe_init(qe_base);
qe_reset();
#endif
diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c
index 83fa709da..5e6dbe333 100644
--- a/cpu/ppc4xx/40x_spd_sdram.c
+++ b/cpu/ppc4xx/40x_spd_sdram.c
@@ -422,32 +422,31 @@ long int spd_sdram(int(read_spd)(uint addr))
* program all the registers.
* -------------------------------------------------------------------*/
-#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data)
/* disable memcontroller so updates work */
- mtsdram0( mem_mcopt1, 0 );
+ mtsdram(SDRAM0_CFG, 0);
#ifndef CONFIG_405EP /* not on PPC405EP */
- mtsdram0( mem_besra , sdram0_besr0 );
- mtsdram0( mem_besrb , sdram0_besr1 );
- mtsdram0( mem_ecccf , sdram0_ecccfg );
- mtsdram0( mem_eccerr, sdram0_eccesr );
+ mtsdram(SDRAM0_BESR0, sdram0_besr0);
+ mtsdram(SDRAM0_BESR1, sdram0_besr1);
+ mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg);
+ mtsdram(SDRAM0_ECCESR, sdram0_eccesr);
#endif
- mtsdram0( mem_rtr , sdram0_rtr );
- mtsdram0( mem_pmit , sdram0_pmit );
- mtsdram0( mem_mb0cf , sdram0_b0cr );
- mtsdram0( mem_mb1cf , sdram0_b1cr );
+ mtsdram(SDRAM0_RTR, sdram0_rtr);
+ mtsdram(SDRAM0_PMIT, sdram0_pmit);
+ mtsdram(SDRAM0_B0CR, sdram0_b0cr);
+ mtsdram(SDRAM0_B1CR, sdram0_b1cr);
#ifndef CONFIG_405EP /* not on PPC405EP */
- mtsdram0( mem_mb2cf , sdram0_b2cr );
- mtsdram0( mem_mb3cf , sdram0_b3cr );
+ mtsdram(SDRAM0_B2CR, sdram0_b2cr);
+ mtsdram(SDRAM0_B3CR, sdram0_b3cr);
#endif
- mtsdram0( mem_sdtr1 , sdram0_tr );
+ mtsdram(SDRAM0_TR, sdram0_tr);
/* SDRAM have a power on delay, 500 micro should do */
udelay(500);
sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
if (ecc_on)
sdram0_cfg |= SDRAM0_CFG_MEMCHK;
- mtsdram0(mem_mcopt1, sdram0_cfg);
+ mtsdram(SDRAM0_CFG, sdram0_cfg);
return (total_size);
}
diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c
index c93f23a67..6176eabfb 100644
--- a/cpu/ppc4xx/44x_spd_ddr.c
+++ b/cpu/ppc4xx/44x_spd_ddr.c
@@ -230,7 +230,7 @@ long int spd_sdram(void) {
/*
* program SDRAM Clock Timing Register (SDRAM0_CLKTR)
*/
- mtsdram(mem_clktr, 0x40000000);
+ mtsdram(SDRAM0_CLKTR, 0x40000000);
/*
* delay to ensure 200 usec has elapsed
@@ -240,14 +240,14 @@ long int spd_sdram(void) {
/*
* enable the memory controller
*/
- mfsdram(mem_cfg0, cfg0);
- mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
+ mfsdram(SDRAM0_CFG0, cfg0);
+ mtsdram(SDRAM0_CFG0, cfg0 | SDRAM_CFG0_DCEN);
/*
* wait for SDRAM_CFG0_DC_EN to complete
*/
while (1) {
- mfsdram(mem_mcsts, mcsts);
+ mfsdram(SDRAM0_MCSTS, mcsts);
if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
break;
}
@@ -386,7 +386,7 @@ static void program_cfg0(unsigned long *dimm_populated,
/*
* get Memory Controller Options 0 data
*/
- mfsdram(mem_cfg0, cfg0);
+ mfsdram(SDRAM0_CFG0, cfg0);
/*
* clear bits
@@ -457,7 +457,7 @@ static void program_cfg0(unsigned long *dimm_populated,
* Note: DCEN must be enabled after all DDR SDRAM controller
* configuration registers get initialized.
*/
- mtsdram(mem_cfg0, cfg0);
+ mtsdram(SDRAM0_CFG0, cfg0);
}
static void program_cfg1(unsigned long *dimm_populated,
@@ -465,7 +465,7 @@ static void program_cfg1(unsigned long *dimm_populated,
unsigned long num_dimm_banks)
{
unsigned long cfg1;
- mfsdram(mem_cfg1, cfg1);
+ mfsdram(SDRAM0_CFG1, cfg1);
/*
* Self-refresh exit, disable PM
@@ -475,7 +475,7 @@ static void program_cfg1(unsigned long *dimm_populated,
/*
* program Memory Controller Options 1
*/
- mtsdram(mem_cfg1, cfg1);
+ mtsdram(SDRAM0_CFG1, cfg1);
}
static void program_rtr(unsigned long *dimm_populated,
@@ -535,7 +535,7 @@ static void program_rtr(unsigned long *dimm_populated,
/*
* program Refresh Timer Register (SDRAM0_RTR)
*/
- mtsdram(mem_rtr, sdram_rtr);
+ mtsdram(SDRAM0_RTR, sdram_rtr);
}
static void program_tr0(unsigned long *dimm_populated,
@@ -576,7 +576,7 @@ static void program_tr0(unsigned long *dimm_populated,
/*
* get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
*/
- mfsdram(mem_tr0, tr0);
+ mfsdram(SDRAM0_TR0, tr0);
tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
@@ -821,7 +821,7 @@ static void program_tr0(unsigned long *dimm_populated,
}
debug("tr0: %x\n", tr0);
- mtsdram(mem_tr0, tr0);
+ mtsdram(SDRAM0_TR0, tr0);
}
static int short_mem_test(void)
@@ -848,7 +848,7 @@ static int short_mem_test(void)
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
- mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bxcr_num << 2));
+ mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bxcr_num << 2));
if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
/* Bank is enabled */
membase = (unsigned long*)
@@ -918,11 +918,11 @@ static void program_tr1(void)
/*
* get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
*/
- mfsdram(mem_tr1, tr1);
+ mfsdram(SDRAM0_TR1, tr1);
tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
- mfsdram(mem_tr0, tr0);
+ mfsdram(SDRAM0_TR0, tr0);
if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
(sys_info.freqPLB > 100000000)) {
tr1 |= SDRAM_TR1_RDSS_TR2;
@@ -937,14 +937,14 @@ static void program_tr1(void)
/*
* save CFG0 ECC setting to a temporary variable and turn ECC off
*/
- mfsdram(mem_cfg0, cfg0);
+ mfsdram(SDRAM0_CFG0, cfg0);
ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
+ mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
/*
* get the delay line calibration register value
*/
- mfsdram(mem_dlycal, dlycal);
+ mfsdram(SDRAM0_DLYCAL, dlycal);
dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
max_pass_length = 0;
@@ -964,7 +964,7 @@ static void program_tr1(void)
/*
* Set the timing reg for the test.
*/
- mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
+ mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
if (short_mem_test()) {
if (fail_found == TRUE) {
@@ -1018,7 +1018,7 @@ static void program_tr1(void)
/*
* restore the orignal ECC setting
*/
- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
+ mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
/*
* set the SDRAM TR1 RDCD value
@@ -1056,7 +1056,7 @@ static void program_tr1(void)
/*
* program SDRAM Timing Register 1 TR1
*/
- mtsdram(mem_tr1, tr1);
+ mtsdram(SDRAM0_TR1, tr1);
}
static unsigned long program_bxcr(unsigned long *dimm_populated,
@@ -1086,7 +1086,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
* Set the BxCR regs. First, wipe out the bank config registers.
*/
for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
- mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bx_cr_num << 2));
+ mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bx_cr_num << 2));
mtdcr(SDRAM0_CFGDATA, 0x00000000);
bank_parms[bx_cr_num].bank_size_bytes = 0;
}
@@ -1232,7 +1232,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
/* Set the SDRAM0_BxCR regs thanks to sort tables */
for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
- mtdcr(SDRAM0_CFGADDR, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
+ mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (sorted_bank_num[bx_cr_num] << 2));
temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index 5a3336e3c..30c6e0e38 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -188,14 +188,14 @@ phys_size_t initdram(int board_type)
/*
* Disable memory controller.
*/
- mtsdram(mem_mcopt1, 0x00000000);
+ mtsdram(SDRAM0_CFG, 0x00000000);
/*
* Set MB0CF for bank 0.
*/
- mtsdram(mem_mb0cf, mb0cf[i].reg);
- mtsdram(mem_sdtr1, sdtr1);
- mtsdram(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));
+ mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
+ mtsdram(SDRAM0_TR, sdtr1);
+ mtsdram(SDRAM0_RTR, compute_rtr(speed, mb0cf[i].rows, 64));
udelay(200);
@@ -204,7 +204,7 @@ phys_size_t initdram(int board_type)
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
- mtsdram(mem_mcopt1, 0x80800000);
+ mtsdram(SDRAM0_CFG, 0x80800000);
udelay(10000);
@@ -216,9 +216,9 @@ phys_size_t initdram(int board_type)
* defined (assumes same type as bank 0)
*/
#ifdef CONFIG_SDRAM_BANK1
- mtsdram(mem_mcopt1, 0x00000000);
- mtsdram(mem_mb1cf, mb0cf[i].size | mb0cf[i].reg);
- mtsdram(mem_mcopt1, 0x80800000);
+ mtsdram(SDRAM0_CFG, 0x00000000);
+ mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
+ mtsdram(SDRAM0_CFG, 0x80800000);
udelay(10000);
/*
@@ -228,8 +228,8 @@ phys_size_t initdram(int board_type)
*/
if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
mb0cf[i].size) {
- mtsdram(mem_mb1cf, 0);
- mtsdram(mem_mcopt1, 0);
+ mtsdram(SDRAM0_B1CR, 0);
+ mtsdram(SDRAM0_CFG, 0);
} else {
/*
* We have two identical banks, so the size
@@ -315,7 +315,7 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
/* go through all possible SDRAM0_TR1[RDCT] values */
for (i=0; i<=0x1ff; i++) {
/* set the current value for TR1 */
- mtsdram(mem_tr1, (0x80800800 | i));
+ mtsdram(SDRAM0_TR1, (0x80800800 | i));
/* write values */
for (j=0; j<NUM_TRIES; j++) {
@@ -383,31 +383,31 @@ phys_size_t initdram(int board_type)
/*
* Disable memory controller.
*/
- mtsdram(mem_cfg0, 0x00000000);
+ mtsdram(SDRAM0_CFG0, 0x00000000);
/*
* Setup some default
*/
- mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
- mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram(mem_wddctr, CONFIG_SYS_SDRAM0_WDDCTR);
- mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
+ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram(SDRAM0_WDDCTR, CONFIG_SYS_SDRAM0_WDDCTR);
+ mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
- mtsdram(mem_b0cr, mb0cf[i].reg);
- mtsdram(mem_tr0, CONFIG_SYS_SDRAM0_TR0);
- mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
- mtsdram(mem_rtr, CONFIG_SYS_SDRAM0_RTR);
- mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
+ mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
+ mtsdram(SDRAM0_TR0, CONFIG_SYS_SDRAM0_TR0);
+ mtsdram(SDRAM0_TR1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
+ mtsdram(SDRAM0_RTR, CONFIG_SYS_SDRAM0_RTR);
+ mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
udelay(400); /* Delay 200 usecs (min) */
/*
* Enable the controller, then wait for DCEN to complete
*/
- mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0);
+ mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
udelay(10000);
if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
@@ -416,7 +416,7 @@ phys_size_t initdram(int board_type)
* Optimize TR1 to current hardware environment
*/
sdram_tr1_set(0x00000000, &tr1_bank1);
- mtsdram(mem_tr1, (tr1_bank1 | 0x80800800));
+ mtsdram(SDRAM0_TR1, (tr1_bank1 | 0x80800800));
/*
@@ -424,9 +424,9 @@ phys_size_t initdram(int board_type)
* defined (assumes same type as bank 0)
*/
#ifdef CONFIG_SDRAM_BANK1
- mtsdram(mem_cfg0, 0);
- mtsdram(mem_b1cr, mb0cf[i].size | mb0cf[i].reg);
- mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0);
+ mtsdram(SDRAM0_CFG0, 0);
+ mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
+ mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
udelay(10000);
/*
@@ -436,9 +436,9 @@ phys_size_t initdram(int board_type)
*/
if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size)
!= mb0cf[i].size) {
- mtsdram(mem_cfg0, 0);
- mtsdram(mem_b1cr, 0);
- mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0);
+ mtsdram(SDRAM0_CFG0, 0);
+ mtsdram(SDRAM0_B1CR, 0);
+ mtsdram(SDRAM0_CFG0, CONFIG_SYS_SDRAM0_CFG0);
udelay(10000);
} else {
/*
diff --git a/cpu/ppc4xx/uic.c b/cpu/ppc4xx/uic.c
index d298b312c..8b1b259fa 100644
--- a/cpu/ppc4xx/uic.c
+++ b/cpu/ppc4xx/uic.c
@@ -109,7 +109,7 @@ void external_interrupt(struct pt_regs *regs)
/*
* Read masked interrupt status register to determine interrupt source
*/
- uic_msr = mfdcr(uic0msr);
+ uic_msr = mfdcr(UIC0MSR);
#if (UIC_MAX > 1)
if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
@@ -129,7 +129,7 @@ void external_interrupt(struct pt_regs *regs)
uic_interrupt(UIC3_DCR_BASE, 96);
#endif
- mtdcr(uic0sr, (uic_msr & UICB0_ALL));
+ mtdcr(UIC0SR, (uic_msr & UICB0_ALL));
if (uic_msr & ~(UICB0_ALL))
uic_interrupt(UIC0_DCR_BASE, 0);
@@ -140,13 +140,13 @@ void external_interrupt(struct pt_regs *regs)
void pic_irq_ack(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
- mtdcr(uicsr, UIC_MASK(vec));
+ mtdcr(UIC0SR, UIC_MASK(vec));
else if ((vec >= 32) && (vec < 64))
- mtdcr(uic1sr, UIC_MASK(vec));
+ mtdcr(UIC1SR, UIC_MASK(vec));
else if ((vec >= 64) && (vec < 96))
- mtdcr(uic2sr, UIC_MASK(vec));
+ mtdcr(UIC2SR, UIC_MASK(vec));
else if (vec >= 96)
- mtdcr(uic3sr, UIC_MASK(vec));
+ mtdcr(UIC3SR, UIC_MASK(vec));
}
/*
@@ -156,13 +156,13 @@ void pic_irq_enable(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
- mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
+ mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec));
else if ((vec >= 32) && (vec < 64))
- mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
+ mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec));
else if ((vec >= 64) && (vec < 96))
- mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
+ mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec));
else if (vec >= 96)
- mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
+ mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec));
debug("Install interrupt vector %d\n", vec);
}
@@ -170,11 +170,11 @@ void pic_irq_enable(unsigned int vec)
void pic_irq_disable(unsigned int vec)
{
if ((vec >= 0) && (vec < 32))
- mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
+ mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec));
else if ((vec >= 32) && (vec < 64))
- mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
+ mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec));
else if ((vec >= 64) && (vec < 96))
- mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
+ mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec));
else if (vec >= 96)
- mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));
+ mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec));
}
generated by cgit v1.2.3-70-g09d2 (git 2.51.2) at 2025-10-31 19:34:49 +0000