diff options
Diffstat (limited to 'cpu')
36 files changed, 1119 insertions, 535 deletions
diff --git a/cpu/arm720t/lpc2292/mmc.c b/cpu/arm720t/lpc2292/mmc.c index fd7f149b6..beaffe944 100644 --- a/cpu/arm720t/lpc2292/mmc.c +++ b/cpu/arm720t/lpc2292/mmc.c @@ -93,12 +93,12 @@ static int mmc_hw_get_parameters(void) return 0; } -int mmc_init(int verbose) +int mmc_legacy_init(int verbose) { int ret = -ENODEV; if (verbose) - printf("mmc_init\n"); + printf("mmc_legacy_init\n"); spi_init(); /* this meeds to be done twice */ @@ -128,30 +128,4 @@ int mmc_init(int verbose) return ret; } -int mmc_write(uchar * src, ulong dst, int size) -{ -#ifdef MMC_DEBUG - printf("mmc_write: src=%p, dst=%lu, size=%u\n", src, dst, size); -#endif - /* Since mmc2info always returns 0 this function will never be called */ - return 0; -} - -int mmc_read(ulong src, uchar * dst, int size) -{ -#ifdef MMC_DEBUG - printf("mmc_read: src=%lu, dst=%p, size=%u\n", src, dst, size); -#endif - /* Since mmc2info always returns 0 this function will never be called */ - return 0; -} - -int mmc2info(ulong addr) -{ - /* This function is used by cmd_cp to determine if source or destination - address resides on MMC-card or not. We do not support copy to and from - MMC-card so we always return 0. */ - return 0; -} - #endif /* CONFIG_MMC */ diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index ebc5ea266..ad2085b01 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -238,4 +238,3 @@ static void cache_flush(void) { asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } - diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c index 6091f8cef..ae0016de1 100644 --- a/cpu/blackfin/initcode.c +++ b/cpu/blackfin/initcode.c @@ -20,7 +20,7 @@ #include "serial.h" __attribute__((always_inline)) -static inline uint32_t serial_init(void) +static inline void serial_init(void) { #ifdef __ADSPBF54x__ # ifdef BFIN_BOOT_UART_USE_RTS @@ -61,25 +61,16 @@ static inline uint32_t serial_init(void) } #endif - uint32_t old_baud; - if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) - old_baud = serial_early_get_baud(); - else - old_baud = CONFIG_BAUDRATE; - if (BFIN_DEBUG_EARLY_SERIAL) { + int ucen = *pUART_GCTL & UCEN; serial_early_init(); /* If the UART is off, that means we need to program * the baud rate ourselves initially. */ - if (!old_baud) { - old_baud = CONFIG_BAUDRATE; + if (ucen != UCEN) serial_early_set_baud(CONFIG_BAUDRATE); - } } - - return old_baud; } __attribute__((always_inline)) @@ -93,30 +84,6 @@ static inline void serial_deinit(void) #endif } -/* We need to reset the baud rate when we have early debug turned on - * or when we are booting over the UART. - * XXX: we should fix this to calc the old baud and restore it rather - * than hardcoding it via CONFIG_LDR_LOAD_BAUD ... but we have - * to figure out how to avoid the division in the baud calc ... - */ -__attribute__((always_inline)) -static inline void serial_reset_baud(uint32_t baud) -{ - if (!BFIN_DEBUG_EARLY_SERIAL && CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) - return; - -#ifndef CONFIG_LDR_LOAD_BAUD -# define CONFIG_LDR_LOAD_BAUD 115200 -#endif - - if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) - serial_early_set_baud(baud); - else if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) - serial_early_set_baud(CONFIG_LDR_LOAD_BAUD); - else - serial_early_set_baud(CONFIG_BAUDRATE); -} - __attribute__((always_inline)) static inline void serial_putc(char c) { @@ -133,12 +100,22 @@ static inline void serial_putc(char c) } -/* Max SCLK can be 133MHz ... dividing that by 4 gives - * us a freq of 33MHz for SPI which should generally be +/* Max SCLK can be 133MHz ... dividing that by (2*4) gives + * us a freq of 16MHz for SPI which should generally be * slow enough for the slow reads the bootrom uses. */ +#if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \ + ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \ + (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1)) +# define BOOTROM_SUPPORTS_SPI_FAST_READ 1 +#else +# define BOOTROM_SUPPORTS_SPI_FAST_READ 0 +#endif #ifndef CONFIG_SPI_BAUD_INITBLOCK -# define CONFIG_SPI_BAUD_INITBLOCK 4 +# define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4) +#endif +#ifdef SPI0_BAUD +# define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD #endif /* PLL_DIV defines */ @@ -168,11 +145,18 @@ static inline void serial_putc(char c) #ifndef CONFIG_EBIU_RSTCTL_VAL # define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */ #endif +#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0) +# error invalid EBIU_RSTCTL value: must not set reserved bits +#endif #ifndef CONFIG_EBIU_MBSCTL_VAL # define CONFIG_EBIU_MBSCTL_VAL 0 #endif +#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0) +# error invalid EBIU_DDRQUE value: must not set reserved bits +#endif + /* Make sure our voltage value is sane so we don't blow up! */ #ifndef CONFIG_VR_CTL_VAL # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV) @@ -199,6 +183,9 @@ static inline void serial_putc(char c) # elif defined(__ADSPBF54x__) /* TBD; use default */ # undef CONFIG_VR_CTL_VLEV # define CONFIG_VR_CTL_VLEV VLEV_120 +# elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */ +# undef CONFIG_VR_CTL_VLEV +# define CONFIG_VR_CTL_VLEV VLEV_125 # endif # ifdef CONFIG_BFIN_MAC @@ -216,10 +203,17 @@ static inline void serial_putc(char c) # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ) #endif -__attribute__((saveall)) +BOOTROM_CALLED_FUNC_ATTR void initcode(ADI_BOOT_DATA *bootstruct) { - uint32_t old_baud = serial_init(); + /* Save the clock pieces that are used in baud rate calculation */ + unsigned int sdivB, divB, vcoB; + serial_init(); + if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { + sdivB = bfin_read_PLL_DIV() & 0xf; + vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f; + divB = serial_early_get_div(); + } #ifdef CONFIG_HW_WATCHDOG # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE @@ -244,12 +238,11 @@ void initcode(ADI_BOOT_DATA *bootstruct) * boot. Once we switch over to u-boot's SPI flash driver, we'll * increase the speed appropriately. */ - if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#ifdef SPI0_BAUD - bfin_write_SPI0_BAUD(CONFIG_SPI_BAUD_INITBLOCK); -#else + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) { + if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4) + bootstruct->dFlags |= BFLAG_FASTREAD; bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK); -#endif + } serial_putc('B'); @@ -267,40 +260,68 @@ void initcode(ADI_BOOT_DATA *bootstruct) bfin_write_SIC_IWR(1); #endif - serial_putc('L'); + /* With newer bootroms, we use the helper function to set up + * the memory controller. Older bootroms lacks such helpers + * so we do it ourselves. + */ + if (BOOTROM_CAPS_SYSCONTROL) { + serial_putc('S'); + + ADI_SYSCTRL_VALUES memory_settings; + memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL; + memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL; + memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL; + memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL; + syscontrol(SYSCTRL_WRITE | SYSCTRL_VRCTL | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT | + (CONFIG_VR_CTL_VAL & FREQ_MASK ? SYSCTRL_INTVOLTAGE : SYSCTRL_EXTVOLTAGE), &memory_settings, NULL); + } else { + serial_putc('L'); - bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL); + bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL); - serial_putc('A'); + serial_putc('A'); - /* Only reprogram when needed to avoid triggering unnecessary - * PLL relock sequences. - */ - if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) { - serial_putc('!'); - bfin_write_VR_CTL(CONFIG_VR_CTL_VAL); - asm("idle;"); - } + /* Only reprogram when needed to avoid triggering unnecessary + * PLL relock sequences. + */ + if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) { + serial_putc('!'); + bfin_write_VR_CTL(CONFIG_VR_CTL_VAL); + asm("idle;"); + } - serial_putc('C'); + serial_putc('C'); - bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL); + bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL); - serial_putc('K'); + serial_putc('K'); - /* Only reprogram when needed to avoid triggering unnecessary - * PLL relock sequences. - */ - if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) { - serial_putc('!'); - bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL); - asm("idle;"); + /* Only reprogram when needed to avoid triggering unnecessary + * PLL relock sequences. + */ + if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) { + serial_putc('!'); + bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL); + asm("idle;"); + } } /* Since we've changed the SCLK above, we may need to update * the UART divisors (UART baud rates are based on SCLK). + * Do the division by hand as there are no native instructions + * for dividing which means we'd generate a libgcc reference. */ - serial_reset_baud(old_baud); + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { + unsigned int sdivR, vcoR; + sdivR = bfin_read_PLL_DIV() & 0xf; + vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f; + int dividend = sdivB * divB * vcoR; + int divisor = vcoB * sdivR; + unsigned int quotient; + for (quotient = 0; dividend > 0; ++quotient) + dividend -= divisor; + serial_early_put_div(quotient - ANOMALY_05000230); + } serial_putc('F'); diff --git a/cpu/blackfin/serial.h b/cpu/blackfin/serial.h index f67109676..ce39148f8 100644 --- a/cpu/blackfin/serial.h +++ b/cpu/blackfin/serial.h @@ -156,16 +156,25 @@ static inline void serial_early_init(void) } __attribute__((always_inline)) -static inline uint32_t serial_early_get_baud(void) +static inline void serial_early_put_div(uint16_t divisor) { - /* If the UART isnt enabled, then we are booting an LDR - * from a non-UART source (so like flash) which means - * the baud rate here is meaningless. - */ - if ((*pUART_GCTL & UCEN) != UCEN) - return 0; + /* Set DLAB in LCR to Access DLL and DLH */ + ACCESS_LATCH(); + SSYNC(); -#if (0) /* See comment for serial_reset_baud() in initcode.c */ + /* Program the divisor to get the baud rate we want */ + *pUART_DLL = LOB(divisor); + *pUART_DLH = HIB(divisor); + SSYNC(); + + /* Clear DLAB in LCR to Access THR RBR IER */ + ACCESS_PORT_IER(); + SSYNC(); +} + +__attribute__((always_inline)) +static inline uint16_t serial_early_get_div(void) +{ /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH(); SSYNC(); @@ -173,16 +182,12 @@ static inline uint32_t serial_early_get_baud(void) uint8_t dll = *pUART_DLL; uint8_t dlh = *pUART_DLH; uint16_t divisor = (dlh << 8) | dll; - uint32_t baud = get_sclk() / (divisor * 16); /* Clear DLAB in LCR to Access THR RBR IER */ ACCESS_PORT_IER(); SSYNC(); - return baud; -#else - return CONFIG_BAUDRATE; -#endif + return divisor; } __attribute__((always_inline)) @@ -192,20 +197,7 @@ static inline void serial_early_set_baud(uint32_t baud) * weird multiplication is to make sure we over sample just * a little rather than under sample the incoming signals. */ - uint16_t divisor = (get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230; - - /* Set DLAB in LCR to Access DLL and DLH */ - ACCESS_LATCH(); - SSYNC(); - - /* Program the divisor to get the baud rate we want */ - *pUART_DLL = LOB(divisor); - *pUART_DLH = HIB(divisor); - SSYNC(); - - /* Clear DLAB in LCR to Access THR RBR IER */ - ACCESS_PORT_IER(); - SSYNC(); + serial_early_put_div((get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230); } #ifndef BFIN_IN_INITCODE @@ -235,32 +227,6 @@ static inline void serial_early_puts(const char *s) #endif .endm -/* Recursively expand calls to _serial_putc for every byte - * passed to us. Append a newline when we're all done. - */ -.macro _serial_early_putc byte:req morebytes:vararg -#ifdef CONFIG_DEBUG_EARLY_SERIAL - R0 = \byte; - call _serial_putc; -.ifnb \morebytes - _serial_early_putc \morebytes -.else -.if (\byte != '\n') - _serial_early_putc '\n' -.endif -.endif -#endif -.endm - -/* Wrapper around recurisve _serial_early_putc macro which - * simply prepends the string "Early: " - */ -.macro serial_early_putc byte:req morebytes:vararg -#ifdef CONFIG_DEBUG_EARLY_SERIAL - _serial_early_putc 'E', 'a', 'r', 'l', 'y', ':', ' ', \byte, \morebytes -#endif -.endm - /* Since we embed the string right into our .text section, we need * to find its address. We do this by getting our PC and adding 2 * bytes (which is the length of the jump instruction). Then we diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c index 12e8f3871..b958f8dc0 100644 --- a/cpu/i386/sc520.c +++ b/cpu/i386/sc520.c @@ -341,7 +341,7 @@ void pci_sc520_init(struct pci_controller *hose) SC520_PCI_MEMORY_BUS, SC520_PCI_MEMORY_PHYS, SC520_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI memory space */ pci_set_region(hose->regions + 1, diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index 66f9164d5..11f70b0db 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -181,9 +181,14 @@ void cpu_init_f(void) /* FlexBus Chipselect */ init_fbcs(); +#ifdef CONFIG_SYS_MCF_SYNCR + /* Set clockspeed according to board header file */ + mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR); +#else /* Set clockspeed to 100MHz */ - mbar_writeShort(MCF_FMPLL_SYNCR, + mbar_writeLong(MCF_FMPLL_SYNCR, MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); +#endif while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ; } @@ -219,7 +224,8 @@ int fecpin_setclear(struct eth_device *dev, int setclear) { if (setclear) { /* Enable Ethernet pins */ - mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C); + mbar_writeByte(MCF_GPIO_PAR_FECI2C, + (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0)); } else { } diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c index fe51fb480..c93a5180e 100644 --- a/cpu/mcf52x2/speed.c +++ b/cpu/mcf52x2/speed.c @@ -77,7 +77,8 @@ int get_clocks (void) #endif gd->cpu_clk = CONFIG_SYS_CLK; -#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275) +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \ + defined(CONFIG_M5271) || defined(CONFIG_M5275) gd->bus_clk = gd->cpu_clk / 2; #else gd->bus_clk = gd->cpu_clk; diff --git a/cpu/mcf5445x/pci.c b/cpu/mcf5445x/pci.c index c4a3b05ee..7f9784c3c 100644 --- a/cpu/mcf5445x/pci.c +++ b/cpu/mcf5445x/pci.c @@ -146,7 +146,7 @@ void pci_mcf5445x_init(struct pci_controller *hose) pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS, CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 3; diff --git a/cpu/mcf547x_8x/pci.c b/cpu/mcf547x_8x/pci.c index f5c25367f..f867dc127 100644 --- a/cpu/mcf547x_8x/pci.c +++ b/cpu/mcf547x_8x/pci.c @@ -149,7 +149,7 @@ void pci_mcf547x_8x_init(struct pci_controller *hose) pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS, CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 3; diff --git a/cpu/mpc512x/Makefile b/cpu/mpc512x/Makefile index e8f106074..297d13584 100644 --- a/cpu/mpc512x/Makefile +++ b/cpu/mpc512x/Makefile @@ -26,6 +26,9 @@ LIB = $(obj)lib$(CPU).a START = start.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o +ifdef CONFIG_IIM +COBJS += iim.o +endif SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc512x/iim.c b/cpu/mpc512x/iim.c new file mode 100644 index 000000000..6cdc42259 --- /dev/null +++ b/cpu/mpc512x/iim.c @@ -0,0 +1,394 @@ +/* + * Copyright 2008 Silicon Turnkey Express, Inc. + * Martha Marx <mmarx@silicontkx.com> + * + * ADS5121 IIM (Fusebox) Interface + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#ifdef CONFIG_CMD_FUSE + +DECLARE_GLOBAL_DATA_PTR; + +static char cur_bank = '1'; + +char *iim_err_msg(u32 err) +{ + static char *IIM_errs[] = { + "Parity Error in cache", + "Explicit Sense Cycle Error", + "Write to Locked Register Error", + "Read Protect Error", + "Override Protect Error", + "Write Protect Error"}; + + int i; + + if (!err) + return ""; + for (i = 1; i < 8; i++) + if (err & (1 << i)) + printf("IIM - %s\n", IIM_errs[i-1]); + return ""; +} + +int in_range(int n, int min, int max, char *err, char *usg) +{ + if (n > max || n < min) { + printf(err); + printf("Usage:\n%s\n", usg); + return 0; + } + return 1; +} + +int ads5121_fuse_read(int bank, int fstart, int num) +{ + iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim; + u32 *iim_fb, dummy; + int f, ctr; + + out_be32(&iim->err, in_be32(&iim->err)); + if (bank == 0) + iim_fb = (u32 *)&(iim->fbac0); + else + iim_fb = (u32 *)&(iim->fbac1); +/* try a read to see if Read Protect is set */ + dummy = in_be32(&iim_fb[0]); + if (in_be32(&iim->err) & IIM_ERR_RPE) { + printf("\tRead protect fuse is set\n"); + out_be32(&iim->err, IIM_ERR_RPE); + return 0; + } + printf("Reading Bank %d cache\n", bank); + for (f = fstart, ctr = 0; num > 0; ctr++, num--, f++) { + if (ctr % 4 == 0) + printf("F%2d:", f); + printf("\t%#04x", (u8)(iim_fb[f])); + if (ctr % 4 == 3) + printf("\n"); + } + if (ctr % 4 != 0) + printf("\n"); +} + +int ads5121_fuse_override(int bank, int f, u8 val) +{ + iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim; + u32 *iim_fb; + u32 iim_stat; + int i; + + out_be32(&iim->err, in_be32(&iim->err)); + if (bank == 0) + iim_fb = (u32 *)&(iim->fbac0); + else + iim_fb = (u32 *)&(iim->fbac1); +/* try a read to see if Read Protect is set */ + iim_stat = in_be32(&iim_fb[0]); + if (in_be32(&iim->err) & IIM_ERR_RPE) { + printf("Read protect fuse is set on bank %d;" + "Override protect may also be set\n", bank); + printf("An attempt will be made to override\n"); + out_be32(&iim->err, IIM_ERR_RPE); + } + if (iim_stat & IIM_FBAC_FBOP) { + printf("Override protect fuse is set on bank %d\n", bank); + return 1; + } + if (f > IIM_FMAX) /* reset the entire bank */ + for (i = 0; i < IIM_FMAX + 1; i++) + out_be32(&iim_fb[i], 0); + else + out_be32(&iim_fb[f], val); + return 0; +} + +int ads5121_fuse_prog(cmd_tbl_t *cmdtp, int bank, char *fuseno_bitno) +{ + iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim; + int f, i, bitno; + u32 stat, err; + + f = simple_strtol(fuseno_bitno, NULL, 10); + if (f == 0 && fuseno_bitno[0] != '0') + f = -1; + if (!in_range(f, 0, IIM_FMAX, + "<frow> must be between 0-31\n\n", cmdtp->usage)) + return 1; + bitno = -1; + for (i = 0; i < 6; i++) { + if (fuseno_bitno[i] == '_') { + bitno = simple_strtol(&(fuseno_bitno[i+1]), NULL, 10); + if (bitno == 0 && fuseno_bitno[i+1] != '0') + bitno = -1; + break; + } + } + if (!in_range(bitno, 0, 7, "Bit number ranges from 0-7\n" + "Example of <frow_bitno>: \"18_4\" sets bit 4 of row 18\n", + cmdtp->usage)) + return 1; + out_be32(&iim->err, in_be32(&iim->err)); + out_be32(&iim->prg_p, IIM_PRG_P_SET); + out_be32(&iim->ua, IIM_SET_UA(bank, f)); + out_be32(&iim->la, IIM_SET_LA(f, bitno)); +#ifdef DEBUG + printf("Programming disabled with DEBUG defined \n"); + printf(""Set up to pro + printf("iim.ua = %x; iim.la = %x\n", iim->ua, iim->la); +#else + out_be32(&iim->fctl, IIM_FCTL_PROG_PULSE | IIM_FCTL_PROG); + do + udelay(20); + while ((stat = in_be32(&iim->stat)) & IIM_STAT_BUSY); + out_be32(&iim->prg_p, 0); + err = in_be32(&iim->err); + if (stat & IIM_STAT_PRGD) { + if (!(err & (IIM_ERR_WPE | IIM_ERR_WPE))) { + printf("Fuse is successfully set"); + if (err) + printf(" - however there are other errors"); + printf("\n"); + } + iim->stat = 0; + } + if (err) { + iim_err_msg(err); + out_be32(&iim->err, in_be32(&iim->err)); + } +#endif +} + +int ads5121_fuse_sense(int bank, int fstart, int num) +{ + iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim; + u32 iim_fbac; + u32 stat, err, err_hold = 0; + int f, ctr; + + out_be32(&iim->err, in_be32(&iim->err)); + if (bank == 0) + iim_fbac = in_be32(&iim->fbac0); + else + iim_fbac = in_be32(&iim->fbac1); + if (iim_fbac & IIM_FBAC_FBESP) { + printf("\tSense Protect disallows this operation\n"); + out_be32(&iim->err, IIM_FBAC_FBESP); + return 1; + } + err = in_be32(&iim->err); + if (err) { + iim_err_msg(err); + err_hold |= err; + } + if (err & IIM_ERR_RPE) + printf("\tRead protect fuse is set; " + "Sense Protect may be set but will be attempted\n"); + if (err) + out_be32(&iim->err, err); + printf("Sensing fuse(s) on Bank %d\n", bank); + for (f = fstart, ctr = 0; num > 0; ctr++, f++, num--) { + out_be32(&iim->ua, IIM_SET_UA(bank, f)); + out_be32(&iim->la, IIM_SET_LA(f, 0)); + out_be32(&iim->fctl, IIM_FCTL_ESNS_N); + do + udelay(20); + while ((stat = in_be32(&iim->stat)) & IIM_STAT_BUSY); + err = in_be32(&iim->err); + if (err & IIM_ERR_SNSE) { + iim_err_msg(err); + out_be32(&iim->err, IIM_ERR_SNSE); + return 1; + } + if (stat & IIM_STAT_SNSD) { + out_be32(&iim->stat, 0); + if (ctr % 4 == 0) + printf("F%2d:", f); + printf("\t%#04x", (u8)iim->sdat); + if (ctr % 4 == 3) + printf("\n"); + } + if (err) { + err_hold |= err; + out_be32(&iim->err, err); + } + } + if (ctr % 4 != 0) + printf("\n"); + if (err_hold) + iim_err_msg(err_hold); + + return 0; +} + +int ads5121_fuse_stat(int bank) +{ + iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim; + u32 iim_fbac; + u32 err; + + out_be32(&iim->err, in_be32(&iim->err)); + if (bank == 0) + iim_fbac = in_be32(&iim->fbac0); + else + iim_fbac = in_be32(&iim->fbac1); + err = in_be32(&iim->err); + if (err) + iim_err_msg(err); + if (err & IIM_ERR_RPE || iim_fbac & IIM_FBAC_FBRP) { + if (iim_fbac == 0) + printf("Since protection settings can't be read - " + "try sensing fuse row 0;\n"); + return 0; + } + if (iim_fbac & IIM_PROTECTION) + printf("Protection Fuses Bank %d = %#04x:\n", bank, iim_fbac); + else if (!(err & IIM_ERR_RPE)) + printf("No Protection fuses are set\n"); + if (iim_fbac & IIM_FBAC_FBWP) + printf("\tWrite Protect fuse is set\n"); + if (iim_fbac & IIM_FBAC_FBOP) + printf("\tOverride Protect fuse is set\n"); + if (iim_fbac & IIM_FBAC_FBESP) + printf("\tSense Protect Fuse is set\n"); + out_be32(&iim->err, in_be32(&iim->err)); + + return 0; +} + +int do_ads5121_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int frow, n, v, bank; + + if (cur_bank == '0') + bank = 0; + else + bank = 1; + + switch (argc) { + case 0: + case 1: + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + case 2: + if (strncmp(argv[1], "stat", 4) == 0) + return ads5121_fuse_stat(bank); + if (strncmp(argv[1], "read", 4) == 0) + return ads5121_fuse_read(bank, 0, IIM_FMAX + 1); + if (strncmp(argv[1], "sense", 5) == 0) + return ads5121_fuse_sense(bank, 0, IIM_FMAX + 1); + if (strncmp(argv[1], "ovride", 6) == 0) + return ads5121_fuse_override(bank, IIM_FMAX + 1, 0); + if (strncmp(argv[1], "bank", 4) == 0) { + printf("Active Fuse Bank is %c\n", cur_bank); + return 0; + } + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + case 3: + if (strncmp(argv[1], "bank", 4) == 0) { + if (argv[2][0] == '0') + cur_bank = '0'; + else if (argv[2][0] == '1') + cur_bank = '1'; + else { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + printf("Setting Active Fuse Bank to %c\n", cur_bank); + return 0; + } + if (strncmp(argv[1], "prog", 4) == 0) + return ads5121_fuse_prog(cmdtp, bank, argv[2]); + + frow = (int)simple_strtol(argv[2], NULL, 10); + if (frow == 0 && argv[2][0] != '0') + frow = -1; + if (!in_range(frow, 0, IIM_FMAX, + "<frow> must be between 0-31\n\n", cmdtp->usage)) + return 1; + if (strncmp(argv[1], "read", 4) == 0) + return ads5121_fuse_read(bank, frow, 1); + if (strncmp(argv[1], "ovride", 6) == 0) + return ads5121_fuse_override(bank, frow, 0); + if (strncmp(argv[1], "sense", 5) == 0) + return ads5121_fuse_sense(bank, frow, 1); + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + case 4: + frow = (int)simple_strtol(argv[2], NULL, 10); + if (frow == 0 && argv[2][0] != '0') + frow = -1; + if (!in_range(frow, 0, IIM_FMAX, + "<frow> must be between 0-31\n\n", cmdtp->usage)) + return 1; + if (strncmp(argv[1], "read", 4) == 0) { + n = (int)simple_strtol(argv[3], NULL, 10); + if (!in_range(frow + n, frow + 1, IIM_FMAX + 1, + "<frow>+<n> must be between 1-32\n\n", + cmdtp->usage)) + return 1; + return ads5121_fuse_read(bank, frow, n); + } + if (strncmp(argv[1], "ovride", 6) == 0) { + v = (int)simple_strtol(argv[3], NULL, 10); + return ads5121_fuse_override(bank, frow, v); + } + if (strncmp(argv[1], "sense", 5) == 0) { + n = (int)simple_strtol(argv[3], NULL, 10); + if (!in_range(frow + n, frow + 1, IIM_FMAX + 1, + "<frow>+<n> must be between 1-32\n\n", + cmdtp->usage)) + return 1; + return ads5121_fuse_sense(bank, frow, n); + } + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + default: /* at least 5 args */ + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } +} + +U_BOOT_CMD( + fuse, CONFIG_SYS_MAXARGS, 0, do_ads5121_fuse, + " - Read, Sense, Override or Program Fuses\n", + "bank <n> - sets active Fuse Bank to 0 or 1\n" + " no args shows current active bank\n" + "fuse stat - print active fuse bank's protection status\n" + "fuse read [<frow> [<n>]] - print <n> fuse rows starting at <frow>\n" + " no args to print entire bank's fuses\n" + "fuse ovride [<frow> [<v>]]- override fuses at <frow> with <v>\n" + " no <v> defaults to 0 for the row\n" + " no args resets entire bank to 0\n" + " NOTE - settings persist until hard reset\n" + "fuse sense [<frow>] - senses current fuse at <frow>\n" + " no args for entire bank\n" + "fuse prog <frow_bit> - program fuse at row <frow>, bit <_bit>\n" + " <frow> is 0-31, <bit> is 0-7; eg. 13_2 \n" + " WARNING - this is permanent\n" + ); +#endif /* CONFIG_CMD_FUSE */ diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c index a3251abf5..225738a07 100644 --- a/cpu/mpc5xxx/pci_mpc5200.c +++ b/cpu/mpc5xxx/pci_mpc5200.c @@ -93,7 +93,7 @@ void pci_mpc5xxx_init (struct pci_controller *hose) CONFIG_PCI_MEMORY_BUS, CONFIG_PCI_MEMORY_PHYS, CONFIG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI memory space */ pci_set_region(hose->regions + 1, diff --git a/cpu/mpc8220/pci.c b/cpu/mpc8220/pci.c index a78a82850..7ef43b72c 100644 --- a/cpu/mpc8220/pci.c +++ b/cpu/mpc8220/pci.c @@ -165,7 +165,7 @@ pci_mpc8220_init(struct pci_controller *hose) CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, CONFIG_PCI_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 3; diff --git a/cpu/mpc824x/pci.c b/cpu/mpc824x/pci.c index 7e3c4c3b7..cf9cf41ae 100644 --- a/cpu/mpc824x/pci.c +++ b/cpu/mpc824x/pci.c @@ -34,7 +34,7 @@ void pci_mpc824x_init (struct pci_controller *hose) CHRP_PCI_MEMORY_BUS, CHRP_PCI_MEMORY_PHYS, CHRP_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI memory space */ pci_set_region(hose->regions + 1, diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c index f4beca55b..1b034cd57 100644 --- a/cpu/mpc8260/cpu.c +++ b/cpu/mpc8260/cpu.c @@ -327,7 +327,7 @@ int cpu_eth_init(bd_t *bis) fec_initialize(bis); #endif #if defined(CONFIG_ETHER_ON_SCC) - mpc82xx_scc_enet_initialize(bd); + mpc82xx_scc_enet_initialize(bis); #endif return 0; } diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c index 378d6c573..f1e9bb4b9 100644 --- a/cpu/mpc8260/pci.c +++ b/cpu/mpc8260/pci.c @@ -410,12 +410,12 @@ void pci_mpc8250_init (struct pci_controller *hose) pci_set_region (hose->regions + 0, PCI_SLV_MEM_BUS, PCI_SLV_MEM_LOCAL, - gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); + gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); #else pci_set_region (hose->regions + 0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE, - 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY); + 0x4000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); #endif /* PCI memory space */ diff --git a/cpu/mpc8260/serial_smc.c b/cpu/mpc8260/serial_smc.c index a6efa6689..fbb3fb042 100644 --- a/cpu/mpc8260/serial_smc.c +++ b/cpu/mpc8260/serial_smc.c @@ -64,6 +64,23 @@ DECLARE_GLOBAL_DATA_PTR; #endif +#if !defined(CONFIG_SYS_SMC_RXBUFLEN) +#define CONFIG_SYS_SMC_RXBUFLEN 1 +#define CONFIG_SYS_MAXIDLE 0 +#else +#if !defined(CONFIG_SYS_MAXIDLE) +#error "you must define CONFIG_SYS_MAXIDLE" +#endif +#endif + +typedef volatile struct serialbuffer { + cbd_t rxbd; /* Rx BD */ + cbd_t txbd; /* Tx BD */ + uint rxindex; /* index for next character to read */ + volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */ + volatile uchar txbuf; /* tx buffers */ +} serialbuffer_t; + /* map rs_table index to baud rate generator index */ static unsigned char brg_map[] = { 6, /* BRG7 for SMC1 */ @@ -79,9 +96,9 @@ int serial_init (void) volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile smc_t *sp; volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; volatile cpm8260_t *cp = &(im->im_cpm); uint dpaddr; + volatile serialbuffer_t *rtx; /* initialize pointers to SMC */ @@ -89,8 +106,7 @@ int serial_init (void) *(ushort *)(&im->im_dprambase[PROFF_SMC_BASE]) = PROFF_SMC; up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC]; - /* Disable transmitter/receiver. - */ + /* Disable transmitter/receiver. */ sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */ @@ -99,20 +115,23 @@ int serial_init (void) * damm: allocating space after the two buffers for rx/tx data */ - dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16); + /* allocate size of struct serialbuffer with bd rx/tx, + * buffer rx/tx and rx index + */ + dpaddr = m8260_cpm_dpalloc((sizeof(serialbuffer_t)), 16); + + rtx = (serialbuffer_t *)&im->im_dprambase[dpaddr]; /* Set the physical address of the host memory buffers in * the buffer descriptors. */ - rbdf = (cbd_t *)&im->im_dprambase[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = 0; + rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf; + rtx->rxbd.cbd_sc = 0; + + rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf; + rtx->txbd.cbd_sc = 0; - /* Set up the uart parameters in the parameter ram. - */ + /* Set up the uart parameters in the parameter ram. */ up->smc_rbase = dpaddr; up->smc_tbase = dpaddr+sizeof(cbd_t); up->smc_rfcr = CPMFCR_EB; @@ -126,8 +145,7 @@ int serial_init (void) */ sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - /* Mask all interrupts and remove anything pending. - */ + /* Mask all interrupts and remove anything pending. */ sp->smc_smcm = 0; sp->smc_smce = 0xff; @@ -136,22 +154,19 @@ int serial_init (void) */ im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr&~CMXSMR_MASK)|CMXSMR_VALUE; - /* Set up the baud rate generator. - */ + /* Set up the baud rate generator. */ serial_setbrg (); - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; + /* Make the first buffer the only buffer. */ + rtx->txbd.cbd_sc |= BD_SC_WRAP; + rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - /* Single character receive. - */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; + /* single/multi character receive. */ + up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN; + up->smc_maxidl = CONFIG_SYS_MAXIDLE; + rtx->rxindex = 0; - /* Initialize Tx/Rx parameters. - */ + /* Initialize Tx/Rx parameters. */ while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ ; @@ -162,8 +177,7 @@ int serial_init (void) while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ ; - /* Enable transmitter/receiver. - */ + /* Enable transmitter/receiver. */ sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; return (0); @@ -183,27 +197,23 @@ serial_setbrg (void) void serial_putc(const char c) { - volatile cbd_t *tbdf; - volatile char *buf; volatile smc_uart_t *up; volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile serialbuffer_t *rtx; if (c == '\n') serial_putc ('\r'); up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); - tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase]; + rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase]; - /* Wait for last character to go. - */ - buf = (char *)tbdf->cbd_bufaddr; - while (tbdf->cbd_sc & BD_SC_READY) + /* Wait for last character to go. */ + while (rtx->txbd.cbd_sc & BD_SC_READY & BD_SC_READY) ; - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; + rtx->txbuf = c; + rtx->txbd.cbd_datlen = 1; + rtx->txbd.cbd_sc |= BD_SC_READY; } void @@ -217,39 +227,44 @@ serial_puts (const char *s) int serial_getc(void) { - volatile cbd_t *rbdf; - volatile unsigned char *buf; volatile smc_uart_t *up; volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - unsigned char c; + volatile serialbuffer_t *rtx; + unsigned char c; up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); - rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase]; + rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase]; - /* Wait for character to show up. - */ - buf = (unsigned char *)rbdf->cbd_bufaddr; - while (rbdf->cbd_sc & BD_SC_EMPTY) + /* Wait for character to show up. */ + while (rtx->rxbd.cbd_sc & BD_SC_EMPTY) ; - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; + /* the characters are read one by one, + * use the rxindex to know the next char to deliver + */ + c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr + rtx->rxindex); + rtx->rxindex++; + + /* check if all char are readout, then make prepare for next receive */ + if (rtx->rxindex >= rtx->rxbd.cbd_datlen) { + rtx->rxindex = 0; + rtx->rxbd.cbd_sc |= BD_SC_EMPTY; + } return(c); } int serial_tstc() { - volatile cbd_t *rbdf; volatile smc_uart_t *up; volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile serialbuffer_t *rtx; up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]); + rtx = (serialbuffer_t *)&im->im_dprambase[up->smc_rbase]; - rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase]; - - return(!(rbdf->cbd_sc & BD_SC_EMPTY)); + return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY); } #endif /* CONFIG_CONS_ON_SMC */ @@ -309,8 +324,7 @@ kgdb_serial_init (void) *(ushort *)(&im->im_dprambase[KGDB_PROFF_SMC_BASE]) = KGDB_PROFF_SMC; up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC]; - /* Disable transmitter/receiver. - */ + /* Disable transmitter/receiver. */ sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); /* NOTE: I/O port pins are set up via the iop_conf_tab[] table */ @@ -331,8 +345,7 @@ kgdb_serial_init (void) tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; tbdf->cbd_sc = 0; - /* Set up the uart parameters in the parameter ram. - */ + /* Set up the uart parameters in the parameter ram. */ up->smc_rbase = dpaddr; up->smc_tbase = dpaddr+sizeof(cbd_t); up->smc_rfcr = CPMFCR_EB; @@ -346,8 +359,7 @@ kgdb_serial_init (void) */ sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART; - /* Mask all interrupts and remove anything pending. - */ + /* Mask all interrupts and remove anything pending. */ sp->smc_smcm = 0; sp->smc_smce = 0xff; @@ -357,8 +369,7 @@ kgdb_serial_init (void) im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr & ~KGDB_CMXSMR_MASK) | KGDB_CMXSMR_VALUE; - /* Set up the baud rate generator. - */ + /* Set up the baud rate generator. */ #if defined(CONFIG_KGDB_USE_EXTC) m8260_cpm_extcbrg(brg_map[KGDB_SMC_INDEX], speed, CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL); @@ -366,18 +377,15 @@ kgdb_serial_init (void) m8260_cpm_setbrg(brg_map[KGDB_SMC_INDEX], speed); #endif - /* Make the first buffer the only buffer. - */ + /* Make the first buffer the only buffer. */ tbdf->cbd_sc |= BD_SC_WRAP; rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - /* Single character receive. - */ + /* Single character receive. */ up->smc_mrblr = 1; up->smc_maxidl = 0; - /* Initialize Tx/Rx parameters. - */ + /* Initialize Tx/Rx parameters. */ while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ ; @@ -388,8 +396,7 @@ kgdb_serial_init (void) while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ ; - /* Enable transmitter/receiver. - */ + /* Enable transmitter/receiver. */ sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; printf("SMC%d at %dbps ", CONFIG_KGDB_INDEX, speed); @@ -410,8 +417,7 @@ putDebugChar(const char c) tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase]; - /* Wait for last character to go. - */ + /* Wait for last character to go. */ buf = (char *)tbdf->cbd_bufaddr; while (tbdf->cbd_sc & BD_SC_READY) ; @@ -442,8 +448,7 @@ getDebugChar(void) rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase]; - /* Wait for character to show up. - */ + /* Wait for character to show up. */ buf = (unsigned char *)rbdf->cbd_bufaddr; while (rbdf->cbd_sc & BD_SC_EMPTY) ; diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 587fca323..9e0a05d61 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -34,6 +34,7 @@ #include <libfdt.h> #include <tsec.h> #include <netdev.h> +#include <fsl_esdhc.h> DECLARE_GLOBAL_DATA_PTR; @@ -385,3 +386,16 @@ int cpu_eth_init(bd_t *bis) #endif return 0; } + +/* + * Initializes on-chip MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t *bis) +{ +#ifdef CONFIG_FSL_ESDHC + return fsl_esdhc_mmc_init(bis); +#else + return 0; +#endif +} diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c index e9965d7df..5fe89646c 100644 --- a/cpu/mpc83xx/pci.c +++ b/cpu/mpc83xx/pci.c @@ -89,7 +89,7 @@ static void pci_init_bus(int bus, struct pci_region *reg) hose->regions[i].bus_start = 0; hose->regions[i].phys_start = 0; hose->regions[i].size = gd->ram_size; - hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY; + hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; hose->first_busno = 0; hose->last_busno = 0xff; diff --git a/cpu/mpc83xx/pcie.c b/cpu/mpc83xx/pcie.c index 02150bafd..12b5f69ce 100644 --- a/cpu/mpc83xx/pcie.c +++ b/cpu/mpc83xx/pcie.c @@ -109,13 +109,13 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, hose->regions[i].bus_start = 0; hose->regions[i].phys_start = 0; hose->regions[i].size = gd->ram_size; - hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY; + hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; i = hose->region_count++; hose->regions[i].bus_start = CONFIG_SYS_IMMR; hose->regions[i].phys_start = CONFIG_SYS_IMMR; hose->regions[i].size = 0x100000; - hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_MEMORY; + hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; hose->first_busno = max_bus; hose->last_busno = 0xff; diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 627e61b05..99d88a888 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -48,6 +48,7 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o # supports ddr1/2/3 COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o +COBJS-$(CONFIG_P2020) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index a34e2515e..5b72fe544 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -31,6 +31,7 @@ #include <command.h> #include <tsec.h> #include <netdev.h> +#include <fsl_esdhc.h> #include <asm/cache.h> #include <asm/io.h> @@ -62,6 +63,8 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(8568, 8568_E), CPU_TYPE_ENTRY(8572, 8572), CPU_TYPE_ENTRY(8572, 8572_E), + CPU_TYPE_ENTRY(P2020, P2020), + CPU_TYPE_ENTRY(P2020, P2020_E), }; struct cpu_type *identify_cpu(u32 ver) @@ -142,11 +145,14 @@ int checkcpu (void) get_sys_info(&sysinfo); - puts("Clock Configuration:\n "); - for (i = 0; i < CONFIG_NUM_CPUS; i++) + puts("Clock Configuration:"); + for (i = 0; i < CONFIG_NUM_CPUS; i++) { + if (!(i & 3)) + printf ("\n "); printf("CPU%d:%-4s MHz, ", i,strmhz(buf1, sysinfo.freqProcessor[i])); - printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); + } + printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); switch (ddr_ratio) { case 0x0: @@ -390,5 +396,19 @@ int cpu_eth_init(bd_t *bis) #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) tsec_standard_init(bis); #endif + + return 0; +} + +/* + * Initializes on-chip MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t *bis) +{ +#ifdef CONFIG_FSL_ESDHC + return fsl_esdhc_mmc_init(bis); +#else return 0; +#endif } diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c index a2b45c571..8dc2b3ac5 100644 --- a/cpu/mpc85xx/ddr-gen3.c +++ b/cpu/mpc85xx/ddr-gen3.c @@ -19,6 +19,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, { unsigned int i; volatile ccsr_ddr_t *ddr; + u32 temp_sdram_cfg; switch (ctrl_num) { case 0: @@ -78,6 +79,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); + /* Do not enable the memory */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg); + temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg); /* * For 8572 DDR1 erratum - DDR controller may enter illegal state * when operatiing in 32-bit bus mode with 4-beat bursts, @@ -99,7 +104,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, udelay(200); asm volatile("sync;isync"); - out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); + /* Let the controller go */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ while (in_be32(&ddr->sdram_cfg_2) & 0x10) { diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 25fa9ee8f..c73bf056e 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -132,61 +132,41 @@ void init_addr_map(void) unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { unsigned int tlb_size; - unsigned int ram_tlb_index; - unsigned int ram_tlb_address; + unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START; + unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; + unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff; + u64 size, memsize = (u64)memsize_in_meg << 20; - /* - * Determine size of each TLB1 entry. - */ - switch (memsize_in_meg) { - case 16: - case 32: - tlb_size = BOOKE_PAGESZ_16M; - break; - case 64: - case 128: - tlb_size = BOOKE_PAGESZ_64M; - break; - case 256: - case 512: - tlb_size = BOOKE_PAGESZ_256M; - break; - case 1024: - case 2048: - if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx)) - tlb_size = BOOKE_PAGESZ_1G; - else - tlb_size = BOOKE_PAGESZ_256M; - break; - default: - puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G" - " and 2G are supported.\n"); + size = min(memsize, CONFIG_MAX_MEM_MAPPED); - /* - * The memory was not able to be mapped. - * Default to a small size. - */ - tlb_size = BOOKE_PAGESZ_64M; - memsize_in_meg = 64; - break; - } + /* Convert (4^max) kB to (2^max) bytes */ + max_cam = max_cam * 2 + 10; + + for (; size && ram_tlb_index < 16; ram_tlb_index++) { + u32 camsize = __ilog2_u64(size) & ~1U; + u32 align = __ilog2(ram_tlb_address) & ~1U; + + if (align == -2) align = max_cam; + if (camsize > align) + camsize = align; + + if (camsize > max_cam) + camsize = max_cam; + + tlb_size = (camsize - 10) / 2; - /* - * Configure DDR TLB1 entries. - * Starting at TLB1 8, use no more than 8 TLB1 entries. - */ - ram_tlb_index = CONFIG_SYS_DDR_TLB_START; - ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; - while (ram_tlb_address < (memsize_in_meg * 1024 * 1024) - && ram_tlb_index < 16) { set_tlb(1, ram_tlb_address, ram_tlb_address, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, ram_tlb_index, tlb_size, 1); - ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2)); - ram_tlb_index++; + size -= 1ULL << camsize; + memsize -= 1ULL << camsize; + ram_tlb_address += 1UL << camsize; } + if (memsize) + printf("%lldM left unmapped\n", memsize >> 20); + /* * Confirm that the requested amount of memory was mapped. */ diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index dc53bee58..c41616d2f 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -32,6 +32,17 @@ #include <asm/fsl_law.h> +/* + * Default board reset function + */ +static void +__board_reset(void) +{ + /* Do nothing */ +} +void board_reset(void) __attribute((weak, alias("__board_reset"))); + + int checkcpu(void) { @@ -39,49 +50,25 @@ checkcpu(void) uint pvr, svr; uint ver; uint major, minor; + char buf1[32], buf2[32]; volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; - - puts("Freescale PowerPC\n"); - - pvr = get_pvr(); - ver = PVR_VER(pvr); - major = PVR_MAJ(pvr); - minor = PVR_MIN(pvr); - - puts("CPU:\n"); - puts(" Core: "); - - switch (ver) { - case PVR_VER(PVR_86xx): - { - uint msscr0 = mfspr(MSSCR0); - printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); - if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) - puts("\n Core1Translation Enabled"); - debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); - } - break; - default: - puts("Unknown"); - break; - } - printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); + uint msscr0 = mfspr(MSSCR0); svr = get_svr(); ver = SVR_SOC_VER(svr); major = SVR_MAJ(svr); minor = SVR_MIN(svr); - puts(" System: "); + puts("CPU: "); + switch (ver) { case SVR_8641: - if (SVR_SUBVER(svr) == 1) { - puts("8641D"); - } else { puts("8641"); - } - break; + break; + case SVR_8641D: + puts("8641D"); + break; case SVR_8610: puts("8610"); break; @@ -90,98 +77,69 @@ checkcpu(void) break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); + puts("Core: "); + + pvr = get_pvr(); + ver = PVR_E600_VER(pvr); + major = PVR_E600_MAJ(pvr); + minor = PVR_E600_MIN(pvr); + + printf("E600 Core %d", (msscr0 & 0x20) ? 1 : 0 ); + if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) + puts("\n Core1Translation Enabled"); + debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); + + printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); - puts(" Clocks: "); - printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); - printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000); - printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000); + puts("Clock Configuration:\n"); + printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); + printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); + printf(" DDR:%-4s MHz (%s MT/s data rate), ", + strmhz(buf1, sysinfo.freqSystemBus / 2), + strmhz(buf2, sysinfo.freqSystemBus)); if (sysinfo.freqLocalBus > LCRR_CLKDIV) { - printf("LBC:%4lu MHz\n", sysinfo.freqLocalBus / 1000000); + printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); } - puts(" L2: "); - if (get_l2cr() & 0x80000000) - puts("Enabled\n"); - else + puts("L1: D-cache 32 KB enabled\n"); + puts(" I-cache 32 KB enabled\n"); + + puts("L2: "); + if (get_l2cr() & 0x80000000) { +#if defined(CONFIG_MPC8610) + puts("256"); +#elif defined(CONFIG_MPC8641) + puts("512"); +#endif + puts(" KB enabled\n"); + } else { puts("Disabled\n"); + } return 0; } -static inline void -soft_restart(unsigned long addr) -{ -#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD) - - /* - * SRR0 has system reset vector, SRR1 has default MSR value - * rfi restores MSR from SRR1 and sets the PC to the SRR0 value - */ - - __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); - __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); - __asm__ __volatile__ ("mtspr 27, 4"); - __asm__ __volatile__ ("rfi"); - -#else /* CONFIG_MPC8641HPCN */ - - out8(PIXIS_BASE + PIXIS_RST, 0); - -#endif /* !CONFIG_MPC8641HPCN */ - - while (1) ; /* not reached */ -} - - -/* - * No generic way to do board reset. Simply call soft_reset. - */ void do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD) - -#ifdef CONFIG_SYS_RESET_ADDRESS - ulong addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* - * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, - * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid - * address. Better pick an address known to be invalid on your - * system and assign it to CONFIG_SYS_RESET_ADDRESS. - */ - ulong addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong); -#endif - - /* flush and disable I/D cache */ - __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); - __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); - __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); - __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("mtspr 1008, 4"); - __asm__ __volatile__ ("isync"); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("mtspr 1008, 5"); - __asm__ __volatile__ ("isync"); - __asm__ __volatile__ ("sync"); - - soft_restart(addr); - -#else /* CONFIG_MPC8641HPCN */ + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; - out8(PIXIS_BASE + PIXIS_RST, 0); + /* Attempt board-specific reset */ + board_reset(); -#endif /* !CONFIG_MPC8641HPCN */ + /* Next try asserting HRESET_REQ */ + out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ); - while (1) ; /* not reached */ + while (1) + ; } diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index a7e6036db..4f29122f4 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -154,3 +154,30 @@ void setup_bats(void) return; } + +#ifdef CONFIG_ADDR_MAP +/* Initialize address mapping array */ +void init_addr_map(void) +{ + int i; + ppc_bat_t bat = DBAT0; + phys_size_t size; + unsigned long upper, lower; + + for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) { + if (read_bat(bat, &upper, &lower) != -1) { + if (!BATU_VALID(upper)) + size = 0; + else + size = BATU_SIZE(upper); + addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower), + size, i); + } +#ifdef CONFIG_HIGH_BATS + /* High bats are not contiguous with low BAT numbers */ + if (bat == DBAT3) + bat = DBAT4 - 1; +#endif + } +} +#endif diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c index bd90dcd3b..664db65a5 100644 --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@ -65,6 +65,23 @@ DECLARE_GLOBAL_DATA_PTR; #endif /* CONFIG_8xx_CONS_SCCx */ +#if !defined(CONFIG_SYS_SMC_RXBUFLEN) +#define CONFIG_SYS_SMC_RXBUFLEN 1 +#define CONFIG_SYS_MAXIDLE 0 +#else +#if !defined(CONFIG_SYS_MAXIDLE) +#error "you must define CONFIG_SYS_MAXIDLE" +#endif +#endif + +typedef volatile struct serialbuffer { + cbd_t rxbd; /* Rx BD */ + cbd_t txbd; /* Tx BD */ + uint rxindex; /* index for next character to read */ + volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */ + volatile uchar txbuf; /* tx buffers */ +} serialbuffer_t; + static void serial_setdivisor(volatile cpm8xx_t *cp) { int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate; @@ -113,12 +130,12 @@ static int smc_init (void) volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile smc_t *sp; volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; volatile cpm8xx_t *cp = &(im->im_cpm); #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850)) volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport); #endif uint dpaddr; + volatile serialbuffer_t *rtx; /* initialize pointers to SMC */ @@ -131,12 +148,10 @@ static int smc_init (void) up->smc_rpbase = 0; #endif - /* Disable transmitter/receiver. - */ + /* Disable transmitter/receiver. */ sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - /* Enable SDMA. - */ + /* Enable SDMA. */ im->im_siu_conf.sc_sdcr = 1; /* clear error conditions */ @@ -154,21 +169,19 @@ static int smc_init (void) #endif #if defined(CONFIG_8xx_CONS_SMC1) - /* Use Port B for SMC1 instead of other functions. - */ + /* Use Port B for SMC1 instead of other functions. */ cp->cp_pbpar |= 0x000000c0; cp->cp_pbdir &= ~0x000000c0; cp->cp_pbodr &= ~0x000000c0; #else /* CONFIG_8xx_CONS_SMC2 */ # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850) - /* Use Port A for SMC2 instead of other functions. - */ + /* Use Port A for SMC2 instead of other functions. */ ip->iop_papar |= 0x00c0; ip->iop_padir &= ~0x00c0; ip->iop_paodr &= ~0x00c0; # else /* must be a 860 then */ /* Use Port B for SMC2 instead of other functions. - */ + */ cp->cp_pbpar |= 0x00000c00; cp->cp_pbdir &= ~0x00000c00; cp->cp_pbodr &= ~0x00000c00; @@ -194,26 +207,28 @@ static int smc_init (void) */ #ifdef CONFIG_SYS_ALLOC_DPRAM - dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; + /* allocate + * size of struct serialbuffer with bd rx/tx, buffer rx/tx and rx index + */ + dpaddr = dpram_alloc_align((sizeof(serialbuffer_t)), 8); #else dpaddr = CPM_SERIAL_BASE ; #endif + rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr]; /* Allocate space for two buffer descriptors in the DP ram. * For now, this address seems OK, but it may have to * change with newer versions of the firmware. * damm: allocating space after the two buffers for rx/tx data */ - rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf+2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; - tbdf->cbd_sc = 0; + rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf; + rtx->rxbd.cbd_sc = 0; - /* Set up the uart parameters in the parameter ram. - */ + rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf; + rtx->txbd.cbd_sc = 0; + + /* Set up the uart parameters in the parameter ram. */ up->smc_rbase = dpaddr; up->smc_tbase = dpaddr+sizeof(cbd_t); up->smc_rfcr = SMC_EB; @@ -254,19 +269,16 @@ static int smc_init (void) smc_setbrg (); #endif - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; + /* Make the first buffer the only buffer. */ + rtx->txbd.cbd_sc |= BD_SC_WRAP; + rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - /* Single character receive. - */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; - - /* Initialize Tx/Rx parameters. - */ + /* single/multi character receive. */ + up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN; + up->smc_maxidl = CONFIG_SYS_MAXIDLE; + rtx->rxindex = 0; + /* Initialize Tx/Rx parameters. */ while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ ; @@ -275,8 +287,7 @@ static int smc_init (void) while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ ; - /* Enable transmitter/receiver. - */ + /* Enable transmitter/receiver. */ sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; return (0); @@ -285,11 +296,10 @@ static int smc_init (void) static void smc_putc(const char c) { - volatile cbd_t *tbdf; - volatile char *buf; volatile smc_uart_t *up; volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cpmp = &(im->im_cpm); + volatile serialbuffer_t *rtx; #ifdef CONFIG_MODEM_SUPPORT if (gd->be_quiet) @@ -304,19 +314,15 @@ smc_putc(const char c) up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; #endif - tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase]; - - /* Wait for last character to go. - */ - - buf = (char *)tbdf->cbd_bufaddr; + rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; + /* Wait for last character to go. */ + rtx->txbuf = c; + rtx->txbd.cbd_datlen = 1; + rtx->txbd.cbd_sc |= BD_SC_READY; __asm__("eieio"); - while (tbdf->cbd_sc & BD_SC_READY) { + while (rtx->txbd.cbd_sc & BD_SC_READY) { WATCHDOG_RESET (); __asm__("eieio"); } @@ -333,49 +339,52 @@ smc_puts (const char *s) static int smc_getc(void) { - volatile cbd_t *rbdf; - volatile unsigned char *buf; volatile smc_uart_t *up; volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cpmp = &(im->im_cpm); - unsigned char c; + volatile serialbuffer_t *rtx; + unsigned char c; up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; #ifdef CONFIG_SYS_SMC_UCODE_PATCH up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; #endif + rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; - - /* Wait for character to show up. - */ - buf = (unsigned char *)rbdf->cbd_bufaddr; - - while (rbdf->cbd_sc & BD_SC_EMPTY) + /* Wait for character to show up. */ + while (rtx->rxbd.cbd_sc & BD_SC_EMPTY) WATCHDOG_RESET (); - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; + /* the characters are read one by one, + * use the rxindex to know the next char to deliver + */ + c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex); + rtx->rxindex++; + /* check if all char are readout, then make prepare for next receive */ + if (rtx->rxindex >= rtx->rxbd.cbd_datlen) { + rtx->rxindex = 0; + rtx->rxbd.cbd_sc |= BD_SC_EMPTY; + } return(c); } static int smc_tstc(void) { - volatile cbd_t *rbdf; volatile smc_uart_t *up; volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cpmp = &(im->im_cpm); + volatile serialbuffer_t *rtx; up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; #ifdef CONFIG_SYS_SMC_UCODE_PATCH up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase]; #endif - rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase]; + rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase]; - return(!(rbdf->cbd_sc & BD_SC_EMPTY)); + return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY); } struct serial_device serial_smc_device = @@ -445,8 +454,7 @@ static int scc_init (void) } #endif /* CONFIG_LWMON */ - /* Disable transmitter/receiver. - */ + /* Disable transmitter/receiver. */ sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); #if (SCC_INDEX == 2) && defined(CONFIG_MPC850) @@ -471,8 +479,7 @@ static int scc_init (void) ip->iop_pdpar |= ((3 << (2 * SCC_INDEX))); #endif - /* Allocate space for two buffer descriptors in the DP ram. - */ + /* Allocate space for two buffer descriptors in the DP ram. */ #ifdef CONFIG_SYS_ALLOC_DPRAM dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; @@ -480,8 +487,7 @@ static int scc_init (void) dpaddr = CPM_SERIAL2_BASE ; #endif - /* Enable SDMA. - */ + /* Enable SDMA. */ im->im_siu_conf.sc_sdcr = 0x0001; /* Set the physical address of the host memory buffers in @@ -495,17 +501,14 @@ static int scc_init (void) tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1; tbdf->cbd_sc = 0; - /* Set up the baud rate generator. - */ + /* Set up the baud rate generator. */ scc_setbrg (); - /* Set up the uart parameters in the parameter ram. - */ + /* Set up the uart parameters in the parameter ram. */ up->scc_genscc.scc_rbase = dpaddr; up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t); - /* Initialize Tx/Rx parameters. - */ + /* Initialize Tx/Rx parameters. */ while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ ; cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG; @@ -536,8 +539,7 @@ static int scc_init (void) up->scc_char8 = 0x8000; up->scc_rccm = 0xc0ff; - /* Set low latency / small fifo. - */ + /* Set low latency / small fifo. */ sp->scc_gsmrh = SCC_GSMRH_RFW; /* Set SCC(x) clock mode to 16x @@ -546,8 +548,7 @@ static int scc_init (void) * Wire BRG1 to SCCn */ - /* Set UART mode, clock divider 16 on Tx and Rx - */ + /* Set UART mode, clock divider 16 on Tx and Rx */ sp->scc_gsmrl &= ~0xF; sp->scc_gsmrl |= (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); @@ -555,20 +556,17 @@ static int scc_init (void) sp->scc_psmr = 0; sp->scc_psmr |= SCU_PSMR_CL; - /* Mask all interrupts and remove anything pending. - */ + /* Mask all interrupts and remove anything pending. */ sp->scc_sccm = 0; sp->scc_scce = 0xffff; sp->scc_dsr = 0x7e7e; sp->scc_psmr = 0x3000; - /* Make the first buffer the only buffer. - */ + /* Make the first buffer the only buffer. */ tbdf->cbd_sc |= BD_SC_WRAP; rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - /* Enable transmitter/receiver. - */ + /* Enable transmitter/receiver. */ sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); return (0); @@ -595,8 +593,7 @@ scc_putc(const char c) tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase]; - /* Wait for last character to go. - */ + /* Wait for last character to go. */ buf = (char *)tbdf->cbd_bufaddr; @@ -633,8 +630,7 @@ scc_getc(void) rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; - /* Wait for character to show up. - */ + /* Wait for character to show up. */ buf = (unsigned char *)rbdf->cbd_bufaddr; while (rbdf->cbd_sc & BD_SC_EMPTY) diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c index f1ad13286..305f7fbd4 100644 --- a/cpu/mpc8xxx/ddr/main.c +++ b/cpu/mpc8xxx/ddr/main.c @@ -429,7 +429,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step) if (max_end >= 0xff) { printf("This U-Boot only supports < 4G of DDR\n"); printf("You could rebuild it with CONFIG_PHYS_64BIT\n"); - return 0; /* Ensure DDR setup failure. */ + return CONFIG_MAX_MEM_MAPPED; } #endif diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c index d4702d73b..29d414343 100644 --- a/cpu/mpc8xxx/ddr/options.c +++ b/cpu/mpc8xxx/ddr/options.c @@ -22,7 +22,9 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, unsigned int ctrl_num) { unsigned int i; +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) const char *p; +#endif /* Chip select options. */ @@ -195,6 +197,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * requested ranks interleaved together such that the result * should be a subset of the requested configuration. */ +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) if ((p = getenv("memctl_intlv_ctl")) != NULL) { if (pdimm[0].n_ranks == 0) { printf("There is no rank on CS0. Because only rank on " @@ -262,6 +265,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, break; } } +#endif fsl_ddr_board_options(popts, pdimm, ctrl_num); diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index b40e4b151..33788cc90 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -160,9 +160,6 @@ * SDRAM. This is because we only map the first 2GB on such systems, and therefore * the ECC parity byte of the remaining area can't be written. */ -#ifndef CONFIG_MAX_MEM_MAPPED -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) -#endif /* * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed @@ -1104,11 +1101,8 @@ static void program_codt(unsigned long *dimm_populated, * Set the SDRAM Controller On Die Termination Register *-----------------------------------------------------------------*/ mfsdram(SDRAM_CODT, codt); - codt |= (SDRAM_CODT_IO_NMODE - & (~SDRAM_CODT_DQS_SINGLE_END - & ~SDRAM_CODT_CKSE_SINGLE_END - & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END - & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END)); + codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END); + codt |= SDRAM_CODT_IO_NMODE; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { if (dimm_populated[dimm_num] != SDRAM_NONE) { diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 1e3e20df2..91bf582d6 100644 --- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -61,6 +61,8 @@ #define NUMLOOPS 1 /* configure as you deem approporiate */ #define NUMMEMWORDS 16 +#define SDRAM_RDCC_RDSS_VAL(n) SDRAM_RDCC_RDSS_DECODE(ddr_rdss_opt(n)) + /* Private Structure Definitions */ struct autocal_regs { @@ -147,6 +149,13 @@ ulong __ddr_scan_option(ulong default_val) } ulong ddr_scan_option(ulong) __attribute__((weak, alias("__ddr_scan_option"))); +u32 __ddr_rdss_opt(u32 default_val) +{ + return default_val; +} +u32 ddr_rdss_opt(ulong) __attribute__((weak, alias("__ddr_rdss_opt"))); + + static u32 *get_membase(int bxcr_num) { ulong bxcf; @@ -341,6 +350,7 @@ static int short_mem_test(u32 *base_address) ppcDcbf((ulong)&(base_address[j])); } sync(); + iobarrier_rw(); for (l = 0; l < NUMLOOPS; l++) { for (j = 0; j < NUMMEMWORDS; j++) { if (base_address[j] != test[i][j]) { @@ -355,6 +365,7 @@ static int short_mem_test(u32 *base_address) ppcDcbf((u32)&(base_address[j])); } /* for (j = 0; j < NUMMEMWORDS; j++) */ sync(); + iobarrier_rw(); } /* for (l=0; l<NUMLOOPS; l++) */ } @@ -447,7 +458,8 @@ static u32 DQS_calibration_methodA(struct ddrautocal *cal) * Program RDCC register * Read sample cycle auto-update enable */ - mtsdram(SDRAM_RDCC, SDRAM_RDCC_RDSS_T1 | SDRAM_RDCC_RSAE_ENABLE); + mtsdram(SDRAM_RDCC, + ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE); #ifdef DEBUG mfsdram(SDRAM_RDCC, temp); @@ -633,7 +645,8 @@ static u32 program_DQS_calibration_methodB(struct ddrautocal *ddrcal) * Program RDCC register * Read sample cycle auto-update enable */ - mtsdram(SDRAM_RDCC, SDRAM_RDCC_RDSS_T2 | SDRAM_RDCC_RSAE_ENABLE); + mtsdram(SDRAM_RDCC, + ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE); #ifdef DEBUG mfsdram(SDRAM_RDCC, temp); @@ -1091,32 +1104,36 @@ u32 DQS_autocalibration(void) * if no passing window was found, or is the * size of the RFFD passing window. */ - if (result != 0) { - tcal.autocal.flags = 1; - debug("*** (%d)(%d) result passed window size: 0x%08x, " - "rqfd = 0x%08x, rffd = 0x%08x, rdcc = 0x%08x\n", - wdtr, clkp, result, ddrcal.rqfd, - ddrcal.rffd, ddrcal.rdcc); - /* - * Save the SDRAM_WRDTR and SDRAM_CLKTR - * settings for the largest returned - * RFFD passing window size. - */ - if (result > best_result) { + /* + * want the lowest Read Sample Cycle Select + */ + val = SDRAM_RDCC_RDSS_DECODE(val); + debug("*** (%d) (%d) current_rdcc, best_rdcc\n", + val, best_rdcc); + + if ((result != 0) && + (val >= SDRAM_RDCC_RDSS_VAL(SDRAM_RDCC_RDSS_T2))) { + if (((result == best_result) && (val < best_rdcc)) || + ((result > best_result) && (val <= best_rdcc))) { + tcal.autocal.flags = 1; + debug("*** (%d)(%d) result passed window " + "size: 0x%08x, rqfd = 0x%08x, " + "rffd = 0x%08x, rdcc = 0x%08x\n", + wdtr, clkp, result, ddrcal.rqfd, + ddrcal.rffd, ddrcal.rdcc); + /* - * want the lowest Read Sample Cycle Select + * Save the SDRAM_WRDTR and SDRAM_CLKTR + * settings for the largest returned + * RFFD passing window size. */ - val = (val & SDRAM_RDCC_RDSS_MASK) >> 30; - debug("*** (%d) (%d) current_rdcc, best_rdcc\n", - val, best_rdcc); - if (val <= best_rdcc) { - best_rdcc = val; - tcal.clocks.wrdtr = wdtr; - tcal.clocks.clktr = clkp; - tcal.clocks.rdcc = (val << 30); - tcal.autocal.rqfd = ddrcal.rqfd; - tcal.autocal.rffd = ddrcal.rffd; - best_result = result; + best_rdcc = val; + tcal.clocks.wrdtr = wdtr; + tcal.clocks.clktr = clkp; + tcal.clocks.rdcc = SDRAM_RDCC_RDSS_ENCODE(val); + tcal.autocal.rqfd = ddrcal.rqfd; + tcal.autocal.rffd = ddrcal.rffd; + best_result = result; if (verbose_lvl > 2) { printf("** (%d)(%d) " @@ -1152,9 +1169,8 @@ u32 DQS_autocalibration(void) "loop FCSR: 0x%08x\n", wdtr, clkp, val); } - } /* if (val <= best_rdcc) */ - } /* if (result >= best_result) */ - } /* if (result != 0) */ + } + } /* if ((result != 0) && (val >= (ddr_rdss_opt()))) */ scan_list++; } /* while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) */ diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index e8871fc45..6fd36dea3 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -179,7 +179,7 @@ void pci_405gp_init(struct pci_controller *hose) ptmpcila[i], ptmla[i], ~(ptmms[i] & 0xfffff000) + 1, PCI_REGION_MEM | - PCI_REGION_MEMORY); + PCI_REGION_SYS_MEMORY); } /* PCI memory spaces */ @@ -504,7 +504,7 @@ int pci_440_init (struct pci_controller *hose) CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, CONFIG_PCI_SYS_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY ); + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY ); #endif hose->region_count = reg_num; @@ -588,8 +588,9 @@ void pci_init_board(void) int busno; busno = pci_440_init (&ppc440_hose); -#if defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if (defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \ + !defined(CONFIG_PCI_DISABLE_PCIE) pcie_setup_hoses(busno + 1); #endif } diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index fd40d8abd..58d96bb5a 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -33,7 +33,7 @@ #if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \ - defined(CONFIG_PCI) + defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_PCIE) #include <asm/4xx_pcie.h> diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index c55e1cfbb..ba5c120ad 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -113,6 +113,7 @@ void fdt_pcie_setup(void *blob) void ft_cpu_setup(void *blob, bd_t *bd) { sys_info_t sys_info; + int off, ndepth = 0; get_sys_info(&sys_info); @@ -133,9 +134,28 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); /* - * Setup all baudrates for the UARTs + * Fixup all UART clocks for CPU internal UARTs + * (only these UARTs are definitely clocked by gd->uart_clk) + * + * These UARTs are direct childs of /plb/opb. This code + * does not touch any UARTs that are connected to the ebc. */ - do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", gd->uart_clk, 1); + off = fdt_path_offset(blob, "/plb/opb"); + while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) { + /* + * process all sub nodes and stop when we are back + * at the starting depth + */ + if (ndepth <= 0) + break; + + /* only update direct childs */ + if ((ndepth == 1) && + (fdt_node_check_compatible(blob, off, "ns16550") == 0)) + fdt_setprop(blob, off, + "clock-frequency", + (void*)&(gd->uart_clk), 4); + } /* * Fixup all ethernet nodes diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c index d735c8d48..8f5277e10 100644 --- a/cpu/pxa/mmc.c +++ b/cpu/pxa/mmc.c @@ -28,6 +28,8 @@ #include <asm/arch/hardware.h> #include <part.h> +#include "mmc.h" + #ifdef CONFIG_MMC extern int fat_register_device(block_dev_desc_t * dev_desc, int part_no); @@ -543,7 +545,7 @@ static void mmc_decode_csd(uint32_t * resp) int /****************************************************/ -mmc_init(int verbose) +mmc_legacy_init(int verbose) /****************************************************/ { int retries, rc = -ENODEV; @@ -645,18 +647,4 @@ mmc_init(int verbose) return rc; } -int mmc_ident(block_dev_desc_t * dev) -{ - return 0; -} - -int mmc2info(ulong addr) -{ - if (addr >= CONFIG_SYS_MMC_BASE - && addr < CONFIG_SYS_MMC_BASE + (mmc_dev.lba * mmc_dev.blksz)) { - return 1; - } - return 0; -} - #endif /* CONFIG_MMC */ diff --git a/cpu/pxa/mmc.h b/cpu/pxa/mmc.h new file mode 100644 index 000000000..85e144b68 --- /dev/null +++ b/cpu/pxa/mmc.h @@ -0,0 +1,189 @@ +/* + * linux/drivers/mmc/mmc_pxa.h + * + * Author: Vladimir Shebordaev, Igor Oblakov + * Copyright: MontaVista Software Inc. + * + * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __MMC_PXA_P_H__ +#define __MMC_PXA_P_H__ + +/* PXA-250 MMC controller registers */ + +/* MMC_STRPCL */ +#define MMC_STRPCL_STOP_CLK (0x0001UL) +#define MMC_STRPCL_START_CLK (0x0002UL) + +/* MMC_STAT */ +#define MMC_STAT_END_CMD_RES (0x0001UL << 13) +#define MMC_STAT_PRG_DONE (0x0001UL << 12) +#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11) +#define MMC_STAT_CLK_EN (0x0001UL << 8) +#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7) +#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6) +#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5) +#define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4) +#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3) +#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2) +#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1) +#define MMC_STAT_READ_TIME_OUT (0x0001UL) + +#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\ + |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\ + |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR) + +/* MMC_CLKRT */ +#define MMC_CLKRT_20MHZ (0x0000UL) +#define MMC_CLKRT_10MHZ (0x0001UL) +#define MMC_CLKRT_5MHZ (0x0002UL) +#define MMC_CLKRT_2_5MHZ (0x0003UL) +#define MMC_CLKRT_1_25MHZ (0x0004UL) +#define MMC_CLKRT_0_625MHZ (0x0005UL) +#define MMC_CLKRT_0_3125MHZ (0x0006UL) + +/* MMC_SPI */ +#define MMC_SPI_DISABLE (0x00UL) +#define MMC_SPI_EN (0x01UL) +#define MMC_SPI_CS_EN (0x01UL << 2) +#define MMC_SPI_CS_ADDRESS (0x01UL << 3) +#define MMC_SPI_CRC_ON (0x01UL << 1) + +/* MMC_CMDAT */ +#define MMC_CMDAT_SD_4DAT (0x0001UL << 8) +#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7) +#define MMC_CMDAT_INIT (0x0001UL << 6) +#define MMC_CMDAT_BUSY (0x0001UL << 5) +#define MMC_CMDAT_BCR (0x0003UL << 5) +#define MMC_CMDAT_STREAM (0x0001UL << 4) +#define MMC_CMDAT_BLOCK (0x0000UL << 4) +#define MMC_CMDAT_WRITE (0x0001UL << 3) +#define MMC_CMDAT_READ (0x0000UL << 3) +#define MMC_CMDAT_DATA_EN (0x0001UL << 2) +#define MMC_CMDAT_R0 (0) +#define MMC_CMDAT_R1 (0x0001UL) +#define MMC_CMDAT_R2 (0x0002UL) +#define MMC_CMDAT_R3 (0x0003UL) + +/* MMC_RESTO */ +#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */ + +/* MMC_RDTO */ +#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */ + +/* MMC_BLKLEN */ +#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ + +/* MMC_PRTBUF */ +#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) +#define MMC_PRTBUF_BUF_FULL (0x00UL ) + +/* MMC_I_MASK */ +#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6) +#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5) +#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4) +#define MMC_I_MASK_STOP_CMD (0x01UL << 3) +#define MMC_I_MASK_END_CMD_RES (0x01UL << 2) +#define MMC_I_MASK_PRG_DONE (0x01UL << 1) +#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL) +#define MMC_I_MASK_ALL (0x07fUL) + + +/* MMC_I_REG */ +#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6) +#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5) +#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4) +#define MMC_I_REG_STOP_CMD (0x01UL << 3) +#define MMC_I_REG_END_CMD_RES (0x01UL << 2) +#define MMC_I_REG_PRG_DONE (0x01UL << 1) +#define MMC_I_REG_DATA_TRAN_DONE (0x01UL) +#define MMC_I_REG_ALL (0x007fUL) + +/* MMC_CMD */ +#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */ +#define CMD(x) (x) + +#define MMC_DEFAULT_RCA 1 + +#define MMC_BLOCK_SIZE 512 +#define MMC_MAX_BLOCK_SIZE 512 + +#define MMC_R1_IDLE_STATE 0x01 +#define MMC_R1_ERASE_STATE 0x02 +#define MMC_R1_ILLEGAL_CMD 0x04 +#define MMC_R1_COM_CRC_ERR 0x08 +#define MMC_R1_ERASE_SEQ_ERR 0x01 +#define MMC_R1_ADDR_ERR 0x02 +#define MMC_R1_PARAM_ERR 0x04 + +#define MMC_R1B_WP_ERASE_SKIP 0x0002 +#define MMC_R1B_ERR 0x0004 +#define MMC_R1B_CC_ERR 0x0008 +#define MMC_R1B_CARD_ECC_ERR 0x0010 +#define MMC_R1B_WP_VIOLATION 0x0020 +#define MMC_R1B_ERASE_PARAM 0x0040 +#define MMC_R1B_OOR 0x0080 +#define MMC_R1B_IDLE_STATE 0x0100 +#define MMC_R1B_ERASE_RESET 0x0200 +#define MMC_R1B_ILLEGAL_CMD 0x0400 +#define MMC_R1B_COM_CRC_ERR 0x0800 +#define MMC_R1B_ERASE_SEQ_ERR 0x1000 +#define MMC_R1B_ADDR_ERR 0x2000 +#define MMC_R1B_PARAM_ERR 0x4000 + +typedef struct mmc_cid +{ +/* FIXME: BYTE_ORDER */ + uchar year:4, + month:4; + uchar sn[3]; + uchar fwrev:4, + hwrev:4; + uchar name[6]; + uchar id[3]; +} mmc_cid_t; + +typedef struct mmc_csd +{ + uint8_t csd_structure:2, + spec_ver:4, + rsvd1:2; + uint8_t taac; + uint8_t nsac; + uint8_t tran_speed; + uint16_t ccc:12, + read_bl_len:4; + uint64_t read_bl_partial:1, + write_blk_misalign:1, + read_blk_misalign:1, + dsr_imp:1, + rsvd2:2, + c_size:12, + vdd_r_curr_min:3, + vdd_r_curr_max:3, + vdd_w_curr_min:3, + vdd_w_curr_max:3, + c_size_mult:3, + erase_blk_en:1, + sector_size:7, + wp_grp_size:7, + wp_grp_enable:1, + default_ecc:2, + r2w_factor:3, + write_bl_len:4, + write_bl_partial:1, + rsvd3:4, + content_prot_app:1; + uint8_t file_format_grp:1, + copy:1, + perm_write_protect:1, + tmp_write_protect:1, + file_format:2, + ecc:2; +} mmc_csd_t; + +#endif /* __MMC_PXA_P_H__ */ |