diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/blackfin/initcode.c | 17 | ||||
| -rw-r--r-- | cpu/blackfin/serial.c | 21 | ||||
| -rw-r--r-- | cpu/blackfin/serial.h | 2 | 
3 files changed, 37 insertions, 3 deletions
diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c index 3120447c5..aba00e0fb 100644 --- a/cpu/blackfin/initcode.c +++ b/cpu/blackfin/initcode.c @@ -246,6 +246,15 @@ static inline void serial_putc(char c)  #endif  #endif +/* Conflicting Column Address Widths Causes SDRAM Errors: + * EB2CAW and EB3CAW must be the same + */ +#if ANOMALY_05000362 +# if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000) +#  error "Anomaly 05000362: EB2CAW and EB3CAW must be the same" +# endif +#endif +  BOOTROM_CALLED_FUNC_ATTR  void initcode(ADI_BOOT_DATA *bootstruct)  { @@ -335,6 +344,7 @@ void initcode(ADI_BOOT_DATA *bootstruct)  	if (!ANOMALY_05000386) {  		serial_putc('F'); +		/* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */  		ADI_SYSCTRL_VALUES memory_settings;  		uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT;  		if (CONFIG_HAS_VR) { @@ -356,6 +366,10 @@ void initcode(ADI_BOOT_DATA *bootstruct)  #if ANOMALY_05000432  		bfin_write_SIC_IWR1(-1);  #endif +#if ANOMALY_05000171 +		bfin_write_SICA_IWR0(-1); +		bfin_write_SICA_IWR1(-1); +#endif  	} else {  		serial_putc('G'); @@ -375,6 +389,7 @@ void initcode(ADI_BOOT_DATA *bootstruct)  		serial_putc('H'); +		/* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */  		bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);  		serial_putc('I'); @@ -397,7 +412,7 @@ void initcode(ADI_BOOT_DATA *bootstruct)  		/* Only reprogram when needed to avoid triggering unnecessary  		 * PLL relock sequences.  		 */ -		if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) { +		if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {  			serial_putc('!');  			bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);  			asm("idle;"); diff --git a/cpu/blackfin/serial.c b/cpu/blackfin/serial.c index 386195556..2abda186e 100644 --- a/cpu/blackfin/serial.c +++ b/cpu/blackfin/serial.c @@ -24,6 +24,19 @@   * Licensed under the GPL-2 or later.   */ +/* Anomaly notes: + *  05000086 - we don't support autobaud + *  05000099 - we only use DR bit, so losing others is not a problem + *  05000100 - we don't use the UART_IIR register + *  05000215 - we poll the uart (no dma/interrupts) + *  05000225 - no workaround possible, but this shouldnt cause errors ... + *  05000230 - we tweak the baud rate calculation slightly + *  05000231 - we always use 1 stop bit + *  05000309 - we always enable the uart before we modify it in anyway + *  05000350 - we always enable the uart regardless of boot mode + *  05000363 - we don't support break signals, so don't generate one + */ +  #include <common.h>  #include <watchdog.h>  #include <asm/blackfin.h> @@ -43,7 +56,9 @@ uint16_t cached_rbr[256];  size_t cache_count;  /* The LSR is read-to-clear on some parts, so we have to make sure status - * bits aren't inadvertently lost when doing various tests. + * bits aren't inadvertently lost when doing various tests.  This also + * works around anomaly 05000099 at the same time by keeping a cumulative + * tally of all the status bits.   */  static uint16_t uart_lsr_save;  static uint16_t uart_lsr_read(void) @@ -59,6 +74,10 @@ static void uart_lsr_clear(void)  	*pUART_LSR |= -1;  }  #else +/* When debugging is disabled, we only care about the DR bit, so if other + * bits get set/cleared, we don't really care since we don't read them + * anyways (and thus anomaly 05000099 is irrelevant). + */  static inline uint16_t uart_lsr_read(void) { return *pUART_LSR; }  static inline void uart_lsr_clear(void) { *pUART_LSR = -1; }  #endif diff --git a/cpu/blackfin/serial.h b/cpu/blackfin/serial.h index ce39148f8..7b47878df 100644 --- a/cpu/blackfin/serial.h +++ b/cpu/blackfin/serial.h @@ -146,7 +146,7 @@ static inline void serial_early_init(void)  	/* handle portmux crap on different Blackfins */  	serial_do_portmux(); -	/* Enable UART */ +	/* always enable UART -- avoids anomalies 05000309 and 05000350 */  	*pUART_GCTL = UCEN;  	/* Set LCR to Word Lengh 8-bit word select */  |