diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/pxa/i2c.c | 19 | ||||
| -rw-r--r-- | cpu/pxa/start.S | 17 |
2 files changed, 29 insertions, 7 deletions
diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c index b6155b137..722d94947 100644 --- a/cpu/pxa/i2c.c +++ b/cpu/pxa/i2c.c @@ -47,7 +47,13 @@ /*#define DEBUG_I2C 1 /###* activate local debugging output */ #define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ -#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) + +#if (CFG_I2C_SPEED == 400000) +#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) +#else +#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) +#endif + #define I2C_ISR_INIT 0x7FF #ifdef DEBUG_I2C @@ -91,7 +97,11 @@ static void i2c_reset( void ) ICR |= ICR_UR; /* reset the unit */ udelay(100); ICR &= ~ICR_IUE; /* disable unit */ +#ifdef CONFIG_CPU_MONAHANS + CKENB |= (CKENB_4_I2C); /* | CKENB_1_PWM1 | CKENB_0_PWM0); */ +#else /* CONFIG_CPU_MONAHANS */ CKEN |= CKEN14_I2C; /* set the global I2C clock on */ +#endif ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */ ICR = I2C_ICR_INIT; /* set control register values */ ISR = I2C_ISR_INIT; /* set clear interrupt bits */ @@ -104,9 +114,8 @@ static void i2c_reset( void ) * i2c_isr_set_cleared: - wait until certain bits of the I2C status register * are set and cleared * - * @return: 0 in case of success, 1 means timeout (no match within 10 ms). + * @return: 1 in case of success, 0 means timeout (no match within 10 ms). */ - static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask ) { int timeout = 10000; @@ -360,9 +369,9 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) msg.data = 0x00; if ((ret=i2c_transfer(&msg))) return -1; - *(buffer++) = msg.data; - + *buffer = msg.data; PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); + buffer++; } diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index 9541c9b2b..ffaa30fdc 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -190,6 +190,14 @@ OSTIMER_BASE: .word 0x40a00000 #define OIER 0x1C /* Clock Manager Registers */ +#ifdef CONFIG_CPU_MONAHANS +# ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO +# error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!" +# endif +# ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO +# define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1 +# endif +#else /* ! CONFIG_CPU_MONAHANS */ #ifdef CFG_CPUSPEED CC_BASE: .word 0x41300000 #define CCCR 0x00 @@ -197,6 +205,7 @@ cpuspeed: .word CFG_CPUSPEED #else #error "You have to define CFG_CPUSPEED!!" #endif +#endif /* CONFIG_CPU_MONAHANS */ /* takes care the CP15 update has taken place */ .macro CPWAIT reg @@ -233,9 +242,13 @@ cpu_init_crit: str r2, [r1] #endif -#ifndef CONFIG_CPU_MONAHANS + /* set clock speed */ +#ifdef CONFIG_CPU_MONAHANS + ldr r0, =ACCR + ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK)) + str r1, [r0] +#else /* ! CONFIG_CPU_MONAHANS */ #ifdef CFG_CPUSPEED - /* set clock speed tbd@mk: required for monahans? */ ldr r0, CC_BASE ldr r1, cpuspeed str r1, [r0, #CCCR] |