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-rw-r--r--cpu/ppc4xx/4xx_pci.c2
-rw-r--r--cpu/ppc4xx/4xx_pcie.c4
-rw-r--r--cpu/ppc4xx/cpu.c20
-rw-r--r--cpu/ppc4xx/fdt.c26
-rw-r--r--cpu/ppc4xx/i2c.c2
-rw-r--r--cpu/ppc4xx/kgdb.S2
-rw-r--r--cpu/ppc4xx/speed.c4
-rw-r--r--cpu/ppc4xx/start.S58
-rw-r--r--cpu/ppc4xx/usb_ohci.c2
9 files changed, 80 insertions, 40 deletions
diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c
index 941d4dc78..c28c7ac86 100644
--- a/cpu/ppc4xx/4xx_pci.c
+++ b/cpu/ppc4xx/4xx_pci.c
@@ -46,7 +46,7 @@
* 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
* 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
* really required after a reset since PMMxMAs are already
- * disabled but is a good practice nonetheless. JWB
+ * disabled but is a good practice nonetheless. JWB
* 12-Jun-01 stefan.roese@esd-electronics.com
* - PCI host/adapter handling reworked
* 09-Jul-01 stefan.roese@esd-electronics.com
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index f9a1988d4..503facca3 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -444,8 +444,8 @@ static void ppc4xx_setup_utl(u32 port)
/*
* TODO: double check PCI express SDR based on the latest user manual
- * Some registers specified here no longer exist.. has to be
- * updated based on the final EAS spec.
+ * Some registers specified here no longer exist.. has to be
+ * updated based on the final EAS spec.
*/
static int check_error(void)
{
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 54cc25679..39f439df9 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -346,6 +346,26 @@ int checkcpu (void)
strcpy(addstr, "No Security support");
break;
+ case PVR_405EX1_RC:
+ puts("EX Rev. C");
+ strcpy(addstr, "Security support");
+ break;
+
+ case PVR_405EX2_RC:
+ puts("EX Rev. C");
+ strcpy(addstr, "No Security support");
+ break;
+
+ case PVR_405EXR1_RC:
+ puts("EXr Rev. C");
+ strcpy(addstr, "Security support");
+ break;
+
+ case PVR_405EXR2_RC:
+ puts("EXr Rev. C");
+ strcpy(addstr, "No Security support");
+ break;
+
#if defined(CONFIG_440)
case PVR_440GP_RB:
puts("GP Rev. B");
diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c
index 02dece0c0..ccc73d5d6 100644
--- a/cpu/ppc4xx/fdt.c
+++ b/cpu/ppc4xx/fdt.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -27,7 +27,7 @@
#include <asm/cache.h>
#include <ppc4xx.h>
-#if defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
#include <libfdt.h>
#include <libfdt_env.h>
#include <fdt_support.h>
@@ -35,6 +35,26 @@
DECLARE_GLOBAL_DATA_PTR;
+void __ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 val[4];
+ int rc;
+
+ ft_cpu_setup(blob, bd);
+
+ /* Fixup NOR mapping */
+ val[0] = 0; /* chip select number */
+ val[1] = 0; /* always 0 */
+ val[2] = gd->bd->bi_flashstart;
+ val[3] = gd->bd->bi_flashsize;
+ rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
+ val, sizeof(val), 1);
+ if (rc)
+ printf("Unable to update property NOR mapping, err=%s\n",
+ fdt_strerror(rc));
+}
+void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup")));
+
/*
* Fixup all PCIe nodes by setting the device_type property
* to "pci-endpoint" instead is "pci" for endpoint ports.
@@ -109,4 +129,4 @@ void ft_cpu_setup(void *blob, bd_t *bd)
*/
fdt_pcie_setup(blob);
}
-#endif /* CONFIG_OF_LIBFDT */
+#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c
index 47c264e22..d8be2cef1 100644
--- a/cpu/ppc4xx/i2c.c
+++ b/cpu/ppc4xx/i2c.c
@@ -61,7 +61,7 @@ static void _i2c_bus_reset(void)
/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
out_8((u8 *)IIC_EXTSTS, 0x8F);
- /* Place chip in the reset state */
+ /* Place chip in the reset state */
out_8((u8 *)IIC_XTCNTLSS, IIC_XTCNTLSS_SRST);
/* Check if bus is free */
diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S
index 42b9546d3..4227a4c15 100644
--- a/cpu/ppc4xx/kgdb.S
+++ b/cpu/ppc4xx/kgdb.S
@@ -45,7 +45,7 @@ kgdb_flush_cache_all:
iccci r0,r0 /* iccci invalidates the entire I cache */
/* dcache */
addi r6,0,0x0000 /* clear GPR 6 */
- addi r7,r0, 128 /* do loop for # of dcache lines */
+ addi r7,r0, 128 /* do loop for # of dcache lines */
/* NOTE: dccci invalidates both */
mtctr r7 /* ways in the D cache */
..dcloop:
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index 05b42fec9..ef47ffc95 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -238,7 +238,7 @@ static u8 pll_fbdv_multi_bits[] = {
/* values for: 101 - 200 */
0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3,
0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90,
- 0x20, 0xc0, 0x01, 0x83, 0x77, 0xff, 0x1f, 0xbf, 0x7f, 0xfe,
+ 0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe,
0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6,
0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd,
0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1,
@@ -1126,7 +1126,7 @@ void get_sys_info (sys_info_t * sysInfo)
m = sysInfo->pllFwdDiv * plb2xDiv * 2
* sysInfo->pllOpbDiv * sysInfo->pllExtBusDiv;
break;
- case PLL_FBK_PLL_LOCAL:
+ case PLL_FBK_PLL_LOCAL:
break;
default:
printf("%s unknown m\n", __FUNCTION__);
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index a513b4507..000817012 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -852,7 +852,7 @@ _start:
mtdccr r1 /* data cache */
addis r1,r0,CFG_INIT_RAM_ADDR@h
- ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
+ ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack to SDRAM */
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
stwu r0, -4(r1) /* stack backtraces terminate cleanly */
@@ -947,11 +947,11 @@ _start:
/*----------------------------------------------------------------------- */
/* DMA Status, clear to come up clean */
/*----------------------------------------------------------------------- */
- addis r3,r0, 0xFFFF /* Clear all existing DMA status */
+ addis r3,r0, 0xFFFF /* Clear all existing DMA status */
ori r3,r3, 0xFFFF
mtdcr dmasr, r3
- bl ppc405ep_init /* do ppc405ep specific init */
+ bl ppc405ep_init /* do ppc405ep specific init */
#endif /* CONFIG_405EP */
#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
@@ -1809,13 +1809,13 @@ ppc405ep_init:
!-----------------------------------------------------------------------
*/
mfdcr r5, CPC0_PLLMR1
- rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
+ rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
cmpi cr0,0,r4,0x1
- beq pll_done /* if SSCS =b'1' then PLL has */
- /* already been set */
- /* and CPU has been reset */
- /* so skip to next section */
+ beq pll_done /* if SSCS =b'1' then PLL has */
+ /* already been set */
+ /* and CPU has been reset */
+ /* so skip to next section */
#ifdef CONFIG_BUBINGA
/*
@@ -1837,13 +1837,13 @@ ppc405ep_init:
lwz r4, 0(r3)
addis r5,0,NVRVFY1@h
addi r5,r5,NVRVFY1@l
- cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
+ cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
bne ..no_pllset
addi r3,r3,4
lwz r4, 0(r3)
addis r5,0,NVRVFY2@h
addi r5,r5,NVRVFY2@l
- cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
+ cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
bne ..no_pllset
addi r3,r3,8 /* Skip over conf_size */
lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
@@ -1867,7 +1867,7 @@ ppc405ep_init:
#if defined(CONFIG_ZEUS)
mfdcr r4, CPC0_BOOT
andi. r5, r4, CPC0_BOOT_SEP@l
- bne strap_1 /* serial eeprom present */
+ bne strap_1 /* serial eeprom present */
lis r3,0x0000
addi r3,r3,0x3030
lis r4,0x8042
@@ -1879,10 +1879,10 @@ strap_1:
b 1f
#endif
- addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
- ori r3,r3,PLLMR0_DEFAULT@l /* */
- addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
- ori r4,r4,PLLMR1_DEFAULT@l /* */
+ addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
+ ori r3,r3,PLLMR0_DEFAULT@l /* */
+ addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
+ ori r4,r4,PLLMR1_DEFAULT@l /* */
#ifdef CONFIG_TAIHU
b 1f
@@ -1898,7 +1898,7 @@ strap_1:
#endif /* CONFIG_TAIHU */
1:
- b pll_write /* Write the CPC0_PLLMR with new value */
+ b pll_write /* Write the CPC0_PLLMR with new value */
pll_done:
/*
@@ -1915,7 +1915,7 @@ pll_done:
pci_wait:
bdnz pci_wait
- blr /* return to main code */
+ blr /* return to main code */
/*
!-----------------------------------------------------------------------------
@@ -1936,20 +1936,20 @@ pci_wait:
pll_write:
mfdcr r5, CPC0_UCR
andis. r5,r5,0xFFFF
- ori r5,r5,0x0101 /* Stop the UART clocks */
- mtdcr CPC0_UCR,r5 /* Before changing PLL */
+ ori r5,r5,0x0101 /* Stop the UART clocks */
+ mtdcr CPC0_UCR,r5 /* Before changing PLL */
mfdcr r5, CPC0_PLLMR1
- rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
+ rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
mtdcr CPC0_PLLMR1,r5
- oris r5,r5,0x4000 /* Set PLL Reset */
+ oris r5,r5,0x4000 /* Set PLL Reset */
mtdcr CPC0_PLLMR1,r5
- mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
- rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
- oris r5,r5,0x4000 /* Set PLL Reset */
- mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
- rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
+ mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
+ rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
+ oris r5,r5,0x4000 /* Set PLL Reset */
+ mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
+ rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
mtdcr CPC0_PLLMR1,r5
/*
@@ -1970,9 +1970,9 @@ pll_wait:
* Not sure if this is needed...
*/
addis r3,0,0x1000
- mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
- /* execution will continue from the poweron */
- /* vector of 0xfffffffc */
+ mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
+ /* execution will continue from the poweron */
+ /* vector of 0xfffffffc */
#endif /* CONFIG_405EP */
#if defined(CONFIG_440)
diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c
index 7dbb288eb..5dbd84227 100644
--- a/cpu/ppc4xx/usb_ohci.c
+++ b/cpu/ppc4xx/usb_ohci.c
@@ -1600,7 +1600,7 @@ int usb_lowlevel_init(void)
gohci.sleeping = 0;
gohci.irq = -1;
#if defined(CONFIG_440EP)
- gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
+ gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000);
#elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST)
gohci.regs = (struct ohci_regs *)(CFG_USB_HOST);
#endif
generated by cgit v1.2.3-70-g09d2 (git 2.51.2) at 2025-11-01 07:52:46 +0000