diff options
Diffstat (limited to 'cpu/mpc86xx')
| -rw-r--r-- | cpu/mpc86xx/cache.S | 4 | ||||
| -rw-r--r-- | cpu/mpc86xx/cpu_init.c | 25 | ||||
| -rw-r--r-- | cpu/mpc86xx/fdt.c | 2 | ||||
| -rw-r--r-- | cpu/mpc86xx/start.S | 119 |
4 files changed, 30 insertions, 120 deletions
diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S index 2e4ea0239..80ff68889 100644 --- a/cpu/mpc86xx/cache.S +++ b/cpu/mpc86xx/cache.S @@ -232,6 +232,10 @@ _GLOBAL(icache_enable) * Disable L1 Instruction cache */ _GLOBAL(icache_disable) + mflr r4 + bl invalidate_l1_instruction_cache /* uses r3 */ + sync + mtlr r4 mfspr r3, HID0 li r5, 0 ori r5, r5, HID0_ICE diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 78ba1ea8e..1fda3fe80 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -26,8 +26,10 @@ * cpu_init.c - low level cpu init */ +#include <config.h> #include <common.h> #include <mpc86xx.h> +#include <asm/mmu.h> #include <asm/fsl_law.h> DECLARE_GLOBAL_DATA_PTR; @@ -121,3 +123,26 @@ int cpu_init_r(void) { return 0; } + +/* Set up BAT registers */ +void setup_bats(void) +{ + write_bat(DBAT0, CFG_DBAT0U, CFG_DBAT0L); + write_bat(IBAT0, CFG_IBAT0U, CFG_IBAT0L); + write_bat(DBAT1, CFG_DBAT1U, CFG_DBAT1L); + write_bat(IBAT1, CFG_IBAT1U, CFG_IBAT1L); + write_bat(DBAT2, CFG_DBAT2U, CFG_DBAT2L); + write_bat(IBAT2, CFG_IBAT2U, CFG_IBAT2L); + write_bat(DBAT3, CFG_DBAT3U, CFG_DBAT3L); + write_bat(IBAT3, CFG_IBAT3U, CFG_IBAT3L); + write_bat(DBAT4, CFG_DBAT4U, CFG_DBAT4L); + write_bat(IBAT4, CFG_IBAT4U, CFG_IBAT4L); + write_bat(DBAT5, CFG_DBAT5U, CFG_DBAT5L); + write_bat(IBAT5, CFG_IBAT5U, CFG_IBAT5L); + write_bat(DBAT6, CFG_DBAT6U, CFG_DBAT6L); + write_bat(IBAT6, CFG_IBAT6U, CFG_IBAT6L); + write_bat(DBAT7, CFG_DBAT7U, CFG_DBAT7L); + write_bat(IBAT7, CFG_IBAT7U, CFG_IBAT7L); + + return; +} diff --git a/cpu/mpc86xx/fdt.c b/cpu/mpc86xx/fdt.c index 80a5c78a7..12d905203 100644 --- a/cpu/mpc86xx/fdt.c +++ b/cpu/mpc86xx/fdt.c @@ -25,7 +25,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) \ || defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) - fdt_fixup_ethernet(blob, bd); + fdt_fixup_ethernet(blob); #endif #ifdef CFG_NS16550 diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index c39dc4681..03f212844 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -358,125 +358,6 @@ invalidate_bats: sync blr - - /* setup_bats - set them up to some initial state */ - /* Skip any BATS setup in early_bats */ - .globl setup_bats -setup_bats: - - addis r0, r0, 0x0000 - - /* IBAT 0 */ - addis r4, r0, CFG_IBAT0L@h - ori r4, r4, CFG_IBAT0L@l - addis r3, r0, CFG_IBAT0U@h - ori r3, r3, CFG_IBAT0U@l - mtspr IBAT0L, r4 - mtspr IBAT0U, r3 - isync - - /* DBAT 0 */ - addis r4, r0, CFG_DBAT0L@h - ori r4, r4, CFG_DBAT0L@l - addis r3, r0, CFG_DBAT0U@h - ori r3, r3, CFG_DBAT0U@l - mtspr DBAT0L, r4 - mtspr DBAT0U, r3 - isync - - /* IBAT 1 */ - addis r4, r0, CFG_IBAT1L@h - ori r4, r4, CFG_IBAT1L@l - addis r3, r0, CFG_IBAT1U@h - ori r3, r3, CFG_IBAT1U@l - mtspr IBAT1L, r4 - mtspr IBAT1U, r3 - isync - - /* DBAT 1 */ - addis r4, r0, CFG_DBAT1L@h - ori r4, r4, CFG_DBAT1L@l - addis r3, r0, CFG_DBAT1U@h - ori r3, r3, CFG_DBAT1U@l - mtspr DBAT1L, r4 - mtspr DBAT1U, r3 - isync - - /* IBAT 2 */ - addis r4, r0, CFG_IBAT2L@h - ori r4, r4, CFG_IBAT2L@l - addis r3, r0, CFG_IBAT2U@h - ori r3, r3, CFG_IBAT2U@l - mtspr IBAT2L, r4 - mtspr IBAT2U, r3 - isync - - /* DBAT 2 */ - addis r4, r0, CFG_DBAT2L@h - ori r4, r4, CFG_DBAT2L@l - addis r3, r0, CFG_DBAT2U@h - ori r3, r3, CFG_DBAT2U@l - mtspr DBAT2L, r4 - mtspr DBAT2U, r3 - isync - - /* IBAT 3 */ - addis r4, r0, CFG_IBAT3L@h - ori r4, r4, CFG_IBAT3L@l - addis r3, r0, CFG_IBAT3U@h - ori r3, r3, CFG_IBAT3U@l - mtspr IBAT3L, r4 - mtspr IBAT3U, r3 - isync - - /* DBAT 3 */ - addis r4, r0, CFG_DBAT3L@h - ori r4, r4, CFG_DBAT3L@l - addis r3, r0, CFG_DBAT3U@h - ori r3, r3, CFG_DBAT3U@l - mtspr DBAT3L, r4 - mtspr DBAT3U, r3 - isync - - /* IBAT 4 */ - addis r4, r0, CFG_IBAT4L@h - ori r4, r4, CFG_IBAT4L@l - addis r3, r0, CFG_IBAT4U@h - ori r3, r3, CFG_IBAT4U@l - mtspr IBAT4L, r4 - mtspr IBAT4U, r3 - isync - - /* DBAT 4 */ - addis r4, r0, CFG_DBAT4L@h - ori r4, r4, CFG_DBAT4L@l - addis r3, r0, CFG_DBAT4U@h - ori r3, r3, CFG_DBAT4U@l - mtspr DBAT4L, r4 - mtspr DBAT4U, r3 - isync - - /* IBAT 7 */ - addis r4, r0, CFG_IBAT7L@h - ori r4, r4, CFG_IBAT7L@l - addis r3, r0, CFG_IBAT7U@h - ori r3, r3, CFG_IBAT7U@l - mtspr IBAT7L, r4 - mtspr IBAT7U, r3 - isync - - /* DBAT 7 */ - addis r4, r0, CFG_DBAT7L@h - ori r4, r4, CFG_DBAT7L@l - addis r3, r0, CFG_DBAT7U@h - ori r3, r3, CFG_DBAT7U@l - mtspr DBAT7L, r4 - mtspr DBAT7U, r3 - isync - - sync - blr - /* * early_bats: * |