diff options
Diffstat (limited to 'cpu/mpc85xx')
| -rw-r--r-- | cpu/mpc85xx/ether_fcc.c | 14 | ||||
| -rw-r--r-- | cpu/mpc85xx/i2c.c | 4 | ||||
| -rw-r--r-- | cpu/mpc85xx/pci.c | 20 | ||||
| -rw-r--r-- | cpu/mpc85xx/start.S | 5 |
4 files changed, 30 insertions, 13 deletions
diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c index cbbb3a402..d15d24249 100644 --- a/cpu/mpc85xx/ether_fcc.c +++ b/cpu/mpc85xx/ether_fcc.c @@ -48,6 +48,10 @@ #include <config.h> #include <net.h> +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) +#include <miiphy.h> +#endif + #if defined(CONFIG_CPM2) #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \ @@ -303,7 +307,9 @@ static int fec_init(struct eth_device* dev, bd_t *bis) * Allocate space in the reserved FCC area of DPRAM for the * internal buffers. No one uses this space (yet), so we * can do this. Later, we will add resource management for - * this area. CPM_FCC_SPECIAL_BASE: 0xb000. + * this area. + * CPM_FCC_SPECIAL_BASE: 0xB000 for MPC8540, MPC8560 + * 0x9000 for MPC8541, MPC8555 */ mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64); pram_ptr->fen_genfcc.fcc_riptr = mem_addr; @@ -451,6 +457,12 @@ int fec_initialize(bd_t *bis) dev->recv = fec_recv; eth_register(dev); + +#if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) \ + && defined(CONFIG_BITBANGMII) + miiphy_register(dev->name, + bb_miiphy_read, bb_miiphy_write); +#endif } return 1; diff --git a/cpu/mpc85xx/i2c.c b/cpu/mpc85xx/i2c.c index 2d0848799..32dcf5d47 100644 --- a/cpu/mpc85xx/i2c.c +++ b/cpu/mpc85xx/i2c.c @@ -245,12 +245,12 @@ int i2c_probe (uchar chip) * and looking for an <ACK> back. */ udelay(10000); - return i2c_read (chip, 0, 1, (char *)&tmp, 1); + return i2c_read (chip, 0, 1, (uchar *)&tmp, 1); } uchar i2c_reg_read (uchar i2c_addr, uchar reg) { - char buf[1]; + uchar buf[1]; i2c_read (i2c_addr, reg, 1, buf, 1); diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index 069fe4e69..a94493e08 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -61,16 +61,6 @@ pci_mpc85xx_init(struct pci_controller *hose) (CFG_IMMR+0x8000), (CFG_IMMR+0x8004)); - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); - pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); - pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; pcix->potear1 = 0x00000000; pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; @@ -93,6 +83,16 @@ pci_mpc85xx_init(struct pci_controller *hose) */ pci_register_hose(hose); + pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); + + /* + * Clear non-reserved bits in status register. + */ + pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); + pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); + #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS) /* * This is a SW workaround for an apparent HW problem diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 5f75bc1af..7ac65736b 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -995,6 +995,11 @@ relocate_code: 7: sync /* Wait for all icbi to complete on bus */ isync + /* + * Re-point the IVPR at RAM + */ + mtspr IVPR,r10 + /* * We are done. Do not return, instead branch to second part of board * initialization, now running from RAM. |