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Diffstat (limited to 'cpu/mpc85xx/start.S')
-rw-r--r--cpu/mpc85xx/start.S18
1 files changed, 13 insertions, 5 deletions
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 7bca008b5..5f75bc1af 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -155,11 +155,13 @@ _start_e500:
mtspr MCSR,r0
mtspr DEAR,r0
- mtspr DBCR0,r0
+ /* not needed and conflicts with some debuggers */
+ /* mtspr DBCR0,r0 */
mtspr DBCR1,r0
mtspr DBCR2,r0
- mtspr IAC1,r0
- mtspr IAC2,r0
+ /* not needed and conflicts with some debuggers */
+ /* mtspr IAC1,r0 */
+ /* mtspr IAC2,r0 */
mtspr DAC1,r0
mtspr DAC2,r0
@@ -174,6 +176,9 @@ _start_e500:
mtspr BUCSR,r0 /* disable branch prediction */
mtspr MAS4,r0
mtspr MAS6,r0
+#if defined(CONFIG_ENABLE_36BIT_PHYS)
+ mtspr MAS7,r0
+#endif
isync
/* Setup interrupt vectors */
@@ -204,8 +209,8 @@ _start_e500:
li r1,0x0b00
mtspr IVOR11,r1 /* 11: Interval timer */
li r1,0x0c00
- mtspr IVOR12,r1 /* 11: Watchdog timer */
- li r10,0x0d00
+ mtspr IVOR12,r1 /* 12: Watchdog timer */
+ li r1,0x0d00
mtspr IVOR13,r1 /* 13: Data TLB error */
li r1,0x0e00
mtspr IVOR14,r1 /* 14: Instruction TLB error */
@@ -358,6 +363,9 @@ _start:
/* Enable Time Base and Select Time Base Clock */
lis r0,HID0_EMCP@h /* Enable machine check */
ori r0,r0,0x4000 /* time base is processor clock */
+#if defined(CONFIG_ENABLE_36BIT_PHYS)
+ ori r0,r0,0x0080 /* enable MAS7 updates */
+#endif
mtspr HID0,r0
#if defined(CONFIG_ADDR_STREAMING)