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-rw-r--r--cpu/mpc83xx/Makefile1
-rw-r--r--cpu/mpc83xx/cpu.c6
-rw-r--r--cpu/mpc83xx/i2c.c8
-rw-r--r--cpu/mpc83xx/pci.c252
-rw-r--r--cpu/mpc83xx/speed.c113
5 files changed, 38 insertions, 342 deletions
diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile
index 14574f45e..60df4cdec 100644
--- a/cpu/mpc83xx/Makefile
+++ b/cpu/mpc83xx/Makefile
@@ -32,7 +32,6 @@ COBJS = traps.o \
cpu_init.o \
speed.o \
interrupts.o \
- pci.o \
i2c.o \
spd_sdram.o
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index c84aeb4df..8c9b515fa 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -50,7 +50,7 @@ int checkcpu(void)
return -1;
}
- puts("CPU: MPC83xx, ");
+ puts("CPU: MPC83xx, ");
switch(pvr) {
case PVR_8349_REV10:
break;
@@ -60,7 +60,9 @@ int checkcpu(void)
puts("Rev: Unknown\n");
return -1; /* Not sure what this is */
}
- printf("Rev: %02x at %s MHz\n",pvr & 0x0000FFFF, strmhz(buf, clock));
+ printf("Rev: %d.%d at %s MHz\n", (pvr & 0xf0) >> 4,
+ (pvr & 0x0f), strmhz(buf, clock));
+
return 0;
}
diff --git a/cpu/mpc83xx/i2c.c b/cpu/mpc83xx/i2c.c
index 3db7d2cbc..4e70f808a 100644
--- a/cpu/mpc83xx/i2c.c
+++ b/cpu/mpc83xx/i2c.c
@@ -41,7 +41,7 @@
#include <i2c.h>
#include <asm/i2c.h>
-#ifdef CONFIG_MPC8349ADS
+#if defined(CONFIG_MPC8349ADS) || defined(CONFIG_TQM834X)
i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET);
#endif
@@ -109,7 +109,9 @@ i2c_wait (int write)
return 0;
} while (get_timer (timeval) < I2C_TIMEOUT);
+
debug("i2c_wait: timed out\n");
+ return -1;
}
static __inline__ int
@@ -231,12 +233,12 @@ int i2c_probe (uchar chip)
* and looking for an <ACK> back.
*/
udelay(10000);
- return i2c_read (chip, 0, 1, (char *)&tmp, 1);
+ return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
}
uchar i2c_reg_read (uchar i2c_addr, uchar reg)
{
- char buf[1];
+ uchar buf[1];
i2c_read (i2c_addr, reg, 1, buf, 1);
diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c
deleted file mode 100644
index d5fa811ed..000000000
--- a/cpu/mpc83xx/pci.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright (C) 2003 Motorola Inc.
- * Xianghua Xiao (x.xiao@motorola.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Change log:
- *
- * 20050101: Eran Liberty (liberty@freescale.com)
- * Initial file creating (porting from 85XX & 8260)
- */
-
-/*
- * PCI Configuration space access support for MPC85xx PCI Bridge
- */
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <common.h>
-#include <pci.h>
-
-#ifdef CONFIG_MPC8349ADS
-#include <asm/i2c.h>
-#endif
-
-#if defined(CONFIG_PCI)
-
-void
-pci_mpc83xx_init(volatile struct pci_controller *hose)
-{
- volatile immap_t * immr;
- volatile clk8349_t * clk;
- volatile law8349_t * pci_law;
- volatile pot8349_t * pci_pot;
- volatile pcictrl8349_t * pci_ctrl;
- volatile pciconf8349_t * pci_conf;
-
- u8 val8,tmp8,ret;
- u16 reg16,tmp16;
- u32 val32,tmp32;
-
- immr = (immap_t *)CFG_IMMRBAR;
- clk = (clk8349_t *)&immr->clk;
- pci_law = immr->sysconf.pcilaw;
- pci_pot = immr->ios.pot;
- pci_ctrl = immr->pci_ctrl;
- pci_conf = immr->pci_conf;
-
- /*
- * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
- */
- val32 = clk->occr;
- udelay(2000);
- clk->occr = 0xff000000;
- udelay(2000);
-
- /*
- * Configure PCI Local Access Windows
- */
- pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
- pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
-
- /*
- * Configure PCI Outbound Translation Windows
- */
- pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
-
- /* mapped to PCI1 IO space 0x0 to local 0xe2000000 */
- pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
-
- pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK);
-
- /* mapped to PCI2 IO space 0x0 to local 0xe3000000 */
- pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
- pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
- pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
-
- /*
- * Configure PCI Inbound Translation Windows
- */
- pci_ctrl[0].pitar1 = 0x0;
- pci_ctrl[0].pibar1 = 0x0;
- pci_ctrl[0].piebar1 = 0x0;
- pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
-
- pci_ctrl[1].pitar1 = 0x0;
- pci_ctrl[1].pibar1 = 0x0;
- pci_ctrl[1].piebar1 = 0x0;
- pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
- /*
- * Assign PIB PMC slot to desired PCI bus
- */
-#ifdef CONFIG_MPC8349ADS
- mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET);
- i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE);
-#endif
- val8 = 0;
- ret = i2c_write(0x23,0x6,1,&val8,1);
- ret = i2c_write(0x23,0x7,1,&val8,1);
- val8 = 0xff;
- ret = i2c_write(0x23,0x2,1,&val8,1);
- ret = i2c_write(0x23,0x3,1,&val8,1);
-
- val8 = 0;
- ret = i2c_write(0x26,0x6,1,&val8,1);
- val8 = 0x34;
- ret = i2c_write(0x26,0x7,1,&val8,1);
-#if defined(PCI_64BIT)
- val8 = 0xf4; /* PMC2<->PCI1 64bit */
-#elif defined(PCI_ALL_PCI1)
- val8 = 0xf3; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit */
-#elif defined(PCI_ONE_PCI1)
- val8 = 0xf9; /* PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit */
-#elif defined(PCI_TWO_PCI1)
- val8 = 0xf5; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit */
-#else
- val8 = 0xf5;
-#endif
- ret = i2c_write(0x26,0x2,1,&val8,1);
- val8 = 0xff;
- ret = i2c_write(0x26,0x3,1,&val8,1);
- val8 = 0;
- ret = i2c_write(0x27,0x6,1,&val8,1);
- ret = i2c_write(0x27,0x7,1,&val8,1);
- val8 = 0xff;
- ret = i2c_write(0x27,0x2,1,&val8,1);
- val8 = 0xef;
- ret = i2c_write(0x27,0x3,1,&val8,1);
- asm("eieio");
-
- /*
- * Release PCI RST Output signal
- */
- udelay(2000);
- pci_ctrl[0].gcr = 1;
-#ifndef PCI_64BIT
- pci_ctrl[1].gcr = 1;
-#endif
- udelay(2000);
-
- hose[0].first_busno = 0;
- hose[0].last_busno = 0xff;
-
- pci_set_region(hose[0].regions + 0,
- CFG_PCI1_MEM_BASE,
- CFG_PCI1_MEM_PHYS,
- CFG_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- pci_set_region(hose[0].regions + 1,
- CFG_PCI1_IO_BASE,
- CFG_PCI1_IO_PHYS,
- CFG_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- hose[0].region_count = 2;
-
- pci_setup_indirect(&hose[0],
- (CFG_IMMRBAR+0x8300),
- (CFG_IMMRBAR+0x8304));
-#define PCI_CLASS_BRIDGE 0x06
- reg16 = 0xff;
- tmp32 = 0xffff;
- pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
-
- pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, &reg16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
-#ifndef PCI_64BIT
- hose[1].first_busno = 0;
- hose[1].last_busno = 0xff;
-
- pci_set_region(hose[1].regions + 0,
- CFG_PCI2_MEM_BASE,
- CFG_PCI2_MEM_PHYS,
- CFG_PCI2_MEM_SIZE,
- PCI_REGION_MEM);
-
- pci_set_region(hose[1].regions + 1,
- CFG_PCI2_IO_BASE,
- CFG_PCI2_IO_PHYS,
- CFG_PCI2_IO_SIZE,
- PCI_REGION_IO);
-
- hose[1].region_count = 2;
-
- pci_setup_indirect(&hose[1],
- (CFG_IMMRBAR+0x8380),
- (CFG_IMMRBAR+0x8384));
-
- pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
- pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
- reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
- pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16);
-
- /*
- * Clear non-reserved bits in status register.
- */
- pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
- pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
-#endif
-
-#if defined(PCI_64BIT)
- printf("PCI1 64bit on PMC2\n");
-#elif defined(PCI_ALL_PCI1)
- printf("PCI1 32bit on PMC1 & PMC2 & PMC3\n");
-#elif defined(PCI_ONE_PCI1)
- printf("PCI1 32bit on PMC1,PCI2 32bit on PMC2 & PMC3\n");
-#else
- printf("PCI1 32bit on PMC1 & PMC2 & PMC3 in default\n");
-#endif
-
-#if 1
- /*
- * Hose scan.
- */
- pci_register_hose(hose);
- hose->last_busno = pci_hose_scan(hose);
-#endif
-}
-
-#endif /* CONFIG_PCI */
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 260137da8..1368fc3fe 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -118,41 +118,50 @@ int get_clocks (void)
return -1;
#ifndef CFG_HRCW_HIGH
-# error "CFG_HRCW_HIGH must be defined in include/configs/MCP83XXADS.h"
+# error "CFG_HRCW_HIGH must be defined in board config file"
#endif /* CFG_HCWD_HIGH */
#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST)
+
# ifndef CONFIG_83XX_CLKIN
-# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in include/configs/MCP83XXADS.h"
+# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file"
# endif /* CONFIG_83XX_CLKIN */
# ifdef CONFIG_83XX_PCICLK
-# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in include/configs/MCP83XXADS.h is igonred."
+# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred"
# endif /* CONFIG_83XX_PCICLK */
-/* PCI Host Mode */
+
+ /* PCI Host Mode */
if (!(im->reset.rcwh & RCWH_PCIHOST)) {
- /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */
- /* FIXME: findout if there is a way to issue some warning */
+ /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH
+ * the im->reset.rcwhr PCI Host Mode is disabled
+ * FIXME: findout if there is a way to issue some warning */
return -2;
}
if (im->clk.spmr & SPMR_CKID) {
- pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */
+ /* PCI Clock is half CONFIG_83XX_CLKIN */
+ pci_sync_in = CONFIG_83XX_CLKIN / 2;
}
else {
pci_sync_in = CONFIG_83XX_CLKIN;
}
-#else
+
+#else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */
+
# ifdef CONFIG_83XX_CLKIN
-# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in include/configs/MCP83XXADS.h is igonred."
+# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred"
# endif /* CONFIG_83XX_CLKIN */
# ifndef CONFIG_83XX_PCICLK
-# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in include/configs/MCP83XXADS.h"
+# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file"
# endif /* CONFIG_83XX_PCICLK */
-/* PCI Agent Mode */
+
+ /* PCI Agent Mode */
if (im->reset.rcwh & RCWH_PCIHOST) {
- /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is enabled */
+ /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH
+ * the im->reset.rcwhr PCI Host Mode is enabled */
return -3;
}
pci_sync_in = CONFIG_83XX_PCICLK;
+
#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
/* we have up to date pci_sync_in */
@@ -320,6 +329,7 @@ int get_clocks (void)
gd->lbiu_clk = lbiu_clk ;
gd->lclk_clk = lclk_clk ;
gd->ddr_clk = ddr_clk ;
+ gd->pci_clk = pci_sync_in;
gd->cpu_clk = gd->core_clk;
gd->bus_clk = gd->lbiu_clk;
@@ -343,79 +353,14 @@ int print_clock_conf (void)
printf("Clock configuration:\n");
printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
printf(" Core: %4d MHz\n",gd->core_clk/1000000);
- printf(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
+ debug(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000);
- printf(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
- printf(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
- printf(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
- printf(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
- printf(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
- printf(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
-
-#if 0
- DECLARE_GLOBAL_DATA_PTR;
-
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
- ulong sccr, dfbrg;
- ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
- corecnf_t *cp;
-
- sccr = immap->im_clkrst.car_sccr;
- dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
-
- scmr = immap->im_clkrst.car_scmr;
- corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
- busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
- cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
- plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
- pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
-
- cp = &corecnf_tab[corecnf];
-
- puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult ");
-
- switch (cp->b2c_mult) {
- case _byp:
- puts ("BYPASS");
- break;
+ debug(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
+ debug(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
+ debug(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
+ debug(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
+ debug(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
+ debug(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
- case _off:
- puts ("OFF");
- break;
-
- case _unk:
- puts ("UNKNOWN");
- break;
-
- default:
- printf ("%d%sx",
- cp->b2c_mult / 2,
- (cp->b2c_mult % 2) ? ".5" : "");
- break;
- }
-
- printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n",
- cp->vco_div, cp->freq_60x, cp->freq_core);
-
- printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
- "plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf,
- pllmf);
-
- printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
- gd->vco_out, gd->scc_clk, gd->brg_clk);
-
- printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
- gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
-
- if (sccr & SCCR_PCI_MODE) {
- uint pci_div;
-
- pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
- ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
-
- printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div);
- }
- putc ('\n');
-#endif
return 0;
}
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