diff options
Diffstat (limited to 'cpu/i386')
| -rw-r--r-- | cpu/i386/interrupts.c | 2 | ||||
| -rw-r--r-- | cpu/i386/sc520.c | 12 | ||||
| -rw-r--r-- | cpu/i386/sc520_asm.S | 12 | ||||
| -rw-r--r-- | cpu/i386/start.S | 4 | ||||
| -rw-r--r-- | cpu/i386/timer.c | 4 |
5 files changed, 17 insertions, 17 deletions
diff --git a/cpu/i386/interrupts.c b/cpu/i386/interrupts.c index f34011990..f6dbccac5 100644 --- a/cpu/i386/interrupts.c +++ b/cpu/i386/interrupts.c @@ -509,7 +509,7 @@ int disable_interrupts(void) } -#ifdef CFG_RESET_GENERIC +#ifdef CONFIG_SYS_RESET_GENERIC void __attribute__ ((regparm(0))) generate_gpf(void); asm(".globl generate_gpf\n" diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c index 640b25584..8bcb979c1 100644 --- a/cpu/i386/sc520.c +++ b/cpu/i386/sc520.c @@ -113,7 +113,7 @@ void init_sc520(void) write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */ - if (CFG_SC520_HIGH_SPEED) { + if (CONFIG_SYS_SC520_HIGH_SPEED) { write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */ gd->cpu_clk = 133000000; printf("## CPU Speed set to 133MHz\n"); @@ -145,7 +145,7 @@ unsigned long init_sc520_dram(void) u32 dram_present=0; u32 dram_ctrl; -#ifdef CFG_SDRAM_DRCTMCTL +#ifdef CONFIG_SYS_SDRAM_DRCTMCTL /* these memory control registers are set up in the assember part, * in sc520_asm.S, during 'mem_init'. If we muck with them here, * after we are running a stack in RAM, we have troubles. Besides, @@ -156,9 +156,9 @@ unsigned long init_sc520_dram(void) #else int val; - int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY; - int refresh_rate = CFG_SDRAM_REFRESH_RATE; - int ras_cas_delay = CFG_SDRAM_RAS_CAS_DELAY; + int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY; + int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE; + int ras_cas_delay = CONFIG_SYS_SDRAM_RAS_CAS_DELAY; /* set SDRAM speed here */ @@ -393,7 +393,7 @@ void pci_sc520_init(struct pci_controller *hose) #endif -#ifdef CFG_TIMER_SC520 +#ifdef CONFIG_SYS_TIMER_SC520 void reset_timer(void) diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S index 34322ea25..59ed2b8d6 100644 --- a/cpu/i386/sc520_asm.S +++ b/cpu/i386/sc520_asm.S @@ -460,21 +460,21 @@ emptybank: incl %edi loop cleanuplp -#if defined CFG_SDRAM_DRCTMCTL +#if defined CONFIG_SYS_SDRAM_DRCTMCTL /* just have your hardware desinger _GIVE_ you what you need here! */ movl $DRCTMCTL, %edi - movb $CFG_SDRAM_DRCTMCTL,%al + movb $CONFIG_SYS_SDRAM_DRCTMCTL,%al movb (%edi), %al #else -#if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T) +#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T) /* set the CAS latency now since it is hard to do * when we run from the RAM */ movl $DRCTMCTL, %edi /* DRAM timing register */ movb (%edi), %al -#ifdef CFG_SDRAM_CAS_LATENCY_2T +#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T andb $0xef, %al #endif -#ifdef CFG_SDRAM_CAS_LATENCY_3T +#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T orb $0x10, %al #endif movb %al, (%edi) @@ -540,7 +540,7 @@ bank0: movl (%edi), %eax done: movl %ebx, %eax -#if CFG_SDRAM_ECC_ENABLE +#if CONFIG_SYS_SDRAM_ECC_ENABLE /* A nominal memory test: just a byte at each address line */ movl %eax, %ecx shrl $0x1, %ecx diff --git a/cpu/i386/start.S b/cpu/i386/start.S index 264ac0940..f5ad833aa 100644 --- a/cpu/i386/start.S +++ b/cpu/i386/start.S @@ -67,7 +67,7 @@ mem_init_ret: * (we need atleast bss start+bss size+stack size) */ movl $_i386boot_bss_start, %ecx /* BSS start */ addl $_i386boot_bss_size, %ecx /* BSS size */ - addl $CFG_STACK_SIZE, %ecx + addl $CONFIG_SYS_STACK_SIZE, %ecx cmpl %ecx, %eax jae mem_ok @@ -88,7 +88,7 @@ mem_ok: /* create a stack after the bss */ movl $_i386boot_bss_start, %eax addl $_i386boot_bss_size, %eax - addl $CFG_STACK_SIZE, %eax + addl $CONFIG_SYS_STACK_SIZE, %eax movl %eax, %esp pushl $0 diff --git a/cpu/i386/timer.c b/cpu/i386/timer.c index 486d927a5..46db23f59 100644 --- a/cpu/i386/timer.c +++ b/cpu/i386/timer.c @@ -72,9 +72,9 @@ int timer_init(void) } -#ifdef CFG_TIMER_GENERIC +#ifdef CONFIG_SYS_TIMER_GENERIC -/* the unit for these is CFG_HZ */ +/* the unit for these is CONFIG_SYS_HZ */ /* FixMe: implement these */ void reset_timer (void) |