diff options
Diffstat (limited to 'board')
26 files changed, 32 insertions, 2018 deletions
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 313f9f36a..c90f86b8d 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -466,143 +466,6 @@ phys_size_t initdram (int board_type) #endif } -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long addr; - - /*-------------------------------------------------------------------------+ - | Set priority for all PLB3 devices to 0. - | Set PLB3 arbiter to fair mode. - +-------------------------------------------------------------------------*/ - mfsdr(SD0_AMP1, addr); - mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB3_ACR); - mtdcr(PLB3_ACR, addr | 0x80000000); - - /*-------------------------------------------------------------------------+ - | Set priority for all PLB4 devices to 0. - +-------------------------------------------------------------------------*/ - mfsdr(SD0_AMP0, addr); - mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ - mtdcr(PLB4_ACR, addr); - - /*-------------------------------------------------------------------------+ - | Set Nebula PLB4 arbiter to fair mode. - +-------------------------------------------------------------------------*/ - /* Segment0 */ - addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; - addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; - addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; - addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; - mtdcr(PLB0_ACR, addr); - - /* Segment1 */ - addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; - addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; - addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; - addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; - mtdcr(PLB1_ACR, addr); - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Set up Direct MMIO registers - *--------------------------------------------------------------------------*/ - /*--------------------------------------------------------------------------+ - | PowerPC440 EP PCI Master configuration. - | Map one 1Gig range of PLB/processor addresses to PCI memory space. - | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF - | Use byte reversed out routines to handle endianess. - | Make this region non-prefetchable. - +--------------------------------------------------------------------------*/ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /*--------------------------------------------------------------------------+ - * Set up Configuration registers - *--------------------------------------------------------------------------*/ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/************************************************************************* - * pci_master_init - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - unsigned short temp_short; - - /*--------------------------------------------------------------------------+ - | Write the PowerPC440 EP PCI Configuration regs. - | Enable PowerPC440 EP to be a master on the PCI bus (PMM). - | Enable PowerPC440 EP to act as a PCI memory target (PTM). - +--------------------------------------------------------------------------*/ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ - /*----------------------------------------------------------------------------+ | is_powerpc440ep_pass1. +----------------------------------------------------------------------------*/ diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 9a8ca8ece..13a0daced 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -326,43 +326,6 @@ phys_size_t initdram(int board_type) } #endif -/* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /* - * Disable everything - */ - out_le32((void *)PCIL0_PIM0SA, 0); /* disable */ - out_le32((void *)PCIL0_PIM1SA, 0); /* disable */ - out_le32((void *)PCIL0_PIM2SA, 0); /* disable */ - out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */ - - /* - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 - * strapping options to not support sizes such as 128/256 MB. - */ - out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out_le32((void *)PCIL0_PIM0LAH, 0); - out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); - out_le32((void *)PCIL0_BAR0, 0); - - /* - * Program the board's subsystem id/vendor id - */ - out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - - out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - #if defined(CONFIG_PCI) int board_pcie_first(void) { diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index 1524b5333..923dbca71 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -164,73 +164,3 @@ long int fixed_sdram(void) return (128 * 1024 * 1024); /* 128 MB */ } #endif /* !defined(CONFIG_SPD_EEPROM) */ - -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long strap; - - /*--------------------------------------------------------------------------+ - * The ebony board is always configured as the host & requires the - * PCI arbiter to be enabled. - *--------------------------------------------------------------------------*/ - strap = mfdcr(CPC0_STRP1); - if ((strap & 0x00100000) == 0) { - printf("PCI: CPC0_STRP1[PAE] not set.\n"); - return 0; - } - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r(PCIL0_PIM0SA, 0); /* disable */ - out32r(PCIL0_PIM1SA, 0); /* disable */ - out32r(PCIL0_PIM2SA, 0); /* disable */ - out32r(PCIL0_EROMBA, 0); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out32r(PCIL0_PIM0LAH, 0); - out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); - - out32r(PCIL0_BAR0, 0); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - - out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index f43e76448..86dc923e7 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007-2008 + * (C) Copyright 2007-2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -260,75 +260,6 @@ u32 ddr_clktr(u32 default_val) { return (SDRAM_CLKTR_CLKP_90_DEG_ADV); } -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller * hose ) -{ - unsigned long strap; - - /*-------------------------------------------------------------------+ - * The katmai board is always configured as the host & requires the - * PCI arbiter to be enabled. - *-------------------------------------------------------------------*/ - mfsdr(SDR0_SDSTP1, strap); - if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { - printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); - return 0; - } - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /*-------------------------------------------------------------------+ - * Disable everything - *-------------------------------------------------------------------*/ - out32r( PCIL0_PIM0SA, 0 ); /* disable */ - out32r( PCIL0_PIM1SA, 0 ); /* disable */ - out32r( PCIL0_PIM2SA, 0 ); /* disable */ - out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ - - /*-------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 - * strapping options to not support sizes such as 128/256 MB. - *-------------------------------------------------------------------*/ - out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIL0_PIM0LAH, 0 ); - out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIL0_BAR0, 0 ); - - /*-------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *-------------------------------------------------------------------*/ - out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - - out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - #if defined(CONFIG_PCI) int board_pcie_card_present(int port) { diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index c4f8a6496..2f99ea113 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -285,25 +285,6 @@ int checkboard (void) return (0); } -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller * hose ) -{ - return 0; -} -#endif /* defined(CONFIG_PCI) */ - #if defined(CONFIG_POST) /* * Returns 1 if keys pressed to start the power-on long-running tests diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 94ba6437f..332d170d6 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -127,79 +127,6 @@ u32 ddr_clktr(u32 default_val) { } /************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init( struct pci_controller *hose ) -{ - unsigned long strap; - - /*--------------------------------------------------------------------------+ - * The luan board is always configured as the host & requires the - * PCI arbiter to be enabled. - *--------------------------------------------------------------------------*/ - mfsdr(SDR0_SDSTP1, strap); - if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { - printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); - - return 0; - } - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0SA, 0 ); /* disable */ - out32r( PCIL0_PIM1SA, 0 ); /* disable */ - out32r( PCIL0_PIM2SA, 0 ); /* disable */ - out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIL0_PIM0LAH, 0 ); - out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIL0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - - out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - - -/************************************************************************* * hw_watchdog_reset * * This routine is called to reset (keep alive) the watchdog timer diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c index 43b9bc6ba..3d860af9a 100644 --- a/board/amcc/makalu/makalu.c +++ b/board/amcc/makalu/makalu.c @@ -237,25 +237,6 @@ int checkboard (void) return (0); } -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller * hose ) -{ - return 0; -} -#endif /* defined(CONFIG_PCI) */ - #if defined(CONFIG_POST) /* * Returns 1 if keys pressed to start the power-on long-running tests diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 2f64764ee..951a8b539 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -275,78 +275,6 @@ long int fixed_sdram (void) } #endif /* !defined(CONFIG_SPD_EEPROM) */ - -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller * hose ) -{ - unsigned long strap; - - /*--------------------------------------------------------------------------+ - * The ocotea board is always configured as the host & requires the - * PCI arbiter to be enabled. - *--------------------------------------------------------------------------*/ - mfsdr(SDR0_SDSTP1, strap); - if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ - printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); - return 0; - } - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0SA, 0 ); /* disable */ - out32r( PCIL0_PIM1SA, 0 ); /* disable */ - out32r( PCIL0_PIM2SA, 0 ); /* disable */ - out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIL0_PIM0LAH, 0 ); - out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIL0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - - out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - - void fpga_init(void) { unsigned long group; diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 439382006..cb34c9d7d 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -364,151 +364,12 @@ int checkboard(void) /* * Assign interrupts to PCI devices. */ -void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2); } #endif -/* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - */ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long addr; - - /* - * Set priority for all PLB3 devices to 0. - * Set PLB3 arbiter to fair mode. - */ - mfsdr(SD0_AMP1, addr); - mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB3_ACR); - mtdcr(PLB3_ACR, addr | 0x80000000); - - /* - * Set priority for all PLB4 devices to 0. - */ - mfsdr(SD0_AMP0, addr); - mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ - mtdcr(PLB4_ACR, addr); - - /* - * Set Nebula PLB4 arbiter to fair mode. - */ - /* Segment0 */ - addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; - addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; - addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; - addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; - mtdcr(PLB0_ACR, addr); - - /* Segment1 */ - addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; - addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; - addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; - addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; - mtdcr(PLB1_ACR, addr); - -#ifdef CONFIG_PCI_PNP - hose->fixup_irq = sequoia_pci_fixup_irq; -#endif - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /* - * Set up Direct MMIO registers - */ - /* - * PowerPC440EPX PCI Master configuration. - * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0xA0000000-0xDFFFFFFF - * ==> PCI address 0xA0000000-0xDFFFFFFF - * Use byte reversed out routines to handle endianess. - * Make this region non-prefetchable. - */ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ - /* and enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ - /* and enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /* - * Set up Configuration registers - */ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - unsigned short temp_short; - - /* - * Write the PowerPC440 EP PCI Configuration regs. - * Enable PowerPC440 EP to be a master on the PCI bus (PMM). - * Enable PowerPC440 EP to act as a PCI memory target (PTM). - */ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ - #if defined(CONFIG_POST) /* * Returns 1 if keys pressed to start the power-on long-running tests diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index 81e8fe14a..279fae21c 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -209,76 +209,6 @@ int checkboard (void) return (0); } -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller * hose ) -{ - unsigned long strap; - - /*--------------------------------------------------------------------------+ - * The ocotea board is always configured as the host & requires the - * PCI arbiter to be enabled. - *--------------------------------------------------------------------------*/ - mfsdr(SDR0_SDSTP1, strap); - if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ - printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); - return 0; - } - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0SA, 0 ); /* disable */ - out32r( PCIL0_PIM1SA, 0 ); /* disable */ - out32r( PCIL0_PIM2SA, 0 ); /* disable */ - out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIL0_PIM0LAH, 0 ); - out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIL0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - - out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - #ifdef CONFIG_POST /* * Returns 1 if keys pressed to start the power-on long-running tests diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index e416eeb16..98c1f3b81 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -353,143 +353,6 @@ phys_size_t initdram(int board) } /************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long addr; - - /*-------------------------------------------------------------------------+ - | Set priority for all PLB3 devices to 0. - | Set PLB3 arbiter to fair mode. - +-------------------------------------------------------------------------*/ - mfsdr(SD0_AMP1, addr); - mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB3_ACR); - mtdcr(PLB3_ACR, addr | 0x80000000); - - /*-------------------------------------------------------------------------+ - | Set priority for all PLB4 devices to 0. - +-------------------------------------------------------------------------*/ - mfsdr(SD0_AMP0, addr); - mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ - mtdcr(PLB4_ACR, addr); - - /*-------------------------------------------------------------------------+ - | Set Nebula PLB4 arbiter to fair mode. - +-------------------------------------------------------------------------*/ - /* Segment0 */ - addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; - addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; - addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; - addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; - mtdcr(PLB0_ACR, addr); - - /* Segment1 */ - addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; - addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; - addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; - addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; - mtdcr(PLB1_ACR, addr); - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Set up Direct MMIO registers - *--------------------------------------------------------------------------*/ - /*--------------------------------------------------------------------------+ - | PowerPC440 EP PCI Master configuration. - | Map one 1Gig range of PLB/processor addresses to PCI memory space. - | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF - | Use byte reversed out routines to handle endianess. - | Make this region non-prefetchable. - +--------------------------------------------------------------------------*/ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /*--------------------------------------------------------------------------+ - * Set up Configuration registers - *--------------------------------------------------------------------------*/ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/************************************************************************* - * pci_master_init - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - unsigned short temp_short; - - /*--------------------------------------------------------------------------+ - | Write the PowerPC440 EP PCI Configuration regs. - | Enable PowerPC440 EP to be a master on the PCI bus (PMM). - | Enable PowerPC440 EP to act as a PCI memory target (PTM). - +--------------------------------------------------------------------------*/ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ - -/************************************************************************* * hw_watchdog_reset * * This routine is called to reset (keep alive) the watchdog timer diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 7315033dc..e0d19bcb6 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -588,75 +588,6 @@ u32 ddr_clktr(u32 default_val) { return default_val; } -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller * hose ) -{ - unsigned long strap; - - /*-------------------------------------------------------------------+ - * The yucca board is always configured as the host & requires the - * PCI arbiter to be enabled. - *-------------------------------------------------------------------*/ - mfsdr(SDR0_SDSTP1, strap); - if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { - printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); - return 0; - } - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /*-------------------------------------------------------------------+ - * Disable everything - *-------------------------------------------------------------------*/ - out32r( PCIL0_PIM0SA, 0 ); /* disable */ - out32r( PCIL0_PIM1SA, 0 ); /* disable */ - out32r( PCIL0_PIM2SA, 0 ); /* disable */ - out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ - - /*-------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 - * strapping options to not support sizes such as 128/256 MB. - *-------------------------------------------------------------------*/ - out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIL0_PIM0LAH, 0 ); - out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIL0_BAR0, 0 ); - - /*-------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *-------------------------------------------------------------------*/ - out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - - out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - #if defined(CONFIG_PCI) int board_pcie_card_present(int port) { diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 8f9f9500e..111cce52a 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -360,144 +360,6 @@ int checkboard(void) return (0); } -/* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - */ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long addr; - - /* - * Set priority for all PLB3 devices to 0. - * Set PLB3 arbiter to fair mode. - */ - mfsdr(SD0_AMP1, addr); - mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB3_ACR); - mtdcr(PLB3_ACR, addr | 0x80000000); - - /* - * Set priority for all PLB4 devices to 0. - */ - mfsdr(SD0_AMP0, addr); - mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ - mtdcr(PLB4_ACR, addr); - - /* - * Set Nebula PLB4 arbiter to fair mode. - */ - /* Segment0 */ - addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; - addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; - addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; - addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; - mtdcr(PLB0_ACR, addr); - - /* Segment1 */ - addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; - addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; - addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; - addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; - mtdcr(PLB1_ACR, addr); - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /* - * Set up Direct MMIO registers - */ - /* - * PowerPC440EPX PCI Master configuration. - * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0xA0000000-0xDFFFFFFF - * ==> PCI address 0xA0000000-0xDFFFFFFF - * Use byte reversed out routines to handle endianess. - * Make this region non-prefetchable. - */ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ - /* and enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ - /* and enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /* - * Set up Configuration registers - */ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - PCI_VENDOR_ID_ESDGMBH); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, PCI_DEVICE_ID_DU440); - - pci_write_config_word(0, PCI_CLASS_SUB_CODE, PCI_CLASS_BRIDGE_HOST); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - unsigned short temp_short; - - /* - * Write the PowerPC440 EP PCI Configuration regs. - * Enable PowerPC440 EP to be a master on the PCI bus (PMM). - * Enable PowerPC440 EP to act as a PCI memory target (PTM). - */ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ - int last_stage_init(void) { int e, i; diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h index a124a7ee9..37697ec85 100644 --- a/board/esd/du440/du440.h +++ b/board/esd/du440/du440.h @@ -38,6 +38,3 @@ #define PWR_RDY 0x10 #define CPLD_IRQ (32+30) - -#define PCI_VENDOR_ID_ESDGMBH 0x12fe -#define PCI_DEVICE_ID_DU440 0x0444 diff --git a/board/esd/pmc440/config.mk b/board/esd/pmc440/config.mk index 0c4d58282..91e65ec8a 100644 --- a/board/esd/pmc440/config.mk +++ b/board/esd/pmc440/config.mk @@ -20,10 +20,6 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -# -# AMCC 440EPx Reference Platform (Sequoia) board -# - sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 10901b400..d0ff080fa 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -39,6 +39,8 @@ #include <miiphy.h> #endif #include <serial.h> +#include <asm/4xx_pci.h> + #include "fpga.h" #include "pmc440.h" @@ -478,7 +480,7 @@ int checkboard(void) /* * Assign interrupts to PCI devices. Some OSs rely on this. */ -void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB}; @@ -488,64 +490,6 @@ void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) #endif /* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - */ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long addr; - - /* - * Set priority for all PLB3 devices to 0. - * Set PLB3 arbiter to fair mode. - */ - mfsdr(SD0_AMP1, addr); - mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB3_ACR); - mtdcr(PLB3_ACR, addr | 0x80000000); - - /* - * Set priority for all PLB4 devices to 0. - */ - mfsdr(SD0_AMP0, addr); - mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ - mtdcr(PLB4_ACR, addr); - - /* - * Set Nebula PLB4 arbiter to fair mode. - */ - /* Segment0 */ - addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; - addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; - addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; - addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; - mtdcr(PLB0_ACR, addr); - - /* Segment1 */ - addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; - addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; - addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; - addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; - mtdcr(PLB1_ACR, addr); - -#ifdef CONFIG_PCI_PNP - hose->fixup_irq = pmc440_pci_fixup_irq; -#endif - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/* * pci_target_init * * The bootstrap configuration provides default settings for the pci @@ -658,24 +602,16 @@ void pci_target_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /* - * pci_master_init + * Override weak default pci_master_init() */ #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { - unsigned short temp_short; - /* - * Write the PowerPC440 EP PCI Configuration regs. - * Enable PowerPC440 EP to be a master on the PCI bus (PMM). - * Enable PowerPC440 EP to act as a PCI memory target (PTM). + * Only configure the master in monach mode */ - if (is_monarch()) { - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); - } + if (is_monarch()) + __pci_master_init(hose); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c index 92f5d822f..ecbc3c3d1 100644 --- a/board/gdsys/gdppc440etx/gdppc440etx.c +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -29,6 +29,7 @@ #include <ppc4xx.h> #include <asm/processor.h> #include <asm/io.h> +#include <asm/4xx_pci.h> DECLARE_GLOBAL_DATA_PTR; @@ -158,55 +159,13 @@ int checkboard(void) } /* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * + * Override weak pci_pre_init() */ #if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { - unsigned long addr; - - /* - * Set priority for all PLB3 devices to 0. - * Set PLB3 arbiter to fair mode. - */ - mfsdr(SD0_AMP1, addr); - mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB3_ACR); - mtdcr(PLB3_ACR, addr | 0x80000000); - - /* - * Set priority for all PLB4 devices to 0. - */ - mfsdr(SD0_AMP0, addr); - mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ - mtdcr(PLB4_ACR, addr); - - /* - * Set Nebula PLB4 arbiter to fair mode. - */ - /* Segment0 */ - addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; - addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; - addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; - addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; - mtdcr(PLB0_ACR, addr); - - /* Segment1 */ - addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; - addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; - addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; - addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; - mtdcr(PLB1_ACR, addr); + /* First call common code */ + __pci_pre_init(hose); /* enable 66 MHz ext. Clock */ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000); @@ -215,87 +174,3 @@ int pci_pre_init(struct pci_controller *hose) return 1; } #endif /* defined(CONFIG_PCI) */ - -/* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /* - * Set up Direct MMIO registers - */ - - /* - * PowerPC440 EP PCI Master configuration. - * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0xA0000000-0xDFFFFFFF - * ==> PCI address 0xA0000000-0xDFFFFFFF - * Use byte reversed out routines to handle endianess. - * Make this region non-prefetchable. - */ - out32r(PCIL0_PMM0MA, 0x00000000); /* disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); - out32r(PCIL0_PMM0PCIHA, 0x00000000); - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* disabled b4 setting */ - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); - out32r(PCIL0_PMM1PCIHA, 0x00000000); - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); - out32r(PCIL0_PTM1LA, 0); - out32r(PCIL0_PTM2MS, 0); - out32r(PCIL0_PTM2LA, 0); - - /* - * Set up Configuration registers - */ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/* - * pci_master_init - * - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - unsigned short temp_short; - - /* - * Write the PowerPC440 EP PCI Configuration regs. - * Enable PowerPC440 EP to be a master on the PCI bus (PMM). - * Enable PowerPC440 EP to act as a PCI memory target (PTM). - */ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c index 49d245135..23a10c41f 100644 --- a/board/gdsys/intip/intip.c +++ b/board/gdsys/intip/intip.c @@ -141,43 +141,6 @@ int checkboard(void) return 0; } -/* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /* - * Disable everything - */ - out_le32((void *)PCIL0_PIM0SA, 0); /* disable */ - out_le32((void *)PCIL0_PIM1SA, 0); /* disable */ - out_le32((void *)PCIL0_PIM2SA, 0); /* disable */ - out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */ - - /* - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 - * strapping options to not support sizes such as 128/256 MB. - */ - out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out_le32((void *)PCIL0_PIM0LAH, 0); - out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); - out_le32((void *)PCIL0_BAR0, 0); - - /* - * Program the board's subsystem id/vendor id - */ - out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - - out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - int board_early_init_r(void) { /* diff --git a/board/korat/korat.c b/board/korat/korat.c index b0e6a56a6..f942052bd 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -35,6 +35,7 @@ #include <asm/io.h> #include <asm/ppc4xx-uic.h> #include <asm/processor.h> +#include <asm/4xx_pci.h> DECLARE_GLOBAL_DATA_PTR; @@ -594,71 +595,13 @@ int checkboard(void) /* * Assign interrupts to PCI devices. */ -void korat_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2); } #endif /* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - */ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long addr; - - /* - * Set priority for all PLB3 devices to 0. - * Set PLB3 arbiter to fair mode. - */ - mfsdr(SD0_AMP1, addr); - mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB3_ACR); - mtdcr(PLB3_ACR, addr | 0x80000000); - - /* - * Set priority for all PLB4 devices to 0. - */ - mfsdr(SD0_AMP0, addr); - mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ - mtdcr(PLB4_ACR, addr); - - /* - * Set Nebula PLB4 arbiter to fair mode. - */ - /* Segment0 */ - addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; - addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; - addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; - addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; - mtdcr(PLB0_ACR, addr); - - /* Segment1 */ - addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; - addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; - addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; - addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; - mtdcr(PLB1_ACR, addr); - -#if defined(CONFIG_PCI_PNP) - hose->fixup_irq = korat_pci_fixup_irq; -#endif - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/* * pci_target_init * * The bootstrap configuration provides default settings for the pci @@ -668,60 +611,8 @@ int pci_pre_init(struct pci_controller *hose) #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { - /* - * Set up Direct MMIO registers - */ - /* - * PowerPC440EPX PCI Master configuration. - * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0x80000000-0xBFFFFFFF - * ==> PCI address 0x80000000-0xBFFFFFFF - * Use byte reversed out routines to handle endianess. - * Make this region non-prefetchable. - */ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, - CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ - /* and enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ - /* - disabled b4 setting */ - out32r(PCIL0_PMM1LA, - CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 Local Address */ - out32r(PCIL0_PMM1PCILA, - CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ - /* and enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /* - * Set up Configuration registers - */ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + /* First do 440EP(x) common setup */ + __pci_target_init(hose); /* * Set up Configuration registers for on-board NEC uPD720101 USB @@ -731,23 +622,6 @@ void pci_target_init(struct pci_controller *hose) } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - unsigned short temp_short; - - /* - * Write the PowerPC440 EP PCI Configuration regs. - * Enable PowerPC440 EP to be a master on the PCI bus (PMM). - * Enable PowerPC440 EP to act as a PCI memory target (PTM). - */ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -} -#endif - #if defined(CONFIG_POST) /* * Returns 1 if keys pressed to start the power-on long-running tests diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 09ba2b933..415e036c0 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -275,143 +275,6 @@ int checkboard(void) return (0); } -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long addr; - - /*-------------------------------------------------------------------------+ - | Set priority for all PLB3 devices to 0. - | Set PLB3 arbiter to fair mode. - +-------------------------------------------------------------------------*/ - mfsdr(SD0_AMP1, addr); - mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB3_ACR); - mtdcr(PLB3_ACR, addr | 0x80000000); - - /*-------------------------------------------------------------------------+ - | Set priority for all PLB4 devices to 0. - +-------------------------------------------------------------------------*/ - mfsdr(SD0_AMP0, addr); - mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ - mtdcr(PLB4_ACR, addr); - - /*-------------------------------------------------------------------------+ - | Set Nebula PLB4 arbiter to fair mode. - +-------------------------------------------------------------------------*/ - /* Segment0 */ - addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; - addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; - addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; - addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; - mtdcr(PLB0_ACR, addr); - - /* Segment1 */ - addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; - addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; - addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; - addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; - mtdcr(PLB1_ACR, addr); - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Set up Direct MMIO registers - *--------------------------------------------------------------------------*/ - /*--------------------------------------------------------------------------+ - | PowerPC440EPX PCI Master configuration. - | Map one 1Gig range of PLB/processor addresses to PCI memory space. - | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF - | Use byte reversed out routines to handle endianess. - | Make this region non-prefetchable. - +--------------------------------------------------------------------------*/ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /*--------------------------------------------------------------------------+ - * Set up Configuration registers - *--------------------------------------------------------------------------*/ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/************************************************************************* - * pci_master_init - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - unsigned short temp_short; - - /*--------------------------------------------------------------------------+ - | Write the PowerPC440 EP PCI Configuration regs. - | Enable PowerPC440 EP to be a master on the PCI bus (PMM). - | Enable PowerPC440 EP to act as a PCI memory target (PTM). - +--------------------------------------------------------------------------*/ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ - void hw_watchdog_reset(void) { int val; diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 7ffc26202..861564564 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -22,6 +22,8 @@ #include <asm/processor.h> #include <ppc440.h> #include <asm/io.h> +#include <asm/4xx_pci.h> + #include "../common/nm.h" DECLARE_GLOBAL_DATA_PTR; @@ -377,88 +379,14 @@ int pci_pre_init(struct pci_controller *hose) } /* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - */ -void pci_target_init(struct pci_controller *hose) -{ - if (!board_with_pci()) { return; } - /* - * Set up Direct MMIO registers - * - * PowerPC440EPX PCI Master configuration. - * Map one 1Gig range of PLB/processor addresses to PCI memory space. - * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address - * 0xA0000000-0xDFFFFFFF - * Use byte reversed out routines to handle endianess. - * Make this region non-prefetchable. - */ - /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM0MA, 0x00000000); - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - /* 512M + No prefetching, and enable region */ - out32r(PCIL0_PMM0MA, 0xE0000001); - - /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM1MA, 0x00000000); - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - /* 512M + No prefetching, and enable region */ - out32r(PCIL0_PMM1MA, 0xE0000001); - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /* - * Set up Configuration registers - */ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); -} - -/* - * pci_master_init - * + * Override weak default pci_master_init() */ void pci_master_init(struct pci_controller *hose) { - unsigned short temp_short; - if (!board_with_pci()) { return; } + if (!board_with_pci()) + return; - /*--------------------------------------------------------------- - * Write the PowerPC440 EP PCI Configuration regs. - * Enable PowerPC440 EP to be a master on the PCI bus (PMM). - * Enable PowerPC440 EP to act as a PCI memory target (PTM). - *--------------------------------------------------------------*/ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); + __pci_master_init(hose); } #endif /* defined(CONFIG_PCI) */ diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 2155711d6..ce1e61667 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -551,143 +551,6 @@ phys_size_t initdram (int board_type) } /************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long addr; - - /*-------------------------------------------------------------------------+ - | Set priority for all PLB3 devices to 0. - | Set PLB3 arbiter to fair mode. - +-------------------------------------------------------------------------*/ - mfsdr(SD0_AMP1, addr); - mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB3_ACR); - mtdcr(PLB3_ACR, addr | 0x80000000); - - /*-------------------------------------------------------------------------+ - | Set priority for all PLB4 devices to 0. - +-------------------------------------------------------------------------*/ - mfsdr(SD0_AMP0, addr); - mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ - mtdcr(PLB4_ACR, addr); - - /*-------------------------------------------------------------------------+ - | Set Nebula PLB4 arbiter to fair mode. - +-------------------------------------------------------------------------*/ - /* Segment0 */ - addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; - addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; - addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; - addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; - mtdcr(PLB0_ACR, addr); - - /* Segment1 */ - addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; - addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; - addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; - addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; - mtdcr(PLB1_ACR, addr); - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Set up Direct MMIO registers - *--------------------------------------------------------------------------*/ - /*--------------------------------------------------------------------------+ - | PowerPC440 EP PCI Master configuration. - | Map one 1Gig range of PLB/processor addresses to PCI memory space. - | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF - | Use byte reversed out routines to handle endianess. - | Make this region non-prefetchable. - +--------------------------------------------------------------------------*/ - out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ - - /*--------------------------------------------------------------------------+ - * Set up Configuration registers - *--------------------------------------------------------------------------*/ - - /* Program the board's subsystem id/vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CONFIG_SYS_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); - - /* Configure command register as bus master */ - pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); - - /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); - - /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); - - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/************************************************************************* - * pci_master_init - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) -void pci_master_init(struct pci_controller *hose) -{ - unsigned short temp_short; - - /*--------------------------------------------------------------------------+ - | Write the PowerPC440 EP PCI Configuration regs. - | Enable PowerPC440 EP to be a master on the PCI bus (PMM). - | Enable PowerPC440 EP to act as a PCI memory target (PTM). - +--------------------------------------------------------------------------*/ - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ - -/************************************************************************* * hw_watchdog_reset * * This routine is called to reset (keep alive) the watchdog timer diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index e9e2bf3e0..66153279f 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -29,6 +29,7 @@ #include <ppc4xx_enet.h> #include <miiphy.h> #include <asm/processor.h> +#include <asm/4xx_pci.h> DECLARE_GLOBAL_DATA_PTR; @@ -144,78 +145,20 @@ int checkboard (void) return (0); } -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ #if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller * hose ) +/* + * Override weak pci_pre_init() + */ +int pci_pre_init(struct pci_controller *hose) { - unsigned long strap; - - /*--------------------------------------------------------------------------+ - * The ocotea board is always configured as the host & requires the - * PCI arbiter to be enabled. - *--------------------------------------------------------------------------*/ - mfsdr(SDR0_SDSTP1, strap); - if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ - printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); + if (__pci_pre_init(hose) == 0) return 0; - } /* FPGA Init */ - alpr_fpga_init (); + alpr_fpga_init(); return 1; } -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0SA, 0 ); /* disable */ - out32r( PCIL0_PIM1SA, 0 ); /* disable */ - out32r( PCIL0_PIM2SA, 0 ); /* disable */ - out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIL0_PIM0LAH, 0 ); - out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIL0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - - out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* * Override weak is_pci_host() @@ -232,8 +175,6 @@ void pci_target_init(struct pci_controller * hose ) * * ************************************************************************/ -#if defined(CONFIG_PCI) - static void wait_for_pci_ready(void) { /* diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index e07400794..020f66dd8 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -165,76 +165,6 @@ int misc_init_r (void) } /************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long strap; - - /*--------------------------------------------------------------------------+ - * The P3P440 board is always configured as the host & requires the - * PCI arbiter to be disabled because it's an PMC module. - *--------------------------------------------------------------------------*/ - strap = mfdcr(CPC0_STRP1); - if (strap & 0x00100000) { - printf("PCI: CPC0_STRP1[PAE] set.\n"); - return 0; - } - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller *hose) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r(PCIL0_PIM0SA, 0); /* disable */ - out32r(PCIL0_PIM1SA, 0); /* disable */ - out32r(PCIL0_PIM2SA, 0); /* disable */ - out32r(PCIL0_EROMBA, 0); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out32r(PCIL0_PIM0LAH, 0); - out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); - - out32r(PCIL0_BAR0, 0); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - - out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - -/************************************************************************* * Override weak is_pci_host() * * This routine is called to determine if a pci scan should be diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index 574908458..6b910743d 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -300,78 +300,6 @@ long int fixed_sdram (void) } #endif /* !defined(CONFIG_SPD_EEPROM) */ - -/************************************************************************* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - * - ************************************************************************/ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller * hose ) -{ - unsigned long strap; - - /*--------------------------------------------------------------------------+ - * The metrobox is always configured as the host & requires the - * PCI arbiter to be enabled. - *--------------------------------------------------------------------------*/ - mfsdr(SDR0_SDSTP1, strap); - if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ - printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); - return 0; - } - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/************************************************************************* - * pci_target_init - * - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - * - ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) -{ - /*--------------------------------------------------------------------------+ - * Disable everything - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0SA, 0 ); /* disable */ - out32r( PCIL0_PIM1SA, 0 ); /* disable */ - out32r( PCIL0_PIM2SA, 0 ); /* disable */ - out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ - - /*--------------------------------------------------------------------------+ - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - *--------------------------------------------------------------------------*/ - out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIL0_PIM0LAH, 0 ); - out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - - out32r( PCIL0_BAR0, 0 ); - - /*--------------------------------------------------------------------------+ - * Program the board's subsystem id/vendor id - *--------------------------------------------------------------------------*/ - out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - - out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - - /************************************************************************* * board_get_enetaddr * diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c index 0c4cf9463..b4cbb2fce 100644 --- a/board/xes/xpedite1000/xpedite1000.c +++ b/board/xes/xpedite1000/xpedite1000.c @@ -136,6 +136,8 @@ phys_size_t initdram(int board_type) } /* + * Override weak pci_pre_init() + * * This routine is called just prior to registering the hose and gives * the board the opportunity to check things. Returning a value of zero * indicates that things are bad & PCI initialization should be aborted. @@ -144,7 +146,6 @@ phys_size_t initdram(int board_type) * (add regions, override default access routines, etc) or perform * certain pre-initialization actions. */ - #if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose) { @@ -166,38 +167,6 @@ int pci_pre_init(struct pci_controller * hose) } #endif /* defined(CONFIG_PCI) */ -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) -/* - * The bootstrap configuration provides default settings for the pci - * inbound map (PIM). But the bootstrap config choices are limited and - * may not be sufficient for a given board. - */ -void pci_target_init(struct pci_controller * hose) -{ - /* Disable everything */ - out32r(PCIL0_PIM0SA, 0); - out32r(PCIL0_PIM1SA, 0); - out32r(PCIL0_PIM2SA, 0); - out32r(PCIL0_EROMBA, 0); /* disable expansion rom */ - - /* - * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping - * options to not support sizes such as 128/256 MB. - */ - out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out32r(PCIL0_PIM0LAH, 0); - out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); - - out32r(PCIL0_BAR0, 0); - - /* Program the board's subsystem id/vendor id */ - out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - - out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); -} -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ - #if defined(CONFIG_PCI) /* * Override weak is_pci_host() |