29 files changed, 846 insertions, 240 deletions

diff --git a/board/amcc/bluestone/Makefile b/board/amcc/bluestone/Makefile
new file mode 100644
index 000000000..41751c870
--- /dev/null
+++ b/board/amcc/bluestone/Makefile
@@ -0,0 +1,52 @@
+#
+# Copyright (c) 2010, Applied Micro Circuits Corporation
+# Author: Tirumala R Marri <tmarri@apm.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+SOBJS	:= init.o
+
+COBJS   := $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/amcc/bluestone/bluestone.c b/board/amcc/bluestone/bluestone.c
new file mode 100644
index 000000000..fe8929c38
--- /dev/null
+++ b/board/amcc/bluestone/bluestone.c
@@ -0,0 +1,111 @@
+/*
+ * Bluestone board support
+ *
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tirumala R Marri <tmarri@apm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/apm821xx.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx-gpio.h>
+
+int board_early_init_f(void)
+{
+	/*
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC0ER, 0x00000000);	/* disable all */
+	mtdcr(UIC0CR, 0x00000005);	/* ATI & UIC1 crit are critical */
+	mtdcr(UIC0PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC0TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC0VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC0SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC1ER, 0x00000000);	/* disable all */
+	mtdcr(UIC1CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC1PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC1TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC1VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC1SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC2ER, 0x00000000);	/* disable all */
+	mtdcr(UIC2CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC2PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC2TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC2VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC2SR, 0xffffffff);	/* clear all */
+
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+	mtdcr(UIC3ER, 0x00000000);	/* disable all */
+	mtdcr(UIC3CR, 0x00000000);	/* all non-critical */
+	mtdcr(UIC3PR, 0xffffffff);	/* per ref-board manual */
+	mtdcr(UIC3TR, 0x00000000);	/* per ref-board manual */
+	mtdcr(UIC3VR, 0x00000000);	/* int31 highest, base=0x000 */
+	mtdcr(UIC3SR, 0xffffffff);	/* clear all */
+
+	/*
+	 * Configure PFC (Pin Function Control) registers
+	 * UART0: 2 pins
+	 */
+	mtsdr(SDR0_PFC1, 0x0000000);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: Bluestone Evaluation Board");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	u32 sdr0_srst1 = 0;
+
+	/* Setup PLB4-AHB bridge based on the system address map */
+	mtdcr(AHB_TOP, 0x8000004B);
+	mtdcr(AHB_BOT, 0x8000004B);
+
+	/*
+	 * The AHB Bridge core is held in reset after power-on or reset
+	 * so enable it now
+	 */
+	mfsdr(SDR0_SRST1, sdr0_srst1);
+	sdr0_srst1 &= ~SDR0_SRST1_AHB;
+	mtsdr(SDR0_SRST1, sdr0_srst1);
+
+	return 0;
+}
diff --git a/board/amcc/bluestone/config.mk b/board/amcc/bluestone/config.mk
new file mode 100644
index 000000000..e2194e4e0
--- /dev/null
+++ b/board/amcc/bluestone/config.mk
@@ -0,0 +1,40 @@
+#
+# Copyright (c) 2010, Applied Micro Circuits Corporation
+# Author: Tirumala R Marri <tmarri@apm.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Applied Micro APM821XX Evaluation board.
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFA0000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_440=1
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+ifeq ($(dbcr),1)
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
+endif
diff --git a/board/amcc/bluestone/init.S b/board/amcc/bluestone/init.S
new file mode 100644
index 000000000..e969fcfd9
--- /dev/null
+++ b/board/amcc/bluestone/init.S
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tirumala R Marri <tmarri@apm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <config.h>
+#include <asm/mmu.h>
+#include <asm/ppc4xx.h>
+
+/**************************************************************************
+ * TLB TABLE
+ *
+ * This table is used by the cpu boot code to setup the initial tlb
+ * entries. Rather than make broad assumptions in the cpu source tree,
+ * this table lets each board set things up however they like.
+ *
+ *  Pointer to the table is returned in r1
+ *
+ *************************************************************************/
+	.section .bootpg,"ax"
+	.globl tlbtab
+
+tlbtab:
+	tlbtab_start
+
+	/* TLB 0 */
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
+	4, AC_RWX | SA_G)
+
+	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
+			0, AC_RWX | SA_G)
+
+	/* TLB-entry for OCM */
+	tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4,
+			AC_RWX | SA_I)
+
+	/* TLB-entry for Local Configuration registers => peripherals */
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K,
+			CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG)
+	tlbtab_end
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index b26cadb6b..faa3720df 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -34,16 +34,16 @@ extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH ch
 
 DECLARE_GLOBAL_DATA_PTR;
 
-	struct board_bcsr {
-		u8	board_id;
-		u8	cpld_rev;
-		u8	led_user;
-		u8	board_status;
-		u8	reset_ctrl;
-		u8	flash_ctrl;
-		u8	eth_ctrl;
-		u8	usb_ctrl;
-		u8	irq_ctrl;
+struct board_bcsr {
+	u8	board_id;
+	u8	cpld_rev;
+	u8	led_user;
+	u8	board_status;
+	u8	reset_ctrl;
+	u8	flash_ctrl;
+	u8	eth_ctrl;
+	u8	usb_ctrl;
+	u8	irq_ctrl;
 };
 
 #define BOARD_CANYONLANDS_PCIE	1
@@ -195,16 +195,6 @@ int board_early_init_f(void)
 	mtdcr(AHB_TOP, 0x8000004B);
 	mtdcr(AHB_BOT, 0x8000004B);
 
-	if (pvr_460ex()) {
-		/*
-		 * Configure USB-STP pins as alternate and not GPIO
-		 * It seems to be neccessary to configure the STP pins as GPIO
-		 * input at powerup (perhaps while USB reset is asserted). So
-		 * we configure those pins to their "real" function now.
-		 */
-		gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
-		gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
-	}
 #endif
 
 	return 0;
@@ -222,6 +212,15 @@ int usb_board_init(void)
 	val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
 	out_8(&bcsr_data->usb_ctrl, val);
 
+	/*
+	 * Configure USB-STP pins as alternate and not GPIO
+	 * It seems to be neccessary to configure the STP pins as GPIO
+	 * input at powerup (perhaps while USB reset is asserted). So
+	 * we configure those pins to their "real" function now.
+	 */
+	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+
 	return 0;
 }
 
@@ -236,6 +235,10 @@ int usb_board_stop(void)
 	val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
 	out_8(&bcsr_data->usb_ctrl, val);
 
+	/* Reconfigure USB-STP pins as input */
+	gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
+	gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
+
 	return 0;
 }
 
diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c
index f17df60c2..31b079b1c 100644
--- a/board/davedenx/aria/aria.c
+++ b/board/davedenx/aria/aria.c
@@ -119,11 +119,6 @@ int misc_init_r(void)
 		 tmp & 0x000000FF
 	);
 
-#ifdef CONFIG_FSL_DIU_FB
-# if	!(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
-	mpc5121_diu_init();
-# endif
-#endif
 	return 0;
 }
 
diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c
index 394b71f32..35ed938be 100644
--- a/board/freescale/common/fsl_diu_fb.c
+++ b/board/freescale/common/fsl_diu_fb.c
@@ -28,7 +28,7 @@
 #include <malloc.h>
 #include <asm/io.h>
 
-#include "fsl_diu_fb.h"
+#include <fsl_diu_fb.h>
 
 struct fb_videomode {
 	const char *name;	/* optional */
@@ -472,3 +472,42 @@ static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align)
 		buf->offset = 0;
 	return 0;
 }
+
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+#include <stdio_dev.h>
+#include <video_fb.h>
+/*
+ * The Graphic Device
+ */
+static GraphicDevice ctfb;
+
+void *video_hw_init(void)
+{
+	struct fb_info *info;
+
+	if (platform_diu_init(&ctfb.winSizeX, &ctfb.winSizeY) < 0)
+		return NULL;
+
+	/* fill in Graphic device struct */
+	sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz",
+		ctfb.winSizeX, ctfb.winSizeY, 32, 64, 60);
+
+	ctfb.frameAdrs = (unsigned int)fsl_fb_open(&info);
+	ctfb.plnSizeX = ctfb.winSizeX;
+	ctfb.plnSizeY = ctfb.winSizeY;
+
+	ctfb.gdfBytesPP = 4;
+	ctfb.gdfIndex = GDF_32BIT_X888RGB;
+
+	ctfb.isaBase = 0;
+	ctfb.pciBase = 0;
+	ctfb.memSize = info->screen_size;
+
+	/* Cursor Start Address */
+	ctfb.dprBase = 0;
+	ctfb.vprBase = 0;
+	ctfb.cprBase = 0;
+
+	return &ctfb;
+}
+#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
diff --git a/board/freescale/common/fsl_diu_fb.h b/board/freescale/common/fsl_diu_fb.h
deleted file mode 100644
index 3a5fc9ff8..000000000
--- a/board/freescale/common/fsl_diu_fb.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2007 Freescale Semiconductor, Inc.
- * York Sun <yorksun@freescale.com>
- *
- * FSL DIU Framebuffer driver
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-struct fb_var_screeninfo {
-	unsigned int xres;		/* visible resolution		*/
-	unsigned int yres;
-
-	unsigned int bits_per_pixel;	/* guess what			*/
-
-	/* Timing: All values in pixclocks, except pixclock (of course) */
-	unsigned int pixclock;		/* pixel clock in ps (pico seconds) */
-	unsigned int left_margin;	/* time from sync to picture	*/
-	unsigned int right_margin;	/* time from picture to sync	*/
-	unsigned int upper_margin;	/* time from sync to picture	*/
-	unsigned int lower_margin;
-	unsigned int hsync_len;		/* length of horizontal sync	*/
-	unsigned int vsync_len;		/* length of vertical sync	*/
-	unsigned int sync;		/* see FB_SYNC_*		*/
-	unsigned int vmode;		/* see FB_VMODE_*		*/
-	unsigned int rotate;		/* angle we rotate counter clockwise */
-};
-
-struct fb_info {
-	struct fb_var_screeninfo var;	/* Current var */
-	unsigned long smem_start;	/* Start of frame buffer mem */
-					/* (physical address) */
-	unsigned int smem_len;		/* Length of frame buffer mem */
-	unsigned int type;		/* see FB_TYPE_*		*/
-	unsigned int line_length;	/* length of a line in bytes    */
-
-	char *screen_base;
-	unsigned long screen_size;
-};
-
-
-extern char *fsl_fb_open(struct fb_info **info);
-int fsl_diu_init(int xres, unsigned int pixel_format, int gamma_fix);
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
index 960c8eda7..81e53e734 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -26,17 +26,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/io.h>
-
-#ifdef CONFIG_FSL_DIU_FB
-
-#include "../common/fsl_diu_fb.h"
-
-#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
-#include <stdio_dev.h>
-#include <video_fb.h>
-#endif
-
-static int xres, yres;
+#include <fsl_diu_fb.h>
 
 void diu_set_pixel_clock(unsigned int pixclock)
 {
@@ -59,7 +49,7 @@ void diu_set_pixel_clock(unsigned int pixclock)
 	debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr);
 }
 
-int mpc8610hpcd_diu_init(void)
+int platform_diu_init(unsigned int *xres, unsigned int *yres)
 {
 	char *monitor_port;
 	int gamma_fix;
@@ -73,8 +63,8 @@ int mpc8610hpcd_diu_init(void)
 
 	monitor_port = getenv("monitor");
 	if (!strncmp(monitor_port, "0", 1)) {	/* 0 - DVI */
-		xres = 1280;
-		yres = 1024;
+		*xres = 1280;
+		*yres = 1024;
 		if (pixis_arch == 0x01)
 			pixel_format = 0x88882317;
 		else
@@ -83,68 +73,26 @@ int mpc8610hpcd_diu_init(void)
 		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08);
 
 	} else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
-		xres = 1024;
-		yres = 768;
+		*xres = 1024;
+		*yres = 768;
 		pixel_format = 0x88883316;
 		gamma_fix = 0;
 		out_8(pixis_base + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10);
 
 	} else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */
-		xres = 1280;
-		yres = 1024;
+		*xres = 1280;
+		*yres = 1024;
 		pixel_format = 0x88883316;
 		gamma_fix = 1;
 		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xe7);
 
 	} else {	/* DVI */
-		xres = 1280;
-		yres = 1024;
+		*xres = 1280;
+		*yres = 1024;
 		pixel_format = 0x88882317;
 		gamma_fix = 0;
 		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08);
 	}
 
-	return fsl_diu_init(xres, pixel_format, gamma_fix);
-}
-
-#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
-
-/*
- * The Graphic Device
- */
-static GraphicDevice ctfb;
-
-void *video_hw_init(void)
-{
-	struct fb_info *info;
-
-	if (mpc8610hpcd_diu_init() < 0)
-		return NULL;
-
-	/* fill in Graphic device struct */
-	sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz", xres, yres, 32, 64, 60);
-
-	ctfb.frameAdrs = (unsigned int)fsl_fb_open(&info);
-	ctfb.winSizeX = xres;
-	ctfb.winSizeY = yres;
-	ctfb.plnSizeX = ctfb.winSizeX;
-	ctfb.plnSizeY = ctfb.winSizeY;
-
-	ctfb.gdfBytesPP = 4;
-	ctfb.gdfIndex = GDF_32BIT_X888RGB;
-
-	ctfb.isaBase = 0;
-	ctfb.pciBase = 0;
-	ctfb.memSize = info->screen_size;
-
-	/* Cursor Start Address */
-	ctfb.dprBase = 0;
-	ctfb.vprBase = 0;
-	ctfb.cprBase = 0;
-
-	return &ctfb;
+	return fsl_diu_init(*xres, pixel_format, gamma_fix);
 }
-
-#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
-
-#endif /* CONFIG_FSL_DIU_FB */
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
index 8ede2d605..678eb2ae0 100644
--- a/board/freescale/p1022ds/Makefile
+++ b/board/freescale/p1022ds/Makefile
@@ -16,6 +16,8 @@ COBJS-y	+= ddr.o
 COBJS-y	+= law.o
 COBJS-y	+= tlb.o
 
+COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
+
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c
new file mode 100644
index 000000000..12b40a01e
--- /dev/null
+++ b/board/freescale/p1022ds/diu.c
@@ -0,0 +1,304 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ * Authors: Timur Tabi <timur@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <stdio_dev.h>
+#include <video_fb.h>
+#include "../common/ngpixis.h"
+#include <fsl_diu_fb.h>
+
+/* The CTL register is called 'csr' in the ngpixis_t structure */
+#define PX_CTL_ALTACC		0x80
+
+#define PX_BRDCFG0_ELBC_SPI_MASK	0xc0
+#define PX_BRDCFG0_ELBC_SPI_ELBC	0x00
+#define PX_BRDCFG0_ELBC_SPI_NULL	0xc0
+#define PX_BRDCFG0_ELBC_DIU		0x02
+
+#define PX_BRDCFG1_DVIEN	0x80
+#define PX_BRDCFG1_DFPEN	0x40
+#define PX_BRDCFG1_BACKLIGHT	0x20
+
+#define PMUXCR_ELBCDIU_MASK	0xc0000000
+#define PMUXCR_ELBCDIU_NOR16	0x80000000
+
+/*
+ * DIU Area Descriptor
+ *
+ * Note that we need to byte-swap the value before it's written to the AD
+ * register.  So even though the registers don't look like they're in the same
+ * bit positions as they are on the MPC8610, the same value is written to the
+ * AD register on the MPC8610 and on the P1022.
+ */
+#define AD_BYTE_F		0x10000000
+#define AD_ALPHA_C_SHIFT	25
+#define AD_BLUE_C_SHIFT		23
+#define AD_GREEN_C_SHIFT	21
+#define AD_RED_C_SHIFT		19
+#define AD_PIXEL_S_SHIFT	16
+#define AD_COMP_3_SHIFT		12
+#define AD_COMP_2_SHIFT		8
+#define AD_COMP_1_SHIFT		4
+#define AD_COMP_0_SHIFT		0
+
+/*
+ * Variables used by the DIU/LBC switching code.  It's safe to makes these
+ * global, because the DIU requires DDR, so we'll only run this code after
+ * relocation.
+ */
+static u8 px_brdcfg0;
+static u32 pmuxcr;
+static void *lbc_lcs0_ba;
+static void *lbc_lcs1_ba;
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	unsigned long speed_ccb, temp;
+	u32 pixval;
+
+	speed_ccb = get_bus_freq(0);
+	temp = 1000000000 / pixclock;
+	temp *= 1000;
+	pixval = speed_ccb / temp;
+	debug("DIU pixval = %lu\n", pixval);
+
+	/* Modify PXCLK in GUTS CLKDVDR */
+	temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
+	out_be32(&gur->clkdvdr, temp);			/* turn off clock */
+	out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
+}
+
+int platform_diu_init(unsigned int *xres, unsigned int *yres)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	char *monitor_port;
+	u32 pixel_format;
+	u8 temp;
+
+	/* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
+	lbc_lcs0_ba = (void *)(get_lbc_br(0) & get_lbc_or(0) & 0xFFFF8000);
+	lbc_lcs1_ba = (void *)(get_lbc_br(1) & get_lbc_or(1) & 0xFFFF8000);
+
+	pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
+		(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
+		(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
+		(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
+		(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
+
+	temp = in_8(&pixis->brdcfg1);
+
+	monitor_port = getenv("monitor");
+	if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */
+		*xres = 1024;
+		*yres = 768;
+		/* Enable the DFP port, disable the DVI and the backlight */
+		temp &= ~(PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT);
+		temp |= PX_BRDCFG1_DFPEN;
+	} else {	/* DVI */
+		*xres = 1280;
+		*yres = 1024;
+		/* Enable the DVI port, disable the DFP and the backlight */
+		temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
+		temp |= PX_BRDCFG1_DVIEN;
+	}
+
+	out_8(&pixis->brdcfg1, temp);
+
+	/*
+	 * Enable PIXIS indirect access mode.  This is a hack that allows us to
+	 * access PIXIS registers even when the LBC pins have been muxed to the
+	 * DIU.
+	 */
+	setbits_8(&pixis->csr, PX_CTL_ALTACC);
+
+	/*
+	 * Route the LAD pins to the DIU.  This will disable access to the eLBC,
+	 * which means we won't be able to read/write any NOR flash addresses!
+	 */
+	out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
+	px_brdcfg0 = in_8(lbc_lcs1_ba);
+	out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
+
+	/* Setting PMUXCR to switch to DVI from ELBC */
+	clrsetbits_be32(&gur->pmuxcr,
+		PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_NOR16);
+	pmuxcr = in_be32(&gur->pmuxcr);
+
+	return fsl_diu_init(*xres, pixel_format, 0);
+}
+
+#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+
+/*
+ * set_mux_to_lbc - disable the DIU so that we can read/write to elbc
+ *
+ * On the Freescale P1022, the DIU video signal and the LBC address/data lines
+ * share the same pins, which means that when the DIU is active (e.g. the
+ * console is on the DVI display), NOR flash cannot be accessed.  So we use the
+ * weak accessor feature of the CFI flash code to temporarily switch the pin
+ * mux from DIU to LBC whenever we want to read or write flash.  This has a
+ * significant performance penalty, but it's the only way to make it work.
+ *
+ * There are two muxes: one on the chip, and one on the board. The chip mux
+ * controls whether the pins are used for the DIU or the LBC, and it is
+ * set via PMUXCR.  The board mux controls whether those signals go to
+ * the video connector or the NOR flash chips, and it is set via the ngPIXIS.
+ */
+static int set_mux_to_lbc(void)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Switch the muxes only if they're currently set to DIU mode */
+	if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) ==
+	    PMUXCR_ELBCDIU_NOR16) {
+		/*
+		 * In DIU mode, the PIXIS can only be accessed indirectly
+		 * since we can't read/write the LBC directly.
+		 */
+
+		/* Set the board mux to LBC.  This will disable the display. */
+		out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
+		px_brdcfg0 = in_8(lbc_lcs1_ba);
+		out_8(lbc_lcs1_ba, (px_brdcfg0 & ~(PX_BRDCFG0_ELBC_SPI_MASK
+			| PX_BRDCFG0_ELBC_DIU)) | PX_BRDCFG0_ELBC_SPI_ELBC);
+
+		/* Disable indirect PIXIS mode */
+		out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
+		clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC);
+
+		/* Set the chip mux to LBC mode, so that writes go to flash. */
+		out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |
+			 PMUXCR_ELBCDIU_NOR16);
+		in_be32(&gur->pmuxcr);
+
+		return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * set_mux_to_diu - re-enable the DIU muxing
+ *
+ * This function restores the chip and board muxing to point to the DIU.
+ */
+static void set_mux_to_diu(void)
+{
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Enable indirect PIXIS mode */
+	setbits_8(&pixis->csr, PX_CTL_ALTACC);
+
+	/* Set the board mux to DIU.  This will enable the display. */
+	out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
+	out_8(lbc_lcs1_ba, px_brdcfg0);
+	in_8(lbc_lcs1_ba);
+
+	/* Set the chip mux to DIU mode. */
+	out_be32(&gur->pmuxcr, pmuxcr);
+	in_be32(&gur->pmuxcr);
+}
+
+void flash_write8(u8 value, void *addr)
+{
+	int sw = set_mux_to_lbc();
+
+	__raw_writeb(value, addr);
+	if (sw)
+		set_mux_to_diu();
+}
+
+void flash_write16(u16 value, void *addr)
+{
+	int sw = set_mux_to_lbc();
+
+	__raw_writew(value, addr);
+	if (sw)
+		set_mux_to_diu();
+}
+
+void flash_write32(u32 value, void *addr)
+{
+	int sw = set_mux_to_lbc();
+
+	__raw_writel(value, addr);
+	if (sw)
+		set_mux_to_diu();
+}
+
+void flash_write64(u64 value, void *addr)
+{
+	int sw = set_mux_to_lbc();
+
+	/* There is no __raw_writeq(), so do the write manually */
+	*(volatile u64 *)addr = value;
+	if (sw)
+		set_mux_to_diu();
+}
+
+u8 flash_read8(void *addr)
+{
+	u8 ret;
+
+	int sw = set_mux_to_lbc();
+
+	ret = __raw_readb(addr);
+	if (sw)
+		set_mux_to_diu();
+
+	return ret;
+}
+
+u16 flash_read16(void *addr)
+{
+	u16 ret;
+
+	int sw = set_mux_to_lbc();
+
+	ret = __raw_readw(addr);
+	if (sw)
+		set_mux_to_diu();
+
+	return ret;
+}
+
+u32 flash_read32(void *addr)
+{
+	u32 ret;
+
+	int sw = set_mux_to_lbc();
+
+	ret = __raw_readl(addr);
+	if (sw)
+		set_mux_to_diu();
+
+	return ret;
+}
+
+u64 flash_read64(void *addr)
+{
+	u64 ret;
+
+	int sw = set_mux_to_lbc();
+
+	/* There is no __raw_readq(), so do the read manually */
+	ret = *(volatile u64 *)addr;
+	if (sw)
+		set_mux_to_diu();
+
+	return ret;
+}
+
+#endif
diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c
index 0e26b890b..5231c7a5c 100644
--- a/board/lwmon5/kbd.c
+++ b/board/lwmon5/kbd.c
@@ -45,6 +45,10 @@ static int compare_magic (uchar *kbd_data, uchar *str);
 /*--------------------- Local macros and constants --------------------*/
 #define	_NOT_USED_	0xFFFFFFFF
 
+/*------------------------- dspic io expander -----------------------*/
+#define DSPIC_PON_STATUS_REG	0x80A
+#define DSPIC_PON_INV_STATUS_REG 0x80C
+#define DSPIC_PON_KEY_REG	0x810
 /*------------------------- Keyboard controller -----------------------*/
 /* command codes */
 #define	KEYBD_CMD_READ_KEYS	0x01
@@ -75,6 +79,7 @@ static int compare_magic (uchar *kbd_data, uchar *str);
 /* maximum number of "magic" key codes that can be assigned */
 
 static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
+static uchar dspic_addr = CONFIG_SYS_I2C_DSPIC_IO_ADDR;
 
 static uchar *key_match (uchar *);
 
@@ -167,6 +172,23 @@ static void kbd_init (void)
 	}
 }
 
+
+/* Read a register from the dsPIC. */
+int _dspic_read(ushort reg, ushort *data)
+{
+	uchar buf[sizeof(*data)];
+	int rval;
+
+	if (i2c_read(dspic_addr, reg, 2, buf, 2))
+		return -1;
+
+	rval = i2c_read(dspic_addr, reg, sizeof(reg), buf, sizeof(*data));
+	*data = (buf[0] << 8) | buf[1];
+
+	return rval;
+}
+
+
 /***********************************************************************
 F* Function:     int misc_init_r (void) P*A*Z*
  *
@@ -197,6 +219,7 @@ int misc_init_r_kbd (void)
 	uchar kbd_init_status = gd->kbd_status >> 8;
 	uchar kbd_status = gd->kbd_status;
 	uchar val;
+	ushort data, inv_data;
 	char *str;
 	int i;
 
@@ -231,9 +254,31 @@ int misc_init_r_kbd (void)
 	i2c_write (kbd_addr, 0, 0, &val, 1);
 	i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
 
+	/* read out start key from bse01 received via can */
+	_dspic_read(DSPIC_PON_STATUS_REG, &data);
+	/* check highbyte from status register */
+	if (data > 0xFF) {
+		_dspic_read(DSPIC_PON_INV_STATUS_REG, &inv_data);
+
+		/* check inverse data */
+		if ((data+inv_data) == 0xFFFF) {
+			/* don't overwrite local key */
+			if (kbd_data[1] == 0) {
+				/* read key value */
+				_dspic_read(DSPIC_PON_KEY_REG, &data);
+				str = (char *)&data;
+				/* swap bytes */
+				kbd_data[1] = str[1];
+				kbd_data[2] = str[0];
+				printf("CAN received startkey: 0x%X\n", data);
+			}
+		}
+	}
+
 	for (i = 0; i < KEYBD_DATALEN; ++i) {
 		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
 	}
+
 	setenv ("keybd", keybd_env);
 
 	str = strdup ((char *)key_match (kbd_data));	/* decode keys */
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index 9622b70d2..dd275bf77 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2010
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * This program is free software; you can redistribute it and/or
@@ -24,10 +24,13 @@
 #include <asm/processor.h>
 #include <asm/ppc4xx-gpio.h>
 #include <asm/io.h>
+#include <post.h>
+#include <flash.h>
+#include <mtd/cfi_flash.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
 
 ulong flash_get_size(ulong base, int banknum);
 int misc_init_r_kbd(void);
@@ -97,16 +100,18 @@ int board_early_init_f(void)
 	gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
 
 #if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
-	gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1);
+	/* enable the LSB transmitter */
+	gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
+	/* enable the CAN transmitter */
+	gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
 
 	reg = 0; /* reuse as counter */
 	out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
 		in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
 			& ~CONFIG_SYS_DSPIC_TEST_MASK);
-	while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
+	while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
 		udelay(1000);
 	}
-	gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0);
 	if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
 		/* set "boot error" flag */
 		out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
@@ -135,9 +140,61 @@ int board_early_init_f(void)
 	return 0;
 }
 
-/*---------------------------------------------------------------------------+
-  | misc_init_r.
-  +---------------------------------------------------------------------------*/
+/*
+ * Override weak default with board specific version
+ */
+phys_addr_t cfi_flash_bank_addr(int bank)
+{
+	return lwmon5_cfi_flash_bank_addr[bank];
+}
+
+/*
+ * Override the weak default mapping function with a board specific one
+ */
+u32 flash_get_bank_size(int cs, int idx)
+{
+	return flash_info[idx].size;
+}
+
+int board_early_init_r(void)
+{
+	u32 val0, val1;
+
+	/*
+	 * lwmon5 is manufactured in 2 different board versions:
+	 * The lwmon5a board has 64MiB NOR flash instead of the
+	 * 128MiB of the original lwmon5. Unfortunately the CFI driver
+	 * will report 2 banks of 64MiB even for the smaller flash
+	 * chip, since the bank is mirrored. To fix this, we bring
+	 * one bank into CFI query mode and read its response. This
+	 * enables us to detect the real number of flash devices/
+	 * banks which will be used later on by the common CFI driver.
+	 */
+
+	/* Put bank 0 into CFI command mode and read */
+	out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
+	val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
+	val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
+
+	/* Reset flash again out of query mode */
+	out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
+
+	/* When not identical, we have 2 different flash devices/banks */
+	if (val0 != val1)
+		return 0;
+
+	/*
+	 * Now we're sure that we're running on a LWMON5a board with
+	 * only 64MiB NOR flash in one bank:
+	 *
+	 * Set flash base address and bank count for CFI driver probing.
+	 */
+	cfi_flash_num_flash_banks = 1;
+	lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
+
+	return 0;
+}
+
 int misc_init_r(void)
 {
 	u32 pbcr;
@@ -145,7 +202,7 @@ int misc_init_r(void)
 	u32 reg;
 	unsigned long usb2d0cr = 0;
 	unsigned long usb2phy0cr, usb2h0cr = 0;
-	unsigned long sdr0_pfc1;
+	unsigned long sdr0_pfc1, sdr0_srst;
 
 	/*
 	 * FLASH stuff...
@@ -158,32 +215,7 @@ int misc_init_r(void)
 	gd->bd->bi_flashoffset = 0;
 
 	mfebc(PB0CR, pbcr);
-	switch (gd->bd->bi_flashsize) {
-	case 1 << 20:
-		size_val = 0;
-		break;
-	case 2 << 20:
-		size_val = 1;
-		break;
-	case 4 << 20:
-		size_val = 2;
-		break;
-	case 8 << 20:
-		size_val = 3;
-		break;
-	case 16 << 20:
-		size_val = 4;
-		break;
-	case 32 << 20:
-		size_val = 5;
-		break;
-	case 64 << 20:
-		size_val = 6;
-		break;
-	case 128 << 20:
-		size_val = 7;
-		break;
-	}
+	size_val = ffs(gd->bd->bi_flashsize) - 21;
 	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 	mtebc(PB0CR, pbcr);
 
@@ -193,53 +225,92 @@ int misc_init_r(void)
 	flash_get_size(gd->bd->bi_flashstart, 0);
 
 	/* Monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CONFIG_SYS_MONITOR_LEN,
-			    0xffffffff,
-			    &flash_info[1]);
+	flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
+		      &flash_info[cfi_flash_num_flash_banks - 1]);
 
 	/* Env protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    CONFIG_ENV_ADDR_REDUND,
-			    CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
-			    &flash_info[1]);
+	flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+		      CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
+		      &flash_info[cfi_flash_num_flash_banks - 1]);
 
 	/*
 	 * USB suff...
 	 */
+
+	/* Reset USB */
+	/* Reset of USB2PHY0 must be active at least 10 us  */
+	mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
+	udelay(2000);
+
+	mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
+	      SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
+	      SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
+	udelay(2000);
+
+	/* Errata CHIP_6 */
+
+	/* 1. Set internal PHY configuration */
 	/* SDR Setting */
 	mfsdr(SDR0_PFC1, sdr0_pfc1);
 	mfsdr(SDR0_USB0, usb2d0cr);
 	mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 	mfsdr(SDR0_USB2H0CR, usb2h0cr);
 
-	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
-	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
-	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
-	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
-	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
-	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/
-	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
-	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
-	usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
-	usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
+	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
+	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/
+	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
+	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/
+	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
+	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_DVBUS_PUREN;		/*1*/
+	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
+	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/
+	usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
+	usb2phy0cr = usb2phy0cr |  SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/
 
-	/* An 8-bit/60MHz interface is the only possible alternative
-	   when connecting the Device to the PHY */
-	usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
-	usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
+	/*
+	 * An 8-bit/60MHz interface is the only possible alternative
+	 * when connecting the Device to the PHY
+	 */
+	usb2h0cr   = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
+	usb2h0cr   = usb2h0cr |  SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/
 
 	mtsdr(SDR0_PFC1, sdr0_pfc1);
 	mtsdr(SDR0_USB0, usb2d0cr);
 	mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 	mtsdr(SDR0_USB2H0CR, usb2h0cr);
 
+	/* 2. De-assert internal PHY reset */
+	mfsdr(SDR0_SRST1, sdr0_srst);
+	sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
+	mtsdr(SDR0_SRST1, sdr0_srst);
+
+	/* 3. Wait for more than 1 ms */
+	udelay(2000);
+
+	/* 4. De-assert USB 2.0 Host main reset */
+	mfsdr(SDR0_SRST0, sdr0_srst);
+	sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
+	mtsdr(SDR0_SRST0, sdr0_srst);
+	udelay(1000);
+
+	/* 5. De-assert reset of OPB2 cores */
+	mfsdr(SDR0_SRST1, sdr0_srst);
+	sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
+	sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
+	sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
+	mtsdr(SDR0_SRST1, sdr0_srst);
+	udelay(1000);
+
+	/* 6. Set EHCI Configure FLAG */
+
+	/* 7. Reassert internal PHY reset: */
+	mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
+	udelay(1000);
+
 	/*
 	 * Clear resets
 	 */
-	udelay (1000);
 	mtsdr(SDR0_SRST1, 0x00000000);
-	udelay (1000);
 	mtsdr(SDR0_SRST0, 0x00000000);
 
 	printf("USB:   Host(int phy) Device(ext phy)\n");
@@ -264,7 +335,7 @@ int checkboard(void)
 {
 	char *s = getenv("serial#");
 
-	printf("Board: lwmon5");
+	puts("Board: lwmon5");
 
 	if (s != NULL) {
 		puts(", serial# ");
@@ -331,34 +402,33 @@ U_BOOT_CMD(
 
 extern GraphicDevice mb862xx;
 
-static const gdc_regs init_regs [] =
-{
-	{0x0100, 0x00000f00},
-	{0x0020, 0x801401df},
-	{0x0024, 0x00000000},
-	{0x0028, 0x00000000},
-	{0x002c, 0x00000000},
-	{0x0110, 0x00000000},
-	{0x0114, 0x00000000},
-	{0x0118, 0x01df0280},
-	{0x0004, 0x031f0000},
-	{0x0008, 0x027f027f},
-	{0x000c, 0x015f028f},
-	{0x0010, 0x020c0000},
-	{0x0014, 0x01df01ea},
-	{0x0018, 0x00000000},
-	{0x001c, 0x01e00280},
-	{0x0100, 0x80010f00},
-	{0x0, 0x0}
+static const gdc_regs init_regs [] = {
+	{ 0x0100, 0x00000f00 },
+	{ 0x0020, 0x801401df },
+	{ 0x0024, 0x00000000 },
+	{ 0x0028, 0x00000000 },
+	{ 0x002c, 0x00000000 },
+	{ 0x0110, 0x00000000 },
+	{ 0x0114, 0x00000000 },
+	{ 0x0118, 0x01df0280 },
+	{ 0x0004, 0x031f0000 },
+	{ 0x0008, 0x027f027f },
+	{ 0x000c, 0x015f028f },
+	{ 0x0010, 0x020c0000 },
+	{ 0x0014, 0x01df01ea },
+	{ 0x0018, 0x00000000 },
+	{ 0x001c, 0x01e00280 },
+	{ 0x0100, 0x80010f00 },
+	{ 0x0, 0x0 }
 };
 
-const gdc_regs *board_get_regs (void)
+const gdc_regs *board_get_regs(void)
 {
 	return init_regs;
 }
 
 /* Returns Lime base address */
-unsigned int board_video_init (void)
+unsigned int board_video_init(void)
 {
 	/*
 	 * Reset Lime controller
@@ -375,7 +445,7 @@ unsigned int board_video_init (void)
 	return CONFIG_SYS_LIME_BASE_0;
 }
 
-#define DEFAULT_BRIGHTNESS 0x64
+#define DEFAULT_BRIGHTNESS	0x64
 
 static void board_backlight_brightness(int brightness)
 {
@@ -390,7 +460,7 @@ static void board_backlight_brightness(int brightness)
 	}
 }
 
-void board_backlight_switch (int flag)
+void board_backlight_switch(int flag)
 {
 	char * param;
 	int rc;
@@ -410,15 +480,14 @@ void board_backlight_switch (int flag)
 /*
  * Return text to be printed besides the logo.
  */
-void video_get_info_str (int line_number, char *info)
+void video_get_info_str(int line_number, char *info)
 {
-	if (line_number == 1) {
-		strcpy (info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
-	} else {
+	if (line_number == 1)
+		strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
+	else
 		info [0] = '\0';
-	}
 }
-#endif
+#endif /* CONFIG_CONSOLE_EXTRA_INFO */
 #endif /* CONFIG_VIDEO */
 
 void board_reset(void)
diff --git a/board/hmi1001/Makefile b/board/manroland/hmi1001/Makefile
index 442e2d0df..442e2d0df 100644
--- a/board/hmi1001/Makefile
+++ b/board/manroland/hmi1001/Makefile
diff --git a/board/hmi1001/config.mk b/board/manroland/hmi1001/config.mk
index 8ccf33e15..8ccf33e15 100644
--- a/board/hmi1001/config.mk
+++ b/board/manroland/hmi1001/config.mk
diff --git a/board/hmi1001/hmi1001.c b/board/manroland/hmi1001/hmi1001.c
index 9cbed4b8c..9cbed4b8c 100644
--- a/board/hmi1001/hmi1001.c
+++ b/board/manroland/hmi1001/hmi1001.c
diff --git a/board/mucmc52/Makefile b/board/manroland/mucmc52/Makefile
index 721c0164b..721c0164b 100644
--- a/board/mucmc52/Makefile
+++ b/board/manroland/mucmc52/Makefile
diff --git a/board/mucmc52/config.mk b/board/manroland/mucmc52/config.mk
index 685072833..685072833 100644
--- a/board/mucmc52/config.mk
+++ b/board/manroland/mucmc52/config.mk
diff --git a/board/mucmc52/mucmc52.c b/board/manroland/mucmc52/mucmc52.c
index 66973f09d..66973f09d 100644
--- a/board/mucmc52/mucmc52.c
+++ b/board/manroland/mucmc52/mucmc52.c
diff --git a/board/uc100/Makefile b/board/manroland/uc100/Makefile
index 92ee091f6..92ee091f6 100644
--- a/board/uc100/Makefile
+++ b/board/manroland/uc100/Makefile
diff --git a/board/uc100/config.mk b/board/manroland/uc100/config.mk
index a65a8ba2c..a65a8ba2c 100644
--- a/board/uc100/config.mk
+++ b/board/manroland/uc100/config.mk
diff --git a/board/uc100/pcmcia.c b/board/manroland/uc100/pcmcia.c
index ad256783c..ad256783c 100644
--- a/board/uc100/pcmcia.c
+++ b/board/manroland/uc100/pcmcia.c
diff --git a/board/uc100/u-boot.lds b/board/manroland/uc100/u-boot.lds
index 0d8f60594..0d8f60594 100644
--- a/board/uc100/u-boot.lds
+++ b/board/manroland/uc100/u-boot.lds
diff --git a/board/uc100/u-boot.lds.debug b/board/manroland/uc100/u-boot.lds.debug
index a7caa8d90..a7caa8d90 100644
--- a/board/uc100/u-boot.lds.debug
+++ b/board/manroland/uc100/u-boot.lds.debug
diff --git a/board/uc100/uc100.c b/board/manroland/uc100/uc100.c
index bdee4de36..bdee4de36 100644
--- a/board/uc100/uc100.c
+++ b/board/manroland/uc100/uc100.c
diff --git a/board/uc101/Makefile b/board/manroland/uc101/Makefile
index 442e2d0df..442e2d0df 100644
--- a/board/uc101/Makefile
+++ b/board/manroland/uc101/Makefile
diff --git a/board/uc101/config.mk b/board/manroland/uc101/config.mk
index 8ccf33e15..8ccf33e15 100644
--- a/board/uc101/config.mk
+++ b/board/manroland/uc101/config.mk
diff --git a/board/uc101/uc101.c b/board/manroland/uc101/uc101.c
index c7dfb7bad..c7dfb7bad 100644
--- a/board/uc101/uc101.c
+++ b/board/manroland/uc101/uc101.c
diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
index e3abeb8ef..e8714e3a7 100644
--- a/board/pdm360ng/pdm360ng.c
+++ b/board/pdm360ng/pdm360ng.c
@@ -237,9 +237,6 @@ int misc_init_r(void)
 #endif
 
 #ifdef CONFIG_FSL_DIU_FB
-# if	!(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
-	mpc5121_diu_init();
-#endif
 #if defined(CONFIG_SERIAL_MULTI)
 	set_lcd_brightness(0);
 #endif