diff options
Diffstat (limited to 'board')
34 files changed, 908 insertions, 478 deletions
diff --git a/board/astro/mcf5373l/Makefile b/board/astro/mcf5373l/Makefile new file mode 100644 index 000000000..c7a1d0551 --- /dev/null +++ b/board/astro/mcf5373l/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o fpga.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/astro/mcf5373l/astro.h b/board/astro/mcf5373l/astro.h new file mode 100644 index 000000000..b55a6f785 --- /dev/null +++ b/board/astro/mcf5373l/astro.h @@ -0,0 +1,44 @@ +#ifndef __ASTRO_H__ +#define __ASTRO_H__ + +/* in mcf5373l.c */ +int rs_serial_init(int port, int baud); +void astro_put_char(char ch); +int astro_is_char(void); +int astro_get_char(void); + +/* in fpga.c */ +int astro5373l_altera_load(void); +int astro5373l_xilinx_load(void); + +/* data structures used for communication (update.c) */ +typedef struct card_id { + char card_type; + char hardware_version; + char software_version; + char software_subversion; /* " ","a".."z" */ + char fpga_version_altera; + char fpga_version_xilinx; +} card_id_t; + +typedef struct { + unsigned char mode; + unsigned char deviation; + unsigned short freq; +} __attribute__ ((packed)) output_params_t; + +typedef struct { + unsigned short satfreq; + unsigned char satdatallg; + unsigned short symbolrate; + unsigned char viterbirate; + unsigned char symbolrate_l; + output_params_t output_params; + unsigned char reserve; + unsigned char card_error; + unsigned short dummy_ts_id; + unsigned char dummy_pat_ver; + unsigned char dummy_sdt_ver; +} __attribute__ ((packed)) parameters_t; + +#endif /* __ASTRO_H__ */ diff --git a/board/astro/mcf5373l/config.mk b/board/astro/mcf5373l/config.mk new file mode 100644 index 000000000..6316a3029 --- /dev/null +++ b/board/astro/mcf5373l/config.mk @@ -0,0 +1,27 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = $(CONFIG_TEXT_BASE) + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c new file mode 100644 index 000000000..467461b8e --- /dev/null +++ b/board/astro/mcf5373l/fpga.c @@ -0,0 +1,425 @@ +/* + * (C) Copyright 2006 + * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH, + * w.wegner@astro-kom.de + * + * based on the files by + * Heiko Schocher, DENX Software Engineering, hs@denx.de + * and + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */ + +#include <common.h> +#include <watchdog.h> +#include <altera.h> +#include <ACEX1K.h> +#include <spartan3.h> +#include <command.h> +#include <asm/immap_5329.h> +#include <asm/io.h> +#include "fpga.h" + +DECLARE_GLOBAL_DATA_PTR; + +int altera_pre_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + unsigned char tmp_char; + unsigned short tmp_short; + + /* first, set the required pins to GPIO function */ + /* PAR_T0IN -> GPIO */ + tmp_char = readb(&gpiop->par_timer); + tmp_char &= 0xfc; + writeb(tmp_char, &gpiop->par_timer); + /* all QSPI pins -> GPIO */ + writew(0x0000, &gpiop->par_qspi); + /* U0RTS, U0CTS -> GPIO */ + tmp_short = __raw_readw(&gpiop->par_uart); + tmp_short &= 0xfff3; + __raw_writew(tmp_short, &gpiop->par_uart); + /* all PWM pins -> GPIO */ + writeb(0x00, &gpiop->par_pwm); + /* next, set data direction registers */ + writeb(0x01, &gpiop->pddr_timer); + writeb(0x25, &gpiop->pddr_qspi); + writeb(0x0c, &gpiop->pddr_uart); + writeb(0x04, &gpiop->pddr_pwm); + + /* ensure other SPI peripherals are deselected */ + writeb(0x08, &gpiop->ppd_uart); + writeb(0x38, &gpiop->ppd_qspi); + + /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ + writeb(0xFB, &gpiop->pclrr_uart); + /* enable Altera configuration by clearing QSPI_CS2 and DT0IN */ + writeb(0xFE, &gpiop->pclrr_timer); + writeb(0xDF, &gpiop->pclrr_qspi); + return FPGA_SUCCESS; +} + +/* Set the state of CONFIG Pin */ +int altera_config_fn(int assert_config, int flush, int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (assert_config) + writeb(0x04, &gpiop->ppd_uart); + else + writeb(0xFB, &gpiop->pclrr_uart); + return FPGA_SUCCESS; +} + +/* Returns the state of STATUS Pin */ +int altera_status_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (readb(&gpiop->ppd_pwm) & 0x08) + return FPGA_FAIL; + return FPGA_SUCCESS; +} + +/* Returns the state of CONF_DONE Pin */ +int altera_done_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (readb(&gpiop->ppd_pwm) & 0x20) + return FPGA_FAIL; + return FPGA_SUCCESS; +} + +/* + * writes the complete buffer to the FPGA + * writing the complete buffer in one function is much faster, + * then calling it for every bit + */ +int altera_write_fn(void *buf, size_t len, int flush, int cookie) +{ + size_t bytecount = 0; + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + unsigned char *data = (unsigned char *)buf; + unsigned char val = 0; + int i; + int len_40 = len / 40; + + while (bytecount < len) { + val = data[bytecount++]; + i = 8; + do { + writeb(0xFB, &gpiop->pclrr_qspi); + if (val & 0x01) + writeb(0x01, &gpiop->ppd_qspi); + else + writeb(0xFE, &gpiop->pclrr_qspi); + writeb(0x04, &gpiop->ppd_qspi); + val >>= 1; + i--; + } while (i > 0); + + if (bytecount % len_40 == 0) { +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET(); +#endif +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + putc('.'); /* let them know we are alive */ +#endif +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC + if (ctrlc()) + return FPGA_FAIL; +#endif + } + } + return FPGA_SUCCESS; +} + +/* called, when programming is aborted */ +int altera_abort_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + writeb(0x20, &gpiop->ppd_qspi); + writeb(0x08, &gpiop->ppd_uart); + return FPGA_SUCCESS; +} + +/* called, when programming was succesful */ +int altera_post_fn(int cookie) +{ + return altera_abort_fn(cookie); +} + +/* + * Note that these are pointers to code that is in Flash. They will be + * relocated at runtime. + * FIXME: relocation not yet working for coldfire, see below! + */ +Altera_CYC2_Passive_Serial_fns altera_fns = { + altera_pre_fn, + altera_config_fn, + altera_status_fn, + altera_done_fn, + altera_write_fn, + altera_abort_fn, + altera_post_fn +}; + +Altera_desc altera_fpga[CONFIG_FPGA_COUNT] = { + {Altera_CYC2, + passive_serial, + 85903, + (void *)&altera_fns, + NULL, + 0} +}; + +/* Initialize the fpga. Return 1 on success, 0 on failure. */ +int astro5373l_altera_load(void) +{ + int i; + + for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + /* + * I did not yet manage to get relocation work properly, + * so set stuff here instead of static initialisation: + */ + altera_fns.pre = altera_pre_fn; + altera_fns.config = altera_config_fn; + altera_fns.status = altera_status_fn; + altera_fns.done = altera_done_fn; + altera_fns.write = altera_write_fn; + altera_fns.abort = altera_abort_fn; + altera_fns.post = altera_post_fn; + altera_fpga[i].iface_fns = (void *)&altera_fns; + fpga_add(fpga_altera, &altera_fpga[i]); + } + return 1; +} + +/* Set the FPGA's PROG_B line to the specified level */ +int xilinx_pgm_fn(int assert, int flush, int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (assert) + writeb(0xFB, &gpiop->pclrr_uart); + else + writeb(0x04, &gpiop->ppd_uart); + return assert; +} + +/* + * Test the state of the active-low FPGA INIT line. Return 1 on INIT + * asserted (low). + */ +int xilinx_init_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + return (readb(&gpiop->ppd_pwm) & 0x08) == 0; +} + +/* Test the state of the active-high FPGA DONE pin */ +int xilinx_done_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + return (readb(&gpiop->ppd_pwm) & 0x20) >> 5; +} + +/* Abort an FPGA operation */ +int xilinx_abort_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + /* ensure all SPI peripherals and FPGAs are deselected */ + writeb(0x08, &gpiop->ppd_uart); + writeb(0x01, &gpiop->ppd_timer); + writeb(0x38, &gpiop->ppd_qspi); + return FPGA_FAIL; +} + +/* + * FPGA pre-configuration function. Just make sure that + * FPGA reset is asserted to keep the FPGA from starting up after + * configuration. + */ +int xilinx_pre_config_fn(int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + unsigned char tmp_char; + unsigned short tmp_short; + + /* first, set the required pins to GPIO function */ + /* PAR_T0IN -> GPIO */ + tmp_char = readb(&gpiop->par_timer); + tmp_char &= 0xfc; + writeb(tmp_char, &gpiop->par_timer); + /* all QSPI pins -> GPIO */ + writew(0x0000, &gpiop->par_qspi); + /* U0RTS, U0CTS -> GPIO */ + tmp_short = __raw_readw(&gpiop->par_uart); + tmp_short &= 0xfff3; + __raw_writew(tmp_short, &gpiop->par_uart); + /* all PWM pins -> GPIO */ + writeb(0x00, &gpiop->par_pwm); + /* next, set data direction registers */ + writeb(0x01, &gpiop->pddr_timer); + writeb(0x25, &gpiop->pddr_qspi); + writeb(0x0c, &gpiop->pddr_uart); + writeb(0x04, &gpiop->pddr_pwm); + + /* ensure other SPI peripherals are deselected */ + writeb(0x08, &gpiop->ppd_uart); + writeb(0x38, &gpiop->ppd_qspi); + writeb(0x01, &gpiop->ppd_timer); + + /* CONFIG = 0, STATUS = 0 -> FPGA in reset state */ + writeb(0xFB, &gpiop->pclrr_uart); + /* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */ + writeb(0xF7, &gpiop->pclrr_uart); + writeb(0xDF, &gpiop->pclrr_qspi); + return 0; +} + +/* + * FPGA post configuration function. Should perform a test if FPGA is running. + */ +int xilinx_post_config_fn(int cookie) +{ + int rc = 0; + + /* + * no test yet + */ + return rc; +} + +int xilinx_clk_fn(int assert_clk, int flush, int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (assert_clk) + writeb(0x04, &gpiop->ppd_qspi); + else + writeb(0xFB, &gpiop->pclrr_qspi); + return assert_clk; +} + +int xilinx_wr_fn(int assert_write, int flush, int cookie) +{ + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + + if (assert_write) + writeb(0x01, &gpiop->ppd_qspi); + else + writeb(0xFE, &gpiop->pclrr_qspi); + return assert_write; +} + +int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie) +{ + size_t bytecount = 0; + gpio_t *gpiop = (gpio_t *)MMAP_GPIO; + unsigned char *data = (unsigned char *)buf; + unsigned char val = 0; + int i; + int len_40 = len / 40; + + for (bytecount = 0; bytecount < len; bytecount++) { + val = *(data++); + for (i = 8; i > 0; i--) { + writeb(0xFB, &gpiop->pclrr_qspi); + if (val & 0x80) + writeb(0x01, &gpiop->ppd_qspi); + else + writeb(0xFE, &gpiop->pclrr_qspi); + writeb(0x04, &gpiop->ppd_qspi); + val <<= 1; + } + if (bytecount % len_40 == 0) { +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + WATCHDOG_RESET(); +#endif +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK + putc('.'); /* let them know we are alive */ +#endif +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC + if (ctrlc()) + return FPGA_FAIL; +#endif + } + } + return FPGA_SUCCESS; +} + +/* + * Note that these are pointers to code that is in Flash. They will be + * relocated at runtime. + * FIXME: relocation not yet working for coldfire, see below! + */ +Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = { + xilinx_pre_config_fn, + xilinx_pgm_fn, + xilinx_clk_fn, + xilinx_init_fn, + xilinx_done_fn, + xilinx_wr_fn, + 0, + xilinx_fastwr_fn +}; + +Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { + {Xilinx_Spartan3, + slave_serial, + XILINX_XC3S4000_SIZE, + (void *)&xilinx_fns, + 0} +}; + +/* Initialize the fpga. Return 1 on success, 0 on failure. */ +int astro5373l_xilinx_load(void) +{ + int i; + + fpga_init(); + + for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + /* + * I did not yet manage to get relocation work properly, + * so set stuff here instead of static initialisation: + */ + xilinx_fns.pre = xilinx_pre_config_fn; + xilinx_fns.pgm = xilinx_pgm_fn; + xilinx_fns.clk = xilinx_clk_fn; + xilinx_fns.init = xilinx_init_fn; + xilinx_fns.done = xilinx_done_fn; + xilinx_fns.wr = xilinx_wr_fn; + xilinx_fns.bwr = xilinx_fastwr_fn; + xilinx_fpga[i].iface_fns = (void *)&xilinx_fns; + fpga_add(fpga_xilinx, &xilinx_fpga[i]); + } + return 1; +} diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c new file mode 100644 index 000000000..3c09a21ee --- /dev/null +++ b/board/astro/mcf5373l/mcf5373l.c @@ -0,0 +1,211 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <command.h> +#include <asm/m5329.h> +#include <asm/immap_5329.h> +#include <asm/io.h> + +/* needed for astro bus: */ +#include <asm/uart.h> +#include "astro.h" + +DECLARE_GLOBAL_DATA_PTR; +extern void uart_port_conf(void); + +int checkboard(void) +{ + puts("Board: "); + puts("ASTRO MCF5373L (Urmel) Board\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + sdram_t *sdp = (sdram_t *)(MMAP_SDRAM); + + /* + * GPIO configuration for bus should be set correctly from reset, + * so we do not care! First, set up address space: at this point, + * we should be running from internal SRAM; + * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM, + * and do not care where it is + */ + __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, + &sdp->cs0); + __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, + &sdp->cs1); + /* + * I am not sure from the data sheet, but it seems burst length + * has to be 8 for the 16 bit data bus we use; + * so these values are for BL = 8 + */ + __raw_writel(0x33211530, &sdp->cfg1); + __raw_writel(0x56570000, &sdp->cfg2); + /* send PrechargeALL, REF and IREF remain cleared! */ + __raw_writel(0xE1462C02, &sdp->ctrl); + udelay(1); + /* refresh SDRAM twice */ + __raw_writel(0xE1462C04, &sdp->ctrl); + udelay(1); + __raw_writel(0xE1462C04, &sdp->ctrl); + /* init MR */ + __raw_writel(0x008D0000, &sdp->mode); + /* initialize EMR */ + __raw_writel(0x80010000, &sdp->mode); + /* wait until DLL is locked */ + udelay(1); + /* + * enable automatic refresh, lock mode register, + * clear iref and ipall + */ + __raw_writel(0x71462C00, &sdp->ctrl); + /* Dummy write to start SDRAM */ + writel(0, CONFIG_SYS_SDRAM_BASE); +#endif + + /* + * for get_ram_size() to work, both CS areas have to be + * configured, i.e. CS1 has to be explicitely disabled, else + * probing for memory will cause the SDRAM bus to hang! + * (Do not rely on the SDCS register(s) being set to 0x00000000 + * during reset as stated in the data sheet.) + */ + return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE, + 0x80000000 - CONFIG_SYS_SDRAM_BASE); +} + +#define UART_BASE MMAP_UART0 +int rs_serial_init(int port, int baud) +{ + uart_t *uart; + u32 counter; + + switch (port) { + case 0: + uart = (uart_t *)(MMAP_UART0); + break; + case 1: + uart = (uart_t *)(MMAP_UART1); + break; + case 2: + uart = (uart_t *)(MMAP_UART2); + break; + default: + uart = (uart_t *)(MMAP_UART0); + } + + uart_port_conf(); + + /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ + writeb(UART_UCR_RESET_RX, &uart->ucr); + writeb(UART_UCR_RESET_TX, &uart->ucr); + writeb(UART_UCR_RESET_ERROR, &uart->ucr); + writeb(UART_UCR_RESET_MR, &uart->ucr); + __asm__ ("nop"); + + writeb(0, &uart->uimr); + + /* write to CSR: RX/TX baud rate from timers */ + writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); + + writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); + writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); + + /* Setting up BaudRate */ + counter = (u32) (gd->bus_clk / (baud)); + counter >>= 5; + + /* write to CTUR: divide counter upper byte */ + writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1); + /* write to CTLR: divide counter lower byte */ + writeb((u8) (counter & 0x00ff), &uart->ubg2); + + writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr); + + return 0; +} + +void astro_put_char(char ch) +{ + uart_t *uart; + unsigned long timer; + + uart = (uart_t *)(MMAP_UART0); + /* + * Wait for last character to go. Timeout of 6ms should + * be enough for our lowest baud rate of 2400. + */ + timer = get_timer(0); + while (get_timer(timer) < 6) { + if (readb(&uart->usr) & UART_USR_TXRDY) + break; + } + writeb(ch, &uart->utb); + + return; +} + +int astro_is_char(void) +{ + uart_t *uart; + + uart = (uart_t *)(MMAP_UART0); + return readb(&uart->usr) & UART_USR_RXRDY; +} + +int astro_get_char(void) +{ + uart_t *uart; + + uart = (uart_t *)(MMAP_UART0); + while (!(readb(&uart->usr) & UART_USR_RXRDY)) ; + return readb(&uart->urb); +} + +int misc_init_r(void) +{ + int retval = 0; + + puts("Configure Xilinx FPGA..."); + retval = astro5373l_xilinx_load(); + if (!retval) { + puts("failed!\n"); + return retval; + } + puts("done\n"); + + puts("Configure Altera FPGA..."); + retval = astro5373l_altera_load(); + if (!retval) { + puts("failed!\n"); + return retval; + } + puts("done\n"); + + return retval; +} diff --git a/board/astro/mcf5373l/u-boot.lds b/board/astro/mcf5373l/u-boot.lds new file mode 100644 index 000000000..a9a4e0a23 --- /dev/null +++ b/board/astro/mcf5373l/u-boot.lds @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf532x/start.o (.text) + lib_m68k/traps.o (.text) + lib_m68k/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o (.text) + + *(.text) +/* *(.fixup)*/ + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c index 6fb0096be..3117b5fbf 100644 --- a/board/bc3450/bc3450.c +++ b/board/bc3450/bc3450.c @@ -104,7 +104,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) phys_size_t initdram (int board_type) { ulong dramsize = 0; @@ -204,57 +203,6 @@ phys_size_t initdram (int board_type) return dramsize; } -#elif defined(CONFIG_MGT5100) - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff; /* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CONFIG_SYS_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { #if defined (CONFIG_TQM5200) @@ -276,10 +224,6 @@ void flash_preinit(void) * Note that CS_BOOT cannot be cleared when * executing in flash. */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } diff --git a/board/bc3450/mt48lc16m16a2-75.h b/board/bc3450/mt48lc16m16a2-75.h index 3f1e1691b..48b43213d 100644 --- a/board/bc3450/mt48lc16m16a2-75.h +++ b/board/bc3450/mt48lc16m16a2-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 /* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ @@ -33,15 +32,3 @@ /*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ #define SDRAM_CONFIG2 0x8AD70000 /*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c index dce07bf78..6ddc858ea 100644 --- a/board/canmb/canmb.c +++ b/board/canmb/canmb.c @@ -81,7 +81,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) phys_size_t initdram (int board_type) { ulong dramsize = 0; @@ -183,57 +182,6 @@ phys_size_t initdram (int board_type) return dramsize + dramsize2; } -#elif defined(CONFIG_MGT5100) - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CONFIG_SYS_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { puts ("Board: CANMB\n"); diff --git a/board/canmb/mt48lc16m32s2-75.h b/board/canmb/mt48lc16m32s2-75.h index ffdf0396a..15477259c 100644 --- a/board/canmb/mt48lc16m32s2-75.h +++ b/board/canmb/mt48lc16m32s2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/davinci/da830evm/da830evm.c b/board/davinci/da830evm/da830evm.c index ed668afcc..638544366 100644 --- a/board/davinci/da830evm/da830evm.c +++ b/board/davinci/da830evm/da830evm.c @@ -150,7 +150,7 @@ int board_init(void) DAVINCI_ABCR_RHOLD(0) | DAVINCI_ABCR_TA(2) | DAVINCI_ABCR_ASIZE_8BIT), - &davinci_emif_regs->AB2CR); + &davinci_emif_regs->ab2cr); #endif /* arch number of the board */ diff --git a/board/esd/cpci5200/mt46v16m16-75.h b/board/esd/cpci5200/mt46v16m16-75.h index 22d0a5544..cf63806a5 100644 --- a/board/esd/cpci5200/mt46v16m16-75.h +++ b/board/esd/cpci5200/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/esd/mecp5200/mt46v16m16-75.h b/board/esd/mecp5200/mt46v16m16-75.h index 22d0a5544..cf63806a5 100644 --- a/board/esd/mecp5200/mt46v16m16-75.h +++ b/board/esd/mecp5200/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/esd/pf5200/mt46v16m16-75.h b/board/esd/pf5200/mt46v16m16-75.h index 22d0a5544..cf63806a5 100644 --- a/board/esd/pf5200/mt46v16m16-75.h +++ b/board/esd/pf5200/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/freescale/m5271evb/m5271evb.c b/board/freescale/m5271evb/m5271evb.c index 5505cc42c..446f102e5 100644 --- a/board/freescale/m5271evb/m5271evb.c +++ b/board/freescale/m5271evb/m5271evb.c @@ -47,6 +47,7 @@ phys_size_t initdram (int board_type) { MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS | MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE | MCF_GPIO_SDRAM_SDCS_11); + asm(" nop"); /* * Check to see if the SDRAM has already been initialized @@ -55,8 +56,9 @@ phys_size_t initdram (int board_type) { if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) { /* Initialize DRAM Control Register: DCR */ mbar_writeShort(MCF_SDRAMC_DCR, - MCF_SDRAMC_DCR_RTIM(0x01) - | MCF_SDRAMC_DCR_RC(0x30)); + MCF_SDRAMC_DCR_RTIM(2) + | MCF_SDRAMC_DCR_RC(0x2E)); + asm(" nop"); /* * Initialize DACR0 @@ -70,15 +72,18 @@ phys_size_t initdram (int board_type) { | MCF_SDRAMC_DACRn_CASL(1) | MCF_SDRAMC_DACRn_CBM(3) | MCF_SDRAMC_DACRn_PS(0)); + asm(" nop"); /* Initialize DMR0 */ mbar_writeLong(MCF_SDRAMC_DMR0, MCF_SDRAMC_DMRn_BAM_16M | MCF_SDRAMC_DMRn_V); + asm(" nop"); /* Set IP bit in DACR */ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) | MCF_SDRAMC_DACRn_IP); + asm(" nop"); /* Wait at least 20ns to allow banks to precharge */ for (i = 0; i < 5; i++) @@ -86,6 +91,7 @@ phys_size_t initdram (int board_type) { /* Write to this block to initiate precharge */ *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; + asm(" nop"); /* Set RE bit in DACR */ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) @@ -98,6 +104,7 @@ phys_size_t initdram (int board_type) { /* Finish the configuration by issuing the MRS */ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) | MCF_SDRAMC_DACRn_MRS); + asm(" nop"); /* * Write to the SDRAM Mode Register A0-A11 = 0x400 @@ -109,6 +116,7 @@ phys_size_t initdram (int board_type) { * Burst Length = 1 */ *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5; + asm(" nop"); } return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c index 293b5b0e4..2a84514a3 100644 --- a/board/freescale/m54455evb/m54455evb.c +++ b/board/freescale/m54455evb/m54455evb.c @@ -107,7 +107,7 @@ int ide_preinit(void) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_MASK) | 0x10; + gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10; gpio->par_feci2c |= (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW); @@ -185,7 +185,7 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) info->flash_id = 0x01000000; info->portwidth = 1; info->chipwidth = 1; - info->buffer_size = 32; + info->buffer_size = 1; info->erase_blk_tout = 16384; info->write_tout = 2; info->buffer_write_tout = 5; diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index 75244610c..47b219555 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -134,7 +134,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) phys_size_t initdram (int board_type) { ulong dramsize = 0; @@ -258,65 +257,12 @@ phys_size_t initdram (int board_type) return dramsize + dramsize2; } -#elif defined(CONFIG_MGT5100) - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CONFIG_SYS_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { #if defined (CONFIG_LITE5200B) puts ("Board: Freescale Lite5200B\n"); -#elif defined(CONFIG_MPC5200) +#else puts ("Board: Motorola MPC5200 (IceCube)\n"); -#elif defined(CONFIG_MGT5100) - puts ("Board: Motorola MGT5100 (IceCube)\n"); #endif return 0; } @@ -329,10 +275,6 @@ void flash_preinit(void) * Note that CS_BOOT cannot be cleared when * executing in flash. */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } diff --git a/board/icecube/mt46v16m16-75.h b/board/icecube/mt46v16m16-75.h index 4c0f9a740..eb857404f 100644 --- a/board/icecube/mt46v16m16-75.h +++ b/board/icecube/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/icecube/mt46v32m16.h b/board/icecube/mt46v32m16.h index de2b48bc6..519bf6d0f 100644 --- a/board/icecube/mt46v32m16.h +++ b/board/icecube/mt46v32m16.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/icecube/mt48lc16m16a2-75.h b/board/icecube/mt48lc16m16a2-75.h index ffdf0396a..15477259c 100644 --- a/board/icecube/mt48lc16m16a2-75.h +++ b/board/icecube/mt48lc16m16a2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c index 6e752c655..967aabdcf 100644 --- a/board/jupiter/jupiter.c +++ b/board/jupiter/jupiter.c @@ -227,10 +227,6 @@ void flash_preinit(void) * Note that CS_BOOT cannot be cleared when * executing in flash. */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } @@ -248,10 +244,8 @@ void flash_afterinit(ulong size) *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); } -#if defined(CONFIG_MPC5200) *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif } int update_flash_size (int flash_size) diff --git a/board/mcc200/mt46v16m16-75.h b/board/mcc200/mt46v16m16-75.h index f650faaa1..423febe20 100644 --- a/board/mcc200/mt46v16m16-75.h +++ b/board/mcc200/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/mcc200/mt48lc16m16a2-75.h b/board/mcc200/mt48lc16m16a2-75.h index ffdf0396a..15477259c 100644 --- a/board/mcc200/mt48lc16m16a2-75.h +++ b/board/mcc200/mt48lc16m16a2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/mcc200/mt48lc16m32s2-75.h b/board/mcc200/mt48lc16m32s2-75.h index ffdf0396a..15477259c 100644 --- a/board/mcc200/mt48lc16m32s2-75.h +++ b/board/mcc200/mt48lc16m32s2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/munices/mt48lc16m16a2-75.h b/board/munices/mt48lc16m16a2-75.h index ffdf0396a..15477259c 100644 --- a/board/munices/mt48lc16m16a2-75.h +++ b/board/munices/mt48lc16m16a2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/pm520/mt46v16m16-75.h b/board/pm520/mt46v16m16-75.h index f650faaa1..423febe20 100644 --- a/board/pm520/mt46v16m16-75.h +++ b/board/pm520/mt46v16m16-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 1 /* is DDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x018D0000 #define SDRAM_EMODE 0x40090000 @@ -31,7 +30,3 @@ #define SDRAM_CONFIG1 0x73722930 #define SDRAM_CONFIG2 0x47770000 #define SDRAM_TAPDELAY 0x10000000 - -#else -#error CONFIG_MPC5200 not defined -#endif diff --git a/board/pm520/mt48lc16m16a2-75.h b/board/pm520/mt48lc16m16a2-75.h index ffdf0396a..15477259c 100644 --- a/board/pm520/mt48lc16m16a2-75.h +++ b/board/pm520/mt48lc16m16a2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c index 9da104173..d6914343f 100644 --- a/board/pm520/pm520.c +++ b/board/pm520/pm520.c @@ -84,7 +84,6 @@ static void sdram_start (int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) phys_size_t initdram (int board_type) { ulong dramsize = 0; @@ -186,64 +185,9 @@ phys_size_t initdram (int board_type) return dramsize + dramsize2; } -#elif defined(CONFIG_MGT5100) - -phys_size_t initdram (int board_type) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; - __asm__ volatile ("sync"); - - /* find RAM size */ - sdram_start(0); - test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CONFIG_SYS_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif - int checkboard (void) { -#if defined(CONFIG_MPC5200) puts ("Board: MicroSys PM520 \n"); -#elif defined(CONFIG_MGT5100) - puts ("Board: MicroSys PM510 \n"); -#endif return 0; } @@ -255,10 +199,6 @@ void flash_preinit(void) * Note that CS_BOOT cannot be cleared when * executing in flash. */ -#if defined(CONFIG_MGT5100) - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ -#endif *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } diff --git a/board/total5200/mt48lc16m16a2-75.h b/board/total5200/mt48lc16m16a2-75.h index 5b0923e3e..ae237c6ca 100644 --- a/board/total5200/mt48lc16m16a2-75.h +++ b/board/total5200/mt48lc16m16a2-75.h @@ -23,21 +23,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/total5200/mt48lc32m16a2-75.h b/board/total5200/mt48lc32m16a2-75.h index 4b5ac80b3..cb4b43d63 100644 --- a/board/total5200/mt48lc32m16a2-75.h +++ b/board/total5200/mt48lc32m16a2-75.h @@ -28,13 +28,8 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x514F0000 #define SDRAM_CONFIG1 0xD2322800 #define SDRAM_CONFIG2 0x8AD70000 - -#else -#error CONFIG_MPC5200 is not defined -#endif diff --git a/board/total5200/sdram.c b/board/total5200/sdram.c index dc4c6f18c..d883eb656 100644 --- a/board/total5200/sdram.c +++ b/board/total5200/sdram.c @@ -76,7 +76,6 @@ static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr) * is something else than 0x00000000. */ -#if defined(CONFIG_MPC5200) long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) { ulong dramsize = 0; @@ -174,54 +173,3 @@ long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) return dramsize + dramsize2; } - -#elif defined(CONFIG_MGT5100) - -long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) -{ - ulong dramsize = 0; -#ifndef CONFIG_SYS_RAMBOOT - ulong test1, test2; - - /* setup and enable SDRAM chip selects */ - *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; - *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ - __asm__ volatile ("sync"); - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2; - - /* address select register */ - *(vu_long *)MPC5XXX_SDRAM_XLBSEL = sdram_conf->addrsel; - __asm__ volatile ("sync"); - - /* find RAM size */ - mpc5xxx_sdram_start(sdram_conf, 0); - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - mpc5xxx_sdram_start(sdram_conf, 1); - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - mpc5xxx_sdram_start(sdram_conf, 0); - dramsize = test1; - } else { - dramsize = test2; - } - - /* set SDRAM end address according to size */ - *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); - -#else /* CONFIG_SYS_RAMBOOT */ - - /* Retrieve amount of SDRAM available */ - dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); - -#endif /* CONFIG_SYS_RAMBOOT */ - - return dramsize; -} - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif diff --git a/board/total5200/sdram.h b/board/total5200/sdram.h index bc21e1d30..396a19014 100644 --- a/board/total5200/sdram.h +++ b/board/total5200/sdram.h @@ -28,12 +28,7 @@ typedef struct { ulong control; ulong config1; ulong config2; -#if defined(CONFIG_MPC5200) ulong tapdelay; -#endif -#if defined(CONFIG_MGT5100) - ulong addrsel; -#endif } sdram_conf_t; long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf); diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c index c524d63f9..61b5b807a 100644 --- a/board/total5200/total5200.c +++ b/board/total5200/total5200.c @@ -47,26 +47,17 @@ phys_size_t initdram (int board_type) sdram_conf.control = SDRAM_CONTROL; sdram_conf.config1 = SDRAM_CONFIG1; sdram_conf.config2 = SDRAM_CONFIG2; -#if defined(CONFIG_MPC5200) sdram_conf.tapdelay = 0; -#endif -#if defined(CONFIG_MGT5100) - sdram_conf.addrsel = SDRAM_ADDRSEL; -#endif return mpc5xxx_sdram_init (&sdram_conf); } int checkboard (void) { -#if defined(CONFIG_MPC5200) #if CONFIG_TOTAL5200_REV==2 puts ("Board: Total5200 Rev.2 "); #else puts ("Board: Total5200 "); #endif -#elif defined(CONFIG_MGT5100) - puts ("Board: Total5100 "); -#endif /* * Retrieve FPGA Revision. @@ -85,20 +76,6 @@ int checkboard (void) return 0; } -#if defined(CONFIG_MGT5100) -int board_early_init_r(void) -{ - /* - * Now, when we are in RAM, enable CS0 - * because CS_BOOT cannot be written. - */ - *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ - *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ - - return 0; -} -#endif - #ifdef CONFIG_PCI static struct pci_controller hose; @@ -266,9 +243,7 @@ static const S1D_REGS init_regs [] = void video_get_info_str (int line_number, char *info) { if (line_number == 1) { -#ifdef CONFIG_MGT5100 - strcpy (info, " Total5100"); -#elif CONFIG_TOTAL5200_REV==1 +#if CONFIG_TOTAL5200_REV==1 strcpy (info, " Total5200"); #elif CONFIG_TOTAL5200_REV==2 strcpy (info, " Total5200 Rev.2"); diff --git a/board/tqc/tqm5200/mt48lc16m16a2-75.h b/board/tqc/tqm5200/mt48lc16m16a2-75.h index 3f1e1691b..48b43213d 100644 --- a/board/tqc/tqm5200/mt48lc16m16a2-75.h +++ b/board/tqc/tqm5200/mt48lc16m16a2-75.h @@ -23,7 +23,6 @@ #define SDRAM_DDR 0 /* is SDR */ -#if defined(CONFIG_MPC5200) /* Settings for XLB = 132 MHz */ #define SDRAM_MODE 0x00CD0000 /* #define SDRAM_MODE 0x008D0000 */ /* CAS latency 2 */ @@ -33,15 +32,3 @@ /*#define SDRAM_CONFIG1 0xD7322800 */ /* SDRAM controller bug workaround */ #define SDRAM_CONFIG2 0x8AD70000 /*#define SDRAM_CONFIG2 0xDDD70000 */ /* SDRAM controller bug workaround */ - -#elif defined(CONFIG_MGT5100) -/* Settings for XLB = 66 MHz */ -#define SDRAM_MODE 0x008D0000 -#define SDRAM_CONTROL 0x504F0000 -#define SDRAM_CONFIG1 0xC2222600 -#define SDRAM_CONFIG2 0x88B70004 -#define SDRAM_ADDRSEL 0x02000000 - -#else -#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined -#endif |