diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/amcc/luan/Makefile | 48 | ||||
| -rw-r--r-- | board/amcc/luan/config.mk | 44 | ||||
| -rw-r--r-- | board/amcc/luan/epld.h | 85 | ||||
| -rw-r--r-- | board/amcc/luan/flash.c | 111 | ||||
| -rw-r--r-- | board/amcc/luan/init.S | 132 | ||||
| -rw-r--r-- | board/amcc/luan/luan.c | 458 | ||||
| -rw-r--r-- | board/amcc/luan/u-boot.lds | 156 |
7 files changed, 1034 insertions, 0 deletions
diff --git a/board/amcc/luan/Makefile b/board/amcc/luan/Makefile new file mode 100644 index 000000000..5654f91a8 --- /dev/null +++ b/board/amcc/luan/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o +OBJS += flash.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/luan/config.mk b/board/amcc/luan/config.mk new file mode 100644 index 000000000..f52c20617 --- /dev/null +++ b/board/amcc/luan/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0x00001000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0xFBD00000 +else +TEXT_BASE = 0xFFFC0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/luan/epld.h b/board/amcc/luan/epld.h new file mode 100644 index 000000000..05362e06d --- /dev/null +++ b/board/amcc/luan/epld.h @@ -0,0 +1,85 @@ +#define EPLD0_FSEL_FB2 0x80 +#define EPLD0_BOOT_SMALL_FLASH 0x40 /* 0 boot from large flash, 1 from small flash */ +#define EPLD0_RAW_CARD_BIT0 0x20 /* raw card EC level */ +#define EPLD0_RAW_CARD_BIT1 0x10 +#define EPLD0_RAW_CARD_BIT2 0x08 +#define EPLD0_EXT_ARB_SEL_N 0x04 /* 0 select on-board ext PCI-X, 1 internal arbiter */ +#define EPLD0_FLASH_ONBRD_N 0x02 /* 0 small flash/SRAM active, 1 block access */ +#define EPLD0_FLASH_SRAM_SEL_N 0x01 /* 0 SRAM at mem top, 1 small flash at mem top */ + +#define EPLD1_CLK_CNTL0 0x80 /* FSEL-FB1 of MPC9772 */ +#define EPLD1_PCIX0_CNTL1 0x40 /* S*0 of 9531 */ +#define EPLD1_PCIX0_CNTL2 0x20 /* S*1 of 9531 */ +#define EPLD1_CLK_CNTL3 0x10 /* FSEL-B1 of MPC9772 */ +#define EPLD1_CLK_CNTL4 0x08 /* FSEL-B0 of MPC9772 */ +#define EPLD1_MASTER_CLOCK6 0x04 /* clock source select 6 */ +#define EPLD1_MASTER_CLOCK7 0x02 /* clock source select 7 */ +#define EPLD1_MASTER_CLOCK8 0x01 /* clock source select 8 */ + +#define EPLD2_ETH_MODE_10 0x80 /* Ethernet mode 10 (default = 1) */ +#define EPLD2_ETH_MODE_100 0x40 /* Ethernet mode 100 (default = 1) */ +#define EPLD2_ETH_MODE_1000 0x20 /* Ethernet mode 1000 (default = 1) */ +#define EPLD2_ETH_DUPLEX_MODE 0x10 /* Ethernet force full duplex mode */ +#define EPLD2_RESET_ETH_N 0x08 /* Ethernet reset (default = 1) */ +#define EPLD2_ETH_AUTO_NEGO 0x04 /* Ethernet auto negotiation */ +#define EPLD2_DEFAULT_UART_N 0x01 /* 0 select DSR DTR for UART1 */ + +#define EPLD3_STATUS_LED4 0x08 /* status LED 8 (1 = LED on) */ +#define EPLD3_STATUS_LED3 0x04 /* status LED 4 (1 = LED on) */ +#define EPLD3_STATUS_LED2 0x02 /* status LED 2 (1 = LED on) */ +#define EPLD3_STATUS_LED1 0x01 /* status LED 1 (1 = LED on) */ + +#define EPLD4_PCIX0_VTH1 0x80 /* PCI-X 0 VTH1 status */ +#define EPLD4_PCIX0_VTH2 0x40 /* PCI-X 0 VTH2 status */ +#define EPLD4_PCIX0_VTH3 0x20 /* PCI-X 0 VTH3 status */ +#define EPLD4_PCIX0_VTH4 0x10 /* PCI-X 0 VTH4 status */ +#define EPLD4_PCIX1_VTH1 0x08 /* PCI-X 1 VTH1 status */ +#define EPLD4_PCIX1_VTH2 0x04 /* PCI-X 1 VTH2 status */ +#define EPLD4_PCIX1_VTH3 0x02 /* PCI-X 1 VTH3 status */ +#define EPLD4_PCIX1_VTH4 0x01 /* PCI-X 1 VTH4 status */ + +#define EPLD5_PCIX0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */ +#define EPLD5_PCIX0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */ +#define EPLD5_PCIX0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */ +#define EPLD5_PCIX0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */ +#define EPLD5_PCIX1_INT0 0x08 /* PCIX1 INT0 status, write 0 to reset */ +#define EPLD5_PCIX1_INT1 0x04 /* PCIX1 INT1 status, write 0 to reset */ +#define EPLD5_PCIX1_INT2 0x02 /* PCIX1 INT2 status, write 0 to reset */ +#define EPLD5_PCIX1_INT3 0x01 /* PCIX1 INT3 status, write 0 to reset */ + +#define EPLD6_PCIX0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */ +#define EPLD6_PCIX1_RESET_CTL 0x40 /* 0=enable slot reset, 1=disable slot reset */ +#define EPLD6_ETH_INT_MODE 0x20 /* 0=IRQ5 recv's external eth int */ +#define EPLD6_PCIX2_RESET_CTL 0x10 /* 0=enable slot reset, 1=disable slot reset */ +#define EPLD6_PCI1_CLKCNTL1 0x80 /* PCI1 clock control S*0 of 9531 */ +#define EPLD6_PCI1_CLKCNTL2 0x40 /* PCI1 clock control S*1 of 9531 */ +#define EPLD6_PCI2_CLKCNTL1 0x20 /* PCI2 clock control S*0 of 9531 */ +#define EPLD6_PCI2_CLKCNTL2 0x10 /* PCI2 clock control S*1 of 9531 */ + +#define EPLD7_VTH1 0x80 /* PCI2 VTH1 status */ +#define EPLD7_VTH2 0x40 /* PCI2 VTH2 status */ +#define EPLD7_VTH3 0x20 /* PCI2 VTH3 status */ +#define EPLD7_VTH4 0x10 /* PCI2 VTH4 status */ +#define EPLD7_INTA_MODE 0x80 /* see S5 on SW2 for details */ +#define EPLD7_PCI_INT_MODE_N 0x40 /* see S1 on SW2 for details */ +#define EPLD7_WRITE_ENABLE_GPIO 0x20 /* see S2 on SW2 for details */ +#define EPLD7_WRITE_ENABLE_INT 0x10 /* see S3 on SW2 for details */ + + +typedef struct { + unsigned char status; /* misc status */ + unsigned char clock; /* clock status, PCI-X clock control */ + unsigned char ethuart; /* Ethernet, UART status */ + unsigned char leds; /* LED register */ + unsigned char vth01; /* PCI0, PCI1 VTH register */ + unsigned char pciints; /* PCI0, PCI1 interrupts */ + unsigned char pci2; /* PCI2 interrupts, clock control */ + unsigned char vth2; /* PCI2 VTH register */ + unsigned char filler1[4096-8]; + unsigned char gpio00; /* GPIO bits 0-7 */ + unsigned char gpio08; /* GPIO bits 8-15 */ + unsigned char gpio16; /* GPIO bits 16-23 */ + unsigned char gpio24; /* GPIO bits 24-31 */ + unsigned char filler2[4096-4]; + unsigned char version; /* EPLD version */ +} epld_t; diff --git a/board/amcc/luan/flash.c b/board/amcc/luan/flash.c new file mode 100644 index 000000000..d3c3c0d05 --- /dev/null +++ b/board/amcc/luan/flash.c @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +static unsigned long flash_addr_table[1][CFG_MAX_FLASH_BANKS] = { + {0xff900000, 0xff980000, 0xffc00000}, /* 0:000: configuraton 3 */ +}; + +/* + * include common flash code (for amcc boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); + +unsigned long flash_init(void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned short index = 0; + int i; + + /* read FPGA base register FPGA_REG0 */ + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + + /* check whether the address is 0 */ + if (flash_addr_table[index][i] == 0) { + continue; + } + + /* call flash_get_size() to initialize sector address */ + size_b[i] = flash_get_size((vu_long *) + flash_addr_table[index][i], + &flash_info[i]); + flash_info[i].size = size_b[i]; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, size_b[i], size_b[i] << 20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[2]); +#ifdef CFG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[2]); + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[2]); +#endif + + total_b += flash_info[i].size; + } + + return total_b; +} diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S new file mode 100644 index 000000000..7830ebdfa --- /dev/null +++ b/board/amcc/luan/init.S @@ -0,0 +1,132 @@ +/* +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <ppc_asm.tmpl> +#include <config.h> + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + +#if (CFG_LARGE_FLASH == 0xffc00000) /* if booting from large flash */ + /* large flash */ + tlbentry( 0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) + tlbentry( 0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) + tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) + tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) + + tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W ) +#else /* else booting from small flash */ + tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + + tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + tlbentry( 0xffa00000, SZ_1M, 0xffa00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) + tlbentry( 0xffb00000, SZ_1M, 0xffb00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) +#endif + + tlbentry( CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I ) + +#if (CFG_SRAM_BASE != 0) /* if SRAM up high and SDRAM at zero */ + tlbentry( 0x00000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) +#elif (CFG_SMALL_FLASH == 0xff900000) /* else SRAM at 0 */ + tlbentry( 0x00000000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) +#elif (CFG_SMALL_FLASH == 0xfff00000) + tlbentry( 0x00000000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ ) +#else + #error DONT KNOW SRAM LOCATION +#endif + + /* internal ram (l2 cache) */ + tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I ) + + /* peripherals at f0000000 */ + tlbentry( CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I ) + + /* PCI */ +#if (CONFIG_COMMANDS & CFG_CMD_PCI) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I ) +#endif + tlbtab_end diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c new file mode 100644 index 000000000..c6b79a9f5 --- /dev/null +++ b/board/amcc/luan/luan.c @@ -0,0 +1,458 @@ +/* + * (C) Copyright 2005 + * John Otken, jotken@softadvances.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <spd_sdram.h> +#include "epld.h" + + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + + +/************************************************************************* + * int board_early_init_f() + * + ************************************************************************/ +int board_early_init_f(void) +{ + volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; + + mtebc( pb0ap, 0x03800000 ); /* set chip selects */ + mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ + mtebc( pb1ap, 0x03800000 ); + mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */ + mtebc( pb2ap, 0x03800000 ); + mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ + + mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */ + mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */ + mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */ + mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */ + mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */ + mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ + mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */ + mtdcr( uic1sr, 0xffffffff ); + + mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */ + mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */ + mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */ + mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */ + mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */ + mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ + mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ + mtdcr( uic0sr, 0xffffffff ); + + x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */ + + return 0; +} + + +/************************************************************************* + * int misc_init_r() + * + ************************************************************************/ +int misc_init_r(void) +{ + volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; + x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */ + + return 0; +} + + +/************************************************************************* + * int checkboard() + * + ************************************************************************/ +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: Luan - AMCC PPC440SP Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + + +/************************************************************************* + * long int fixed_sdram() + * + ************************************************************************/ +static long int fixed_sdram(void) +{ /* DDR2 init from BDI2000 script */ + mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - zero DCEN bit */ + mtdcr( 0x11, 0x84000000 ); + mtdcr( 0x10, 0x00000020 ); /* MCIF0_MCOPT1 - no ECC, 64 bits, 4 banks, DDR2 */ + mtdcr( 0x11, 0x2D122000 ); + mtdcr( 0x10, 0x00000026 ); /* MCIF0_CODT - die termination on */ + mtdcr( 0x11, 0x00800026 ); + mtdcr( 0x10, 0x00000081 ); /* MCIF0_WRDTR - Write DQS Adv 90 + Fractional DQS Delay */ + mtdcr( 0x11, 0x82000800 ); + mtdcr( 0x10, 0x00000080 ); /* MCIF0_CLKTR - advance addr clock by 180 deg */ + mtdcr( 0x11, 0x80000000 ); + mtdcr( 0x10, 0x00000040 ); /* MCIF0_MB0CF - turn on CS0, N x 10 coll */ + mtdcr( 0x11, 0x00000201 ); + mtdcr( 0x10, 0x00000044 ); /* MCIF0_MB1CF - turn on CS0, N x 10 coll */ + mtdcr( 0x11, 0x00000201 ); + mtdcr( 0x10, 0x00000030 ); /* MCIF0_RTR - refresh every 7.8125uS */ + mtdcr( 0x11, 0x08200000 ); + mtdcr( 0x10, 0x00000085 ); /* MCIF0_SDTR1 - timing register 1 */ + mtdcr( 0x11, 0x80201000 ); + mtdcr( 0x10, 0x00000086 ); /* MCIF0_SDTR2 - timing register 2 */ + mtdcr( 0x11, 0x42103242 ); + mtdcr( 0x10, 0x00000087 ); /* MCIF0_SDTR3 - timing register 3 */ + mtdcr( 0x11, 0x0C100D14 ); + mtdcr( 0x10, 0x00000088 ); /* MCIF0_MMODE - CAS is 4 cycles */ + mtdcr( 0x11, 0x00000642 ); + mtdcr( 0x10, 0x00000089 ); /* MCIF0_MEMODE - diff DQS disabled */ + mtdcr( 0x11, 0x00000400 ); /* ODT term disabled */ + + mtdcr( 0x10, 0x00000050 ); /* MCIF0_INITPLR0 - NOP */ + mtdcr( 0x11, 0x81b80000 ); + mtdcr( 0x10, 0x00000051 ); /* MCIF0_INITPLR1 - PRE */ + mtdcr( 0x11, 0x82100400 ); + mtdcr( 0x10, 0x00000052 ); /* MCIF0_INITPLR2 - EMR2 */ + mtdcr( 0x11, 0x80820000 ); + mtdcr( 0x10, 0x00000053 ); /* MCIF0_INITPLR3 - EMR3 */ + mtdcr( 0x11, 0x80830000 ); + mtdcr( 0x10, 0x00000054 ); /* MCIF0_INITPLR4 - EMR DLL ENABLE */ + mtdcr( 0x11, 0x80810000 ); + mtdcr( 0x10, 0x00000055 ); /* MCIF0_INITPLR5 - MR DLL RESET */ + mtdcr( 0x11, 0x80800542 ); + mtdcr( 0x10, 0x00000056 ); /* MCIF0_INITPLR6 - PRE */ + mtdcr( 0x11, 0x82100400 ); + mtdcr( 0x10, 0x00000057 ); /* MCIF0_INITPLR7 - refresh */ + mtdcr( 0x11, 0x99080000 ); + mtdcr( 0x10, 0x00000058 ); /* MCIF0_INITPLR8 */ + mtdcr( 0x11, 0x99080000 ); + mtdcr( 0x10, 0x00000059 ); /* MCIF0_INITPLR9 */ + mtdcr( 0x11, 0x99080000 ); + mtdcr( 0x10, 0x0000005A ); /* MCIF0_INITPLR10 */ + mtdcr( 0x11, 0x99080000 ); + mtdcr( 0x10, 0x0000005B ); /* MCIF0_INITPLR11 - MR */ + mtdcr( 0x11, 0x80800442 ); + mtdcr( 0x10, 0x0000005C ); /* MCIF0_INITPLR12 - EMR OCD Default */ + mtdcr( 0x11, 0x80810380 ); + mtdcr( 0x10, 0x0000005D ); /* MCIF0_INITPLR13 - EMR OCD exit */ + mtdcr( 0x11, 0x80810000 ); + udelay( 10*1000 ); + + mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - execute preloaded init */ + mtdcr( 0x11, 0x28000000 ); /* set DC_EN */ + udelay( 100*1000 ); + + mtdcr( 0x40, 0x0000F800 ); /* MQ0_B0BAS: base addr 00000000 / 256MB */ + mtdcr( 0x41, 0x1000F800 ); /* MQ0_B1BAS: base addr 10000000 / 256MB */ + + mtdcr( 0x10, 0x00000078 ); /* MCIF0_RDCC - auto set read stage */ + mtdcr( 0x11, 0x00000000 ); + mtdcr( 0x10, 0x00000070 ); /* MCIF0_RQDC - read DQS delay control */ + mtdcr( 0x11, 0x8000003A ); /* enabled, frac DQS delay */ + mtdcr( 0x10, 0x00000074 ); /* MCIF0_RFDC - two clock feedback delay */ + mtdcr( 0x11, 0x00000200 ); + + return 512 << 20; +} + + +/************************************************************************* + * long int initdram + * + ************************************************************************/ +long int initdram( int board_type ) +{ + long dram_size = 0; + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (0); +#else + dram_size = fixed_sdram (); +#endif + + return dram_size; +} + + +/************************************************************************* + * int testdram() + * + ************************************************************************/ +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *) 0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + for (k = 0; k < CFG_KBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + + return 0; +} +#endif + + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init( struct pci_controller *hose ) +{ + unsigned long strap; + + /*--------------------------------------------------------------------------+ + * The luan board is always configured as the host & requires the + * PCI arbiter to be enabled. + *--------------------------------------------------------------------------*/ + mfsdr(sdr_sdstp1, strap); + if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { + printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); + + return 0; + } + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + DECLARE_GLOBAL_DATA_PTR; + + /*--------------------------------------------------------------------------+ + * Disable everything + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0SA, 0 ); /* disable */ + out32r( PCIX0_PIM1SA, 0 ); /* disable */ + out32r( PCIX0_PIM2SA, 0 ); /* disable */ + out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + + /*--------------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping + * options to not support sizes such as 128/256 MB. + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAH, 0 ); + out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + + out32r( PCIX0_BAR0, 0 ); + + /*--------------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *--------------------------------------------------------------------------*/ + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + + out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + return 1; +} +#endif /* defined(CONFIG_PCI) */ + + +/************************************************************************* + * hw_watchdog_reset + * + * This routine is called to reset (keep alive) the watchdog timer + * + ************************************************************************/ +#if defined(CONFIG_HW_WATCHDOG) +void hw_watchdog_reset(void) +{ +} +#endif + + +/************************************************************************* + * int on_off() + * + ************************************************************************/ +static int on_off( const char *s ) +{ + if (strcmp(s, "on") == 0) { + return 1; + } else if (strcmp(s, "off") == 0) { + return 0; + } + return -1; +} + + +/************************************************************************* + * void l2cache_disable() + * + ************************************************************************/ +static void l2cache_disable(void) +{ + mtdcr( l2_cache_cfg, 0 ); +} + + +/************************************************************************* + * void l2cache_enable() + * + ************************************************************************/ +static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */ +{ + mtdcr( l2_cache_cfg, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */ + + mtdcr( l2_cache_addr, 0 ); /* set L2_ADDR with all zeros */ + + mtdcr( l2_cache_cmd, 0x80000000 ); /* issue HCLEAR command via L2_CMD */ + + while (!(mfdcr( l2_cache_stat ) & 0x80000000 )) ;; /* poll L2_SR for completion */ + + mtdcr( l2_cache_cmd, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */ + + mtdcr( l2_cache_cmd, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */ + + mtdcr( l2_cache_snp0, 0 ); /* snoop registers */ + mtdcr( l2_cache_snp1, 0 ); + + __asm__ volatile ("sync"); /* msync */ + + mtdcr( l2_cache_cfg, 0xe0000000 ); /* inst and data use L2 */ + + __asm__ volatile ("sync"); +} + + +/************************************************************************* + * int l2cache_status() + * + ************************************************************************/ +static int l2cache_status(void) +{ + return (mfdcr( l2_cache_cfg ) & 0x60000000) != 0; +} + + +/************************************************************************* + * int do_l2cache() + * + ************************************************************************/ +int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) +{ + switch (argc) { + case 2: /* on / off */ + switch (on_off(argv[1])) { + case 0: l2cache_disable(); + break; + case 1: l2cache_enable(); + break; + } + /* FALL TROUGH */ + case 1: /* get status */ + printf ("L2 Cache is %s\n", + l2cache_status() ? "ON" : "OFF"); + return 0; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + return 0; +} + + +U_BOOT_CMD( + l2cache, 2, 1, do_l2cache, + "l2cache - enable or disable L2 cache\n", + "[on, off]\n" + " - enable or disable L2 cache\n" + ); diff --git a/board/amcc/luan/u-boot.lds b/board/amcc/luan/u-boot.lds new file mode 100644 index 000000000..24a0fde51 --- /dev/null +++ b/board/amcc/luan/u-boot.lds @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/luan/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} |