diff options
Diffstat (limited to 'board')
67 files changed, 2846 insertions, 1474 deletions
diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile index b2d7acffe..6a45b7cb2 100644 --- a/board/bf533-ezkit/Makefile +++ b/board/bf533-ezkit/Makefile @@ -35,12 +35,11 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp - mv -f $@.tmp $@ +$(obj)u-boot.lds: u-boot.lds.S + $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk index de80ffe7b..c8b9fb8c1 100644 --- a/board/bf533-ezkit/config.mk +++ b/board/bf533-ezkit/config.mk @@ -1,4 +1,6 @@ # +# Copyright (c) 2005-2008 Analog Device Inc. +# # (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -23,3 +25,9 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me + +LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf533-ezkit/u-boot.lds.S b/board/bf533-ezkit/u-boot.lds.S index 70764acf1..da16726d8 100644 --- a/board/bf533-ezkit/u-boot.lds.S +++ b/board/bf533-ezkit/u-boot.lds.S @@ -28,6 +28,8 @@ #include <config.h> #include <asm/blackfin.h> #undef ALIGN +#undef ENTRY +#undef bfin /* If we don't actually load anything into L1 data, this will avoid * a syntax error. If we do actually load something into L1 data, @@ -50,11 +52,12 @@ MEMORY l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE } +ENTRY(_start) SECTIONS { .text : { - cpu/blackfin/start.o (.text) + cpu/blackfin/start.o (.text .text.*) #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -63,20 +66,20 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/traps.o (.text) - cpu/blackfin/interrupt.o (.text) - cpu/blackfin/serial.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - board/bf533-ezkit/bf533-ezkit.o (.text) + cpu/blackfin/traps.o (.text .text.*) + cpu/blackfin/interrupt.o (.text .text.*) + cpu/blackfin/serial.o (.text .text.*) + common/dlmalloc.o (.text .text.*) + lib_generic/crc32.o (.text .text.*) + lib_generic/zlib.o (.text .text.*) + board/bf533-ezkit/bf533-ezkit.o (.text .text.*) . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text) + common/env_embedded.o (.text .text.*) #endif __initcode_start = .; - cpu/blackfin/initcode.o (.text) + cpu/blackfin/initcode.o (.text .text.*) __initcode_end = .; *(.text .text.*) diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile index 21f6ad1b4..5ae022885 100644 --- a/board/bf533-stamp/Makefile +++ b/board/bf533-stamp/Makefile @@ -35,12 +35,11 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp - mv -f $@.tmp $@ +$(obj)u-boot.lds: u-boot.lds.S + $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk index de80ffe7b..c8b9fb8c1 100644 --- a/board/bf533-stamp/config.mk +++ b/board/bf533-stamp/config.mk @@ -1,4 +1,6 @@ # +# Copyright (c) 2005-2008 Analog Device Inc. +# # (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -23,3 +25,9 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me + +LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf533-stamp/u-boot.lds.S b/board/bf533-stamp/u-boot.lds.S index 187309f3f..76daa75c0 100644 --- a/board/bf533-stamp/u-boot.lds.S +++ b/board/bf533-stamp/u-boot.lds.S @@ -28,6 +28,8 @@ #include <config.h> #include <asm/blackfin.h> #undef ALIGN +#undef ENTRY +#undef bfin /* If we don't actually load anything into L1 data, this will avoid * a syntax error. If we do actually load something into L1 data, @@ -50,11 +52,12 @@ MEMORY l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE } +ENTRY(_start) SECTIONS { .text : { - cpu/blackfin/start.o (.text) + cpu/blackfin/start.o (.text .text.*) #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -63,18 +66,18 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/traps.o (.text) - cpu/blackfin/interrupt.o (.text) - cpu/blackfin/serial.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) + cpu/blackfin/traps.o (.text .text.*) + cpu/blackfin/interrupt.o (.text .text.*) + cpu/blackfin/serial.o (.text .text.*) + common/dlmalloc.o (.text .text.*) + lib_generic/crc32.o (.text .text.*) . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text) + common/env_embedded.o (.text .text.*) #endif __initcode_start = .; - cpu/blackfin/initcode.o (.text) + cpu/blackfin/initcode.o (.text .text.*) __initcode_end = .; *(.text .text.*) diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile index e5481bfc5..e5ef9af5c 100644 --- a/board/bf537-stamp/Makefile +++ b/board/bf537-stamp/Makefile @@ -35,12 +35,11 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp - mv -f $@.tmp $@ +$(obj)u-boot.lds: u-boot.lds.S + $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk index 1b87d53dd..719b97e25 100644 --- a/board/bf537-stamp/config.mk +++ b/board/bf537-stamp/config.mk @@ -1,4 +1,6 @@ # +# Copyright (c) 2005-2008 Analog Device Inc. +# # (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -24,6 +26,9 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me +LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds + # Set some default LDR flags based on boot mode. -LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 +LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf537-stamp/nand.c b/board/bf537-stamp/nand.c index c597f2db1..20a7d0ef4 100644 --- a/board/bf537-stamp/nand.c +++ b/board/bf537-stamp/nand.c @@ -87,7 +87,7 @@ int bfin_device_ready(struct mtd_info *mtd) * Members with a "?" were not set in the merged testing-NAND branch, * so they are not set here either. */ -void board_nand_init(struct nand_chip *nand) +int board_nand_init(struct nand_chip *nand) { *PORT(CONFIG_NAND_GPIO_PORT, _FER) &= ~BFIN_NAND_READY; *PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY; @@ -97,5 +97,7 @@ void board_nand_init(struct nand_chip *nand) nand->ecc.mode = NAND_ECC_SOFT; nand->dev_ready = bfin_device_ready; nand->chip_delay = 30; + + return 0; } #endif diff --git a/board/bf537-stamp/u-boot.lds.S b/board/bf537-stamp/u-boot.lds.S index 187309f3f..76daa75c0 100644 --- a/board/bf537-stamp/u-boot.lds.S +++ b/board/bf537-stamp/u-boot.lds.S @@ -28,6 +28,8 @@ #include <config.h> #include <asm/blackfin.h> #undef ALIGN +#undef ENTRY +#undef bfin /* If we don't actually load anything into L1 data, this will avoid * a syntax error. If we do actually load something into L1 data, @@ -50,11 +52,12 @@ MEMORY l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE } +ENTRY(_start) SECTIONS { .text : { - cpu/blackfin/start.o (.text) + cpu/blackfin/start.o (.text .text.*) #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -63,18 +66,18 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/traps.o (.text) - cpu/blackfin/interrupt.o (.text) - cpu/blackfin/serial.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) + cpu/blackfin/traps.o (.text .text.*) + cpu/blackfin/interrupt.o (.text .text.*) + cpu/blackfin/serial.o (.text .text.*) + common/dlmalloc.o (.text .text.*) + lib_generic/crc32.o (.text .text.*) . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text) + common/env_embedded.o (.text .text.*) #endif __initcode_start = .; - cpu/blackfin/initcode.o (.text) + cpu/blackfin/initcode.o (.text .text.*) __initcode_end = .; *(.text .text.*) diff --git a/board/bf561-ezkit/Makefile b/board/bf561-ezkit/Makefile index a1a4433fc..e7ee24356 100644 --- a/board/bf561-ezkit/Makefile +++ b/board/bf561-ezkit/Makefile @@ -35,12 +35,11 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) u-boot.lds +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) -u-boot.lds: u-boot.lds.S - $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P -Ubfin $^ > $@.tmp - mv -f $@.tmp $@ +$(obj)u-boot.lds: u-boot.lds.S + $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk index de80ffe7b..710809a9e 100644 --- a/board/bf561-ezkit/config.mk +++ b/board/bf561-ezkit/config.mk @@ -1,4 +1,6 @@ # +# Copyright (c) 2005-2008 Analog Device Inc. +# # (C) Copyright 2001 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -23,3 +25,9 @@ # This is not actually used for Blackfin boards so do not change it #TEXT_BASE = do-not-use-me + +LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/board/bf561-ezkit/u-boot.lds.S b/board/bf561-ezkit/u-boot.lds.S index 99d6be634..3d0453e2f 100644 --- a/board/bf561-ezkit/u-boot.lds.S +++ b/board/bf561-ezkit/u-boot.lds.S @@ -28,6 +28,8 @@ #include <config.h> #include <asm/blackfin.h> #undef ALIGN +#undef ENTRY +#undef bfin /* If we don't actually load anything into L1 data, this will avoid * a syntax error. If we do actually load something into L1 data, @@ -50,11 +52,12 @@ MEMORY l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE } +ENTRY(_start) SECTIONS { .text : { - cpu/blackfin/start.o (.text) + cpu/blackfin/start.o (.text .text.*) #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within @@ -63,20 +66,20 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/traps.o (.text) - cpu/blackfin/interrupt.o (.text) - cpu/blackfin/serial.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_generic/zlib.o (.text) - board/bf561-ezkit/bf561-ezkit.o (.text) + cpu/blackfin/traps.o (.text .text.*) + cpu/blackfin/interrupt.o (.text .text.*) + cpu/blackfin/serial.o (.text .text.*) + common/dlmalloc.o (.text .text.*) + lib_generic/crc32.o (.text .text.*) + lib_generic/zlib.o (.text .text.*) + board/bf561-ezkit/bf561-ezkit.o (.text .text.*) . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o (.text) + common/env_embedded.o (.text .text.*) #endif __initcode_start = .; - cpu/blackfin/initcode.o (.text) + cpu/blackfin/initcode.o (.text .text.*) __initcode_end = .; *(.text .text.*) diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile index 3867bd809..7516c2280 100644 --- a/board/esd/cpci405/Makefile +++ b/board/esd/cpci405/Makefile @@ -29,6 +29,7 @@ endif LIB = $(obj)lib$(BOARD).a COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o +COBJS += ../common/cmd_loadpci.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index c5ccb348a..bd569a629 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -20,8 +20,9 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ - #include <common.h> +#include <libfdt.h> +#include <fdt_support.h> #include <asm/processor.h> #include <asm/io.h> #include <command.h> @@ -31,16 +32,16 @@ DECLARE_GLOBAL_DATA_PTR; -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/ -#if 0 -#define FPGA_DEBUG -#endif +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +extern void __ft_board_setup(void *blob, bd_t *bd); + +#undef FPGA_DEBUG /* fpga configuration data - generated by bin2cc */ const unsigned char fpgadata[] = { -#ifdef CONFIG_CPCI405_VER2 -# ifdef CONFIG_CPCI405AB +#if defined(CONFIG_CPCI405_VER2) +# if defined(CONFIG_CPCI405AB) # include "fpgadata_cpci405ab.c" # else # include "fpgadata_cpci4052.c" @@ -56,7 +57,7 @@ const unsigned char fpgadata[] = #include "../common/fpga.c" #include "../common/auto_update.h" -#ifdef CONFIG_CPCI405AB +#if defined(CONFIG_CPCI405AB) au_image_t au_image[] = { {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT}, {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR}, @@ -65,7 +66,7 @@ au_image_t au_image[] = { {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT}, }; #else -#ifdef CONFIG_CPCI405_VER2 +#if defined(CONFIG_CPCI405_VER2) au_image_t au_image[] = { {"cpci4052/preinst.img", 0, -1, AU_SCRIPT}, {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR}, @@ -91,7 +92,7 @@ int cpci405_version(void); int gunzip(void *, int, unsigned char *, unsigned long *); void lxt971_no_sleep(void); -int board_early_init_f (void) +int board_early_init_f(void) { #ifndef CONFIG_CPCI405_VER2 int index, len, i; @@ -100,18 +101,19 @@ int board_early_init_f (void) #ifdef FPGA_DEBUG /* set up serial port with default baudrate */ - (void) get_clocks (); + (void)get_clocks(); gd->baudrate = CONFIG_BAUDRATE; - serial_init (); + serial_init(); console_init_f(); #endif /* - * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) + * First pull fpga-prg pin low, + * to disable fpga logic (on version 2 board) */ out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ - out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ + out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ + out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ out32(GPIO0_OR, 0); /* pull prg low */ /* @@ -124,39 +126,42 @@ int board_early_init_f (void) /* booting FPGA failed */ #ifndef FPGA_DEBUG /* set up serial port with default baudrate */ - (void) get_clocks (); + (void)get_clocks(); gd->baudrate = CONFIG_BAUDRATE; - serial_init (); + serial_init(); console_init_f(); #endif printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + printf("(Timeout: INIT not low after " + "asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + printf("(Timeout: INIT not high after " + "deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); + printf("(Timeout: DONE not high after " + "programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { len = fpgadata[index]; - printf("FPGA: %s\n", &(fpgadata[index+1])); - index += len+3; + printf("FPGA: %s\n", &(fpgadata[index + 1])); + index += len + 3; } - putc ('\n'); + putc('\n'); /* delayed reboot */ - for (i=20; i>0; i--) { + for (i = 20; i > 0; i--) { printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) + for (index = 0; index < 1000; index++) udelay(1000); } - putc ('\n'); + putc('\n'); do_reset(NULL, 0, 0, NULL); } } @@ -167,7 +172,7 @@ int board_early_init_f (void) * IRQ 16 405GP internally generated; active low; level sensitive * IRQ 17-24 RESERVED * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive + * IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052); active low; level sens. * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive @@ -177,7 +182,7 @@ int board_early_init_f (void) mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicer, 0x00000000); /* disable all ints */ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ -#ifdef CONFIG_CPCI405_6U +#if defined(CONFIG_CPCI405_6U) if (cpci405_version() == 3) { mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ } else { @@ -187,21 +192,20 @@ int board_early_init_f (void) mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ #endif mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicvcr, 0x00000001); /* set vect base=0, + * INT0 highest priority */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ return 0; } -/* ------------------------------------------------------------------------- */ - int ctermm2(void) { -#ifdef CONFIG_CPCI405_VER2 +#if defined(CONFIG_CPCI405_VER2) return 0; /* no, board is cpci405 */ #else - if ((*(unsigned char *)0xf0000400 == 0x00) && - (*(unsigned char *)0xf0000401 == 0x01)) + if ((in_8((void*)0xf0000400) == 0x00) && + (in_8((void*)0xf0000401) == 0x01)) return 0; /* no, board is cpci405 */ else return -1; /* yes, board is cterm-m2 */ @@ -228,8 +232,8 @@ int cpci405_version(void) mtdcr(cntrl0, cntrl0Reg | 0x03000000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); - udelay(1000); /* wait some time before reading input */ - value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ + udelay(1000); /* wait some time before reading input */ + value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ /* * Restore GPIO settings @@ -263,7 +267,7 @@ int misc_init_r (void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; -#ifdef CONFIG_CPCI405_VER2 +#if defined(CONFIG_CPCI405_VER2) { unsigned char *dst; ulong len = sizeof(fpgadata); @@ -283,9 +287,10 @@ int misc_init_r (void) mtdcr(cntrl0, cntrl0Reg | 0x00300000); dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); + if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, + (uchar *)fpgadata, &len) != 0) { + printf("GUNZIP ERROR - must RESET board to recover\n"); + do_reset(NULL, 0, 0, NULL); } status = fpga_boot(dst, len); @@ -293,31 +298,34 @@ int misc_init_r (void) printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + printf("(Timeout: INIT not low after " + "asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + printf("(Timeout: INIT not high after " + "deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); + printf("(Timeout: DONE not high after " + "programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; + printf("FPGA: %s\n", &(dst[index + 1])); + index += len + 3; } - putc ('\n'); + putc('\n'); /* delayed reboot */ - for (i=20; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) + for (i = 20; i > 0; i--) { + printf("Rebooting in %2d seconds \r", i); + for (index = 0; index < 1000; index++) udelay(1000); } - putc ('\n'); + putc('\n'); do_reset(NULL, 0, 0, NULL); } @@ -328,12 +336,12 @@ int misc_init_r (void) /* display infos on fpgaimage */ index = 15; - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; + printf("%s ", &(dst[index + 1])); + index += len + 3; } - putc ('\n'); + putc('\n'); free(dst); @@ -345,68 +353,48 @@ int misc_init_r (void) SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); udelay(1000); /* wait 1ms */ -#ifdef CONFIG_CPCI405_6U +#if defined(CONFIG_CPCI405_6U) +#error HIER GETH ES WEITER MIT IO ACCESSORS if (cpci405_version() == 3) { - volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR; - volatile unsigned char *leds = (unsigned char *)CONFIG_SYS_LED_ADDR; - /* * Enable outputs in fpga on version 3 board */ - *fpga_mode |= CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT; + out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, + in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | + CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT); /* * Set outputs to 0 */ - *leds = 0x00; + out_8((void*)CONFIG_SYS_LED_ADDR, 0x00); /* * Reset external DUART */ - *fpga_mode |= CONFIG_SYS_FPGA_MODE_DUART_RESET; + out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, + in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | + CONFIG_SYS_FPGA_MODE_DUART_RESET); udelay(100); - *fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_DUART_RESET); + out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, + in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) & + ~CONFIG_SYS_FPGA_MODE_DUART_RESET); } #endif } else { puts("\n*** U-Boot Version does not match Board Version!\n"); puts("*** CPCI-405 Version 1.x detected!\n"); - puts("*** Please use correct U-Boot version (CPCI405 instead of CPCI4052)!\n\n"); + puts("*** Please use correct U-Boot version " + "(CPCI405 instead of CPCI4052)!\n\n"); } } - #else /* CONFIG_CPCI405_VER2 */ - -#if 0 /* test-only: code-plug now not relavant for ip-address any more */ - /* - * Generate last byte of ip-addr from code-plug @ 0xf0000400 - */ - if (ctermm2()) { - char str[32]; - unsigned char ipbyte = *(unsigned char *)0xf0000400; - - /* - * Only overwrite ip-addr with allowed values - */ - if ((ipbyte != 0x00) && (ipbyte != 0xff)) { - bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte; - sprintf(str, "%ld.%ld.%ld.%ld", - (bd->bi_ip_addr & 0xff000000) >> 24, - (bd->bi_ip_addr & 0x00ff0000) >> 16, - (bd->bi_ip_addr & 0x0000ff00) >> 8, - (bd->bi_ip_addr & 0x000000ff)); - setenv("ipaddr", str); - } - } -#endif - if (cpci405_version() >= 2) { puts("\n*** U-Boot Version does not match Board Version!\n"); puts("*** CPCI-405 Board Version 2.x detected!\n"); - puts("*** Please use correct U-Boot version (CPCI4052 instead of CPCI405)!\n\n"); + puts("*** Please use correct U-Boot version " + "(CPCI4052 instead of CPCI405)!\n\n"); } - #endif /* CONFIG_CPCI405_VER2 */ /* @@ -415,46 +403,33 @@ int misc_init_r (void) cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x00001000); - return (0); + return 0; } /* * Check Board Identity: */ -int checkboard (void) +int checkboard(void) { #ifndef CONFIG_CPCI405_VER2 int index; int len; #endif char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_r("serial#", str, sizeof(str)); unsigned short ver; - puts ("Board: "); + puts("Board: "); - if (i == -1) { - puts ("### No HW ID - assuming CPCI405"); - } else { + if (i == -1) + puts("### No HW ID - assuming CPCI405"); + else puts(str); - } ver = cpci405_version(); printf(" (Ver %d.x, ", ver); -#if 0 /* test-only */ - if (ver >= 2) { - volatile u16 *fpga_status = (u16 *)CONFIG_SYS_FPGA_BASE_ADDR + 1; - - if (*fpga_status & CONFIG_SYS_FPGA_STATUS_FLASH) { - puts ("FLASH Bank B, "); - } else { - puts ("FLASH Bank A, "); - } - } -#endif - if (ctermm2()) { char str[4]; @@ -465,32 +440,31 @@ int checkboard (void) setenv("boardid", str); printf("CTERM-M2 - Id=%s)", str); } else { - if (cpci405_host()) { - puts ("PCI Host Version)"); - } else { - puts ("PCI Adapter Version)"); - } + if (cpci405_host()) + puts("PCI Host Version)"); + else + puts("PCI Adapter Version)"); } #ifndef CONFIG_CPCI405_VER2 - puts ("\nFPGA: "); + puts("\nFPGA: "); /* display infos on fpgaimage */ index = 15; - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { len = fpgadata[index]; - printf("%s ", &(fpgadata[index+1])); - index += len+3; + printf("%s ", &(fpgadata[index + 1])); + index += len + 3; } #endif - putc ('\n'); + putc('\n'); return 0; } void reset_phy(void) { -#ifdef CONFIG_LXT971_NO_SLEEP +#if defined(CONFIG_LXT971_NO_SLEEP) /* * Disable sleep mode in LXT971 @@ -499,25 +473,24 @@ void reset_phy(void) #endif } -#ifdef CONFIG_CPCI405_VER2 -#ifdef CONFIG_IDE_RESET - +#if defined(CONFIG_CPCI405_VER2) && defined (CONFIG_IDE_RESET) void ide_set_reset(int on) { - volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR; - /* * Assert or deassert CompactFlash Reset Pin */ - if (on) { /* assert RESET */ - *fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_CF_RESET); - } else { /* release RESET */ - *fpga_mode |= CONFIG_SYS_FPGA_MODE_CF_RESET; + if (on) { /* assert RESET */ + out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, + in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) & + ~CONFIG_SYS_FPGA_MODE_CF_RESET); + } else { /* release RESET */ + out_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR, + in_be16((void*)CONFIG_SYS_FPGA_BASE_ADDR) | + CONFIG_SYS_FPGA_MODE_CF_RESET); } } -#endif /* CONFIG_IDE_RESET */ -#endif /* CONFIG_CPCI405_VER2 */ +#endif /* CONFIG_IDE_RESET && CONFIG_CPCI405_VER2 */ #if defined(CONFIG_PCI) void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) @@ -552,15 +525,44 @@ int pci_pre_init(struct pci_controller *hose) } #endif /* defined(CONFIG_PCI) */ +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + int rc; + + __ft_board_setup(blob, bd); + + /* + * Disable PCI in adapter mode. + */ + if (!cpci405_host()) { + rc = fdt_find_and_setprop(blob, "/plb/pci@ec000000", "status", + "disabled", sizeof("disabled"), 1); + if (rc) { + printf("Unable to update property status in PCI node, " + "err=%s\n", + fdt_strerror(rc)); + } + } +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +#if defined(CONFIG_CPCI405AB) +#define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ + CONFIG_SYS_FPGA_MODE), \ + in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ + CONFIG_SYS_FPGA_MODE)) | \ + CONFIG_SYS_FPGA_MODE_1WIRE_DIR) -#ifdef CONFIG_CPCI405AB +#define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ + CONFIG_SYS_FPGA_MODE), \ + in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ + CONFIG_SYS_FPGA_MODE)) & \ + ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \ - |= CONFIG_SYS_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_SET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \ - &= ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_GET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_STATUS) \ - & CONFIG_SYS_FPGA_MODE_1WIRE) +#define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \ + CONFIG_SYS_FPGA_STATUS)) & \ + CONFIG_SYS_FPGA_MODE_1WIRE) /* * Generate a 1-wire reset, return 1 if no presence detect was found, @@ -630,7 +632,7 @@ void OWWriteByte(int data) { int loop; - for (loop=0; loop<8; loop++) { + for (loop = 0; loop < 8; loop++) { OWWriteBit(data & 0x01); data >>= 1; } @@ -640,11 +642,10 @@ int OWReadByte(void) { int loop, result = 0; - for (loop=0; loop<8; loop++) { + for (loop = 0; loop < 8; loop++) { result >>= 1; - if (OWReadBit()) { + if (OWReadBit()) result |= 0x80; - } } return result; @@ -652,7 +653,7 @@ int OWReadByte(void) int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - volatile unsigned short val; + unsigned short val; int result; int i; unsigned char ow_id[6]; @@ -662,23 +663,25 @@ int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* * Clear 1-wire bit (open drain with pull-up) */ - val = *(volatile unsigned short *)0xf0400000; - val &= ~0x1000; /* clear 1-wire bit */ - *(volatile unsigned short *)0xf0400000 = val; + val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + + CONFIG_SYS_FPGA_MODE)); + val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */ + out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + + CONFIG_SYS_FPGA_MODE), val); result = OWTouchReset(); - if (result != 0) { + if (result != 0) puts("No 1-wire device detected!\n"); - } OWWriteByte(0x33); /* send read rom command */ OWReadByte(); /* skip family code ( == 0x01) */ - for (i=0; i<6; i++) { + for (i = 0; i < 6; i++) ow_id[i] = OWReadByte(); - } ow_crc = OWReadByte(); /* read crc */ - sprintf(str, "%08X%04X", *(unsigned int *)&ow_id[0], *(unsigned short *)&ow_id[4]); + sprintf(str, "%08X%04X", + *(unsigned int *)&ow_id[0], + *(unsigned short *)&ow_id[4]); printf("Setting environment variable 'ow_id' to %s\n", str); setenv("ow_id", str); @@ -690,8 +693,8 @@ U_BOOT_CMD( NULL ); -#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */ -#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/ +#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */ +#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */ /* * Write backplane ip-address... @@ -706,12 +709,14 @@ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) IPaddr_t ipaddr; buf = malloc(CONFIG_ENV_SIZE_2); - if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) { + if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, + (uchar *)buf, CONFIG_ENV_SIZE_2)) puts("\nError reading backplane EEPROM!\n"); - } else { - crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4); + else { + crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4); if (crc != *(ulong *)buf) { - printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf); + printf("ERROR: crc mismatch %08lx %08lx\n", + crc, *(ulong *)buf); return -1; } @@ -768,12 +773,12 @@ int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) memset(buf, 0, CONFIG_ENV_SIZE_2); sprintf(str, "bp_ip=%s", argv[1]); strcpy(buf+4, str); - crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4); + crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4); *(ulong *)buf = crc; - if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) { + if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, + 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) puts("\nError writing backplane EEPROM!\n"); - } free(buf); diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index 61186a8d7..85057a268 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -104,6 +104,7 @@ int misc_init_r (void) unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); unsigned char *dst; + unsigned char fctr; ulong len = sizeof(fpgadata); int status; int index; @@ -203,6 +204,15 @@ int misc_init_r (void) out_8(duart0_mcr, 0x08); out_8(duart1_mcr, 0x08); + /* + * Enable auto RS485 mode in 2nd external uart + */ + out_8((void *)DUART1_BA + 3, 0xbf); /* write LCR */ + fctr = in_8((void *)DUART1_BA + 1); /* read FCTR */ + fctr |= 0x08; /* enable RS485 mode */ + out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */ + out_8((void *)DUART1_BA + 3, 0); /* write LCR */ + return (0); } diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index a0b6fbd12..9e3f67768 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -133,7 +133,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 7e40c5c80..e6025c8a5 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -308,7 +308,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 14581abdd..977731289 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -121,7 +121,7 @@ pci_init_board(void) volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; struct pci_controller *hose = &pcie3_hose; int pcie_ep = (host_agent == 1); - int pcie_configured = io_sel >= 1; + int pcie_configured = io_sel >= 6; struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -188,7 +188,7 @@ pci_init_board(void) volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 5); - int pcie_configured = io_sel & 6; + int pcie_configured = io_sel >= 2; struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -251,7 +251,7 @@ pci_init_board(void) volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; int pcie_ep = (host_agent == 3); - int pcie_configured = io_sel & 4; + int pcie_configured = io_sel >= 4; struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index c562fc9d9..90e89bc71 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -125,7 +125,7 @@ local_bus_init(void) sys_info_t sysinfo; get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & 0x0f) * 2; + clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 33685c19f..53d5a936a 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -308,7 +308,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 37308189d..ac7778e25 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -337,7 +337,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index bc93be80f..7a23b338a 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -188,7 +188,7 @@ local_bus_init(void) sys_info_t sysinfo; get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & 0x0f) * 2; + clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index a14db5ad2..c2487e5b8 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -166,11 +166,11 @@ void pci_init_board(void) struct pci_controller *hose = &pcie3_hose; int pcie_ep = (host_agent == 0) || (host_agent == 3) || (host_agent == 5) || (host_agent == 6); - int pcie_configured = io_sel >= 1; + int pcie_configured = (io_sel == 0x7); struct pci_region *r = hose->regions; u32 temp32; - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ printf ("\n PCIE3 connected to ULI as %s (base address %x)", pcie_ep ? "End Point" : "Root Complex", (uint)pci); @@ -234,10 +234,10 @@ void pci_init_board(void) struct pci_controller *hose = &pcie2_hose; int pcie_ep = (host_agent == 2) || (host_agent == 4) || (host_agent == 6) || (host_agent == 0); - int pcie_configured = io_sel & 4; + int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7); struct pci_region *r = hose->regions; - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", pcie_ep ? "End Point" : "Root Complex", (uint)pci); @@ -287,7 +287,9 @@ void pci_init_board(void) struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5); - int pcie_configured = io_sel & 6; + int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) || + (io_sel == 0x7) || (io_sel == 0xb) || + (io_sel == 0xc) || (io_sel == 0xf); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index 8d1f646fa..829896ac0 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -41,10 +41,6 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 0), - /* TLB 1 */ /* *I*** - Covers boot page */ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, @@ -86,6 +82,9 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_4K, 1), }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c index 2aad28aee..0fc838484 100644 --- a/board/freescale/mpc8610hpcd/law.c +++ b/board/freescale/mpc8610hpcd/law.c @@ -31,8 +31,8 @@ struct law_entry law_table[] = { #if !defined(CONFIG_SPD_EEPROM) SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1), #endif - SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2), diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 2792778e3..a2097a5af 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -266,14 +266,14 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); @@ -321,14 +321,14 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_BUS, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BASE, + CONFIG_SYS_PCIE2_IO_BUS, CONFIG_SYS_PCIE2_IO_PHYS, CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); @@ -370,14 +370,14 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); diff --git a/board/m501sk/Makefile b/board/m501sk/Makefile index c562c600a..aec3d1c7c 100644 --- a/board/m501sk/Makefile +++ b/board/m501sk/Makefile @@ -27,8 +27,6 @@ LIB = $(obj)lib$(BOARD).a COBJS := m501sk.o eeprom.o -SOBJS := memsetup.o - SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/m501sk/memsetup.S b/board/m501sk/memsetup.S deleted file mode 100644 index 6aea723f9..000000000 --- a/board/m501sk/memsetup.S +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the at91rm9200dk board by - * (C) Copyright 2004 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> - -#ifdef CONFIG_BOOTBINFUNC -/* - * some parameters for the board - * - * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in - * turn is based on the boot.bin code from ATMEL - * - */ - -/* flash */ -#define MC_PUIA 0xFFFFFF10 -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP 0xFFFFFF50 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER 0xFFFFFF54 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR 0xFFFFFF04 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR 0xFFFFFF08 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR 0xFFFFFF64 -#define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0 0xFFFFFF70 -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define PLLAR 0xFFFFFC28 -#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ -#define PLLBR 0xFFFFFC2C -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -#define MCKR 0xFFFFFC30 -/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ -#define MCKR_VAL 0x00000202 - -/* sdram */ -#define PIOC_ASR 0xFFFFF870 -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */ -#define PIOC_BSR 0xFFFFF874 -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR 0xFFFFF804 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA 0xFFFFFF60 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR 0xFFFFFF98 -#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR 0xFFFFFF90 -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR 0xFFFFFF94 -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ - -_TEXT_BASE: - .word TEXT_BASE - -.globl lowlevelinit -lowlevelinit: - /* memory control configuration */ - /* this isn't very elegant, but what the heck */ - ldr r0, =SMRDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - add r2, r0, #80 -0: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 0b - /* delay - this is all done by guess */ - ldr r0, =0x00010000 -1: - subs r0, r0, #1 - bhi 1b - ldr r0, =SMRDATA1 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - add r2, r0, #176 -2: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 2b - - /* everything is fine now */ - mov pc, lr - - .ltorg - -SMRDATA: - .word MC_PUIA - .word MC_PUIA_VAL - .word MC_PUP - .word MC_PUP_VAL - .word MC_PUER - .word MC_PUER_VAL - .word MC_ASR - .word MC_ASR_VAL - .word MC_AASR - .word MC_AASR_VAL - .word EBI_CFGR - .word EBI_CFGR_VAL - .word SMC_CSR0 - .word SMC_CSR0_VAL - .word PLLAR - .word PLLAR_VAL - .word PLLBR - .word PLLBR_VAL - .word MCKR - .word MCKR_VAL - /* SMRDATA is 80 bytes long */ - /* here there's a delay of 100 */ -SMRDATA1: - .word PIOC_ASR - .word PIOC_ASR_VAL - .word PIOC_BSR - .word PIOC_BSR_VAL - .word PIOC_PDR - .word PIOC_PDR_VAL - .word EBI_CSA - .word EBI_CSA_VAL - .word SDRC_CR - .word SDRC_CR_VAL - .word SDRC_MR - .word SDRC_MR_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRC_MR - .word SDRC_MR_VAL1 - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRC_MR - .word SDRC_MR_VAL2 - .word SDRAM1 - .word SDRAM_VAL - .word SDRC_TR - .word SDRC_TR_VAL - .word SDRAM - .word SDRAM_VAL - .word SDRC_MR - .word SDRC_MR_VAL3 - .word SDRAM - .word SDRAM_VAL - /* SMRDATA1 is 176 bytes long */ -#endif /* CONFIG_BOOTBINFUNC */ diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index fa0a33686..bf270f4ce 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -101,7 +101,7 @@ phys_size_t initdram (int board_type) #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ get_sys_info(&sysinfo); /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ - if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) { + if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) { lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000; } else { lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff; diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S index 060957ad0..5f02bd4bb 100644 --- a/board/mpr2/lowlevel_init.S +++ b/board/mpr2/lowlevel_init.S @@ -22,6 +22,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ +#include <asm/macro.h> .global lowlevel_init @@ -33,59 +34,35 @@ lowlevel_init: /* * Set frequency multipliers and dividers in FRQCR. */ - mov.l WTCSR_A,r1 - mov.l WTCSR_D,r0 - mov.w r0,@r1 + write16 WTCSR_A, WTCSR_D - mov.l WTCNT_A,r1 - mov.l WTCNT_D,r0 - mov.w r0,@r1 + write16 WTCNT_A, WTCNT_D - mov.l FRQCR_A,r1 - mov.l FRQCR_D,r0 - mov.w r0,@r1 + write16 FRQCR_A, FRQCR_D /* * Setup CS0 (Flash). */ - mov.l CS0BCR_A, r1 - mov.l CS0BCR_D, r0 - mov.l r0, @r1 + write32 CS0BCR_A, CS0BCR_D - mov.l CS0WCR_A, r1 - mov.l CS0WCR_D, r0 - mov.l r0, @r1 + write32 CS0WCR_A, CS0WCR_D /* * Setup CS3 (SDRAM). */ - mov.l CS3BCR_A, r1 - mov.l CS3BCR_D, r0 - mov.l r0, @r1 + write32 CS3BCR_A, CS3BCR_D - mov.l CS3WCR_A, r1 - mov.l CS3WCR_D, r0 - mov.l r0, @r1 + write32 CS3WCR_A, CS3WCR_D - mov.l SDCR_A, r1 - mov.l SDCR_D1, r0 - mov.l r0, @r1 + write32 SDCR_A, SDCR_D1 - mov.l RTCSR_A, r1 - mov.l RTCSR_D, r0 - mov.l r0, @r1 + write32 RTCSR_A, RTCSR_D - mov.l RTCNT_A, r1 - mov.l RTCNT_D, r0 - mov.l r0, @r1 + write32 RTCNT_A, RTCNT_D - mov.l RTCOR_A, r1 - mov.l RTCOR_D, r0 - mov.l r0, @r1 + write32 RTCOR_A, RTCOR_D - mov.l SDCR_A, r1 - mov.l SDCR_D2, r0 - mov.l r0, @r1 + write32 SDCR_A, SDCR_D2 mov.l SDMR3_A, r1 mov.l SDMR3_D, r0 @@ -112,21 +89,27 @@ WTCSR_D: .long 0xA507 /* divide by 4096 */ /* * Spansion S29GL256N11 @ 48 MHz */ -CS0BCR_D: .long 0x12490400 /* 1 idle cycle inserted, normal space, 16 bit */ -CS0WCR_D: .long 0x00000340 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ +/* 1 idle cycle inserted, normal space, 16 bit */ +CS0BCR_D: .long 0x12490400 +/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ +CS0WCR_D: .long 0x00000340 /* * Samsung K4S511632B-UL75 @ 48 MHz * Micron MT48LC32M16A2-75 @ 48 MHz */ -CS3BCR_D: .long 0x10004400 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ -CS3WCR_D: .long 0x00000091 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ -SDCR_D1: .long 0x00000012 /* no refresh, 13 rows, 10 cols, NO bank active mode */ -SDCR_D2: .long 0x00000812 /* refresh */ -RTCSR_D: .long 0xA55A0008 /* 1/4, once */ -RTCNT_D: .long 0xA55A005D /* count 93 */ -RTCOR_D: .long 0xa55a005d /* count 93 */ -SDMR3_D: .long 0x440 /* mode register CL2, burst read and SINGLE WRITE */ +/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ +CS3BCR_D: .long 0x10004400 +/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ +CS3WCR_D: .long 0x00000091 +/* no refresh, 13 rows, 10 cols, NO bank active mode */ +SDCR_D1: .long 0x00000012 +SDCR_D2: .long 0x00000812 /* refresh */ +RTCSR_D: .long 0xA55A0008 /* 1/4, once */ +RTCNT_D: .long 0xA55A005D /* count 93 */ +RTCOR_D: .long 0xa55a005d /* count 93 */ +/* mode register CL2, burst read and SINGLE WRITE */ +SDMR3_D: .long 0x440 /* * Registers diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S index 8b46595f3..1cb57e72e 100644 --- a/board/ms7722se/lowlevel_init.S +++ b/board/ms7722se/lowlevel_init.S @@ -27,13 +27,14 @@ #include <version.h> #include <asm/processor.h> +#include <asm/macro.h> /* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. * - * (Note: As no stack is available, no subroutines can be called...). + * (Note: As no stack is available, no subroutines can be called...). */ .global lowlevel_init @@ -43,167 +44,96 @@ lowlevel_init: - /* Address of Cache Control Register */ - mov.l CCR_A, r1 - /*Instruction Cache Invalidate */ - mov.l CCR_D, r0 - mov.l r0, @r1 + /* + * Cache Control Register + * Instruction Cache Invalidate + */ + write32 CCR_A, CCR_D - /* Address of MMU Control Register */ - mov.l MMUCR_A, r1 - /* TI == TLB Invalidate bit */ - mov.l MMUCR_D, r0 - mov.l r0, @r1 + /* + * Address of MMU Control Register + * TI == TLB Invalidate bit + */ + write32 MMUCR_A, MMUCR_D /* Address of Power Control Register 0 */ - mov.l MSTPCR0_A, r1 - mov.l MSTPCR0_D, r0 - mov.l r0, @r1 + write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 2 */ - mov.l MSTPCR2_A, r1 - mov.l MSTPCR2_D, r0 - mov.l r0, @r1 + write32 MSTPCR2_A, MSTPCR2_D - mov.l SBSCR_A, r1 - mov.w SBSCR_D, r0 - mov.w r0, @r1 + write16 SBSCR_A, SBSCR_D - mov.l PSCR_A, r1 - mov.w PSCR_D, r0 - mov.w r0, @r1 + write16 PSCR_A, PSCR_D /* 0xA4520004 (Watchdog Control / Status Register) */ -! mov.l RWTCSR_A, r1 - /* 0xA507 -> timer_STOP/WDT_CLK=max */ -! mov.w RWTCSR_D_1, r0 -! mov.w r0, @r1 +! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */ /* 0xA4520000 (Watchdog Count Register) */ - mov.l RWTCNT_A, r1 - /*0x5A00 -> Clear */ - mov.w RWTCNT_D, r0 - mov.w r0, @r1 + write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */ /* 0xA4520004 (Watchdog Control / Status Register) */ - mov.l RWTCSR_A, r1 - /* 0xA504 -> timer_STOP/CLK=500ms */ - mov.w RWTCSR_D_2, r0 - mov.w r0, @r1 + write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */ /* 0xA4150000 Frequency control register */ - mov.l FRQCR_A, r1 - mov.l FRQCR_D, r0 ! - mov.l r0, @r1 + write32 FRQCR_A, FRQCR_D - mov.l CCR_A, r1 - mov.l CCR_D_2, r0 - mov.l r0, @r1 + write32 CCR_A, CCR_D_2 bsc_init: - mov.l PSELA_A, r1 - mov.w PSELA_D, r0 - mov.w r0, @r1 + write16 PSELA_A, PSELA_D - mov.l DRVCR_A, r1 - mov.w DRVCR_D, r0 - mov.w r0, @r1 + write16 DRVCR_A, DRVCR_D - mov.l PCCR_A, r1 - mov.w PCCR_D, r0 - mov.w r0, @r1 + write16 PCCR_A, PCCR_D - mov.l PECR_A, r1 - mov.w PECR_D, r0 - mov.w r0, @r1 + write16 PECR_A, PECR_D - mov.l PJCR_A, r1 - mov.w PJCR_D, r0 - mov.w r0, @r1 + write16 PJCR_A, PJCR_D - mov.l PXCR_A, r1 - mov.w PXCR_D, r0 - mov.w r0, @r1 + write16 PXCR_A, PXCR_D - mov.l CMNCR_A, r1 ! CMNCR address -> R1 - mov.l CMNCR_D, r0 ! CMNCR data -> R0 - mov.l r0, @r1 ! CMNCR set + write32 CMNCR_A, CMNCR_D - mov.l CS0BCR_A, r1 ! CS0BCR address -> R1 - mov.l CS0BCR_D, r0 ! CS0BCR data -> R0 - mov.l r0, @r1 ! CS0BCR set + write32 CS0BCR_A, CS0BCR_D - mov.l CS2BCR_A, r1 ! CS2BCR address -> R1 - mov.l CS2BCR_D, r0 ! CS2BCR data -> R0 - mov.l r0, @r1 ! CS2BCR set + write32 CS2BCR_A, CS2BCR_D - mov.l CS4BCR_A, r1 ! CS4BCR address -> R1 - mov.l CS4BCR_D, r0 ! CS4BCR data -> R0 - mov.l r0, @r1 ! CS4BCR set + write32 CS4BCR_A, CS4BCR_D - mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1 - mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0 - mov.l r0, @r1 ! CS5ABCR set + write32 CS5ABCR_A, CS5ABCR_D - mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1 - mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0 - mov.l r0, @r1 ! CS5BBCR set + write32 CS5BBCR_A, CS5BBCR_D - mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1 - mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0 - mov.l r0, @r1 ! CS6ABCR set + write32 CS6ABCR_A, CS6ABCR_D - mov.l CS0WCR_A, r1 ! CS0WCR address -> R1 - mov.l CS0WCR_D, r0 ! CS0WCR data -> R0 - mov.l r0, @r1 ! CS0WCR set + write32 CS0WCR_A, CS0WCR_D - mov.l CS2WCR_A, r1 ! CS2WCR address -> R1 - mov.l CS2WCR_D, r0 ! CS2WCR data -> R0 - mov.l r0, @r1 ! CS2WCR set + write32 CS2WCR_A, CS2WCR_D - mov.l CS4WCR_A, r1 ! CS4WCR address -> R1 - mov.l CS4WCR_D, r0 ! CS4WCR data -> R0 - mov.l r0, @r1 ! CS4WCR set + write32 CS4WCR_A, CS4WCR_D - mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1 - mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0 - mov.l r0, @r1 ! CS5AWCR set + write32 CS5AWCR_A, CS5AWCR_D - mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1 - mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0 - mov.l r0, @r1 ! CS5BWCR set + write32 CS5BWCR_A, CS5BWCR_D - mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1 - mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0 - mov.l r0, @r1 ! CS6AWCR set + write32 CS6AWCR_A, CS6AWCR_D ! SDRAM initialization - mov.l SDCR_A, r1 ! SB_SDCR address -> R1 - mov.l SDCR_D, r0 ! SB_SDCR data -> R0 - mov.l r0, @r1 ! SB_SDCR set + write32 SDCR_A, SDCR_D - mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1 - mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0 - mov.l r0, @r1 ! SB_SDWCR set + write32 SDWCR_A, SDWCR_D - mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1 - mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0 - mov.l r0, @r1 ! SB_SDPCR set + write32 SDPCR_A, SDPCR_D - mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1 - mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0 - mov.l r0, @r1 ! SB_RTCOR set + write32 RTCOR_A, RTCOR_D - mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1 - mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0 - mov.l r0, @r1 ! SB_RTCSR set + write32 RTCSR_A, RTCSR_D - mov.l SDMR3_A, r1 ! SDMR3 address -> R1 - mov #0x00, r0 ! SDMR3 data -> R0 - mov.b r0, @r1 ! SDMR3 set + write8 SDMR3_A, SDMR3_D - ! BL bit off (init = ON) (?!?) + ! BL bit off (init = ON) (?!?) stc sr, r0 ! BL bit off(init=ON) mov.l SR_MASK_D, r1 @@ -232,28 +162,28 @@ MSTPCR0_D: .long 0x00001001 MSTPCR2_D: .long 0xffffffff FRQCR_D: .long 0x07022538 -PSELA_A: .long 0xa405014E -PSELA_D: .word 0x0A10 +PSELA_A: .long 0xa405014E +PSELA_D: .word 0x0A10 .align 2 -DRVCR_A: .long 0xa405018A -DRVCR_D: .word 0x0554 +DRVCR_A: .long 0xa405018A +DRVCR_D: .word 0x0554 .align 2 -PCCR_A: .long 0xa4050104 -PCCR_D: .word 0x8800 +PCCR_A: .long 0xa4050104 +PCCR_D: .word 0x8800 .align 2 -PECR_A: .long 0xa4050108 -PECR_D: .word 0x0000 +PECR_A: .long 0xa4050108 +PECR_D: .word 0x0000 .align 2 -PJCR_A: .long 0xa4050110 -PJCR_D: .word 0x1000 +PJCR_A: .long 0xa4050110 +PJCR_D: .word 0x1000 .align 2 -PXCR_A: .long 0xa4050148 -PXCR_D: .word 0x0AAA +PXCR_A: .long 0xa4050148 +PXCR_D: .word 0x0AAA .align 2 CMNCR_A: .long CMNCR @@ -295,6 +225,7 @@ RTCOR_D: .long 0xA55A0034 RTCSR_A: .long SBSC_RTCSR RTCSR_D: .long 0xA55A0010 SDMR3_A: .long 0xFE500180 +SDMR3_D: .long 0x0 .align 1 diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S index d3e3cd5e8..5e09a39ba 100644 --- a/board/ms7750se/lowlevel_init.S +++ b/board/ms7750se/lowlevel_init.S @@ -29,120 +29,94 @@ #include <version.h> #include <asm/processor.h> +#include <asm/macro.h> #ifdef CONFIG_CPU_SH7751 -#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ -#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ +#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */ +#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */ #ifdef CONFIG_MARUBUN_PCCARD -#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 - A3:2 A2:15 A1:15 A0:6 A0B:7 */ +#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15 + A3:2 A2:15 A1:15 A0:6 A0B:7 */ #else /* CONFIG_MARUBUN_PCCARD */ -#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 - A3:2 A2:15 A1:15 A0:6 A0B:7 */ +#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15 + A3:2 A2:15 A1:15 A0:6 A0B:7 */ #endif /* CONFIG_MARUBUN_PCCARD */ -#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 - A2: 1-3 A1: 1-3 A0: 0-1 */ -#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ -#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ -#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */ -#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ +#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3 + A2: 1-3 A1: 1-3 A0: 0-1 */ +#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */ +#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */ +#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */ +#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */ #else /* CONFIG_CPU_SH7751 */ -#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ -#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ -#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 - A3:2 A2:15 A1:15 A0:15 A0B:7 */ -#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 - A2: 1-3 A1: 1-3 A0: 0-1 */ -#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ -#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ -#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */ -#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ +#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */ +#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */ +#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15 + A3:2 A2:15 A1:15 A0:15 A0B:7 */ +#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3 + A2: 1-3 A1: 1-3 A0: 0-1 */ +#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */ +#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */ +#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */ +#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */ #endif /* CONFIG_CPU_SH7751 */ .global lowlevel_init .text - .align 2 + .align 2 lowlevel_init: - mov.l CCR_A, r1 ! CCR Address - mov.l CCR_D_DISABLE, r0 ! CCR Data - mov.l r0, @r1 + write32 CCR_A, CCR_D_DISABLE init_bsc: - mov.l FRQCR_A,r1 /* FRQCR Address */ - mov.l FRQCR_D,r0 /* FRQCR Data */ - mov.w r0,@r1 + write16 FRQCR_A, FRQCR_D - mov.l BCR1_A,r1 /* BCR1 Address */ - mov.l BCR1_D,r0 /* BCR1 Data */ - mov.l r0,@r1 + write32 BCR1_A, BCR1_D - mov.l BCR2_A,r1 /* BCR2 Address */ - mov.l BCR2_D,r0 /* BCR2 Data */ - mov.w r0,@r1 + write16 BCR2_A, BCR2_D - mov.l WCR1_A,r1 /* WCR1 Address */ - mov.l WCR1_D,r0 /* WCR1 Data */ - mov.l r0,@r1 + write32 WCR1_A, WCR1_D - mov.l WCR2_A,r1 /* WCR2 Address */ - mov.l WCR2_D,r0 /* WCR2 Data */ - mov.l r0,@r1 + write32 WCR2_A, WCR2_D - mov.l WCR3_A,r1 /* WCR3 Address */ - mov.l WCR3_D,r0 /* WCR3 Data */ - mov.l r0,@r1 + write32 WCR3_A, WCR3_D - mov.l MCR_A,r1 /* MCR Address */ - mov.l MCR_D1,r0 /* MCR Data1 */ - mov.l r0,@r1 + write32 MCR_A, MCR_D1 - mov.l SDMR3_A,r1 /* Set SDRAM mode */ - mov #0,r0 - mov.b r0,@r1 + /* Set SDRAM mode */ + write8 SDMR3_A, SDMR3_D ! Do you need PCMCIA setting? ! If so, please add the lines here... - mov.l RTCNT_A,r1 /* RTCNT Address */ - mov.l RTCNT_D,r0 /* RTCNT Data */ - mov.w r0,@r1 + write16 RTCNT_A, RTCNT_D + + write16 RTCOR_A, RTCOR_D - mov.l RTCOR_A,r1 /* RTCOR Address */ - mov.l RTCOR_D,r0 /* RTCOR Data */ - mov.w r0,@r1 + write16 RTCSR_A, RTCSR_D - mov.l RTCSR_A,r1 /* RTCSR Address */ - mov.l RTCSR_D,r0 /* RTCSR Data */ - mov.w r0,@r1 + write16 RFCR_A, RFCR_D - mov.l RFCR_A,r1 /* RFCR Address */ - mov.l RFCR_D,r0 /* RFCR Data */ - mov.w r0,@r1 /* Clear reflesh counter */ /* Wait DRAM refresh 30 times */ - mov #30,r3 + mov #30, r3 1: - mov.w @r1,r0 - extu.w r0,r2 - cmp/hi r3,r2 + mov.w @r1, r0 + extu.w r0, r2 + cmp/hi r3, r2 bf 1b - mov.l MCR_A,r1 /* MCR Address */ - mov.l MCR_D2,r0 /* MCR Data2 */ - mov.l r0,@r1 + write32 MCR_A, MCR_D2 - mov.l SDMR3_A,r1 /* Set SDRAM mode */ - mov #0,r0 - mov.b r0,@r1 + /* Set SDRAM mode */ + write8 SDMR3_A, SDMR3_D rts - nop + nop .align 2 -CCR_A: .long CCR -CCR_D_DISABLE: .long 0x0808 +CCR_A: .long CCR +CCR_D_DISABLE: .long 0x0808 FRQCR_A: .long FRQCR FRQCR_D: #ifdef CONFIG_CPU_TYPE_R @@ -172,6 +146,7 @@ RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ RTCOR_A: .long RTCOR RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */ SDMR3_A: .long SDMR3_ADDRESS +SDMR3_D: .long 0x00 MCR_A: .long MCR MCR_D1: .long MCR_D1_VALUE MCR_D2: .long MCR_D2_VALUE diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index fed0ed431..5353d738b 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -150,7 +150,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index 932f1121e..b14a3d34b 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -306,7 +306,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/renesas/MigoR/lowlevel_init.S b/board/renesas/MigoR/lowlevel_init.S index 4c1900ec2..e32a7afb4 100644 --- a/board/renesas/MigoR/lowlevel_init.S +++ b/board/renesas/MigoR/lowlevel_init.S @@ -27,13 +27,14 @@ #include <version.h> #include <asm/processor.h> +#include <asm/macro.h> /* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. * - * (Note: As no stack is available, no subroutines can be called...). + * (Note: As no stack is available, no subroutines can be called...). */ .global lowlevel_init @@ -42,141 +43,83 @@ .align 2 lowlevel_init: - mov.l CCR_A, r1 ! Address of Cache Control Register - mov.l CCR_D, r0 ! Instruction Cache Invalidate - mov.l r0, @r1 + write32 CCR_A, CCR_D ! Address of Cache Control Register + ! Instruction Cache Invalidate - mov.l MMUCR_A, r1 ! Address of MMU Control Register - mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit - mov.l r0, @r1 + write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register + ! TI == TLB Invalidate bit - mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0 - mov.l MSTPCR0_D, r0 ! - mov.l r0, @r1 + write32 MSTPCR0_A, MSTPCR0_D ! Address of Power Control Register 0 - mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2 - mov.l MSTPCR2_D, r0 ! - mov.l r0, @r1 + write32 MSTPCR2_A, MSTPCR2_D ! Address of Power Control Register 2 - mov.l PFC_PULCR_A, r1 - mov.w PFC_PULCR_D, r0 - mov.w r0,@r1 + write16 PFC_PULCR_A, PFC_PULCR_D - mov.l PFC_DRVCR_A, r1 - mov.w PFC_DRVCR_D, r0 - mov.w r0, @r1 + write16 PFC_DRVCR_A, PFC_DRVCR_D - mov.l SBSCR_A, r1 ! - mov.w SBSCR_D, r0 ! - mov.w r0, @r1 + write16 SBSCR_A, SBSCR_D - mov.l PSCR_A, r1 ! - mov.w PSCR_D, r0 ! - mov.w r0, @r1 + write16 PSCR_A, PSCR_D - mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) - mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max - mov.w r0, @r1 + write16 RWTCSR_A, RWTCSR_D_1 ! 0xA4520004 (Watchdog Control / Status Register) + ! 0xA507 -> timer_STOP / WDT_CLK = max - mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register) - mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear - mov.w r0, @r1 + write16 RWTCNT_A, RWTCNT_D ! 0xA4520000 (Watchdog Count Register) + ! 0x5A00 -> Clear - mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) - mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms - mov.w r0, @r1 + write16 RWTCSR_A, RWTCSR_D_2 ! 0xA4520004 (Watchdog Control / Status Register) + ! 0xA504 -> timer_STOP / CLK = 500ms - mov.l DLLFRQ_A, r1 ! 20080115 - mov.l DLLFRQ_D, r0 ! 20080115 - mov.l r0, @r1 + write32 DLLFRQ_A, DLLFRQ_D ! 20080115 + ! 20080115 - mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register - mov.l FRQCR_D, r0 ! 20080115 - mov.l r0, @r1 + write32 FRQCR_A, FRQCR_D ! 0xA4150000 Frequency control register + ! 20080115 - mov.l CCR_A, r1 ! Address of Cache Control Register - mov.l CCR_D_2, r0 ! ?? - mov.l r0, @r1 + write32 CCR_A, CCR_D_2 ! Address of Cache Control Register + ! ?? bsc_init: - mov.l CMNCR_A, r1 ! CMNCR address -> R1 - mov.l CMNCR_D, r0 ! CMNCR data -> R0 - mov.l r0, @r1 ! CMNCR set + write32 CMNCR_A, CMNCR_D - mov.l CS0BCR_A, r1 ! CS0BCR address -> R1 - mov.l CS0BCR_D, r0 ! CS0BCR data -> R0 - mov.l r0, @r1 ! CS0BCR set + write32 CS0BCR_A, CS0BCR_D - mov.l CS4BCR_A, r1 ! CS4BCR address -> R1 - mov.l CS4BCR_D, r0 ! CS4BCR data -> R0 - mov.l r0, @r1 ! CS4BCR set + write32 CS4BCR_A, CS4BCR_D - mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1 - mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0 - mov.l r0, @r1 ! CS5ABCR set + write32 CS5ABCR_A, CS5ABCR_D - mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1 - mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0 - mov.l r0, @r1 ! CS5BBCR set + write32 CS5BBCR_A, CS5BBCR_D - mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1 - mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0 - mov.l r0, @r1 ! CS6ABCR set + write32 CS6ABCR_A, CS6ABCR_D - mov.l CS0WCR_A, r1 ! CS0WCR address -> R1 - mov.l CS0WCR_D, r0 ! CS0WCR data -> R0 - mov.l r0, @r1 ! CS0WCR set + write32 CS0WCR_A, CS0WCR_D - mov.l CS4WCR_A, r1 ! CS4WCR address -> R1 - mov.l CS4WCR_D, r0 ! CS4WCR data -> R0 - mov.l r0, @r1 ! CS4WCR set + write32 CS4WCR_A, CS4WCR_D - mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1 - mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0 - mov.l r0, @r1 ! CS5AWCR set + write32 CS5AWCR_A, CS5AWCR_D - mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1 - mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0 - mov.l r0, @r1 ! CS5BWCR set + write32 CS5BWCR_A, CS5BWCR_D - mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1 - mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0 - mov.l r0, @r1 ! CS6AWCR set + write32 CS6AWCR_A, CS6AWCR_D ! SDRAM initialization - mov.l SDCR_A, r1 ! SB_SDCR address -> R1 - mov.l SDCR_D, r0 ! SB_SDCR data -> R0 - mov.l r0, @r1 ! SB_SDCR set + write32 SDCR_A, SDCR_D - mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1 - mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0 - mov.l r0, @r1 ! SB_SDWCR set + write32 SDWCR_A, SDWCR_D - mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1 - mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0 - mov.l r0, @r1 ! SB_SDPCR set + write32 SDPCR_A, SDPCR_D - mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1 - mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0 - mov.l r0, @r1 ! SB_RTCOR set + write32 RTCOR_A, RTCOR_D - mov.l RTCNT_A, r1 ! SB_RTCNT address -> R1 - mov.l RTCNT_D, r0 ! SB_RTCNT data -> R0 - mov.l r0, @r1 + write32 RTCNT_A, RTCNT_D - mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1 - mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0 - mov.l r0, @r1 ! SB_RTCSR set + write32 RTCSR_A, RTCSR_D - mov.l RFCR_A, r1 ! SB_RFCR address -> R1 - mov.l RFCR_D, r0 ! SB_RFCR data -> R0 - mov.l r0, @r1 + write32 RFCR_A, RFCR_D - mov.l SDMR3_A, r1 ! SDMR3 address -> R1 - mov #0x00, r0 ! SDMR3 data -> R0 - mov.b r0, @r1 ! SDMR3 set + write8 SDMR3_A, SDMR3_D - ! BL bit off (init = ON) (?!?) + ! BL bit off (init = ON) (?!?) stc sr, r0 ! BL bit off(init=ON) mov.l SR_MASK_D, r1 @@ -252,6 +195,7 @@ RFCR_A: .long SBSC_RFCR RFCR_D: .long 0xA55A0221 RTCSR_D: .long 0xA55A009a SDMR3_A: .long 0xFE581180 +SDMR3_D: .long 0x0 SR_MASK_D: .long 0xEFFFFF0F diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S index 4f6658879..b32f49132 100644 --- a/board/renesas/ap325rxa/lowlevel_init.S +++ b/board/renesas/ap325rxa/lowlevel_init.S @@ -23,6 +23,7 @@ #include <config.h> #include <version.h> #include <asm/processor.h> +#include <asm/macro.h> /* * Board specific low level init code, called _very_ early in the @@ -38,113 +39,59 @@ .align 2 lowlevel_init: - mov.l DRVCRA_A, r1 - mov.l DRVCRA_D, r0 - mov.w r0, @r1 + write16 DRVCRA_A, DRVCRA_D - mov.l DRVCRB_A, r1 - mov.l DRVCRB_D, r0 - mov.w r0, @r1 + write16 DRVCRB_A, DRVCRB_D - mov.l RWTCSR_A, r1 - mov.l RWTCSR_D1, r0 - mov.w r0, @r1 + write16 RWTCSR_A, RWTCSR_D1 - mov.l RWTCNT_A, r1 - mov.l RWTCNT_D, r0 - mov.w r0, @r1 + write16 RWTCNT_A, RWTCNT_D - mov.l RWTCSR_A, r1 - mov.l RWTCSR_D2, r0 - mov.w r0, @r1 + write16 RWTCSR_A, RWTCSR_D2 - mov.l FRQCR_A, r1 - mov.l FRQCR_D, r0 - mov.l r0, @r1 + write32 FRQCR_A, FRQCR_D - mov.l CMNCR_A, r1 - mov.l CMNCR_D, r0 - mov.l r0, @r1 + write32 CMNCR_A, CMNCR_D - mov.l CS0BCR_A ,r1 - mov.l CS0BCR_D ,r0 - mov.l r0, @r1 + write32 CS0BCR_A, CS0BCR_D - mov.l CS4BCR_A ,r1 - mov.l CS4BCR_D ,r0 - mov.l r0, @r1 + write32 CS4BCR_A, CS4BCR_D - mov.l CS5ABCR_A ,r1 - mov.l CS5ABCR_D ,r0 - mov.l r0, @r1 + write32 CS5ABCR_A, CS5ABCR_D - mov.l CS5BBCR_A ,r1 - mov.l CS5BBCR_D ,r0 - mov.l r0, @r1 + write32 CS5BBCR_A, CS5BBCR_D - mov.l CS6ABCR_A ,r1 - mov.l CS6ABCR_D ,r0 - mov.l r0, @r1 + write32 CS6ABCR_A, CS6ABCR_D - mov.l CS6BBCR_A ,r1 - mov.l CS6BBCR_D ,r0 - mov.l r0, @r1 + write32 CS6BBCR_A, CS6BBCR_D - mov.l CS0WCR_A ,r1 - mov.l CS0WCR_D ,r0 - mov.l r0, @r1 + write32 CS0WCR_A, CS0WCR_D - mov.l CS4WCR_A ,r1 - mov.l CS4WCR_D ,r0 - mov.l r0, @r1 + write32 CS4WCR_A, CS4WCR_D - mov.l CS5AWCR_A ,r1 - mov.l CS5AWCR_D ,r0 - mov.l r0, @r1 + write32 CS5AWCR_A, CS5AWCR_D - mov.l CS5BWCR_A ,r1 - mov.l CS5BWCR_D ,r0 - mov.l r0, @r1 + write32 CS5BWCR_A, CS5BWCR_D - mov.l CS6AWCR_A ,r1 - mov.l CS6AWCR_D ,r0 - mov.l r0, @r1 + write32 CS6AWCR_A, CS6AWCR_D - mov.l CS6BWCR_A ,r1 - mov.l CS6BWCR_D ,r0 - mov.l r0, @r1 + write32 CS6BWCR_A, CS6BWCR_D - mov.l SBSC_SDCR_A, r1 - mov.l SBSC_SDCR_D1, r0 - mov.l r0, @r1 + write32 SBSC_SDCR_A, SBSC_SDCR_D1 - mov.l SBSC_SDWCR_A, r1 - mov.l SBSC_SDWCR_D, r0 - mov.l r0, @r1 + write32 SBSC_SDWCR_A, SBSC_SDWCR_D - mov.l SBSC_SDPCR_A, r1 - mov.l SBSC_SDPCR_D, r0 - mov.l r0, @r1 + write32 SBSC_SDPCR_A, SBSC_SDPCR_D - mov.l SBSC_RTCSR_A, r1 - mov.l SBSC_RTCSR_D, r0 - mov.l r0, @r1 + write32 SBSC_RTCSR_A, SBSC_RTCSR_D - mov.l SBSC_RTCNT_A, r1 - mov.l SBSC_RTCNT_D, r0 - mov.l r0, @r1 + write32 SBSC_RTCNT_A, SBSC_RTCNT_D - mov.l SBSC_RTCOR_A, r1 - mov.l SBSC_RTCOR_D, r0 - mov.l r0, @r1 + write32 SBSC_RTCOR_A, SBSC_RTCOR_D - mov.l SBSC_SDMR3_A1, r1 - mov.l SBSC_SDMR3_D, r0 - mov.b r0, @r1 + write8 SBSC_SDMR3_A1, SBSC_SDMR3_D - mov.l SBSC_SDMR3_A2, r1 - mov.l SBSC_SDMR3_D, r0 - mov.b r0, @r1 + write8 SBSC_SDMR3_A2, SBSC_SDMR3_D mov.l SLEEP_CNT, r1 2: tst r1, r1 @@ -152,19 +99,13 @@ lowlevel_init: bf/s 2b dt r1 - mov.l SBSC_SDMR3_A3, r1 - mov.l SBSC_SDMR3_D, r0 - mov.b r0, @r1 + write8 SBSC_SDMR3_A3, SBSC_SDMR3_D - mov.l SBSC_SDCR_A, r1 - mov.l SBSC_SDCR_D2, r0 - mov.l r0, @r1 + write32 SBSC_SDCR_A, SBSC_SDCR_D2 - mov.l CCR_A, r1 - mov.l CCR_D, r0 - mov.l r0, @r1 + write32 CCR_A, CCR_D - ! BL bit off (init = ON) (?!?) + ! BL bit off (init = ON) (?!?) stc sr, r0 ! BL bit off(init=ON) mov.l SR_MASK_D, r1 @@ -211,7 +152,7 @@ SBSC_SDMR3_D: .long 0x00 CMNCR_A: .long CMNCR CS0BCR_A: .long CS0BCR CS4BCR_A: .long CS4BCR -CS5ABCR_A: .long CS5ABCR +CS5ABCR_A: .long CS5ABCR CS5BBCR_A: .long CS5BBCR CS6ABCR_A: .long CS6ABCR CS6BBCR_A: .long CS6BBCR diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S index 28d2b3769..76d3cfc40 100644 --- a/board/renesas/r2dplus/lowlevel_init.S +++ b/board/renesas/r2dplus/lowlevel_init.S @@ -8,6 +8,7 @@ #include <version.h> #include <asm/processor.h> +#include <asm/macro.h> .global lowlevel_init .text @@ -15,98 +16,56 @@ lowlevel_init: - mov.l CCR_A, r1 - mov.l CCR_D_D, r0 - mov.l r0,@r1 + write32 CCR_A, CCR_D_D - mov.l MMUCR_A,r1 - mov.l MMUCR_D,r0 - mov.l r0,@r1 + write32 MMUCR_A, MMUCR_D - mov.l BCR1_A,r1 - mov.l BCR1_D,r0 - mov.l r0,@r1 + write32 BCR1_A, BCR1_D - mov.l BCR2_A,r1 - mov.l BCR2_D,r0 - mov.w r0,@r1 + write16 BCR2_A, BCR2_D - mov.l BCR3_A,r1 - mov.l BCR3_D,r0 - mov.w r0,@r1 + write16 BCR3_A, BCR3_D - mov.l BCR4_A,r1 - mov.l BCR4_D,r0 - mov.l r0,@r1 + write32 BCR4_A, BCR4_D - mov.l WCR1_A,r1 - mov.l WCR1_D,r0 - mov.l r0,@r1 + write32 WCR1_A, WCR1_D - mov.l WCR2_A,r1 - mov.l WCR2_D,r0 - mov.l r0,@r1 + write32 WCR2_A, WCR2_D - mov.l WCR3_A,r1 - mov.l WCR3_D,r0 - mov.l r0,@r1 + write32 WCR3_A, WCR3_D - mov.l PCR_A,r1 - mov.l PCR_D,r0 - mov.w r0,@r1 + write16 PCR_A, PCR_D - mov.l LED_A,r1 - mov #0xff,r0 - mov.w r0,@r1 + write16 LED_A, LED_D - mov.l MCR_A,r1 - mov.l MCR_D1,r0 - mov.l r0,@r1 + write32 MCR_A, MCR_D1 - mov.l RTCNT_A,r1 - mov.l RTCNT_D,r0 - mov.w r0,@r1 + write16 RTCNT_A, RTCNT_D - mov.l RTCOR_A,r1 - mov.l RTCOR_D,r0 - mov.w r0,@r1 + write16 RTCOR_A, RTCOR_D - mov.l RFCR_A,r1 - mov.l RFCR_D,r0 - mov.w r0,@r1 + write16 RFCR_A, RFCR_D - mov.l RTCSR_A,r1 - mov.l RTCSR_D,r0 - mov.w r0,@r1 + write16 RTCSR_A, RTCSR_D - mov.l SDMR3_A,r1 - mov #0x55,r0 - mov.b r0,@r1 + write8 SDMR3_A, SDMR3_D0 /* Wait DRAM refresh 30 times */ - mov.l RFCR_A,r1 - mov #30,r3 + mov.l RFCR_A, r1 + mov #30, r3 1: - mov.w @r1,r0 - extu.w r0,r2 - cmp/hi r3,r2 + mov.w @r1, r0 + extu.w r0, r2 + cmp/hi r3, r2 bf 1b - mov.l MCR_A,r1 - mov.l MCR_D2,r0 - mov.l r0,@r1 + write32 MCR_A, MCR_D2 - mov.l SDMR3_A,r1 - mov #0,r0 - mov.b r0,@r1 + write8 SDMR3_A, SDMR3_D1 - mov.l IRLMASK_A,r1 - mov.l IRLMASK_D,r0 - mov.l r0,@r1 + write32 IRLMASK_A, IRLMASK_D - mov.l CCR_A, r1 - mov.l CCR_D_E, r0 - mov.l r0, @r1 + write32 CCR_A, CCR_D_E rts nop @@ -133,6 +92,7 @@ WCR2_D: .long 0xcff86fbf WCR3_A: .long WCR3 /* WCR3 Address */ WCR3_D: .long 0x07777707 LED_A: .long 0x04000036 /* LED Address */ +LED_D: .long 0xFF /* LED Data */ RTCNT_A: .long RTCNT /* RTCNT Address */ RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ RTCOR_A: .long RTCOR /* RTCOR Address */ @@ -140,7 +100,8 @@ RTCOR_D: .long 0xA534 /* RTCOR Write Code */ RTCSR_A: .long RTCSR /* RTCSR Address */ RTCSR_D: .long 0xA510 /* RTCSR Write Code */ SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ -SDMR3_D: .long 0x55 +SDMR3_D0: .long 0x55 +SDMR3_D1: .long 0x00 MCR_A: .long MCR /* MCR Address */ MCR_D1: .long 0x081901F4 /* MRSET:'0' */ MCR_D2: .long 0x481901F4 /* MRSET:'1' */ diff --git a/board/renesas/r7780mp/lowlevel_init.S b/board/renesas/r7780mp/lowlevel_init.S index ab0499a3a..bbea62192 100644 --- a/board/renesas/r7780mp/lowlevel_init.S +++ b/board/renesas/r7780mp/lowlevel_init.S @@ -22,13 +22,14 @@ #include <config.h> #include <version.h> #include <asm/processor.h> +#include <asm/macro.h> /* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. + * Board specific low level init code, called _very_ early in the + * startup sequence. Relocation to SDRAM has not happened yet, no + * stack is available, bss section has not been initialised, etc. * - * (Note: As no stack is available, no subroutines can be called...). + * (Note: As no stack is available, no subroutines can be called...). */ .global lowlevel_init @@ -38,63 +39,36 @@ lowlevel_init: - mov.l CCR_A, r1 /* Address of Cache Control Register */ - mov.l CCR_D, r0 /* Instruction Cache Invalidate */ - mov.l r0, @r1 + write32 CCR_A, CCR_D /* Address of Cache Control Register */ + /* Instruction Cache Invalidate */ - mov.l FRQCR_A, r1 /* Frequency control register */ - mov.l FRQCR_D, r0 - mov.l r0, @r1 + write32 FRQCR_A, FRQCR_D /* Frequency control register */ /* pin_multi_setting */ - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR1,r0 - mov.l r0,@r1 + write32 BBG_PMMR_A, BBG_PMMR_D_PMSR1 - mov.l BBG_PMSR1_A,r1 - mov.l BBG_PMSR1_D,r0 - mov.l r0,@r1 + write32 BBG_PMSR1_A, BBG_PMSR1_D - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR2,r0 - mov.l r0,@r1 + write32 BBG_PMMR_A, BBG_PMMR_D_PMSR2 - mov.l BBG_PMSR2_A,r1 - mov.l BBG_PMSR2_D,r0 - mov.l r0,@r1 + write32 BBG_PMSR2_A, BBG_PMSR2_D - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR3,r0 - mov.l r0,@r1 + write32 BBG_PMMR_A, BBG_PMMR_D_PMSR3 - mov.l BBG_PMSR3_A,r1 - mov.l BBG_PMSR3_D,r0 - mov.l r0,@r1 + write32 BBG_PMSR3_A, BBG_PMSR3_D - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSR4,r0 - mov.l r0,@r1 + write32 BBG_PMMR_A, BBG_PMMR_D_PMSR4 - mov.l BBG_PMSR4_A,r1 - mov.l BBG_PMSR4_D,r0 - mov.l r0,@r1 + write32 BBG_PMSR4_A, BBG_PMSR4_D - mov.l BBG_PMMR_A,r1 - mov.l BBG_PMMR_D_PMSRG,r0 - mov.l r0,@r1 + write32 BBG_PMMR_A, BBG_PMMR_D_PMSRG - mov.l BBG_PMSRG_A,r1 - mov.l BBG_PMSRG_D,r0 - mov.l r0,@r1 + write32 BBG_PMSRG_A, BBG_PMSRG_D /* cpg_setting */ - mov.l FRQCR_A,r1 - mov.l FRQCR_D,r0 - mov.l r0,@r1 + write32 FRQCR_A, FRQCR_D - mov.l DLLCSR_A,r1 - mov.l DLLCSR_D,r0 - mov.l r0,@r1 + write32 DLLCSR_A, DLLCSR_D nop nop @@ -108,111 +82,79 @@ lowlevel_init: nop /* wait 200us */ - mov.l REPEAT0_R3,r3 - mov #0,r2 + mov.l REPEAT0_R3, r3 + mov #0, r2 repeat0: - add #1,r2 - cmp/hs r3,r2 - bf repeat0 + add #1, r2 + cmp/hs r3, r2 + bf repeat0 nop /* bsc_setting */ - mov.l MMSELR_A,r1 - mov.l MMSELR_D,r0 - mov.l r0,@r1 + write32 MMSELR_A, MMSELR_D - mov.l BCR_A,r1 - mov.l BCR_D,r0 - mov.l r0,@r1 + write32 BCR_A, BCR_D - mov.l CS0BCR_A,r1 - mov.l CS0BCR_D,r0 - mov.l r0,@r1 + write32 CS0BCR_A, CS0BCR_D - mov.l CS1BCR_A,r1 - mov.l CS1BCR_D,r0 - mov.l r0,@r1 + write32 CS1BCR_A, CS1BCR_D - mov.l CS2BCR_A,r1 - mov.l CS2BCR_D,r0 - mov.l r0,@r1 + write32 CS2BCR_A, CS2BCR_D - mov.l CS4BCR_A,r1 - mov.l CS4BCR_D,r0 - mov.l r0,@r1 + write32 CS4BCR_A, CS4BCR_D - mov.l CS5BCR_A,r1 - mov.l CS5BCR_D,r0 - mov.l r0,@r1 + write32 CS5BCR_A, CS5BCR_D - mov.l CS6BCR_A,r1 - mov.l CS6BCR_D,r0 - mov.l r0,@r1 + write32 CS6BCR_A, CS6BCR_D - mov.l CS0WCR_A,r1 - mov.l CS0WCR_D,r0 - mov.l r0,@r1 + write32 CS0WCR_A, CS0WCR_D - mov.l CS1WCR_A,r1 - mov.l CS1WCR_D,r0 - mov.l r0,@r1 + write32 CS1WCR_A, CS1WCR_D - mov.l CS2WCR_A,r1 - mov.l CS2WCR_D,r0 - mov.l r0,@r1 + write32 CS2WCR_A, CS2WCR_D - mov.l CS4WCR_A,r1 - mov.l CS4WCR_D,r0 - mov.l r0,@r1 + write32 CS4WCR_A, CS4WCR_D - mov.l CS5WCR_A,r1 - mov.l CS5WCR_D,r0 - mov.l r0,@r1 + write32 CS5WCR_A, CS5WCR_D - mov.l CS6WCR_A,r1 - mov.l CS6WCR_D,r0 - mov.l r0,@r1 + write32 CS6WCR_A, CS6WCR_D - mov.l CS5PCR_A,r1 - mov.l CS5PCR_D,r0 - mov.l r0,@r1 + write32 CS5PCR_A, CS5PCR_D - mov.l CS6PCR_A,r1 - mov.l CS6PCR_D,r0 - mov.l r0,@r1 + write32 CS6PCR_A, CS6PCR_D /* ddr_setting */ /* wait 200us */ - mov.l REPEAT0_R3,r3 - mov #0,r2 + mov.l REPEAT0_R3, r3 + mov #0, r2 repeat1: - add #1,r2 - cmp/hs r3,r2 - bf repeat1 + add #1, r2 + cmp/hs r3, r2 + bf repeat1 nop - mov.l MIM_U_A,r0 - mov.l MIM_U_D,r1 + mov.l MIM_U_A, r0 + mov.l MIM_U_D, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco - mov.l MIM_L_A,r0 - mov.l MIM_L_D0,r1 + mov.l MIM_L_A, r0 + mov.l MIM_L_D0, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco - mov.l STR_L_A,r0 - mov.l STR_L_D,r1 + mov.l STR_L_A, r0 + mov.l STR_L_D, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco - mov.l SDR_L_A,r0 - mov.l SDR_L_D,r1 + mov.l SDR_L_A, r0 + mov.l SDR_L_D, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop @@ -220,193 +162,193 @@ repeat1: nop nop - mov.l SCR_L_A,r0 - mov.l SCR_L_D0,r1 + mov.l SCR_L_A, r0 + mov.l SCR_L_D0, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco - mov.l SCR_L_A,r0 - mov.l SCR_L_D1,r1 + mov.l SCR_L_A, r0 + mov.l SCR_L_D1, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop nop nop - mov.l EMRS_A,r0 - mov.l EMRS_D,r1 + mov.l EMRS_A, r0 + mov.l EMRS_D, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop nop nop - mov.l MRS1_A,r0 - mov.l MRS1_D,r1 + mov.l MRS1_A, r0 + mov.l MRS1_D, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop nop nop - mov.l SCR_L_A,r0 - mov.l SCR_L_D2,r1 + mov.l SCR_L_A, r0 + mov.l SCR_L_D2, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop nop nop - mov.l SCR_L_A,r0 - mov.l SCR_L_D3,r1 + mov.l SCR_L_A, r0 + mov.l SCR_L_D3, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop nop nop - mov.l SCR_L_A,r0 - mov.l SCR_L_D4,r1 + mov.l SCR_L_A, r0 + mov.l SCR_L_D4, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop nop nop - mov.l MRS2_A,r0 - mov.l MRS2_D,r1 + mov.l MRS2_A, r0 + mov.l MRS2_D, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco nop nop nop - mov.l SCR_L_A,r0 - mov.l SCR_L_D5,r1 + mov.l SCR_L_A, r0 + mov.l SCR_L_D5, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco /* wait 200us */ - mov.l REPEAT0_R1,r3 - mov #0,r2 + mov.l REPEAT0_R1, r3 + mov #0, r2 repeat2: - add #1,r2 - cmp/hs r3,r2 - bf repeat2 + add #1, r2 + cmp/hs r3, r2 + bf repeat2 synco - mov.l MIM_L_A,r0 - mov.l MIM_L_D1,r1 + mov.l MIM_L_A, r0 + mov.l MIM_L_D1, r1 synco - mov.l r1,@r0 + mov.l r1, @r0 synco rts nop .align 4 -RWTCSR_D_1: .word 0xA507 -RWTCSR_D_2: .word 0xA507 -RWTCNT_D: .word 0x5A00 +RWTCSR_D_1: .word 0xA507 +RWTCSR_D_2: .word 0xA507 +RWTCNT_D: .word 0x5A00 .align 2 -BBG_PMMR_A: .long 0xFF800010 -BBG_PMSR1_A: .long 0xFF800014 -BBG_PMSR2_A: .long 0xFF800018 -BBG_PMSR3_A: .long 0xFF80001C -BBG_PMSR4_A: .long 0xFF800020 -BBG_PMSRG_A: .long 0xFF800024 +BBG_PMMR_A: .long 0xFF800010 +BBG_PMSR1_A: .long 0xFF800014 +BBG_PMSR2_A: .long 0xFF800018 +BBG_PMSR3_A: .long 0xFF80001C +BBG_PMSR4_A: .long 0xFF800020 +BBG_PMSRG_A: .long 0xFF800024 -BBG_PMMR_D_PMSR1: .long 0xffffbffd -BBG_PMSR1_D: .long 0x00004002 -BBG_PMMR_D_PMSR2: .long 0xfc21a7ff -BBG_PMSR2_D: .long 0x03de5800 -BBG_PMMR_D_PMSR3: .long 0xfffffff8 -BBG_PMSR3_D: .long 0x00000007 -BBG_PMMR_D_PMSR4: .long 0xdffdfff9 -BBG_PMSR4_D: .long 0x20020006 -BBG_PMMR_D_PMSRG: .long 0xffffffff -BBG_PMSRG_D: .long 0x00000000 +BBG_PMMR_D_PMSR1: .long 0xffffbffd +BBG_PMSR1_D: .long 0x00004002 +BBG_PMMR_D_PMSR2: .long 0xfc21a7ff +BBG_PMSR2_D: .long 0x03de5800 +BBG_PMMR_D_PMSR3: .long 0xfffffff8 +BBG_PMSR3_D: .long 0x00000007 +BBG_PMMR_D_PMSR4: .long 0xdffdfff9 +BBG_PMSR4_D: .long 0x20020006 +BBG_PMMR_D_PMSRG: .long 0xffffffff +BBG_PMSRG_D: .long 0x00000000 -FRQCR_A: .long FRQCR -DLLCSR_A: .long 0xffc40010 -FRQCR_D: .long 0x40233035 -DLLCSR_D: .long 0x00000000 +FRQCR_A: .long FRQCR +DLLCSR_A: .long 0xffc40010 +FRQCR_D: .long 0x40233035 +DLLCSR_D: .long 0x00000000 /* for DDR-SDRAM */ -MIM_U_A: .long MIM_1 -MIM_L_A: .long MIM_2 -SCR_U_A: .long SCR_1 -SCR_L_A: .long SCR_2 -STR_U_A: .long STR_1 -STR_L_A: .long STR_2 -SDR_U_A: .long SDR_1 -SDR_L_A: .long SDR_2 +MIM_U_A: .long MIM_1 +MIM_L_A: .long MIM_2 +SCR_U_A: .long SCR_1 +SCR_L_A: .long SCR_2 +STR_U_A: .long STR_1 +STR_L_A: .long STR_2 +SDR_U_A: .long SDR_1 +SDR_L_A: .long SDR_2 -EMRS_A: .long 0xFEC02000 -MRS1_A: .long 0xFEC00B08 -MRS2_A: .long 0xFEC00308 +EMRS_A: .long 0xFEC02000 +MRS1_A: .long 0xFEC00B08 +MRS2_A: .long 0xFEC00308 -MIM_U_D: .long 0x00004000 -MIM_L_D0: .long 0x03e80009 -MIM_L_D1: .long 0x03e80209 -SCR_L_D0: .long 0x3 -SCR_L_D1: .long 0x2 -SCR_L_D2: .long 0x2 -SCR_L_D3: .long 0x4 -SCR_L_D4: .long 0x4 -SCR_L_D5: .long 0x0 -STR_L_D: .long 0x000f0000 -SDR_L_D: .long 0x00000400 -EMRS_D: .long 0x0 -MRS1_D: .long 0x0 -MRS2_D: .long 0x0 +MIM_U_D: .long 0x00004000 +MIM_L_D0: .long 0x03e80009 +MIM_L_D1: .long 0x03e80209 +SCR_L_D0: .long 0x3 +SCR_L_D1: .long 0x2 +SCR_L_D2: .long 0x2 +SCR_L_D3: .long 0x4 +SCR_L_D4: .long 0x4 +SCR_L_D5: .long 0x0 +STR_L_D: .long 0x000f0000 +SDR_L_D: .long 0x00000400 +EMRS_D: .long 0x0 +MRS1_D: .long 0x0 +MRS2_D: .long 0x0 /* Cache Controller */ -CCR_A: .long CCR -MMUCR_A: .long MMUCR -RWTCNT_A: .long WTCNT +CCR_A: .long CCR +MMUCR_A: .long MMUCR +RWTCNT_A: .long WTCNT -CCR_D: .long 0x0000090b -CCR_D_2: .long 0x00000103 -MMUCR_D: .long 0x00000004 -MSTPCR0_D: .long 0x00001001 -MSTPCR2_D: .long 0xffffffff +CCR_D: .long 0x0000090b +CCR_D_2: .long 0x00000103 +MMUCR_D: .long 0x00000004 +MSTPCR0_D: .long 0x00001001 +MSTPCR2_D: .long 0xffffffff /* local Bus State Controller */ -MMSELR_A: .long MMSELR -BCR_A: .long BCR -CS0BCR_A: .long CS0BCR -CS1BCR_A: .long CS1BCR -CS2BCR_A: .long CS2BCR -CS4BCR_A: .long CS4BCR -CS5BCR_A: .long CS5BCR -CS6BCR_A: .long CS6BCR -CS0WCR_A: .long CS0WCR -CS1WCR_A: .long CS1WCR -CS2WCR_A: .long CS2WCR -CS4WCR_A: .long CS4WCR -CS5WCR_A: .long CS5WCR -CS6WCR_A: .long CS6WCR -CS5PCR_A: .long CS5PCR -CS6PCR_A: .long CS6PCR +MMSELR_A: .long MMSELR +BCR_A: .long BCR +CS0BCR_A: .long CS0BCR +CS1BCR_A: .long CS1BCR +CS2BCR_A: .long CS2BCR +CS4BCR_A: .long CS4BCR +CS5BCR_A: .long CS5BCR +CS6BCR_A: .long CS6BCR +CS0WCR_A: .long CS0WCR +CS1WCR_A: .long CS1WCR +CS2WCR_A: .long CS2WCR +CS4WCR_A: .long CS4WCR +CS5WCR_A: .long CS5WCR +CS6WCR_A: .long CS6WCR +CS5PCR_A: .long CS5PCR +CS6PCR_A: .long CS6PCR MMSELR_D: .long 0xA5A50003 BCR_D: .long 0x00000000 @@ -425,5 +367,5 @@ CS6WCR_D: .long 0x77777703 CS5PCR_D: .long 0x77000000 CS6PCR_D: .long 0x77000000 -REPEAT0_R3: .long 0x00002000 -REPEAT0_R1: .long 0x0000200 +REPEAT0_R3: .long 0x00002000 +REPEAT0_R1: .long 0x0000200 diff --git a/board/renesas/rsk7203/Makefile b/board/renesas/rsk7203/Makefile index 7365d1930..5412010ae 100644 --- a/board/renesas/rsk7203/Makefile +++ b/board/renesas/rsk7203/Makefile @@ -26,6 +26,10 @@ LIB = lib$(BOARD).a OBJS := rsk7203.o SOBJS := lowlevel_init.o +LIB := $(addprefix $(obj),$(LIB)) +OBJS := $(addprefix $(obj),$(OBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index e4d6f9e7d..7b9ecd89c 100644 --- a/board/renesas/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S @@ -21,6 +21,7 @@ #include <version.h> #include <asm/processor.h> +#include <asm/macro.h> .global lowlevel_init @@ -29,153 +30,89 @@ lowlevel_init: /* Cache setting */ - mov.l CCR1_A ,r1 - mov.l CCR1_D ,r0 - mov.l r0,@r1 + write32 CCR1_A ,CCR1_D /* ConfigurePortPins */ - mov.l PECRL3_A, r1 - mov.l PECRL3_D, r0 - mov.w r0,@r1 + write16 PECRL3_A, PECRL3_D - mov.l PCCRL4_A, r1 - mov.l PCCRL4_D0, r0 - mov.w r0,@r1 + write16 PCCRL4_A, PCCRL4_D0 - mov.l PECRL4_A, r1 - mov.l PECRL4_D0, r0 - mov.w r0,@r1 + write16 PECRL4_A, PECRL4_D0 - mov.l PEIORL_A, r1 - mov.l PEIORL_D0, r0 - mov.w r0,@r1 + write16 PEIORL_A, PEIORL_D0 - mov.l PCIORL_A, r1 - mov.l PCIORL_D, r0 - mov.w r0,@r1 + write16 PCIORL_A, PCIORL_D - mov.l PFCRH2_A, r1 - mov.l PFCRH2_D, r0 - mov.w r0,@r1 + write16 PFCRH2_A, PFCRH2_D - mov.l PFCRH3_A, r1 - mov.l PFCRH3_D, r0 - mov.w r0,@r1 + write16 PFCRH3_A, PFCRH3_D - mov.l PFCRH1_A, r1 - mov.l PFCRH1_D, r0 - mov.w r0,@r1 + write16 PFCRH1_A, PFCRH1_D - mov.l PFIORH_A, r1 - mov.l PFIORH_D, r0 - mov.w r0,@r1 + write16 PFIORH_A, PFIORH_D - mov.l PECRL1_A, r1 - mov.l PECRL1_D0, r0 - mov.w r0,@r1 + write16 PECRL1_A, PECRL1_D0 - mov.l PEIORL_A, r1 - mov.l PEIORL_D1, r0 - mov.w r0,@r1 + write16 PEIORL_A, PEIORL_D1 /* Configure Operating Frequency */ - mov.l WTCSR_A ,r1 - mov.l WTCSR_D0 ,r0 - mov.w r0,@r1 + write16 WTCSR_A, WTCSR_D0 - mov.l WTCSR_A ,r1 - mov.l WTCSR_D1 ,r0 - mov.w r0,@r1 + write16 WTCSR_A, WTCSR_D1 - mov.l WTCNT_A ,r1 - mov.l WTCNT_D ,r0 - mov.w r0,@r1 + write16 WTCNT_A, WTCNT_D /* Set clock mode*/ - mov.l FRQCR_A,r1 - mov.l FRQCR_D,r0 - mov.w r0,@r1 + write16 FRQCR_A, FRQCR_D /* Configure Bus And Memory */ init_bsc_cs0: - mov.l PCCRL4_A,r1 - mov.l PCCRL4_D1,r0 - mov.w r0,@r1 + write16 PCCRL4_A, PCCRL4_D1 - mov.l PECRL1_A,r1 - mov.l PECRL1_D1,r0 - mov.w r0,@r1 + write16 PECRL1_A, PECRL1_D1 - mov.l CMNCR_A,r1 - mov.l CMNCR_D,r0 - mov.l r0,@r1 + write32 CMNCR_A, CMNCR_D - mov.l SC0BCR_A,r1 - mov.l SC0BCR_D,r0 - mov.l r0,@r1 + write32 SC0BCR_A, SC0BCR_D - mov.l CS0WCR_A,r1 - mov.l CS0WCR_D,r0 - mov.l r0,@r1 + write32 CS0WCR_A, CS0WCR_D init_bsc_cs1: - mov.l PECRL4_A,r1 - mov.l PECRL4_D1,r0 - mov.w r0,@r1 + write16 PECRL4_A, PECRL4_D1 - mov.l CS1WCR_A,r1 - mov.l CS1WCR_D,r0 - mov.l r0,@r1 + write32 CS1WCR_A, CS1WCR_D init_sdram: - mov.l PCCRL2_A,r1 - mov.l PCCRL2_D,r0 - mov.w r0,@r1 + write16 PCCRL2_A, PCCRL2_D - mov.l PCCRL4_A,r1 - mov.l PCCRL4_D2,r0 - mov.w r0,@r1 + write16 PCCRL4_A, PCCRL4_D2 - mov.l PCCRL1_A,r1 - mov.l PCCRL1_D,r0 - mov.w r0,@r1 + write16 PCCRL1_A, PCCRL1_D - mov.l PCCRL3_A,r1 - mov.l PCCRL3_D,r0 - mov.w r0,@r1 + write16 PCCRL3_A, PCCRL3_D - mov.l CS3BCR_A,r1 - mov.l CS3BCR_D,r0 - mov.l r0,@r1 + write32 CS3BCR_A, CS3BCR_D - mov.l CS3WCR_A,r1 - mov.l CS3WCR_D,r0 - mov.l r0,@r1 + write32 CS3WCR_A, CS3WCR_D - mov.l SDCR_A,r1 - mov.l SDCR_D,r0 - mov.l r0,@r1 + write32 SDCR_A, SDCR_D - mov.l RTCOR_A,r1 - mov.l RTCOR_D,r0 - mov.l r0,@r1 + write32 RTCOR_A, RTCOR_D - mov.l RTCSR_A,r1 - mov.l RTCSR_D,r0 - mov.l r0,@r1 + write32 RTCSR_A, RTCSR_D /* wait 200us */ - mov.l REPEAT_D,r3 - mov #0,r2 + mov.l REPEAT_D, r3 + mov #0, r2 repeat0: - add #1,r2 - cmp/hs r3,r2 - bf repeat0 + add #1, r2 + cmp/hs r3, r2 + bf repeat0 nop - mov.l SDRAM_MODE, r1 - mov #0,r0 - mov.l r0, @r1 + mov.l SDRAM_MODE, r1 + mov #0, r0 + mov.l r0, @r1 nop rts @@ -208,8 +145,8 @@ PECRL1_D0: .long 0x00000033 WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .long 0x0000A518 -WTCSR_D1: .long 0x0000A51D +WTCSR_D0: .long 0x0000A518 +WTCSR_D1: .long 0x0000A51D WTCNT_A: .long 0xFFFE0002 WTCNT_D: .long 0x00005A84 FRQCR_A: .long 0xFFFE0010 @@ -259,7 +196,7 @@ STBCR4_A: .long 0xFFFE040C STBCR4_D: .long 0x00000008 STBCR5_A: .long 0xFFFE0410 STBCR5_D: .long 0x00000000 -STBCR6_A: .long 0xFFFE0414 +STBCR6_A: .long 0xFFFE0414 STBCR6_D: .long 0x00000002 SDRAM_MODE: .long 0xFFFC5040 REPEAT_D: .long 0x00009C40 diff --git a/board/renesas/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S index 2a44eee1a..3747bf6f8 100644 --- a/board/renesas/sh7763rdp/lowlevel_init.S +++ b/board/renesas/sh7763rdp/lowlevel_init.S @@ -25,6 +25,7 @@ #include <version.h> #include <asm/processor.h> +#include <asm/macro.h> .global lowlevel_init @@ -33,218 +34,141 @@ lowlevel_init: - mov.l WDTCSR_A, r1 /* Watchdog Control / Status Register */ - mov.l WDTCSR_D, r0 - mov.l r0, @r1 + write32 WDTCSR_A, WDTCSR_D /* Watchdog Control / Status Register */ - mov.l WDTST_A, r1 /* Watchdog Stop Time Register */ - mov.l WDTST_D, r0 - mov.l r0, @r1 + write32 WDTST_A, WDTST_D /* Watchdog Stop Time Register */ - mov.l WDTBST_A, r1 /* 0xFFCC0008 (Watchdog Base Stop Time Register */ - mov.l WDTBST_D, r0 - mov.l r0, @r1 + write32 WDTBST_A, WDTBST_D /* + * 0xFFCC0008 + * Watchdog Base Stop Time Register + */ - mov.l CCR_A, r1 /* Address of Cache Control Register */ - mov.l CCR_CACHE_ICI_D, r0 /* Instruction Cache Invalidate */ - mov.l r0, @r1 + write32 CCR_A, CCR_CACHE_ICI_D /* Address of Cache Control Register */ + /* Instruction Cache Invalidate */ - mov.l MMUCR_A, r1 /* Address of MMU Control Register */ - mov.l MMU_CONTROL_TI_D, r0 /* TI == TLB Invalidate bit */ - mov.l r0, @r1 + write32 MMUCR_A, MMU_CONTROL_TI_D /* MMU Control Register */ + /* TI == TLB Invalidate bit */ - mov.l MSTPCR0_A, r1 /* Address of Power Control Register 0 */ - mov.l MSTPCR0_D, r0 - mov.l r0, @r1 + write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */ - mov.l MSTPCR1_A, r1 /*i Address of Power Control Register 1 */ - mov.l MSTPCR1_D, r0 - mov.l r0, @r1 + write32 MSTPCR1_A, MSTPCR1_D /* Address of Power Control Register 1 */ - mov.l RAMCR_A,r1 - mov.l RAMCR_D,r0 - mov.l r0, @r1 + write32 RAMCR_A, RAMCR_D - mov.l MMSELR_A,r1 - mov.l MMSELR_D,r0 + mov.l MMSELR_A, r1 + mov.l MMSELR_D, r0 synco mov.l r0, @r1 - mov.l @r1,r2 /* execute two reads after setting MMSELR*/ - mov.l @r1,r2 + mov.l @r1, r2 /* execute two reads after setting MMSELR */ + mov.l @r1, r2 synco /* issue memory read */ - mov.l DDRSD_START_A,r1 /* memory address to read*/ - mov.l @r1,r0 + mov.l DDRSD_START_A, r1 /* memory address to read*/ + mov.l @r1, r0 synco - mov.l MIM8_A,r1 - mov.l MIM8_D,r0 - mov.l r0,@r1 + write32 MIM8_A, MIM8_D - mov.l MIMC_A,r1 - mov.l MIMC_D1,r0 - mov.l r0,@r1 + write32 MIMC_A, MIMC_D1 - mov.l STRC_A,r1 - mov.l STRC_D,r0 - mov.l r0,@r1 + write32 STRC_A, STRC_D - mov.l SDR4_A,r1 - mov.l SDR4_D,r0 - mov.l r0,@r1 + write32 SDR4_A, SDR4_D - mov.l MIMC_A,r1 - mov.l MIMC_D2,r0 - mov.l r0,@r1 + write32 MIMC_A, MIMC_D2 nop nop nop - mov.l SCR4_A,r1 - mov.l SCR4_D3,r0 - mov.l r0,@r1 + write32 SCR4_A, SCR4_D3 - mov.l SCR4_A,r1 - mov.l SCR4_D2,r0 - mov.l r0,@r1 + write32 SCR4_A, SCR4_D2 - mov.l SDMR02000_A,r1 - mov.l SDMR02000_D,r0 - mov.l r0,@r1 + write32 SDMR02000_A, SDMR02000_D - mov.l SDMR00B08_A,r1 - mov.l SDMR00B08_D,r0 - mov.l r0,@r1 + write32 SDMR00B08_A, SDMR00B08_D - mov.l SCR4_A,r1 - mov.l SCR4_D2,r0 - mov.l r0,@r1 + write32 SCR4_A, SCR4_D2 - mov.l SCR4_A,r1 - mov.l SCR4_D4,r0 - mov.l r0,@r1 + write32 SCR4_A, SCR4_D4 nop nop nop nop - mov.l SCR4_A,r1 - mov.l SCR4_D4,r0 - mov.l r0,@r1 + write32 SCR4_A, SCR4_D4 nop nop nop nop - mov.l SDMR00308_A,r1 - mov.l SDMR00308_D,r0 - mov.l r0,@r1 + write32 SDMR00308_A, SDMR00308_D - mov.l MIMC_A,r1 - mov.l MIMC_D3,r0 - mov.l r0,@r1 + write32 MIMC_A, MIMC_D3 - mov.l SCR4_A,r1 - mov.l SCR4_D1,r0 - mov.l DELAY60_D,r3 + mov.l SCR4_A, r1 + mov.l SCR4_D1, r0 + mov.l DELAY60_D, r3 delay_loop_60: - mov.l r0,@r1 + mov.l r0, @r1 dt r3 bf delay_loop_60 nop - mov.l CCR_A, r1 /* Address of Cache Control Register */ - mov.l CCR_CACHE_D_2, r0 - mov.l r0, @r1 + write32 CCR_A, CCR_CACHE_D_2 /* Address of Cache Control Register */ bsc_init: - mov.l BCR_A, r1 - mov.l BCR_D, r0 - mov.l r0, @r1 + write32 BCR_A, BCR_D - mov.l CS0BCR_A, r1 - mov.l CS0BCR_D, r0 - mov.l r0, @r1 + write32 CS0BCR_A, CS0BCR_D - mov.l CS1BCR_A,r1 - mov.l CS1BCR_D,r0 - mov.l r0,@r1 + write32 CS1BCR_A, CS1BCR_D - mov.l CS2BCR_A, r1 - mov.l CS2BCR_D, r0 - mov.l r0, @r1 + write32 CS2BCR_A, CS2BCR_D - mov.l CS4BCR_A, r1 - mov.l CS4BCR_D, r0 - mov.l r0, @r1 + write32 CS4BCR_A, CS4BCR_D - mov.l CS5BCR_A, r1 - mov.l CS5BCR_D, r0 - mov.l r0, @r1 + write32 CS5BCR_A, CS5BCR_D - mov.l CS6BCR_A, r1 - mov.l CS6BCR_D, r0 - mov.l r0, @r1 + write32 CS6BCR_A, CS6BCR_D - mov.l CS0WCR_A, r1 - mov.l CS0WCR_D, r0 - mov.l r0, @r1 + write32 CS0WCR_A, CS0WCR_D - mov.l CS1WCR_A, r1 - mov.l CS1WCR_D, r0 - mov.l r0, @r1 + write32 CS1WCR_A, CS1WCR_D - mov.l CS2WCR_A, r1 - mov.l CS2WCR_D, r0 - mov.l r0, @r1 + write32 CS2WCR_A, CS2WCR_D - mov.l CS4WCR_A, r1 - mov.l CS4WCR_D, r0 - mov.l r0, @r1 + write32 CS4WCR_A, CS4WCR_D - mov.l CS5WCR_A, r1 - mov.l CS5WCR_D, r0 - mov.l r0, @r1 + write32 CS5WCR_A, CS5WCR_D - mov.l CS6WCR_A, r1 - mov.l CS6WCR_D, r0 - mov.l r0, @r1 + write32 CS6WCR_A, CS6WCR_D - mov.l CS5PCR_A, r1 - mov.l CS5PCR_D, r0 - mov.l r0, @r1 + write32 CS5PCR_A, CS5PCR_D - mov.l CS6PCR_A, r1 - mov.l CS6PCR_D, r0 - mov.l r0, @r1 + write32 CS6PCR_A, CS6PCR_D - mov.l DELAY200_D,r3 + mov.l DELAY200_D, r3 delay_loop_200: dt r3 bf delay_loop_200 nop - mov.l PSEL0_A,r1 - mov.l PSEL0_D,r0 - mov.w r0,@r1 + write16 PSEL0_A, PSEL0_D - mov.l PSEL1_A,r1 - mov.l PSEL1_D,r0 - mov.w r0,@r1 + write16 PSEL1_A, PSEL1_D - mov.l ICR0_A,r1 - mov.l ICR0_D,r0 - mov.l r0,@r1 + write32 ICR0_A, ICR0_D stc sr, r0 /* BL bit off(init=ON) */ - mov.l SR_MASK_D, r1 + mov.l SR_MASK_D, r1 and r1, r0 ldc r0, sr @@ -321,7 +245,7 @@ CS4BCR_D: .long 0x77777670 CS5BCR_D: .long 0x77777670 CS6BCR_D: .long 0x77777670 CS0WCR_D: .long 0x7777770F -CS1WCR_D: .long 0x22000002 +CS1WCR_D: .long 0x22000002 CS2WCR_D: .long 0x7777770F CS4WCR_D: .long 0x7777770F CS5WCR_D: .long 0x7777770F diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S index 50e1789cc..f5ebeb9a7 100644 --- a/board/renesas/sh7785lcr/lowlevel_init.S +++ b/board/renesas/sh7785lcr/lowlevel_init.S @@ -19,33 +19,7 @@ #include <config.h> #include <version.h> #include <asm/processor.h> - -.macro write32, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.l r0, @r1 -.endm - -.macro write16, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.w r0, @r1 -.endm - -.macro write8, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.b r0, @r1 -.endm - -.macro wait_timer, time - mov.l \time ,r3 -1: - nop - tst r3, r3 - bf/s 1b - dt r3 -.endm +#include <asm/macro.h> #include <asm/processor.h> @@ -305,7 +279,7 @@ CS4WCR_D: .long 0x00101012 CS_USB_BCR_D: .long 0x11111200 CS_USB_WCR_D: .long 0x00020004 -/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */ +/* SD setting : 32bit mode = CS3, 29bit mode = CS6 */ CS_SD_BCR_D: .long 0x00000300 CS_SD_WCR_D: .long 0x00030108 diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 8c073cb4b..519b0f749 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -126,7 +126,7 @@ local_bus_init(void) sys_info_t sysinfo; get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & 0x0f) * 2; + clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c index de47fcd63..760c6935d 100644 --- a/board/sbc8641d/law.c +++ b/board/sbc8641d/law.c @@ -45,14 +45,14 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), - SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO) + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 1471e581e..508bdc5dd 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -247,14 +247,14 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); @@ -290,14 +290,14 @@ void pci_init_board(void) /* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI2_MEM_BASE, + CONFIG_SYS_PCI2_MEM_BUS, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI2_IO_BASE, + CONFIG_SYS_PCI2_IO_BUS, CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index d83dc7d6a..df9696e69 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -156,7 +156,7 @@ void local_bus_init (void) uint lcrr = CONFIG_SYS_LBC_LCRR; get_sys_info (&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv; /* Disable PLL bypass for Local Bus Clock >= 66 MHz */ diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 73f1d01bd..cda8208ee 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -361,7 +361,7 @@ uint get_lbc_clock (void) { volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); sys_info_t sys_info; - ulong clkdiv = lbc->lcrr & 0x0f; + ulong clkdiv = lbc->lcrr & LCRR_CLKDIV; get_sys_info (&sys_info); diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile new file mode 100644 index 000000000..e7620f447 --- /dev/null +++ b/board/xes/common/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).a + +COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o +COBJS-$(CONFIG_MPC8572) += fsl_8572_clk.o +COBJS-$(CONFIG_MPC85xx) += fsl_85xx_ddr.o +COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xes/common/actl_nand.c b/board/xes/common/actl_nand.c new file mode 100644 index 000000000..465aeb099 --- /dev/null +++ b/board/xes/common/actl_nand.c @@ -0,0 +1,65 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * This driver support NAND devices which have address lines + * connected as ALE and CLE inputs. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <nand.h> +#include <asm/io.h> + +/* + * Hardware specific access to control-lines + */ +static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + IO_ADDR_W = (ulong)this->IO_ADDR_W; + + IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE | + CONFIG_SYS_NAND_ACTL_ALE | + CONFIG_SYS_NAND_ACTL_NCE); + if (ctrl & NAND_CLE) + IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE; + if (ctrl & NAND_NCE) + IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE; + + this->IO_ADDR_W = (void *)IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = nand_addr_hwcontrol; + nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY; + + return 0; +} diff --git a/board/xes/common/fsl_8572_clk.c b/board/xes/common/fsl_8572_clk.c new file mode 100644 index 000000000..f5df2dae8 --- /dev/null +++ b/board/xes/common/fsl_8572_clk.c @@ -0,0 +1,51 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* + * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config + */ +unsigned long get_board_sys_clk(ulong dummy) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 gpporcr = gur->gpporcr; + + if (gpporcr & 0x10000) + return 66666666; + else + return 50000000; +} + +/* + * Return DDR input clock - synchronous with SYSCLK or 66 MHz + */ +unsigned long get_board_ddr_clk(ulong dummy) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + + if (ddr_ratio == 0x7) + return get_board_sys_clk(dummy); + + return 66666666; +} diff --git a/board/xes/common/fsl_85xx_ddr.c b/board/xes/common/fsl_85xx_ddr.c new file mode 100644 index 000000000..30b476701 --- /dev/null +++ b/board/xes/common/fsl_85xx_ddr.c @@ -0,0 +1,93 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/mmu.h> + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + + dram_size *= 0x100000; + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* Initialize and enable DDR ECC */ + ddr_enable_ecc(dram_size); +#endif + + return dram_size; +} + +#if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1) +void board_add_ram_info(int use_default) +{ +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); +#endif + + puts(" ("); + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + /* Print interleaving information */ + if (ddr1->cs0_config & 0x20000000) { + switch ((ddr1->cs0_config >> 24) & 0xf) { + case 0: + puts("cache line"); + break; + case 1: + puts("page"); + break; + case 2: + puts("bank"); + break; + case 3: + puts("super-bank"); + break; + default: + puts("invalid"); + break; + } + } else { + puts("no"); + } + + puts(" interleaving"); +#endif + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC) + puts(", "); +#endif + +#if defined(CONFIG_DDR_ECC) + puts("ECC enabled"); +#endif + + puts(")"); +} +#endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */ diff --git a/board/xes/common/fsl_85xx_pci.c b/board/xes/common/fsl_85xx_pci.c new file mode 100644 index 000000000..9673a02b5 --- /dev/null +++ b/board/xes/common/fsl_85xx_pci.c @@ -0,0 +1,379 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> +#include <asm/immap_85xx.h> +#include <asm/immap_fsl_pci.h> +#include <libfdt.h> +#include <fdt_support.h> + +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_config_unlock(struct pci_controller *hose); +extern void fsl_pci_init(struct pci_controller *hose); + +int first_free_busno = 0; + +#ifdef CONFIG_PCI1 +static struct pci_controller pci1_hose; +#endif +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif +#ifdef CONFIG_PCIE3 +static struct pci_controller pcie3_hose; +#endif + +#ifdef CONFIG_MPC8572 +/* Correlate host/agent POR bits to usable info. Table 4-14 */ +struct host_agent_cfg_t { + uchar pcie_root[3]; + uchar rio_host; +} host_agent_cfg[8] = { + {{0, 0, 0}, 0}, + {{0, 1, 1}, 1}, + {{1, 0, 1}, 0}, + {{1, 1, 0}, 1}, + {{0, 0, 1}, 0}, + {{0, 1, 0}, 1}, + {{1, 0, 0}, 0}, + {{1, 1, 1}, 1} +}; + +/* Correlate port width POR bits to usable info. Table 4-15 */ +struct io_port_cfg_t { + uchar pcie_width[3]; + uchar rio_width; +} io_port_cfg[16] = { + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{4, 0, 0}, 0}, + {{4, 4, 0}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 4}, + {{4, 2, 2}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{4, 0, 0}, 4}, + {{4, 0, 0}, 4}, + {{0, 0, 0}, 4}, + {{0, 0, 0}, 4}, + {{8, 0, 0}, 0}, +}; +#elif defined CONFIG_MPC8548 +/* Correlate host/agent POR bits to usable info. Table 4-12 */ +struct host_agent_cfg_t { + uchar pci_host[2]; + uchar pcie_root[1]; + uchar rio_host; +} host_agent_cfg[8] = { + {{1, 1}, {0}, 0}, + {{1, 1}, {1}, 0}, + {{1, 1}, {0}, 1}, + {{0, 0}, {0}, 0}, /* reserved */ + {{0, 1}, {1}, 0}, + {{1, 1}, {1}, 0}, + {{0, 1}, {1}, 1}, + {{1, 1}, {1}, 1} +}; + +/* Correlate port width POR bits to usable info. Table 4-13 */ +struct io_port_cfg_t { + uchar pcie_width[1]; + uchar rio_width; +} io_port_cfg[8] = { + {{0}, 0}, + {{0}, 0}, + {{0}, 0}, + {{4}, 4}, + {{4}, 4}, + {{0}, 4}, + {{0}, 4}, + {{8}, 0}, +}; +#endif + +void pci_init_board(void) +{ + struct pci_controller *hose; + volatile ccsr_fsl_pci_t *pci; + int width; + int host; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + struct pci_region *r; + +#ifdef CONFIG_PCI1 + uint pci_spd_norm = (gur->pordevsr & MPC85xx_PORDEVSR_PCI1_SPD); + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + uint pcix = gur->pordevsr & MPC85xx_PORDEVSR_PCI1; + uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000; + + width = 0; /* Silence compiler warning... */ + io_sel &= 0xf; /* Silence compiler warning... */ + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; + hose = &pci1_hose; + host = host_agent_cfg[host_agent].pci_host[0]; + r = hose->regions; + + + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n", + pci_32 ? 32 : 64, + pcix ? "PCIX" : "PCI", + pci_spd_norm ? ">=" : "<=", + pcix ? freq * 2 : freq, + host ? "host" : "agent", + pci_arb ? "arbiter" : "external-arbiter"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + + /* Unlock inbound PCI configuration cycles */ + if (!host) + fsl_pci_config_unlock(hose); + + first_free_busno = hose->last_busno + 1; + printf(" PCI1 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + } else { + printf(" PCI1: disabled\n"); + } +#elif defined CONFIG_MPC8548 + /* PCI1 not present on MPC8572 */ + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif +#ifdef CONFIG_PCIE1 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; + hose = &pcie1_hose; + host = host_agent_cfg[host_agent].pcie_root[0]; + width = io_port_cfg[io_sel].pcie_width[0]; + r = hose->regions; + + if (width && !(devdisr & MPC85xx_DEVDISR_PCIE)) { + printf("\n PCIE1 connected as %s (x%d)", + host ? "Root Complex" : "End Point", width); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + printf("\n"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int) &pci->cfg_data); + + fsl_pci_init(hose); + + /* Unlock inbound PCI configuration cycles */ + if (!host) + fsl_pci_config_unlock(hose); + + first_free_busno = hose->last_busno + 1; + printf(" PCIE1 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif /* CONFIG_PCIE1 */ + +#ifdef CONFIG_PCIE2 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; + hose = &pcie2_hose; + host = host_agent_cfg[host_agent].pcie_root[1]; + width = io_port_cfg[io_sel].pcie_width[1]; + r = hose->regions; + + if (width && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { + printf("\n PCIE2 connected as %s (x%d)", + host ? "Root Complex" : "End Point", width); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + printf("\n"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_PHYS, + CONFIG_SYS_PCIE2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCIE2_IO_BASE, + CONFIG_SYS_PCIE2_IO_PHYS, + CONFIG_SYS_PCIE2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + + /* Unlock inbound PCI configuration cycles */ + if (!host) + fsl_pci_config_unlock(hose); + + first_free_busno = hose->last_busno + 1; + printf(" PCIE2 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ +#endif /* CONFIG_PCIE2 */ + +#ifdef CONFIG_PCIE3 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; + hose = &pcie3_hose; + host = host_agent_cfg[host_agent].pcie_root[2]; + width = io_port_cfg[io_sel].pcie_width[2]; + r = hose->regions; + + if (width && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { + printf("\n PCIE3 connected as %s (x%d)", + host ? "Root Complex" : "End Point", width); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + printf("\n"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCIE3_MEM_BASE, + CONFIG_SYS_PCIE3_MEM_PHYS, + CONFIG_SYS_PCIE3_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCIE3_IO_BASE, + CONFIG_SYS_PCIE3_IO_PHYS, + CONFIG_SYS_PCIE3_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + + /* Unlock inbound PCI configuration cycles */ + if (!host) + fsl_pci_config_unlock(hose); + + first_free_busno = hose->last_busno + 1; + printf(" PCIE3 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ +#endif /* CONFIG_PCIE3 */ +} + +#if defined(CONFIG_OF_BOARD_SETUP) +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); + +void ft_board_pci_setup(void *blob, bd_t *bd) +{ + /* TODO - make node name (eg pci0) dynamic */ +#ifdef CONFIG_PCI1 + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); +#endif +#ifdef CONFIG_PCIE1 + ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); +#endif +#ifdef CONFIG_PCIE2 + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); +#endif +#ifdef CONFIG_PCIE3 + ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); +#endif +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/xes/xpedite5200/Makefile b/board/xes/xpedite5200/Makefile new file mode 100644 index 000000000..02fe8fcd2 --- /dev/null +++ b/board/xes/xpedite5200/Makefile @@ -0,0 +1,55 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2004 Freescale Semiconductor. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xes/xpedite5200/config.mk b/board/xes/xpedite5200/config.mk new file mode 100644 index 000000000..be5a5c32c --- /dev/null +++ b/board/xes/xpedite5200/config.mk @@ -0,0 +1,34 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2004, 2007 Freescale Semiconductor. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# xpedite5200 board +# +ifndef TEXT_BASE +TEXT_BASE = 0xfff80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 +PLATFORM_CPPFLAGS += -mrelocatable diff --git a/board/xes/xpedite5200/ddr.c b/board/xes/xpedite5200/ddr.c new file mode 100644 index 000000000..c5616d546 --- /dev/null +++ b/board/xes/xpedite5200/ddr.c @@ -0,0 +1,91 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +static void +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); + + /* We use soldered memory, but use an SPD EEPROM to describe it. + * The SPD has an unspecified dimm type, but the DDR2 initialization + * code requires a specific type to be specified. This sets the type + * as a standard unregistered SO-DIMM. */ + if (spd->dimm_type == 0) { + spd->dimm_type = 0x4; + ((uchar *)spd)[63] += 0x4; + } +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + + if (ctrl_num) { + printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) + get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 7; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 9; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/xes/xpedite5200/law.c b/board/xes/xpedite5200/law.c new file mode 100644 index 000000000..386f9c587 --- /dev/null +++ b/board/xes/xpedite5200/law.c @@ -0,0 +1,51 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ + SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#if CONFIG_SYS_PCI1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_8M, LAW_TRGT_IF_PCI_1), +#endif +#if CONFIG_SYS_PCI2_MEM_PHYS + SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite5200/tlb.c b/board/xes/xpedite5200/tlb.c new file mode 100644 index 000000000..bd7bff820 --- /dev/null +++ b/board/xes/xpedite5200/tlb.c @@ -0,0 +1,85 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* W**G* - NOR flashes */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* *I*G* - NAND flash */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1M, 1), + +#if CONFIG_PCI1 + /* *I*G* - PCI MEM */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), +#endif + +#if CONFIG_PCI2 + /* *I*G* - PCI MEM */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), +#endif + +#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) + /* *I*G* - PCI IO */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_16M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/xes/xpedite5200/u-boot.lds b/board/xes/xpedite5200/u-boot.lds new file mode 100644 index 000000000..bd952d20f --- /dev/null +++ b/board/xes/xpedite5200/u-boot.lds @@ -0,0 +1,145 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2004, 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xes/xpedite5200/xpedite5200.c b/board/xes/xpedite5200/xpedite5200.c new file mode 100644 index 000000000..e266d1dd8 --- /dev/null +++ b/board/xes/xpedite5200/xpedite5200.c @@ -0,0 +1,125 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2004, 2007 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <asm/immap_fsl_pci.h> +#include <asm/io.h> +#include <asm/cache.h> +#include <asm/mmu.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <pca953x.h> + +extern void ft_board_pci_setup(void *blob, bd_t *bd); + +int checkboard(void) +{ + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + + char *s; + + printf("Board: X-ES %s PMC\n", CONFIG_SYS_BOARD_NAME); + printf(" "); + s = getenv("board_rev"); + if (s) + printf("Rev %s, ", s); + s = getenv("serial#"); + if (s) + printf("Serial# %s, ", s); + s = getenv("board_cfg"); + if (s) + printf("Cfg %s", s); + printf("\n"); + + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ + ecm->eedr = 0xffffffff; /* Clear ecm errors */ + ecm->eeer = 0xffffffff; /* Enable ecm errors */ + + return 0; +} + +static void flash_cs_fixup(void) +{ + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + int flash_sel; + + /* + * Print boot dev and swap flash flash chip selects if booted from 2nd + * flash. Swapping chip selects presents user with a common memory + * map regardless of which flash was booted from. + */ + flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + CONFIG_SYS_PCA953X_FLASH_PASS_CS)); + printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); + + if (flash_sel) { + lbc->br0 = CONFIG_SYS_BR1_PRELIM; + lbc->or0 = CONFIG_SYS_OR1_PRELIM; + + lbc->br1 = CONFIG_SYS_BR0_PRELIM; + lbc->or1 = CONFIG_SYS_OR0_PRELIM; + } +} + +int board_early_init_r(void) +{ + /* Initialize PCA9557 devices */ + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); + + /* + * Remap NOR flash region to caching-inhibited + * so that flash can be erased/programmed properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* Invalidate existing TLB entry for NOR flash */ + disable_tlb(0); + set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1); + + flash_cs_fixup(); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCI + ft_board_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); +} +#endif diff --git a/board/xes/xpedite5370/Makefile b/board/xes/xpedite5370/Makefile new file mode 100644 index 000000000..919397c40 --- /dev/null +++ b/board/xes/xpedite5370/Makefile @@ -0,0 +1,45 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2007 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xes/xpedite5370/config.mk b/board/xes/xpedite5370/config.mk new file mode 100644 index 000000000..39469b22c --- /dev/null +++ b/board/xes/xpedite5370/config.mk @@ -0,0 +1,35 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2007-2008 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# xpedite5370 board +# +ifndef TEXT_BASE +TEXT_BASE = 0xfff80000 +endif + +PLATFORM_RELFLAGS += -mrelocatable + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8572=1 diff --git a/board/xes/xpedite5370/ddr.c b/board/xes/xpedite5370/ddr.c new file mode 100644 index 000000000..4d3f255d7 --- /dev/null +++ b/board/xes/xpedite5370/ddr.c @@ -0,0 +1,270 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, + sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0) + i2c_address = SPD_EEPROM_ADDRESS1; + if (ctrl_num == 1) + i2c_address = SPD_EEPROM_ADDRESS2; + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +/* + * There are four board-specific SDRAM timing parameters which must be + * calculated based on the particular PCB artwork. These are: + * 1.) CPO (Read Capture Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths and + * chip-specific internal delays. + * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths. + * Unless clock and DQ lanes are very different + * lengths (>2"), this should be set to the nominal value + * of 1/2 clock delay. + * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control) + * - DDR_SDRAM_CLK_CNTL register + * Source: Signal Integrity Simulations + * 4.) 2T Timing on Addr/Ctl + * - TIMING_CFG_2 register + * Source: Signal Integrity Simulations + * Usually only needed with heavy load/very high speed (>DDR2-800) + * + * ====== XPedite5370 DDR2-600 read delay calculations ====== + * + * See Freescale's App Note AN2583 as refrence. This document also + * contains the chip-specific delays for 8548E, 8572, etc. + * + * For MPC8572E + * Minimum chip delay (Ch 0): 1.372ns + * Maximum chip delay (Ch 0): 2.914ns + * Minimum chip delay (Ch 1): 1.220ns + * Maximum chip delay (Ch 1): 2.595ns + * + * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps + * + * Minimum delay calc (Ch 0): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps + * = 3808ps + * = 3.808ns + * + * Maximum delay calc (Ch 0): + * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly + * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps + * = 6240ps + * = 6.240ns + * + * Minimum delay calc (Ch 1): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps + * = 3288ps + * = 3.288ns + * + * Maximum delay calc (Ch 1): + * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps + * = 5536ps + * = 5.536ns + * + * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target) + * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) + * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target) + * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7) + * + * + * ====== XPedite5370 DDR2-800 read delay calculations ====== + * + * See Freescale's App Note AN2583 as refrence. This document also + * contains the chip-specific delays for 8548E, 8572, etc. + * + * For MPC8572E + * Minimum chip delay (Ch 0): 1.372ns + * Maximum chip delay (Ch 0): 2.914ns + * Minimum chip delay (Ch 1): 1.220ns + * Maximum chip delay (Ch 1): 2.595ns + * + * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps + * + * Minimum delay calc (Ch 0): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps + * = 3341ps + * = 3.341ns + * + * Maximum delay calc (Ch 0): + * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly + * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps + * = 5673ps + * = 5.673ns + * + * Minimum delay calc (Ch 1): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps + * = 2822ps + * = 2.822ns + * + * Maximum delay calc (Ch 1): + * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps + * = 4968ps + * = 4.968ns + * + * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target) + * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9) + * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target) + * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) + * + * Write latency (WR_DATA_DELAY) is calculated by doing the following: + * + * The DDR SDRAM specification requires DQS be received no sooner than + * 75% of an SDRAM clock period—and no later than 125% of a clock + * period—from the capturing clock edge of the command/address at the + * SDRAM. + * + * Based on the above tracelengths, the following are calculated: + * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns + * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns + * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns + * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns + * + * Difference in arrival time CLK vs. DQS: + * Ch. 0 0.072ns + * Ch. 1 0.138ns + * + * Both of these values are much less than 25% of the clock + * period at DDR2-600 or DDR2-800, so no additional delay is needed over + * the 1/2 cycle which normally aligns the first DQS transition + * exactly WL (CAS latency minus one cycle) after the CAS strobe. + * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's + * terminology corresponds to exactly one clock period delay after + * the CAS strobe. (due to the fact that the "delay" is referenced + * from the *falling* edge of the CLK, just after the rising edge + * which the CAS strobe is latched on. + */ + +typedef struct board_memctl_options { + uint16_t datarate_mhz_low; + uint16_t datarate_mhz_high; + uint8_t clk_adjust; + uint8_t cpo_override; + uint8_t write_data_delay; +} board_memctl_options_t; + +static struct board_memctl_options bopts_ctrl[][2] = { + { + /* Controller 0 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 9, + .write_data_delay = 2, + }, + }, + { + /* Controller 1 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 7, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + }, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + struct board_memctl_options *bopts = bopts_ctrl[ctrl_num]; + sys_info_t sysinfo; + int i; + unsigned int datarate; + + get_sys_info(&sysinfo); + datarate = sysinfo.freqDDRBus / 1000 / 1000; + + for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { + if ((bopts[i].datarate_mhz_low <= datarate) && + (bopts[i].datarate_mhz_high >= datarate)) { + debug("controller %d:\n", ctrl_num); + debug(" clk_adjust = %d\n", bopts[i].clk_adjust); + debug(" cpo = %d\n", bopts[i].cpo_override); + debug(" write_data_delay = %d\n", + bopts[i].write_data_delay); + popts->clk_adjust = bopts[i].clk_adjust; + popts->cpo_override = bopts[i].cpo_override; + popts->write_data_delay = bopts[i].write_data_delay; + } + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/xes/xpedite5370/law.c b/board/xes/xpedite5370/law.c new file mode 100644 index 000000000..daee676c4 --- /dev/null +++ b/board/xes/xpedite5370/law.c @@ -0,0 +1,54 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), +#endif +#ifdef CONFIG_SYS_PCIE2_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2), +#endif +#ifdef CONFIG_SYS_PCIE3_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite5370/tlb.c b/board/xes/xpedite5370/tlb.c new file mode 100644 index 000000000..caafa3011 --- /dev/null +++ b/board/xes/xpedite5370/tlb.c @@ -0,0 +1,94 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* W**G* - NOR flashes */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* *I*G* - NAND flash */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1M, 1), + +#ifdef CONFIG_PCIE1 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), +#endif + +#ifdef CONFIG_PCIE2 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), +#endif + +#ifdef CONFIG_PCIE3 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), +#endif + +#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3) + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_64M, 1), +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/xes/xpedite5370/u-boot.lds b/board/xes/xpedite5370/u-boot.lds new file mode 100644 index 000000000..cb399120d --- /dev/null +++ b/board/xes/xpedite5370/u-boot.lds @@ -0,0 +1,145 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xes/xpedite5370/xpedite5370.c b/board/xes/xpedite5370/xpedite5370.c new file mode 100644 index 000000000..487509527 --- /dev/null +++ b/board/xes/xpedite5370/xpedite5370.c @@ -0,0 +1,128 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/immap_fsl_pci.h> +#include <asm/io.h> +#include <asm/cache.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <pca953x.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern void ft_board_pci_setup(void *blob, bd_t *bd); + +int checkboard(void) +{ + char *s; + + printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME); + printf(" "); + s = getenv("board_rev"); + if (s) + printf("Rev %s, ", s); + s = getenv("serial#"); + if (s) + printf("Serial# %s, ", s); + s = getenv("board_cfg"); + if (s) + printf("Cfg %s", s); + printf("\n"); + + return 0; +} + +static void flash_cs_fixup(void) +{ + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + int flash_sel; + + /* + * Print boot dev and swap flash flash chip selects if booted from 2nd + * flash. Swapping chip selects presents user with a common memory + * map regardless of which flash was booted from. + */ + flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS)); + printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); + + if (flash_sel) { + lbc->br0 = CONFIG_SYS_BR1_PRELIM; + lbc->or0 = CONFIG_SYS_OR1_PRELIM; + + lbc->br1 = CONFIG_SYS_BR0_PRELIM; + lbc->or1 = CONFIG_SYS_OR0_PRELIM; + } +} + +int board_early_init_r(void) +{ + /* Initialize PCA9557 devices */ + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + + /* + * Remap NOR flash region to caching-inhibited + * so that flash can be erased/programmed properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* Invalidate existing TLB entry for NOR flash */ + disable_tlb(0); + set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1); + + flash_cs_fixup(); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCI + ft_board_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); +} +#endif + +#ifdef CONFIG_MP +extern void cpu_mp_lmb_reserve(struct lmb *lmb); + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif |