diff options
Diffstat (limited to 'board/xilinx')
| -rw-r--r-- | board/xilinx/dts/microblaze-generic.dts (renamed from board/xilinx/microblaze-generic/dts/microblaze.dts) | 0 | ||||
| -rw-r--r-- | board/xilinx/dts/microblaze.dts | 1 | ||||
| -rw-r--r-- | board/xilinx/zynq/board.c | 23 |
3 files changed, 23 insertions, 1 deletions
diff --git a/board/xilinx/microblaze-generic/dts/microblaze.dts b/board/xilinx/dts/microblaze-generic.dts index 203330987..203330987 100644 --- a/board/xilinx/microblaze-generic/dts/microblaze.dts +++ b/board/xilinx/dts/microblaze-generic.dts diff --git a/board/xilinx/dts/microblaze.dts b/board/xilinx/dts/microblaze.dts deleted file mode 100644 index bf984b0cf..000000000 --- a/board/xilinx/dts/microblaze.dts +++ /dev/null @@ -1 +0,0 @@ -/include/ BOARD_DTS diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 4bb140e29..f7f1c59ac 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -20,6 +20,7 @@ Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); +Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); #endif int board_init(void) @@ -42,6 +43,9 @@ int board_init(void) case XILINX_ZYNQ_7045: fpga = fpga045; break; + case XILINX_ZYNQ_7100: + fpga = fpga100; + break; } #endif @@ -61,6 +65,23 @@ int board_eth_init(bd_t *bis) { u32 ret = 0; +#ifdef CONFIG_XILINX_AXIEMAC + ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, + XILINX_AXIDMA_BASEADDR); +#endif +#ifdef CONFIG_XILINX_EMACLITE + u32 txpp = 0; + u32 rxpp = 0; +# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG + txpp = 1; +# endif +# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG + rxpp = 1; +# endif + ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, + txpp, rxpp); +#endif + #if defined(CONFIG_ZYNQ_GEM) # if defined(CONFIG_ZYNQ_GEM0) ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, @@ -96,5 +117,7 @@ int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + zynq_ddrc_init(); + return 0; } |