summaryrefslogtreecommitdiff
path: root/board/tqc
diff options
context:
space:
mode:
Diffstat (limited to 'board/tqc')
-rw-r--r--board/tqc/tqm5200/cmd_stk52xx.c22
-rw-r--r--board/tqc/tqm5200/cmd_tb5200.c4
-rw-r--r--board/tqc/tqm8272/tqm8272.c2
-rw-r--r--board/tqc/tqm834x/pci.c2
-rw-r--r--board/tqc/tqm85xx/config.mk6
-rw-r--r--board/tqc/tqm85xx/law.c2
-rw-r--r--board/tqc/tqm85xx/nand.c6
-rw-r--r--board/tqc/tqm85xx/sdram.c141
-rw-r--r--board/tqc/tqm85xx/tlb.c19
-rw-r--r--board/tqc/tqm85xx/tqm85xx.c17
-rw-r--r--board/tqc/tqm8xx/u-boot.lds1
11 files changed, 174 insertions, 48 deletions
diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c
index 5483fcaf7..20632a7f1 100644
--- a/board/tqc/tqm5200/cmd_stk52xx.c
+++ b/board/tqc/tqm5200/cmd_stk52xx.c
@@ -327,7 +327,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
switch (argc) {
case 0:
case 1:
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
case 2:
if (strncmp(argv[1],"saw",3) == 0) {
@@ -342,7 +342,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return rcode;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
case 3:
if (strncmp(argv[1],"saw",3) == 0) {
@@ -358,7 +358,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
LEFT_RIGHT);
return rcode;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
case 4:
if (strncmp(argv[1],"saw",3) == 0) {
@@ -382,7 +382,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
pcm1772_write_reg((uchar)reg, (uchar)val);
return 0;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
case 5:
if (strncmp(argv[1],"saw",3) == 0) {
@@ -412,7 +412,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
channel);
return rcode;
}
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
printf ("Usage:\nsound cmd [arg1] [arg2] ...\n");
@@ -513,7 +513,7 @@ static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
channel = LEFT_RIGHT;
break;
default:
- printf ("Usage:\n%s\n", cmdtp->usage);
+ cmd_usage(cmdtp);
return 1;
}
@@ -1194,7 +1194,7 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
sound , 5, 1, cmd_sound,
- "sound - Sound sub-system\n",
+ "Sound sub-system",
"saw [duration] [freq] [channel]\n"
" - generate sawtooth for 'duration' ms with frequency 'freq'\n"
" on left \"l\" or right \"r\" channel\n"
@@ -1206,14 +1206,14 @@ U_BOOT_CMD(
U_BOOT_CMD(
wav , 3, 1, cmd_wav,
- "wav - play wav file\n",
+ "play wav file",
"[addr] [bytes]\n"
" - play wav file at address 'addr' with length 'bytes'\n"
);
U_BOOT_CMD(
beep , 2, 1, cmd_beep,
- "beep - play short beep\n",
+ "play short beep",
"[channel]\n"
" - play short beep on \"l\"eft or \"r\"ight channel\n"
);
@@ -1222,7 +1222,7 @@ U_BOOT_CMD(
#if defined(CONFIG_STK52XX)
U_BOOT_CMD(
fkt , 4, 1, cmd_fkt,
- "fkt - Function test routines\n",
+ "Function test routines",
"led number on/off\n"
" - 'number's like printed on STK52XX board\n"
"fkt can\n"
@@ -1237,7 +1237,7 @@ U_BOOT_CMD(
#elif defined(CONFIG_FO300)
U_BOOT_CMD(
fkt , 3, 1, cmd_fkt,
- "fkt - Function test routines\n",
+ "Function test routines",
"fkt can\n"
" - loopback plug for X16/X29 required\n"
"fkt rs232 number\n"
diff --git a/board/tqc/tqm5200/cmd_tb5200.c b/board/tqc/tqm5200/cmd_tb5200.c
index 214dca65e..b9c9e7e19 100644
--- a/board/tqc/tqm5200/cmd_tb5200.c
+++ b/board/tqc/tqm5200/cmd_tb5200.c
@@ -90,13 +90,13 @@ int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
led , 2, 1, cmd_led,
- "led - switch status LED on or off\n",
+ "switch status LED on or off",
"on/off\n"
);
U_BOOT_CMD(
backlight , 2, 1, cmd_backlight,
- "backlight - switch backlight on or off\n",
+ "switch backlight on or off",
"on/off\n"
);
diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c
index 5d0741d80..5bc080ff8 100644
--- a/board/tqc/tqm8272/tqm8272.c
+++ b/board/tqc/tqm8272/tqm8272.c
@@ -866,7 +866,7 @@ int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
hwib, 1, 1, do_hwib_dump,
- "hwib - dump HWIB'\n",
+ "dump HWIB'",
"\n"
);
diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c
index 0eedf4ae4..cb2cb8d32 100644
--- a/board/tqc/tqm834x/pci.c
+++ b/board/tqc/tqm834x/pci.c
@@ -181,7 +181,7 @@ pci_init_board(void)
CONFIG_PCI_SYS_MEM_BUS,
CONFIG_PCI_SYS_MEM_PHYS,
CONFIG_PCI_SYS_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 3;
diff --git a/board/tqc/tqm85xx/config.mk b/board/tqc/tqm85xx/config.mk
index 52e84ad77..37b7b234a 100644
--- a/board/tqc/tqm85xx/config.mk
+++ b/board/tqc/tqm85xx/config.mk
@@ -23,7 +23,9 @@
#
# tqm85xx board
-# default CCARBAR is at 0xff700000
-# assume U-Boot is less than 256k
#
+ifeq ($(CONFIG_TQM8548_BE),y)
+TEXT_BASE = 0xfff80000
+else
TEXT_BASE = 0xfffc0000
+endif
diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c
index fc92cd8b3..7e9a2c749 100644
--- a/board/tqc/tqm85xx/law.c
+++ b/board/tqc/tqm85xx/law.c
@@ -66,7 +66,7 @@
#endif
struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_2G, LAW_TRGT_IF_DDR),
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c
index dea652dfd..8133fdc40 100644
--- a/board/tqc/tqm85xx/nand.c
+++ b/board/tqc/tqm85xx/nand.c
@@ -395,7 +395,7 @@ static void upmb_write (u_char addr, ulong val)
*/
static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
{
- uint i;
+ uint i, j;
uint or3 = CONFIG_SYS_OR3_PRELIM;
uint clock = get_lbc_clock ();
@@ -429,8 +429,8 @@ static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
/* Assign address of table */
nand_upm_patt = upm_freq_table[i].upm_patt;
- for (i = 0; i < 64; i++) {
- upmb_write (i, *nand_upm_patt);
+ for (j = 0; j < 64; j++) {
+ upmb_write (j, *nand_upm_patt);
nand_upm_patt++;
}
diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c
index 783b2809e..6d73a88ab 100644
--- a/board/tqc/tqm85xx/sdram.c
+++ b/board/tqc/tqm85xx/sdram.c
@@ -1,3 +1,4 @@
+
/*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
@@ -38,11 +39,20 @@ struct sdram_conf_s {
typedef struct sdram_conf_s sdram_conf_t;
#ifdef CONFIG_TQM8548
+#ifdef CONFIG_TQM8548_AG
+sdram_conf_t ddr_cs_conf[] = {
+ {(1024 << 20), 0x80044202, 0x0002D000}, /* 1024MB, 14x10(4) */
+ { (512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
+ { (256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
+ { (128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
+};
+#else /* !CONFIG_TQM8548_AG */
sdram_conf_t ddr_cs_conf[] = {
{(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
{(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
{(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
};
+#endif /* CONFIG_TQM8548_AG */
#else /* !CONFIG_TQM8548 */
sdram_conf_t ddr_cs_conf[] = {
{(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
@@ -69,6 +79,9 @@ long int sdram_setup (int casl)
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
#ifdef CONFIG_TQM8548
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
+ volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+#endif
#else /* !CONFIG_TQM8548 */
unsigned long cfg_ddr_timing1;
unsigned long cfg_ddr_mode;
@@ -81,21 +94,23 @@ long int sdram_setup (int casl)
ddr->sdram_cfg = 0;
#ifdef CONFIG_TQM8548
+ /* Timing and refresh settings for DDR2-533 and below */
+
ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
ddr->cs0_config = ddr_cs_conf[0].reg;
- ddr->timing_cfg_3 = 0x00010000;
+ ddr->timing_cfg_3 = 0x00020000;
/* TIMING CFG 1, 533MHz
* PRETOACT: 4 Clocks
* ACTTOPRE: 12 Clocks
* ACTTORW: 4 Clocks
* CASLAT: 4 Clocks
- * REFREC: 34 Clocks
+ * REFREC: EXT_REFREC:REFREC 53 Clocks
* WRREC: 4 Clocks
* ACTTOACT: 3 Clocks
* WRTORD: 2 Clocks
*/
- ddr->timing_cfg_1 = 0x4C47A432;
+ ddr->timing_cfg_1 = 0x4C47D432;
/* TIMING CFG 2, 533MHz
* ADD_LAT: 3 Clocks
@@ -103,10 +118,10 @@ long int sdram_setup (int casl)
* WR_LAT: 3 Clocks
* RD_TO_PRE: 2 Clocks
* WR_DATA_DELAY: 1/2 Clock
- * CKE_PLS: 1 Clock
- * FOUR_ACT: 13 Clocks
+ * CKE_PLS: 3 Clock
+ * FOUR_ACT: 14 Clocks
*/
- ddr->timing_cfg_2 = 0x3318484D;
+ ddr->timing_cfg_2 = 0x331848CE;
/* DDR SDRAM Mode, 533MHz
* MRS: Extended Mode Register
@@ -136,13 +151,12 @@ long int sdram_setup (int casl)
ddr->sdram_interval = (1040 << 16) | 0x100;
/*
- * workaround for erratum DD10 of MPC8458 family below rev. 2.0:
- * DDR IO receiver must be set to an acceptable bias point by modifying
- * a hidden register.
+ * Workaround for erratum DDR19 according to MPC8548 Device Errata
+ * document, Rev. 1: DDR IO receiver must be set to an acceptable
+ * bias point by modifying a hidden register.
*/
- if (SVR_REV (get_svr ()) < 0x20) {
+ if (SVR_REV (get_svr ()) < 0x21)
gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */
- }
/* DDR SDRAM CFG 2
* FRC_SR: normal mode
@@ -170,7 +184,104 @@ long int sdram_setup (int casl)
/* wait for clock stabilization */
asm ("sync;isync;msync");
- udelay(1000);
+ udelay (1000);
+
+#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
+ /*
+ * Workaround for erratum DDR20 according to MPC8548 Device Errata
+ * document, Rev. 1: "CKE signal may not function correctly after
+ * assertion of HRESET"
+ */
+
+ /* 1. Configure DDR register as is done in normal DDR configuration.
+ * Do not set DDR_SDRAM_CFG[MEM_EN].
+ *
+ * 2. Set reserved bit EEBACR[3] at offset 0x1000
+ */
+ ecm->eebacr |= 0x10000000;
+
+ /*
+ * 3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT]
+ *
+ * DDR_SDRAM_CFG_2:
+ * FRC_SR: normal mode
+ * SR_IE: no self-refresh interrupt
+ * DLL_RST_DIS: don't care, leave at reset value
+ * DQS_CFG: differential DQS signals
+ * ODT_CFG: assert ODT to internal IOs only during reads to DRAM
+ * LVWx_CFG: don't care, leave at reset value
+ * NUM_PR: 1 refresh will be issued at a time
+ * DM_CFG: don't care, leave at reset value
+ * D_INIT: enable data initialization
+ */
+ ddr->sdram_cfg_2 |= 0x00000010;
+
+ /*
+ * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data
+ * training
+ */
+ ddr->debug_3 |= 0x00000400;
+
+ /*
+ * 5. Wait 200 micro-seconds
+ */
+ udelay (200);
+
+ /*
+ * 6. Set DDR_SDRAM_CFG[MEM_EN]
+ *
+ * BTW, initialize DDR_SDRAM_CFG:
+ * MEM_EN: enabled
+ * SREN: don't care, leave at reset value
+ * ECC_EN: no error report
+ * RD_EN: no registered DIMMs
+ * SDRAM_TYPE: DDR2
+ * DYN_PWR: no power management
+ * 32_BE: don't care, leave at reset value
+ * 8_BE: 4 beat burst
+ * NCAP: don't care, leave at reset value
+ * 2T_EN: 1T Timing
+ * BA_INTLV_CTL: no interleaving
+ * x32_EN: x16 organization
+ * PCHB8: MA[10] for auto-precharge
+ * HSE: half strength for single and 2-layer stacks
+ * (full strength for 3- and 4-layer stacks not
+ * yet considered)
+ * MEM_HALT: no halt
+ * BI: automatic initialization
+ */
+ ddr->sdram_cfg = 0x83000008;
+
+ /*
+ * 7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware
+ */
+ asm ("sync;isync;msync");
+ while (ddr->sdram_cfg_2 & 0x00000010)
+ asm ("eieio");
+
+ /*
+ * 8. Clear D3[21] to re-enable data training
+ */
+ ddr->debug_3 &= ~0x00000400;
+
+ /*
+ * 9. Set D2(21) to force data training to run
+ */
+ ddr->debug_2 |= 0x00000400;
+
+ /*
+ * 10. Poll on D2[21] until it is cleared by hardware
+ */
+ asm ("sync;isync;msync");
+ while (ddr->debug_2 & 0x00000400)
+ asm ("eieio");
+
+ /*
+ * 11. Clear reserved bit EEBACR[3] at offset 0x1000
+ */
+ ecm->eebacr &= ~0x10000000;
+
+#else /* !(CONFIG_TQM8548_AG || CONFIG_TQM8548_BE) */
/* DDR SDRAM CLK CNTL
* MEM_EN: enabled
@@ -192,9 +303,11 @@ long int sdram_setup (int casl)
* BI: automatic initialization
*/
ddr->sdram_cfg = 0x83000008;
- asm ("sync; isync; msync");
- udelay(1000);
+#endif /* CONFIG_TQM8548_AG || CONFIG_TQM8548_BE */
+
+ asm ("sync; isync; msync");
+ udelay (1000);
#else /* !CONFIG_TQM8548 */
switch (casl) {
case 20:
diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
index 16b102d1e..71fe3ab49 100644
--- a/board/tqc/tqm85xx/tlb.c
+++ b/board/tqc/tqm85xx/tlb.c
@@ -121,12 +121,25 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
+#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE)
+ /*
+ * TLB 7+8: 2G DDR, cache enabled
+ * 0x00000000 2G DDR System memory
+ * Without SPD EEPROM configured DDR, this must be setup manually.
+ */
+ SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_1G, 1),
+
+ SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+#else
/*
* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
* 0x00000000 512M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
- * Make sure the TLB count at the top of this table is correct.
- * Likely it needs to be increased by two for these entries.
*/
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
@@ -136,7 +149,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
-
+#endif
#ifdef CONFIG_PCIE1
/*
* TLB 9: 16M Non-cacheable, guarded
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
index 73f1d01bd..e1e75b83a 100644
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ b/board/tqc/tqm85xx/tqm85xx.c
@@ -315,8 +315,7 @@ int misc_init_r (void)
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ CONFIG_SYS_MONITOR_BASE, 0xffffffff,
&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
@@ -361,7 +360,7 @@ uint get_lbc_clock (void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
sys_info_t sys_info;
- ulong clkdiv = lbc->lcrr & 0x0f;
+ ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
get_sys_info (&sys_info);
@@ -541,9 +540,9 @@ static int first_free_busno;
extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
extern void fsl_pci_init(struct pci_controller *hose);
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
-#endif /* CONFIG_PCI || CONFIG_PCI1 */
+#endif /* CONFIG_PCI1 */
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
@@ -552,7 +551,7 @@ static struct pci_controller pcie1_hose;
static inline void init_pci1(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+#ifdef CONFIG_PCI1
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR;
struct pci_controller *hose = &pci1_hose;
@@ -627,9 +626,9 @@ static inline void init_pci1(void)
} else {
puts ("PCI1: disabled\n");
}
-#else /* !(CONFIG_PCI || CONFIG_PCI1) */
+#else /* !CONFIG_PCI1 */
gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
-#endif /* CONFIG_PCI || CONFIG_PCI1) */
+#endif /* CONFIG_PCI1 */
}
static inline void init_pcie1(void)
@@ -708,7 +707,7 @@ void ft_board_setup (void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
+#ifdef CONFIG_PCI1
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds
index 5af36c97a..5c9b26cfd 100644
--- a/board/tqc/tqm8xx/u-boot.lds
+++ b/board/tqc/tqm8xx/u-boot.lds
@@ -63,7 +63,6 @@ SECTIONS
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
generated by cgit v1.2.3-70-g09d2 (git 2.51.2) at 2025-11-01 09:28:41 +0000