diff options
Diffstat (limited to 'board/sc3/sc3.c')
| -rw-r--r-- | board/sc3/sc3.c | 96 |
1 files changed, 48 insertions, 48 deletions
diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c index 6c82fe7e9..5ae7b1244 100644 --- a/board/sc3/sc3.c +++ b/board/sc3/sc3.c @@ -199,14 +199,14 @@ int board_start_ide(void) static int sc3_cameron_init (void) { /* Set up the Memory Controller for the CAMERON version */ - mtebc (pb4ap, 0x01805940); - mtebc (pb4cr, 0x7401a000); - mtebc (pb5ap, 0x01805940); - mtebc (pb5cr, 0x7401a000); - mtebc (pb6ap, 0x0); - mtebc (pb6cr, 0x0); - mtebc (pb7ap, 0x0); - mtebc (pb7cr, 0x0); + mtebc (PB4AP, 0x01805940); + mtebc (PB4CR, 0x7401a000); + mtebc (PB5AP, 0x01805940); + mtebc (PB5CR, 0x7401a000); + mtebc (PB6AP, 0x0); + mtebc (PB6CR, 0x0); + mtebc (PB7AP, 0x0); + mtebc (PB7CR, 0x0); return 0; } @@ -312,18 +312,18 @@ int board_early_init_f (void) mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ /* setup other implementation specific details */ - mtdcr (ecr, 0x60606000); + mtdcr (CPC0_ECR, 0x60606000); - mtdcr (cntrl1, 0x000042C0); + mtdcr (CPC0_CR1, 0x000042C0); if (IS_CAMERON) { - mtdcr (cntrl0, 0x01380000); + mtdcr (CPC0_CR0, 0x01380000); /* Setup the GPIOs */ writel (0x08008000, 0xEF600700); /* Output states */ writel (0x00000000, 0xEF600718); /* Open Drain control */ writel (0x68098000, 0xEF600704); /* Output control */ } else { - mtdcr (cntrl0,0x00080000); + mtdcr (CPC0_CR0,0x00080000); /* Setup the GPIOs */ writel (0x08000000, 0xEF600700); /* Output states */ writel (0x14000000, 0xEF600718); /* Open Drain control */ @@ -331,13 +331,13 @@ int board_early_init_f (void) } /* Code decompression disabled */ - mtdcr (kiar, kconf); - mtdcr (kidr, 0x2B); + mtdcr (KIAR, KCONF); + mtdcr (KIDR, 0x2B); /* CPC0_ER: enable sleep mode of (currently) unused components */ /* CPC0_FR: force unused components into sleep mode */ - mtdcr (cpmer, 0x3F800000); - mtdcr (cpmfr, 0x14000000); + mtdcr (CPMER, 0x3F800000); + mtdcr (CPMFR, 0x14000000); /* set PLB priority */ mtdcr (0x87, 0x08000000); @@ -472,19 +472,19 @@ static void printCSConfig(int reg,unsigned long ap,unsigned long cr) #ifdef SC3_DEBUGOUT -static unsigned int ap[] = {pb0ap, pb1ap, pb2ap, pb3ap, pb4ap, - pb5ap, pb6ap, pb7ap}; -static unsigned int cr[] = {pb0cr, pb1cr, pb2cr, pb3cr, pb4cr, - pb5cr, pb6cr, pb7cr}; +static unsigned int ap[] = {PB0AP, PB1AP, PB2AP, PB3AP, PB4AP, + PB5AP, PB6AP, PB7AP}; +static unsigned int cr[] = {PB0CR, PB1CR, PB2CR, PB3CR, PB4CR, + PB5CR, PB6CR, PB7CR}; static int show_reg (int nr) { unsigned long ul1, ul2; - mtdcr (ebccfga, ap[nr]); - ul1 = mfdcr (ebccfgd); - mtdcr (ebccfga, cr[nr]); - ul2 = mfdcr(ebccfgd); + mtdcr (EBC0_CFGADDR, ap[nr]); + ul1 = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, cr[nr]); + ul2 = mfdcr(EBC0_CFGDATA); printCSConfig(nr, ul1, ul2); return 0; } @@ -500,8 +500,8 @@ int checkboard (void) show_reg (i); } - mtdcr (ebccfga, epcr); - ul1 = mfdcr (ebccfgd); + mtdcr (EBC0_CFGADDR, EBC0_CFG); + ul1 = mfdcr (EBC0_CFGDATA); puts ("\nGeneral configuration:\n"); @@ -591,21 +591,21 @@ phys_size_t initdram (int board_type) puts("\nSDRAM configuration:\n"); - mtdcr (memcfga, mem_mcopt1); - ul1 = mfdcr(memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + ul1 = mfdcr(SDRAM0_CFGDATA); if (!(ul1 & 0x80000000)) { puts(" Controller disabled\n"); return 0; } for (i = 0; i < 4; i++) { - mtdcr (memcfga, mbcf[i]); - ul1 = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mbcf[i]); + ul1 = mfdcr (SDRAM0_CFGDATA); mems += printSDRAMConfig (i, ul1); } - mtdcr (memcfga, mem_sdtr1); - ul1 = mfdcr(memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + ul1 = mfdcr(SDRAM0_CFGDATA); printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1); printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1); @@ -614,15 +614,15 @@ phys_size_t initdram (int board_type) printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4); printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1)); puts ("Misc:\n"); - mtdcr (memcfga, mem_rtr); - ul1 = mfdcr(memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + ul1 = mfdcr(SDRAM0_CFGDATA); printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7); - mtdcr(memcfga,mem_pmit); - ul2=mfdcr(memcfgd); + mtdcr(SDRAM0_CFGADDR,mem_pmit); + ul2=mfdcr(SDRAM0_CFGDATA); - mtdcr(memcfga,mem_mcopt1); - ul1=mfdcr(memcfgd); + mtdcr(SDRAM0_CFGADDR,mem_mcopt1); + ul1=mfdcr(SDRAM0_CFGDATA); if (ul1 & 0x20000000) printf(" -Power Down after: %luns\n", @@ -658,8 +658,8 @@ phys_size_t initdram (int board_type) else puts(" -Memory lines only at write cycles active outputs\n"); - mtdcr (memcfga, mem_status); - ul1 = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_status); + ul1 = mfdcr (SDRAM0_CFGDATA); if (ul1 & 0x80000000) puts(" -SDRAM Controller ready\n"); else @@ -670,20 +670,20 @@ phys_size_t initdram (int board_type) return (mems * 1024 * 1024); #else - mtdcr (memcfga, mem_mb0cf); - ul1 = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + ul1 = mfdcr (SDRAM0_CFGDATA); mems = printSDRAMConfig (0, ul1); - mtdcr (memcfga, mem_mb1cf); - ul1 = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + ul1 = mfdcr (SDRAM0_CFGDATA); mems += printSDRAMConfig (1, ul1); - mtdcr (memcfga, mem_mb2cf); - ul1 = mfdcr(memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + ul1 = mfdcr(SDRAM0_CFGDATA); mems += printSDRAMConfig (2, ul1); - mtdcr (memcfga, mem_mb3cf); - ul1 = mfdcr(memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + ul1 = mfdcr(SDRAM0_CFGDATA); mems += printSDRAMConfig (3, ul1); return (mems * 1024 * 1024); |