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-rw-r--r--board/prodrive/alpr/alpr.c34
-rw-r--r--board/prodrive/alpr/config.mk2
-rw-r--r--board/prodrive/alpr/fpga.c70
-rw-r--r--board/prodrive/alpr/init.S24
-rw-r--r--board/prodrive/alpr/nand.c2
-rw-r--r--board/prodrive/common/flash.c130
-rw-r--r--board/prodrive/common/fpga.c10
-rw-r--r--board/prodrive/p3mx/misc.S26
-rw-r--r--board/prodrive/p3mx/mpsc.c6
-rw-r--r--board/prodrive/p3mx/p3mx.c98
-rw-r--r--board/prodrive/p3mx/pci.c20
-rw-r--r--board/prodrive/p3mx/sdram_init.c6
-rw-r--r--board/prodrive/p3p440/config.mk2
-rw-r--r--board/prodrive/p3p440/init.S12
-rw-r--r--board/prodrive/p3p440/p3p440.c32
-rw-r--r--board/prodrive/p3p440/p3p440.h10
-rw-r--r--board/prodrive/pdnb3/flash.c10
-rw-r--r--board/prodrive/pdnb3/nand.c2
-rw-r--r--board/prodrive/pdnb3/pdnb3.c64
19 files changed, 280 insertions, 280 deletions
diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
index cc491d05b..dc3431961 100644
--- a/board/prodrive/alpr/alpr.c
+++ b/board/prodrive/alpr/alpr.c
@@ -92,8 +92,8 @@ int board_early_init_f (void)
mtdcr (uic0vr, 0x00000001); /* */
/* Setup shutdown/SSD empty interrupt as inputs */
- out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
- out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
+ out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
/* Setup GPIO/IRQ multiplexing */
mtsdr(sdr_pfc0, 0x01a33e00);
@@ -124,8 +124,8 @@ int last_stage_init(void)
static int board_rev(void)
{
/* Setup as input */
- out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
- out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
+ out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
return (in32(GPIO0_IR) >> 16) & 0x3;
}
@@ -186,7 +186,7 @@ int pci_pre_init(struct pci_controller * hose )
* may not be sufficient for a given board.
*
************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
/*--------------------------------------------------------------------------+
@@ -201,7 +201,7 @@ void pci_target_init(struct pci_controller * hose )
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+ out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
out32r( PCIX0_PIM0LAH, 0 );
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
@@ -210,12 +210,12 @@ void pci_target_init(struct pci_controller * hose )
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+ out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+ out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* is_pci_host
@@ -239,11 +239,11 @@ static void wait_for_pci_ready(void)
/*
* Configure EREADY as input
*/
- out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY);
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_GPIO_EREADY);
udelay(1000);
for (;;) {
- if (in32(GPIO0_IR) & CFG_GPIO_EREADY)
+ if (in32(GPIO0_IR) & CONFIG_SYS_GPIO_EREADY)
return;
}
@@ -260,7 +260,7 @@ int is_pci_host(struct pci_controller *hose)
* pci_master_init
*
************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
@@ -274,19 +274,19 @@ void pci_master_init(struct pci_controller *hose)
out32r( PCIX0_POM1SA, 0 ); /* disable */
out32r( PCIX0_POM2SA, 0 ); /* disable */
- out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIX0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_POM0LAH, 0x00000003); /* PMM0 Local Address */
- out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
- out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIX0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_POM1LAH, 0x00000003); /* PMM0 Local Address */
- out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
#ifdef CONFIG_POST
/*
diff --git a/board/prodrive/alpr/config.mk b/board/prodrive/alpr/config.mk
index 9e1833591..b62e776d3 100644
--- a/board/prodrive/alpr/config.mk
+++ b/board/prodrive/alpr/config.mk
@@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c
index e94360f81..0ecebc943 100644
--- a/board/prodrive/alpr/fpga.c
+++ b/board/prodrive/alpr/fpga.c
@@ -61,10 +61,10 @@ static unsigned long regval;
#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit)
#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit)
-#define FPGA_PRG (0x80000000 >> CFG_GPIO_PROG_EN)
-#define FPGA_CONFIG (0x80000000 >> CFG_GPIO_CONFIG)
-#define FPGA_DATA (0x80000000 >> CFG_GPIO_DATA)
-#define FPGA_CLK (0x80000000 >> CFG_GPIO_CLK)
+#define FPGA_PRG (0x80000000 >> CONFIG_SYS_GPIO_PROG_EN)
+#define FPGA_CONFIG (0x80000000 >> CONFIG_SYS_GPIO_CONFIG)
+#define FPGA_DATA (0x80000000 >> CONFIG_SYS_GPIO_DATA)
+#define FPGA_CLK (0x80000000 >> CONFIG_SYS_GPIO_CLK)
#define OLD_VAL (FPGA_PRG | FPGA_CONFIG)
#define SET_FPGA(data) out32(GPIO0_OR, data)
@@ -87,43 +87,43 @@ int fpga_pre_fn (int cookie)
reg = in32(GPIO0_IR);
/* Enable the FPGA Chain */
- SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_PROG_EN);
- SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_PROG_EN);
- SET_GPIO_1(CFG_GPIO_PROG_EN);
- SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_SEL_DPR);
- SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR);
- SET_GPIO_0((CFG_GPIO_SEL_DPR));
+ SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN);
+ SET_GPIO_1(CONFIG_SYS_GPIO_PROG_EN);
+ SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_SEL_DPR);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_SEL_DPR);
+ SET_GPIO_0((CONFIG_SYS_GPIO_SEL_DPR));
/* initialize the GPIO Pins */
/* output */
- SET_GPIO_0(CFG_GPIO_CLK);
- SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK);
- SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CLK);
+ SET_GPIO_0(CONFIG_SYS_GPIO_CLK);
+ SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CLK);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CLK);
/* output */
- SET_GPIO_0(CFG_GPIO_DATA);
- SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_DATA);
- SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_DATA);
+ SET_GPIO_0(CONFIG_SYS_GPIO_DATA);
+ SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_DATA);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_DATA);
/* First we set STATUS to 0 then as an input */
- SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_STATUS);
- SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS);
- SET_GPIO_0(CFG_GPIO_STATUS);
- SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_STATUS);
- SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS);
+ SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
+ SET_GPIO_0(CONFIG_SYS_GPIO_STATUS);
+ SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
/* output */
- SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CONFIG);
- SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CONFIG);
- SET_GPIO_0(CFG_GPIO_CONFIG);
+ SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CONFIG);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CONFIG);
+ SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
/* input */
- SET_GPIO_0(CFG_GPIO_CON_DON);
- SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_CON_DON);
- SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CON_DON);
+ SET_GPIO_0(CONFIG_SYS_GPIO_CON_DON);
+ SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_CON_DON);
+ SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CON_DON);
/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
- SET_GPIO_0(CFG_GPIO_CONFIG);
+ SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
return FPGA_SUCCESS;
}
@@ -131,9 +131,9 @@ int fpga_pre_fn (int cookie)
int fpga_config_fn (int assert_config, int flush, int cookie)
{
if (assert_config) {
- SET_GPIO_1(CFG_GPIO_CONFIG);
+ SET_GPIO_1(CONFIG_SYS_GPIO_CONFIG);
} else {
- SET_GPIO_0(CFG_GPIO_CONFIG);
+ SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
}
return FPGA_SUCCESS;
}
@@ -144,7 +144,7 @@ int fpga_status_fn (int cookie)
unsigned long reg;
reg = in32(GPIO0_IR);
- if (reg &= (0x80000000 >> CFG_GPIO_STATUS)) {
+ if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_STATUS)) {
PRINTF("STATUS = HIGH\n");
return FPGA_FAIL;
}
@@ -157,7 +157,7 @@ int fpga_done_fn (int cookie)
{
unsigned long reg;
reg = in32(GPIO0_IR);
- if (reg &= (0x80000000 >> CFG_GPIO_CON_DON)) {
+ if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_CON_DON)) {
PRINTF("CONF_DON = HIGH\n");
return FPGA_FAIL;
}
@@ -189,10 +189,10 @@ int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
i --;
} while (i > 0);
-#ifdef CFG_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % len_40 == 0) {
putc ('.'); /* let them know we are alive */
-#ifdef CFG_FPGA_CHECK_CTRLC
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
if (ctrlc ())
return FPGA_FAIL;
#endif
@@ -205,7 +205,7 @@ int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
/* called, when programming is aborted */
int fpga_abort_fn (int cookie)
{
- SET_GPIO_1((CFG_GPIO_SEL_DPR));
+ SET_GPIO_1((CONFIG_SYS_GPIO_SEL_DPR));
return FPGA_SUCCESS;
}
diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S
index 76164ce1d..4af7d13bf 100644
--- a/board/prodrive/alpr/init.S
+++ b/board/prodrive/alpr/init.S
@@ -87,26 +87,26 @@
tlbtab:
tlbtab_start
tlbentry( 0xff000000, SZ_16M, 0xff000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+ tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
+ tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
#ifdef CONFIG_4xx_DCACHE
- tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G)
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G)
#else
- tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
#endif
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
#endif
- tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
/* PCI */
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I )
/* NAND */
- tlbentry( CFG_NAND_BASE, SZ_4K, CFG_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbtab_end
diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c
index 99f5737b8..b18c96b29 100644
--- a/board/prodrive/alpr/nand.c
+++ b/board/prodrive/alpr/nand.c
@@ -137,7 +137,7 @@ static int alpr_nand_dev_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand)
{
- alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE;
+ alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE;
nand->ecc.mode = NAND_ECC_SOFT;
diff --git a/board/prodrive/common/flash.c b/board/prodrive/common/flash.c
index 363631fd8..c42fa837f 100644
--- a/board/prodrive/common/flash.c
+++ b/board/prodrive/common/flash.c
@@ -24,7 +24,7 @@
#include <common.h>
#include <asm/processor.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*
* Functions
@@ -91,7 +91,7 @@ void flash_print_info(flash_info_t *info)
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
-#ifdef CFG_FLASH_EMPTY_INFO
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
/*
* Check if whole sector is erased
*/
@@ -136,31 +136,31 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info)
{
short i;
short n;
- CFG_FLASH_WORD_SIZE value;
+ CONFIG_SYS_FLASH_WORD_SIZE value;
ulong base = (ulong)addr;
- volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
/* Write auto select command: read Manufacturer ID */
- addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
- value = addr2[CFG_FLASH_READ0];
+ value = addr2[CONFIG_SYS_FLASH_READ0];
switch (value) {
- case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
- case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
- case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
info->flash_id = FLASH_MAN_SST;
break;
- case (CFG_FLASH_WORD_SIZE)STM_MANUFACT:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT:
info->flash_id = FLASH_MAN_STM;
break;
- case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
info->flash_id = FLASH_MAN_EXCEL;
break;
default:
@@ -170,82 +170,82 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info)
return (0); /* no or unknown flash */
}
- value = addr2[CFG_FLASH_READ1]; /* device ID */
+ value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */
switch (value) {
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
info->flash_id += FLASH_AMDL322T;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
info->flash_id += FLASH_AMDL322B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
info->flash_id += FLASH_AMDL323T;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
info->flash_id += FLASH_AMDL323B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
- case (CFG_FLASH_WORD_SIZE)SST_ID_xF020:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF020:
info->flash_id += FLASH_SST020;
info->sector_count = 64;
info->size = 0x00040000;
break; /* => 256 kB */
- case (CFG_FLASH_WORD_SIZE)SST_ID_xF040:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF040:
info->flash_id += FLASH_SST040;
info->sector_count = 128;
info->size = 0x00080000;
@@ -318,19 +318,19 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info)
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
- addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+ addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
info->protect[i] = 0;
else
- info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+ info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
- addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+ *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
}
return (info->size);
@@ -339,8 +339,8 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info)
int flash_erase(flash_info_t *info, int s_first, int s_last)
{
- volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
- volatile CFG_FLASH_WORD_SIZE *addr2;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
ulong start, now, last;
@@ -375,14 +375,14 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
- addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
/* re-enable interrupts if necessary */
if (flag) {
@@ -392,20 +392,20 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
/* data polling for D7 */
start = get_timer (0);
- while ((addr2[0] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
- (CFG_FLASH_WORD_SIZE)0x00800080) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+ while ((addr2[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+ (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
return (1);
}
} else {
if (sect == s_first) {
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
}
- addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
}
l_sect = sect;
}
@@ -426,9 +426,9 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
start = get_timer (0);
last = start;
- addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);
- while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
+ while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
@@ -441,8 +441,8 @@ int flash_erase(flash_info_t *info, int s_first, int s_last)
DONE:
/* reset to read mode */
- addr = (CFG_FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+ addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
printf (" done\n");
return 0;
@@ -522,9 +522,9 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
*/
static int write_word(flash_info_t *info, ulong dest, ulong data)
{
- volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
- volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
- volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data;
ulong start;
int flag;
int i;
@@ -536,10 +536,10 @@ static int write_word(flash_info_t *info, ulong dest, ulong data)
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
- for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) {
- addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+ for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
dest2[i] = data2[i];
@@ -549,9 +549,9 @@ static int write_word(flash_info_t *info, ulong dest, ulong data)
/* data polling for D7 */
start = get_timer (0);
- while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
- (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+ while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+ (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
return (1);
}
}
diff --git a/board/prodrive/common/fpga.c b/board/prodrive/common/fpga.c
index f9412a21e..14bff07bf 100644
--- a/board/prodrive/common/fpga.c
+++ b/board/prodrive/common/fpga.c
@@ -37,11 +37,11 @@
#define DBG(x...)
#endif /* DEBUG */
-#define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (cpu output)*/
-#define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (cpu output) */
-#define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (cpu output) */
-#define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (cpu input) */
-#define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (cpu input) */
+#define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (cpu output)*/
+#define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (cpu output) */
+#define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (cpu output) */
+#define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (cpu input) */
+#define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (cpu input) */
#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
diff --git a/board/prodrive/p3mx/misc.S b/board/prodrive/p3mx/misc.S
index 160b1d31f..233fd83bc 100644
--- a/board/prodrive/p3mx/misc.S
+++ b/board/prodrive/p3mx/misc.S
@@ -16,7 +16,7 @@
board_relocate_rom:
mflr r7
/* update the location of the GT registers */
- lis r11, CFG_GT_REGS@h
+ lis r11, CONFIG_SYS_GT_REGS@h
/* if we're using ECC, we must use the DMA engine to copy ourselves */
bl start_idma_transfer_0
bl wait_for_idma_0
@@ -29,12 +29,12 @@ board_relocate_rom:
board_init_ecc:
mflr r7
/* NOTE: r10 still contains the location we've been relocated to
- * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
+ * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
/* now that we're running from ram, init the rest of main memory
* for ECC use */
- lis r8, CFG_MONITOR_LEN@h
- ori r8, r8, CFG_MONITOR_LEN@l
+ lis r8, CONFIG_SYS_MONITOR_LEN@h
+ ori r8, r8, CONFIG_SYS_MONITOR_LEN@l
divw r3, r10, r8
@@ -120,15 +120,15 @@ stop_idma_engine_0:
blr
#endif
-#ifdef CFG_BOARD_ASM_INIT
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
/* NOTE: trashes r3-r7 */
.globl board_asm_init
board_asm_init:
/* just move the GT registers to where they belong */
- lis r3, CFG_DFL_GT_REGS@h
- ori r3, r3, CFG_DFL_GT_REGS@l
- lis r4, CFG_GT_REGS@h
- ori r4, r4, CFG_GT_REGS@l
+ lis r3, CONFIG_SYS_DFL_GT_REGS@h
+ ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l
+ lis r4, CONFIG_SYS_GT_REGS@h
+ ori r4, r4, CONFIG_SYS_GT_REGS@l
li r5, INTERNAL_SPACE_DECODE
/* test to see if we've already moved */
@@ -153,11 +153,11 @@ board_asm_init:
cmp cr0, r7, r6
bne 1b
- lis r3, CFG_INT_SRAM_BASE@h
- ori r3, r3, CFG_INT_SRAM_BASE@l
+ lis r3, CONFIG_SYS_INT_SRAM_BASE@h
+ ori r3, r3, CONFIG_SYS_INT_SRAM_BASE@l
rlwinm r3, r3, 16, 16, 31
- lis r4, CFG_GT_REGS@h
- ori r4, r4, CFG_GT_REGS@l
+ lis r4, CONFIG_SYS_GT_REGS@h
+ ori r4, r4, CONFIG_SYS_GT_REGS@l
li r5, INTEGRATED_SRAM_BASE_ADDR
stwbrx r3, r5, r4
diff --git a/board/prodrive/p3mx/mpsc.c b/board/prodrive/p3mx/mpsc.c
index 2494ec6df..cc05b4503 100644
--- a/board/prodrive/p3mx/mpsc.c
+++ b/board/prodrive/p3mx/mpsc.c
@@ -422,7 +422,7 @@ void mpsc_sdma_init (void)
(MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
/* Setup MPSC internal address space base address */
- GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+ GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
/* no high address remap*/
GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
@@ -512,9 +512,9 @@ int galbrg_set_baudrate (int channel, int rate)
#ifdef ZUMA_NTL
/* from tclk */
- clock = (CFG_TCLK / (16 * rate)) - 1;
+ clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
#else
- clock = (CFG_TCLK / (16 * rate)) - 1;
+ clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
#endif
galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */
diff --git a/board/prodrive/p3mx/p3mx.c b/board/prodrive/p3mx/p3mx.c
index 69d7c9b28..0247bb80a 100644
--- a/board/prodrive/p3mx/p3mx.c
+++ b/board/prodrive/p3mx/p3mx.c
@@ -67,7 +67,7 @@ extern flash_info_t flash_info[];
/* ------------------------------------------------------------------------- */
/* this is the current GT register space location */
-/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
/* Unfortunately, we cant change it while we are in flash, so we initialize it
* to the "final" value. This means that any debug_led calls before
@@ -76,7 +76,7 @@ extern flash_info_t flash_info[];
*/
void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
int display_mem_map (void);
void set_led(int);
@@ -129,7 +129,7 @@ static void gt_pci_config (void)
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CFG_PCI_IDSEL);
+ (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */
@@ -138,7 +138,7 @@ static void gt_pci_config (void)
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CFG_PCI_IDSEL);
+ (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
/* Enable master */
@@ -157,21 +157,21 @@ static void gt_pci_config (void)
* in 64360 when writing to pci base go and overide remap automaticaly,
* in 64460 it doesn't
*/
- GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16);
- GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16);
- GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
+ GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
+ GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
- GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
- GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16);
- GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16);
- GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
+ GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
+ GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
- GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
/* PCI interface settings */
/* Timeout set to retry forever */
@@ -189,7 +189,7 @@ static void gt_pci_config (void)
for (stat = 0; stat <= PCI_HOST1; stat++)
pciWriteConfigReg (stat,
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
- SELF, CFG_GT_REGS);
+ SELF, CONFIG_SYS_GT_REGS);
#endif
}
@@ -204,7 +204,7 @@ static void gt_cpu_config (void)
/* cpu configuration register */
tmp = GTREGREAD (CPU_CONFIGURATION);
/* set the SINGLE_CPU bit see MV64460 */
-#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
+#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
tmp |= CPU_CONF_SINGLE_CPU;
#endif
tmp &= ~CPU_CONF_AACK_DELAY_2;
@@ -246,7 +246,7 @@ int board_early_init_f (void)
* that if it's not at the power-on location, it's where we put
* it last time. (huber)
*/
- my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+ my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
#ifdef CONFIG_PCI
gt_pci_config ();
@@ -274,17 +274,17 @@ int board_early_init_f (void)
memoryMapDeviceSpace(DEVICE3, 0, 0);
GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0);
- GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_BOOT_PAR);
+ GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_BOOT_PAR);
gt_cpu_config();
/* MPP setup */
- GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
- GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
- GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
- GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+ GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+ GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+ GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+ GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
- GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+ GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
set_led(LED_RED);
@@ -298,7 +298,7 @@ int misc_init_r ()
u8 val;
icache_enable ();
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
l2cache_enable ();
#endif
#ifdef CONFIG_MPSC
@@ -311,7 +311,7 @@ int misc_init_r ()
* No diode, 250 ohm series resistor
*/
val = 0xa5;
- i2c_write(CFG_I2C_RTC_ADDR, 8, 1, &val, 1);
+ i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 8, 1, &val, 1);
return 0;
}
@@ -328,7 +328,7 @@ int board_early_init_r(void)
void after_reloc (ulong dest_addr, gd_t * gd)
{
- memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE);
+ memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE);
/* display_mem_map(); */
@@ -347,7 +347,7 @@ int checkboard (void)
{
char *s = getenv("serial#");
- printf("Board: %s", CFG_BOARD_NAME);
+ printf("Board: %s", CONFIG_SYS_BOARD_NAME);
if (s != NULL) {
puts(", serial# ");
@@ -458,7 +458,7 @@ int display_mem_map (void)
/* DRAM check routines copied from gw8260 */
-#if defined (CFG_DRAM_TEST)
+#if defined (CONFIG_SYS_DRAM_TEST)
/*********************************************************************/
/* NAME: move64() - moves a double word (64-bit) */
@@ -489,7 +489,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
}
-#if defined (CFG_DRAM_TEST_DATA)
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
unsigned long long pattern[] = {
0xaaaaaaaaaaaaaaaaULL,
@@ -552,7 +552,7 @@ unsigned long long pattern[] = {
/*********************************************************************/
int mem_test_data (void)
{
- unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+ unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
@@ -579,9 +579,9 @@ int mem_test_data (void)
return 0;
}
-#endif /* CFG_DRAM_TEST_DATA */
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
-#if defined (CFG_DRAM_TEST_ADDRESS)
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
/*********************************************************************/
/* NAME: mem_test_address() - test address lines */
/* */
@@ -606,8 +606,8 @@ int mem_test_data (void)
int mem_test_address (void)
{
volatile unsigned int *pmem =
- (volatile unsigned int *) CFG_MEMTEST_START;
- const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+ (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
+ const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
unsigned int i;
/* write address to each location */
@@ -623,9 +623,9 @@ int mem_test_address (void)
}
return 0;
}
-#endif /* CFG_DRAM_TEST_ADDRESS */
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
-#if defined (CFG_DRAM_TEST_WALK)
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
/*********************************************************************/
/* NAME: mem_march() - memory march */
/* */
@@ -683,7 +683,7 @@ int mem_march (volatile unsigned long long *base,
}
return 0;
}
-#endif /* CFG_DRAM_TEST_WALK */
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
/*********************************************************************/
/* NAME: mem_test_walk() - a simple walking ones test */
@@ -715,8 +715,8 @@ int mem_test_walk (void)
{
unsigned long long mask;
volatile unsigned long long *pmem =
- (volatile unsigned long long *) CFG_MEMTEST_START;
- const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+ (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
+ const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
unsigned int i;
@@ -782,15 +782,15 @@ int testdram (void)
int runaddress = 0;
int runwalk = 0;
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
s = getenv ("testdramdata");
rundata = (s && (*s == 'y')) ? 1 : 0;
#endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
s = getenv ("testdramaddress");
runaddress = (s && (*s == 'y')) ? 1 : 0;
#endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
s = getenv ("testdramwalk");
runwalk = (s && (*s == 'y')) ? 1 : 0;
#endif
@@ -798,8 +798,8 @@ int testdram (void)
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
printf ("Testing RAM from 0x%08x to 0x%08x ... "
"(don't panic... that will take a moment !!!!)\n",
- CFG_MEMTEST_START, CFG_MEMTEST_END);
-#ifdef CFG_DRAM_TEST_DATA
+ CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
if (rundata == 1) {
printf ("Test DATA ... ");
if (mem_test_data () == 1) {
@@ -809,7 +809,7 @@ int testdram (void)
printf ("ok \n");
}
#endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
if (runaddress == 1) {
printf ("Test ADDRESS ... ");
if (mem_test_address () == 1) {
@@ -819,7 +819,7 @@ int testdram (void)
printf ("ok \n");
}
#endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
if (runwalk == 1) {
printf ("Test WALKING ONEs ... ");
if (mem_test_walk () == 1) {
@@ -834,7 +834,7 @@ int testdram (void)
return 0;
}
-#endif /* CFG_DRAM_TEST */
+#endif /* CONFIG_SYS_DRAM_TEST */
/* ronen - the below functions are used by the bootm function */
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
diff --git a/board/prodrive/p3mx/pci.c b/board/prodrive/p3mx/pci.c
index 137739bed..85f7caab0 100644
--- a/board/prodrive/p3mx/pci.c
+++ b/board/prodrive/p3mx/pci.c
@@ -932,14 +932,14 @@ void pci_init_board (void)
/* PCI memory space */
pci_set_region (pci0_hose.regions + 0,
- CFG_PCI0_0_MEM_SPACE,
- CFG_PCI0_0_MEM_SPACE,
- CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+ CONFIG_SYS_PCI0_0_MEM_SPACE,
+ CONFIG_SYS_PCI0_0_MEM_SPACE,
+ CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci0_hose.regions + 1,
- CFG_PCI0_IO_SPACE_PCI,
- CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+ CONFIG_SYS_PCI0_IO_SPACE_PCI,
+ CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci0_hose,
pci_hose_read_config_byte_via_dword,
@@ -981,14 +981,14 @@ void pci_init_board (void)
/* PCI memory space */
pci_set_region (pci1_hose.regions + 0,
- CFG_PCI1_0_MEM_SPACE,
- CFG_PCI1_0_MEM_SPACE,
- CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+ CONFIG_SYS_PCI1_0_MEM_SPACE,
+ CONFIG_SYS_PCI1_0_MEM_SPACE,
+ CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci1_hose.regions + 1,
- CFG_PCI1_IO_SPACE_PCI,
- CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+ CONFIG_SYS_PCI1_IO_SPACE_PCI,
+ CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci1_hose,
pci_hose_read_config_byte_via_dword,
diff --git a/board/prodrive/p3mx/sdram_init.c b/board/prodrive/p3mx/sdram_init.c
index d881d3807..bac6c12b9 100644
--- a/board/prodrive/p3mx/sdram_init.c
+++ b/board/prodrive/p3mx/sdram_init.c
@@ -243,9 +243,9 @@ phys_size_t initdram (int board_type)
udelay(2); /* FIXME make this dynamic for the system clock */
/* SDRAM init done */
- memory_map_bank(0, CFG_SDRAM_BASE, (256 << 20));
-#ifdef CFG_SDRAM1_BASE
- memory_map_bank(1, CFG_SDRAM1_BASE, (256 << 20));
+ memory_map_bank(0, CONFIG_SYS_SDRAM_BASE, (256 << 20));
+#ifdef CONFIG_SYS_SDRAM1_BASE
+ memory_map_bank(1, CONFIG_SYS_SDRAM1_BASE, (256 << 20));
#endif
/* DUNIT_MMASK: enable SnoopHitEn bit to avoid errata CPU-#4
diff --git a/board/prodrive/p3p440/config.mk b/board/prodrive/p3p440/config.mk
index e5722dd36..60d3bf4d2 100644
--- a/board/prodrive/p3p440/config.mk
+++ b/board/prodrive/p3p440/config.mk
@@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
diff --git a/board/prodrive/p3p440/init.S b/board/prodrive/p3p440/init.S
index ee6b7066e..8c1a79c4b 100644
--- a/board/prodrive/p3p440/init.S
+++ b/board/prodrive/p3p440/init.S
@@ -90,10 +90,10 @@
tlbtab:
tlbtab_start
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
+ tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
tlbtab_end
diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
index 1a8aacbdf..1a0486f5c 100644
--- a/board/prodrive/p3p440/p3p440.c
+++ b/board/prodrive/p3p440/p3p440.c
@@ -35,29 +35,29 @@ void set_led(int color)
{
switch (color) {
case LED_OFF:
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LED_GREEN & ~CFG_LED_RED);
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_LED_GREEN & ~CONFIG_SYS_LED_RED);
break;
case LED_GREEN:
- out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_GREEN) & ~CFG_LED_RED);
+ out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN) & ~CONFIG_SYS_LED_RED);
break;
case LED_RED:
- out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_RED) & ~CFG_LED_GREEN);
+ out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_RED) & ~CONFIG_SYS_LED_GREEN);
break;
case LED_ORANGE:
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LED_GREEN | CFG_LED_RED);
+ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN | CONFIG_SYS_LED_RED);
break;
}
}
static int is_monarch(void)
{
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_GPIO_RDY);
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_GPIO_RDY);
udelay(1000);
- if (in32(GPIO0_IR) & CFG_MONARCH_IO)
+ if (in32(GPIO0_IR) & CONFIG_SYS_MONARCH_IO)
return 0;
else
return 1;
@@ -68,11 +68,11 @@ static void wait_for_pci_ready(void)
/*
* Configure EREADY_IO as input
*/
- out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_EREADY_IO);
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_EREADY_IO);
udelay(1000);
for (;;) {
- if (in32(GPIO0_IR) & CFG_EREADY_IO)
+ if (in32(GPIO0_IR) & CONFIG_SYS_EREADY_IO)
return;
}
@@ -95,8 +95,8 @@ int board_early_init_f(void)
mtdcr(cpc0_gpio, 0x03F01F80);
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(GPIO0_TCR, CFG_GPIO_RDY | CFG_EREADY_IO | CFG_LED_RED | CFG_LED_GREEN);
- out32(GPIO0_OR, CFG_GPIO_RDY);
+ out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN);
+ out32(GPIO0_OR, CONFIG_SYS_GPIO_RDY);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
@@ -152,7 +152,7 @@ int misc_init_r (void)
/*
* Check if only one FLASH bank is available
*/
- if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
+ if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
mtebc(pb1cr, 0); /* disable cs */
mtebc(pb1ap, 0);
mtebc(pb2cr, 0); /* disable cs */
@@ -203,7 +203,7 @@ int pci_pre_init(struct pci_controller *hose)
* may not be sufficient for a given board.
*
************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
@@ -218,7 +218,7 @@ void pci_target_init(struct pci_controller *hose)
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/
- out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
+ out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
out32r(PCIX0_PIM0LAH, 0);
out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
@@ -227,12 +227,12 @@ void pci_target_init(struct pci_controller *hose)
/*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/
- out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
- out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
+ out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+ out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*************************************************************************
* is_pci_host
diff --git a/board/prodrive/p3p440/p3p440.h b/board/prodrive/p3p440/p3p440.h
index e4e87d1f5..47e901894 100644
--- a/board/prodrive/p3p440/p3p440.h
+++ b/board/prodrive/p3p440/p3p440.h
@@ -24,11 +24,11 @@
#ifndef __P3P440_H__
#define __P3P440_H__
-#define CFG_GPIO_RDY (0x80000000 >> 11)
-#define CFG_MONARCH_IO (0x80000000 >> 18)
-#define CFG_EREADY_IO (0x80000000 >> 20)
-#define CFG_LED_GREEN (0x80000000 >> 21)
-#define CFG_LED_RED (0x80000000 >> 22)
+#define CONFIG_SYS_GPIO_RDY (0x80000000 >> 11)
+#define CONFIG_SYS_MONARCH_IO (0x80000000 >> 18)
+#define CONFIG_SYS_EREADY_IO (0x80000000 >> 20)
+#define CONFIG_SYS_LED_GREEN (0x80000000 >> 21)
+#define CONFIG_SYS_LED_RED (0x80000000 >> 22)
#define LED_OFF 1
#define LED_GREEN 2
diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c
index 5738c5bd0..351aed1e1 100644
--- a/board/prodrive/pdnb3/flash.c
+++ b/board/prodrive/pdnb3/flash.c
@@ -52,7 +52,7 @@ unsigned long flash_init(void)
int i;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; i++)
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; i++)
flash_info[i].flash_id = FLASH_UNKNOWN;
size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
@@ -66,20 +66,20 @@ unsigned long flash_init(void)
/* Monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+ CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
/* Redundant environment protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
- &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
flash_info[0].size = size;
diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c
index 1ce3c8c61..2efe027ec 100644
--- a/board/prodrive/pdnb3/nand.c
+++ b/board/prodrive/pdnb3/nand.c
@@ -136,7 +136,7 @@ static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand)
{
- pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CFG_NAND_BASE;
+ pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE;
nand->ecc.mode = NAND_ECC_SOFT;
diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c
index 3445a3abf..3773ba181 100644
--- a/board/prodrive/pdnb3/pdnb3.c
+++ b/board/prodrive/pdnb3/pdnb3.c
@@ -34,8 +34,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
/* predefine these here for FPGA programming (before including fpga.c) */
#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data)
-#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CFG_FPGA_DONE)
-#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CFG_FPGA_INIT)
+#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
+#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
#define OLD_VAL old_val
static unsigned long old_val = 0;
@@ -56,46 +56,46 @@ int board_init(void)
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x00000100;
- GPIO_OUTPUT_SET(CFG_GPIO_FPGA_RESET);
- GPIO_OUTPUT_ENABLE(CFG_GPIO_FPGA_RESET);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);
- GPIO_OUTPUT_SET(CFG_GPIO_SYS_RUNNING);
- GPIO_OUTPUT_ENABLE(CFG_GPIO_SYS_RUNNING);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);
/*
* Setup GPIO's for FPGA programming
*/
- GPIO_OUTPUT_CLEAR(CFG_GPIO_PRG);
- GPIO_OUTPUT_CLEAR(CFG_GPIO_CLK);
- GPIO_OUTPUT_CLEAR(CFG_GPIO_DATA);
- GPIO_OUTPUT_ENABLE(CFG_GPIO_PRG);
- GPIO_OUTPUT_ENABLE(CFG_GPIO_CLK);
- GPIO_OUTPUT_ENABLE(CFG_GPIO_DATA);
- GPIO_OUTPUT_DISABLE(CFG_GPIO_INIT);
- GPIO_OUTPUT_DISABLE(CFG_GPIO_DONE);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);
/*
* Setup GPIO's for interrupts
*/
- GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTA);
- GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTA);
- GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTB);
- GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTB);
- GPIO_OUTPUT_DISABLE(CFG_GPIO_RESTORE_INT);
- GPIO_INT_ACT_LOW_SET(CFG_GPIO_RESTORE_INT);
- GPIO_OUTPUT_DISABLE(CFG_GPIO_RESTART_INT);
- GPIO_INT_ACT_LOW_SET(CFG_GPIO_RESTART_INT);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
+ GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
+ GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);
/*
* Setup GPIO's for 33MHz clock output
*/
*IXP425_GPIO_GPCLKR = 0x01FF0000;
- GPIO_OUTPUT_ENABLE(CFG_GPIO_CLK_33M);
+ GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);
/*
* Setup other chip select's
*/
- *IXP425_EXP_CS1 = CFG_EXP_CS1;
+ *IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;
return 0;
}
@@ -132,14 +132,14 @@ int do_fpga_boot(unsigned char *fpgadata)
int status;
int index;
int i;
- ulong len = CFG_MALLOC_LEN;
+ ulong len = CONFIG_SYS_MALLOC_LEN;
/*
* Setup GPIO's for FPGA programming
*/
- GPIO_OUTPUT_CLEAR(CFG_GPIO_PRG);
- GPIO_OUTPUT_CLEAR(CFG_GPIO_CLK);
- GPIO_OUTPUT_CLEAR(CFG_GPIO_DATA);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
/*
* Save value so no readback is required upon programming
@@ -149,8 +149,8 @@ int do_fpga_boot(unsigned char *fpgadata)
/*
* First try to decompress fpga image (gzip compressed?)
*/
- dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf("Error: Image has to be gzipp'ed!\n");
return -1;
}
@@ -204,9 +204,9 @@ int do_fpga_boot(unsigned char *fpgadata)
/*
* Reset FPGA
*/
- GPIO_OUTPUT_CLEAR(CFG_GPIO_FPGA_RESET);
+ GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
udelay(10);
- GPIO_OUTPUT_SET(CFG_GPIO_FPGA_RESET);
+ GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
return (0);
}
generated by cgit v1.2.3-70-g09d2 (git 2.51.2) at 2025-10-31 03:32:26 +0000