1 files changed, 316 insertions, 0 deletions
diff --git a/board/olio/h1/pinmux.h b/board/olio/h1/pinmux.h
new file mode 100644
index 000000000..6676f9ee1
--- /dev/null
+++ b/board/olio/h1/pinmux.h
@@ -0,0 +1,316 @@
+#ifndef _PINMUX_H_
+#define _PINMUX_H_
+
+/*
+ * M0 - Mux mode 0
+ * M1 - Mux mode 1
+ * M2 - Mux mode 2
+ * M3 - Mux mode 3
+ * M4 - Mux mode 4
+ * M5 - Mux mode 5
+ * M6 - Mux mode 6
+ * M7 - Mux mode 7
+ * IDIS - Input disabled
+ * IEN - Input enabled
+ * PD - Active-mode pull-down enabled
+ * PU - Active-mode pull-up enabled
+ * PI - Active-mode pull inhibited
+ * SB_LOW - Standby mode configuration: Output low-level
+ * SB_HI - Standby mode configuration: Output high-level
+ * SB_HIZ - Standby mode configuration: Output hi-impedence
+ * SB_PD - Standby mode pull-down enabled
+ * SB_PU - Standby mode pull-up enabled
+ * WKEN - Wakeup input enabled
+ */
+
+#define MUX_EVM() \
+/* Design Status: NO ERRORS */\
+MUX_VAL(CONTROL_PADCONF_GPIO_112, (IEN | PD | M4 )) /* gpio_112 */\
+MUX_VAL(CONTROL_PADCONF_GPIO_113, (IEN | PD | M4 )) /* gpio_113 */\
+MUX_VAL(CONTROL_PADCONF_GPIO_114, (IEN | PD | M4 )) /* gpio_114 */\
+MUX_VAL(CONTROL_PADCONF_GPIO_115, (IEN | PD | M4 )) /* gpio_115 */\
+MUX_VAL(CONTROL_PADCONF_GPIO_126, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPIO_127, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPIO_128, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPIO_129, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_D0, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_D3, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_D4, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_D6, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_D7, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_D8, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_D10, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_VS, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_CAM_XCLKB, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA0, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA1, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA2, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA3, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA4, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA5, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA6, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA7, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA8, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA9, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA10, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA11, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA12, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA13, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA14, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA15, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA16, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA17, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA18, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IEN | PU | M4 )) /* gpio_12 */\
+MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IEN | PU | M4 )) /* gpio_13 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PU | M4 )) /* gpio_14 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PU | M4 )) /* gpio_15 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PU | M4 )) /* gpio_16 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PU | M4 )) /* gpio_17 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PD | M4 )) /* gpio_18 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PD | M4 )) /* gpio_19 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PD | M4 )) /* gpio_20 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PD | M4 )) /* gpio_21 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D8_ES2, (IEN | PD | M4 )) /* gpio_22 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D9_ES2, (IEN | PD | M4 )) /* gpio_23 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D10_ES2, (IEN | PD | M4 )) /* gpio_24 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D11_ES2, (IEN | PD | M4 )) /* gpio_25 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D12_ES2, (IEN | PD | M4 )) /* gpio_26 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D13_ES2, (IEN | PD | M4 )) /* gpio_27 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D14_ES2, (IEN | PD | M4 )) /* gpio_28 */\
+MUX_VAL(CONTROL_PADCONF_ETK_D15_ES2, (IEN | PD | M4 )) /* gpio_29 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IDIS | PI | M0 )) /* gpmc_clk */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PU | M0 )) /* gpmc_d0 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PU | M0 )) /* gpmc_d1 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PU | M0 )) /* gpmc_d2 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PU | M0 )) /* gpmc_d3 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PU | M0 )) /* gpmc_d4 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PU | M0 )) /* gpmc_d5 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D6, (IEN | PU | M0 )) /* gpmc_d6 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D7, (IEN | PU | M0 )) /* gpmc_d7 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D8, (IEN | PU | M0 )) /* gpmc_d8 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D9, (IEN | PU | M0 )) /* gpmc_d9 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D10, (IEN | PU | M0 )) /* gpmc_d10 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D11, (IEN | PU | M0 )) /* gpmc_d11 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D12, (IEN | PU | M0 )) /* gpmc_d12 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D13, (IEN | PU | M0 )) /* gpmc_d13 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D14, (IEN | PU | M0 )) /* gpmc_d14 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_D15, (IEN | PU | M0 )) /* gpmc_d15 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_NADV_ALE, (IDIS | PI | M0 )) /* gpmc_nadv_ale */\
+MUX_VAL(CONTROL_PADCONF_GPMC_NBE0_CLE, (IDIS | PI | M0 )) /* gpmc_nbe0_cle */\
+MUX_VAL(CONTROL_PADCONF_GPMC_NBE1, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS0, (IDIS | PI | M0 )) /* gpmc_ncs0 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS1, (IDIS | PI | M0 )) /* gpmc_ncs1 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS2, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS3, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS4, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS5, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS6, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_NCS7, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | PI | M0 )) /* gpmc_noe */\
+MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | PI | M0 )) /* gpmc_nwe */\
+MUX_VAL(CONTROL_PADCONF_GPMC_NWP, (IDIS | PI | M0 )) /* gpmc_nwp */\
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | PU | M0 )) /* gpmc_wait0 */\
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PD | M4 )) /* gpio_125 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PD | M4 )) /* gpio_130 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PD | M4 )) /* gpio_131 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PD | M4 )) /* gpio_169 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PD | M4 )) /* gpio_188 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PD | M4 )) /* gpio_189 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PD | M4 )) /* gpio_190 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PD | M4 )) /* gpio_191 */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_I2C1_SCL, (IDIS | PU | M0 )) /* i2c1_scl */\
+MUX_VAL(CONTROL_PADCONF_I2C1_SDA, (IEN | PU | M0 )) /* i2c1_sda */\
+MUX_VAL(CONTROL_PADCONF_I2C2_SCL, (IDIS | PU | M0 )) /* i2c2_scl */\
+MUX_VAL(CONTROL_PADCONF_I2C2_SDA, (IEN | PU | M0 )) /* i2c2_sda */\
+MUX_VAL(CONTROL_PADCONF_I2C3_SCL, (IDIS | PU | M0 )) /* i2c3_scl */\
+MUX_VAL(CONTROL_PADCONF_I2C3_SDA, (IEN | PU | M0 )) /* i2c3_sda */\
+MUX_VAL(CONTROL_PADCONF_I2C4_SCL, (IDIS | PU | M0 )) /* i2c4_scl */\
+MUX_VAL(CONTROL_PADCONF_I2C4_SDA, (IEN | PU | M0 )) /* i2c4_sda */\
+MUX_VAL(CONTROL_PADCONF_JTAG_EMU0, (IEN | PU | M0 )) /* jtag_emu0 */\
+MUX_VAL(CONTROL_PADCONF_JTAG_EMU1, (IEN | PU | M0 )) /* jtag_emu1 */\
+MUX_VAL(CONTROL_PADCONF_JTAG_NTRST, (IEN | PD | M0 )) /* jtag_ntrst */\
+MUX_VAL(CONTROL_PADCONF_JTAG_RTCK, (IDIS | PI | M0 )) /* jtag_rtck */\
+MUX_VAL(CONTROL_PADCONF_JTAG_TCK, (IEN | PD | M0 )) /* jtag_tck */\
+MUX_VAL(CONTROL_PADCONF_JTAG_TDI, (IEN | PU | M0 )) /* jtag_tdi */\
+MUX_VAL(CONTROL_PADCONF_JTAG_TDO, (IDIS | PI | M0 )) /* jtag_tdo */\
+MUX_VAL(CONTROL_PADCONF_JTAG_TMS, (IEN | PU | M0 )) /* jtag_tms_tmsc */\
+MUX_VAL(CONTROL_PADCONF_MCBSP_CLKS, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKR, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCBSP1_DR, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCBSP1_DX, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCBSP1_FSR, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCBSP1_FSX, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCBSP2_CLKX, (IEN | PD | M0 )) /* mcbsp2_clkx */\
+MUX_VAL(CONTROL_PADCONF_MCBSP2_DR, (IEN | PD | M0 )) /* mcbsp2_dr */\
+MUX_VAL(CONTROL_PADCONF_MCBSP2_DX, (IDIS | PD | M0 )) /* mcbsp2_dx */\
+MUX_VAL(CONTROL_PADCONF_MCBSP2_FSX, (IEN | PD | M0 )) /* mcbsp2_fsx */\
+MUX_VAL(CONTROL_PADCONF_MCBSP3_CLKX, (IEN | PD | M0 )) /* mcbsp3_clkx */\
+MUX_VAL(CONTROL_PADCONF_MCBSP3_DR, (IEN | PD | M0 )) /* mcbsp3_dr */\
+MUX_VAL(CONTROL_PADCONF_MCBSP3_DX, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCBSP3_FSX, (IEN | PD | M0 )) /* mcbsp3_fsx */\
+MUX_VAL(CONTROL_PADCONF_MCBSP4_CLKX, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCBSP4_DR, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCBSP4_DX, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCBSP4_FSX, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CLK, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS0, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS1, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS2, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT1, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT2, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC1_DAT3, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC2_CLK, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC2_CMD, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT0, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT1, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT2, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT3, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT4, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT5, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT6, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_MMC2_DAT7, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_SDRC_A0, (IDIS | PI | M0 )) /* sdrc_a0 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_A1, (IDIS | PI | M0 )) /* sdrc_a1 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_A2, (IDIS | PI | M0 )) /* sdrc_a2 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_A3, (IDIS | PI | M0 )) /* sdrc_a3 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_A4, (IDIS | PI | M0 )) /* sdrc_a4 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_A5, (IDIS | PI | M0 )) /* sdrc_a5 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_A6, (IDIS | PI | M0 )) /* sdrc_a6 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_A7, (IDIS | PI | M0 )) /* sdrc_a7 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_A8, (IDIS | PI | M0 )) /* sdrc_a8 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_A9, (IDIS | PI | M0 )) /* sdrc_a9 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_A10, (IDIS | PI | M0 )) /* sdrc_a10 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_A11, (IDIS | PI | M0 )) /* sdrc_a11 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_A12, (IDIS | PI | M0 )) /* sdrc_a12 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_A13, (IDIS | PI | M0 )) /* sdrc_a13 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_A14, (IDIS | PI | M0 )) /* sdrc_a14 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_BA0, (IDIS | PI | M0 )) /* sdrc_ba0 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_BA1, (IDIS | PI | M0 )) /* sdrc_ba1 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_CKE0, (IDIS | PI | M7 )) /* safe_mode_out1 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_CKE1, (IDIS | PI | M7 )) /* safe_mode_out1 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_CLK, (IEN | PI | M0 )) /* sdrc_clk */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D0, (IEN | PI | M0 )) /* sdrc_d0 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D1, (IEN | PI | M0 )) /* sdrc_d1 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D2, (IEN | PI | M0 )) /* sdrc_d2 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D3, (IEN | PI | M0 )) /* sdrc_d3 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D4, (IEN | PI | M0 )) /* sdrc_d4 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D5, (IEN | PI | M0 )) /* sdrc_d5 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D6, (IEN | PI | M0 )) /* sdrc_d6 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D7, (IEN | PI | M0 )) /* sdrc_d7 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D8, (IEN | PI | M0 )) /* sdrc_d8 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D9, (IEN | PI | M0 )) /* sdrc_d9 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D10, (IEN | PI | M0 )) /* sdrc_d10 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D11, (IEN | PI | M0 )) /* sdrc_d11 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D12, (IEN | PI | M0 )) /* sdrc_d12 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D13, (IEN | PI | M0 )) /* sdrc_d13 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D14, (IEN | PI | M0 )) /* sdrc_d14 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D15, (IEN | PI | M0 )) /* sdrc_d15 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D16, (IEN | PI | M0 )) /* sdrc_d16 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D17, (IEN | PI | M0 )) /* sdrc_d17 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D18, (IEN | PI | M0 )) /* sdrc_d18 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D19, (IEN | PI | M0 )) /* sdrc_d19 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D20, (IEN | PI | M0 )) /* sdrc_d20 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D21, (IEN | PI | M0 )) /* sdrc_d21 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D22, (IEN | PI | M0 )) /* sdrc_d22 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D23, (IEN | PI | M0 )) /* sdrc_d23 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D24, (IEN | PI | M0 )) /* sdrc_d24 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D25, (IEN | PI | M0 )) /* sdrc_d25 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D26, (IEN | PI | M0 )) /* sdrc_d26 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D27, (IEN | PI | M0 )) /* sdrc_d27 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D28, (IEN | PI | M0 )) /* sdrc_d28 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D29, (IEN | PI | M0 )) /* sdrc_d29 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D30, (IEN | PI | M0 )) /* sdrc_d30 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_D31, (IEN | PI | M0 )) /* sdrc_d31 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_DM0, (IDIS | PI | M0 )) /* sdrc_dm0 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_DM1, (IDIS | PI | M0 )) /* sdrc_dm1 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_DM2, (IDIS | PI | M0 )) /* sdrc_dm2 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_DM3, (IDIS | PI | M0 )) /* sdrc_dm3 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS0, (IEN | PI | M0 )) /* sdrc_dqs0 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS1, (IEN | PI | M0 )) /* sdrc_dqs1 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS2, (IEN | PI | M0 )) /* sdrc_dqs2 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_DQS3, (IEN | PI | M0 )) /* sdrc_dqs3 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_NCAS, (IDIS | PI | M0 )) /* sdrc_ncas */\
+MUX_VAL(CONTROL_PADCONF_SDRC_NCLK, (IDIS | PI | M0 )) /* sdrc_nclk */\
+MUX_VAL(CONTROL_PADCONF_SDRC_NCS0, (IDIS | PI | M0 )) /* sdrc_ncs0 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_NCS1, (IDIS | PI | M0 )) /* sdrc_ncs1 */\
+MUX_VAL(CONTROL_PADCONF_SDRC_NRAS, (IDIS | PI | M0 )) /* sdrc_nras */\
+MUX_VAL(CONTROL_PADCONF_SDRC_NWE, (IDIS | PI | M0 )) /* sdrc_nwe */\
+MUX_VAL(CONTROL_PADCONF_SYS_32K, (IEN | PI | M0 )) /* sys_32k */\
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT0, (IEN | PI | M0 )) /* sys_boot0 */\
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT1, (IEN | PI | M0 )) /* sys_boot1 */\
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT2, (IEN | PI | M0 )) /* sys_boot2 */\
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT3, (IEN | PI | M0 )) /* sys_boot3 */\
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT4, (IEN | PI | M0 )) /* sys_boot4 */\
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT5, (IEN | PI | M0 )) /* sys_boot5 */\
+MUX_VAL(CONTROL_PADCONF_SYS_BOOT6, (IEN | PI | M0 )) /* sys_boot6 */\
+MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT1, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT2, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_SYS_CLKREQ, (IEN | PI | M4 )) /* gpio_1 */\
+MUX_VAL(CONTROL_PADCONF_SYS_NIRQ, (IEN | PU | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_SYS_NRESWARM, (IEN | PU | M0 )) /* sys_nreswarm */\
+MUX_VAL(CONTROL_PADCONF_SYS_OFF_MODE, (IEN | PD | M7 )) /* safe_mode */\
+MUX_VAL(CONTROL_PADCONF_UART1_CTS, (IEN | PD | M0 )) /* uart1_cts */\
+MUX_VAL(CONTROL_PADCONF_UART1_RTS, (IDIS | PD | M0 )) /* uart1_rts */\
+MUX_VAL(CONTROL_PADCONF_UART1_RX, (IEN | PD | M0 )) /* uart1_rx */\
+MUX_VAL(CONTROL_PADCONF_UART1_TX, (IDIS | PD | M0 )) /* uart1_tx */\
+MUX_VAL(CONTROL_PADCONF_UART2_CTS, (IEN | PU | M4 )) /* gpio_144 */\
+MUX_VAL(CONTROL_PADCONF_UART2_RTS, (IEN | PU | M4 )) /* gpio_145 */\
+MUX_VAL(CONTROL_PADCONF_UART2_RX, (IEN | PU | M4 )) /* gpio_147 */\
+MUX_VAL(CONTROL_PADCONF_UART2_TX, (IEN | PU | M4 )) /* gpio_146 */\
+MUX_VAL(CONTROL_PADCONF_UART3_CTS_RCTX, (IEN | PU | M0 )) /* uart3_cts_rctx */\
+MUX_VAL(CONTROL_PADCONF_UART3_RTS_SD, (IDIS | PU | M0 )) /* uart3_rts_sd */\
+MUX_VAL(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | PU | M0 )) /* uart3_rx_irrx */\
+MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | PU | M0 )) /* uart3_tx_irtx */
+#endif