diff options
Diffstat (limited to 'board/olio/h1/h1.c')
| -rw-r--r-- | board/olio/h1/h1.c | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/board/olio/h1/h1.c b/board/olio/h1/h1.c index c9350347f..21a7ffb38 100644 --- a/board/olio/h1/h1.c +++ b/board/olio/h1/h1.c @@ -21,10 +21,8 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-types.h> -#include <asm/errno.h> #include "h1.h" #include <command.h> -#include <power/tps65910.h> DECLARE_GLOBAL_DATA_PTR; @@ -49,7 +47,8 @@ int board_init(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(struct board_sdrc_timings *timings) +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) { int pop_mfr, pop_id; @@ -60,12 +59,12 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) */ identify_nand_chip(&pop_mfr, &pop_id); - timings->mr = MICRON_V_MR_165; + *mr = MICRON_V_MR_165; /* 128MB DDR */ - timings->mcfg = MICRON_V_MCFG_200(128 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + *mcfg = MICRON_V_MCFG_200(128 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } #endif |