diff options
Diffstat (limited to 'board/mpc8540eval/mpc8540eval.c')
| -rw-r--r-- | board/mpc8540eval/mpc8540eval.c | 84 | 
1 files changed, 48 insertions, 36 deletions
| diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index 7c54458a5..fa0a33686 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -24,6 +24,7 @@   */  #include <common.h> +#include <netdev.h>  #include <asm/processor.h>  #include <asm/mmu.h>  #include <asm/immap_85xx.h> @@ -35,7 +36,7 @@ long int fixed_sdram (void);  int board_pre_init (void)  {  #if defined(CONFIG_PCI) -	volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); +	volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);  	pci->peer &= 0xffffffdf; /* disable master abort */  #endif @@ -52,10 +53,10 @@ int checkboard (void)  	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);  	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);  	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000); -	if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \ -		|| (CFG_LBC_LCRR & 0x0f) == 8) { +	if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \ +		|| (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {  		printf ("\tLBC: %lu MHz\n", -			sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f)); +			sysinfo.freqSystemBus / 1000000/(CONFIG_SYS_LBC_LCRR & 0x0f));  	} else {  		printf("\tLBC: unknown\n");  	} @@ -68,12 +69,12 @@ phys_size_t initdram (int board_type)  	long dram_size = 0;  #if !defined(CONFIG_RAM_AS_FLASH) -	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); +	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);  	sys_info_t sysinfo;  	uint temp_lbcdll = 0;  #endif  #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) -	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); +	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);  #endif  #if defined(CONFIG_DDR_DLL) @@ -93,42 +94,42 @@ phys_size_t initdram (int board_type)  	dram_size = fixed_sdram ();  #endif -#if defined(CFG_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT)  	return dram_size;  #endif  #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */  	get_sys_info(&sysinfo); -	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ -	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) { -		lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000; +	/* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ +	if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) { +		lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;  	} else { -		lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff; +		lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;  		udelay(200);  		temp_lbcdll = gur->lbcdllcr;  		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;  		asm("sync;isync;msync");  	} -	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */ -	lbc->br2 = CFG_BR2_PRELIM; -	lbc->lbcr = CFG_LBC_LBCR; -	lbc->lsdmr = CFG_LBC_LSDMR_1; +	lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */ +	lbc->br2 = CONFIG_SYS_BR2_PRELIM; +	lbc->lbcr = CONFIG_SYS_LBC_LBCR; +	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;  	asm("sync");  	* (ulong *)0 = 0x000000ff; -	lbc->lsdmr = CFG_LBC_LSDMR_2; +	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;  	asm("sync");  	* (ulong *)0 = 0x000000ff; -	lbc->lsdmr = CFG_LBC_LSDMR_3; +	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;  	asm("sync");  	* (ulong *)0 = 0x000000ff; -	lbc->lsdmr = CFG_LBC_LSDMR_4; +	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;  	asm("sync");  	* (ulong *)0 = 0x000000ff; -	lbc->lsdmr = CFG_LBC_LSDMR_5; +	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;  	asm("sync"); -	lbc->lsrt = CFG_LBC_LSRT; +	lbc->lsrt = CONFIG_SYS_LBC_LSRT;  	asm("sync"); -	lbc->mrtpr = CFG_LBC_MRTPR; +	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;  	asm("sync");  #endif @@ -138,7 +139,7 @@ phys_size_t initdram (int board_type)  		 * enable errors */  		uint *p = 0;  		uint i = 0; -		volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); +		volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);  		dma_init();  		for (*p = 0; p < (uint *)(8 * 1024); p++) {  			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } @@ -180,11 +181,11 @@ phys_size_t initdram (int board_type)  	return dram_size;  } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST)  int testdram (void)  { -	uint *pstart = (uint *) CFG_MEMTEST_START; -	uint *pend = (uint *) CFG_MEMTEST_END; +	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; +	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;  	uint *p;  	printf("SDRAM test phase 1:\n"); @@ -220,15 +221,15 @@ int testdram (void)   ************************************************************************/  long int fixed_sdram (void)  { -#ifndef CFG_RAMBOOT -	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); +#ifndef CONFIG_SYS_RAMBOOT +	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); -	ddr->cs0_bnds = CFG_DDR_CS0_BNDS; -	ddr->cs0_config = CFG_DDR_CS0_CONFIG; -	ddr->timing_cfg_1 = CFG_DDR_TIMING_1; -	ddr->timing_cfg_2 = CFG_DDR_TIMING_2; -	ddr->sdram_mode = CFG_DDR_MODE; -	ddr->sdram_interval = CFG_DDR_INTERVAL; +	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; +	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; +	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; +	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; +	ddr->sdram_mode = CONFIG_SYS_DDR_MODE; +	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;  #if defined (CONFIG_DDR_ECC)  	ddr->err_disable = 0x0000000D;  	ddr->err_sbe = 0x00ff0000; @@ -237,13 +238,24 @@ long int fixed_sdram (void)  	udelay(500);  #if defined (CONFIG_DDR_ECC)  	/* Enable ECC checking */ -	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); +	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);  #else -	ddr->sdram_cfg = CFG_DDR_CONTROL; +	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;  #endif  	asm("sync; isync; msync");  	udelay(500);  #endif -	return (CFG_SDRAM_SIZE * 1024 * 1024); +	return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024);  }  #endif	/* !defined(CONFIG_SPD_EEPROM) */ + +int board_eth_init(bd_t *bis) +{ +	/* +	 * This board either has PCI NICs or uses the CPU's TSECs +	 * pci_eth_init() will return 0 if no NICs found, so in that case +	 * returning -1 will force cpu_eth_init() to be called. +	 */ +	int num = pci_eth_init(bis); +	return (num <= 0 ? -1 : num); +} |