diff options
Diffstat (limited to 'board/idmr')
| -rw-r--r-- | board/idmr/flash.c | 22 | ||||
| -rw-r--r-- | board/idmr/idmr.c | 10 | ||||
| -rw-r--r-- | board/idmr/mii.c | 10 |
3 files changed, 21 insertions, 21 deletions
diff --git a/board/idmr/flash.c b/board/idmr/flash.c index 33512b894..57c994863 100644 --- a/board/idmr/flash.c +++ b/board/idmr/flash.c @@ -23,11 +23,11 @@ #include <common.h> -#define PHYS_FLASH_1 CFG_FLASH_BASE +#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE #define FLASH_BANK_SIZE 0x800000 #define EN29LV640 0x227e227e -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; void flash_print_info (flash_info_t * info) { @@ -75,15 +75,15 @@ unsigned long flash_init (void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | (EN29LV640 & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); if (i == 0) flashbase = PHYS_FLASH_1; else @@ -96,8 +96,8 @@ unsigned long flash_init (void) } flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + 0x2ffff, &flash_info[0]); + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + 0x2ffff, &flash_info[0]); return size; } @@ -111,8 +111,8 @@ unsigned long flash_init (void) #define CMD_PROGRAM 0x00A0 #define CMD_UNLOCK_BYPASS 0x0020 -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1))) #define BIT_ERASE_DONE 0x0080 #define BIT_RDY_MASK 0x0080 @@ -191,7 +191,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) result = *addr; /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) { + if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip1 = TMO; break; @@ -280,7 +280,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) result = *addr; /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) { + if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { chip1 = ERR | TMO; break; } diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c index 4f073fc31..3771c191e 100644 --- a/board/idmr/idmr.c +++ b/board/idmr/idmr.c @@ -35,7 +35,7 @@ phys_size_t initdram (int board_type) { /* * After reset, CS0 is configured to cover entire address space. We * need to configure it to its proper values, so that writes to - * CFG_SDRAM_BASE and vicinity during SDRAM controller setup below do + * CONFIG_SYS_SDRAM_BASE and vicinity during SDRAM controller setup below do * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual). */ @@ -99,7 +99,7 @@ phys_size_t initdram (int board_type) { * PS: 16 bit */ mbar_writeLong(MCF_SDRAMC_DACR0, - MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) | + MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) | MCF_SDRAMC_DACRn_BA(0x00) | MCF_SDRAMC_DACRn_CASL(0x03) | MCF_SDRAMC_DACRn_CBM(0x03) | @@ -117,7 +117,7 @@ phys_size_t initdram (int board_type) { MCF_SDRAMC_DACRn_IP); /* Write to this block to initiate precharge */ - *(volatile u16 *)(CFG_SDRAM_BASE) = 0xa5a5; + *(volatile u16 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5; /* * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We @@ -153,9 +153,9 @@ phys_size_t initdram (int board_type) { * Burst Type = Sequential * Burst Length = 1 */ - *(volatile u32 *)(CFG_SDRAM_BASE + 0x1800) = 0xa5a5a5a5; + *(volatile u32 *)(CONFIG_SYS_SDRAM_BASE + 0x1800) = 0xa5a5a5a5; - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; }; diff --git a/board/idmr/mii.c b/board/idmr/mii.c index 78a7028bc..e79fa1958 100644 --- a/board/idmr/mii.c +++ b/board/idmr/mii.c @@ -38,14 +38,14 @@ int fecpin_setclear(struct eth_device *dev, int setclear) { if (setclear) { /* Enable Ethernet pins */ - mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); + mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C); } else { } return 0; } -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII) #include <miiphy.h> /* Make MII read/write commands for the FEC. */ @@ -131,9 +131,9 @@ uint mii_send(uint mii_cmd) return (mii_reply & 0xffff); /* data read from phy */ } -#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ +#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */ -#if defined(CFG_DISCOVER_PHY) +#if defined(CONFIG_SYS_DISCOVER_PHY) int mii_discover_phy(struct eth_device *dev) { #define MAX_PHY_PASSES 11 @@ -198,7 +198,7 @@ int mii_discover_phy(struct eth_device *dev) return phyaddr; } -#endif /* CFG_DISCOVER_PHY */ +#endif /* CONFIG_SYS_DISCOVER_PHY */ void mii_init(void) __attribute__((weak,alias("__mii_init"))); |