diff options
Diffstat (limited to 'board/freescale')
28 files changed, 960 insertions, 130 deletions
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index 41887c2c7..a39c17a56 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -166,11 +166,13 @@ int configure_vsc3316_3308(void) ret = select_i2c_ch_pca(I2C_CH_VSC3316); if (!ret) { ret = vsc3316_config(VSC3316_TX_ADDRESS, - vsc16_tx_sgmii_lane_ab, num_vsc16_con); + vsc16_tx_4sfp_sgmii_12_56, + num_vsc16_con); if (ret) return ret; ret = vsc3316_config(VSC3316_RX_ADDRESS, - vsc16_rx_sgmii_lane_ab, num_vsc16_con); + vsc16_rx_4sfp_sgmii_12_56, + num_vsc16_con); if (ret) return ret; } else { diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h index 994dec570..c2b6c44d2 100644 --- a/board/freescale/b4860qds/b4860qds_crossbar_con.h +++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h @@ -26,42 +26,53 @@ static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10}, {5, 11}, {4, 5}, {2, 6}, {12, 9} }; -static const int8_t vsc16_tx_sfp[8][2] = { {15, 8}, {0, 0}, {7, 7}, {9, 1}, - {5, 15}, {4, 14}, {2, 12}, {12, 13} }; +static const int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; -static const int8_t vsc16_tx_sgmii_lane_ab[8][2] = { {2, 14}, {12, 15}, - {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; +static const int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1}, + {7, 8}, {9, 0}, {2, 14}, {12, 15}, + {-1, -1}, {-1, -1} }; + +static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1}, + {7, 8}, {9, 0}, {5, 14}, {4, 15}, + {-1, -1}, {-1, -1} }; #ifdef CONFIG_PPC_B4420 static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; #endif + static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9}, {11, 11}, {5, 10}, {6, 3}, {9, 12} }; -static const int8_t vsc16_rx_sfp[8][2] = { {0, 15}, {8, 1}, {1, 8}, {7, 9}, +static const int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; -static const int8_t vsc16_rx_sgmii_lane_ab[8][2] = { {14, 3}, {15, 12}, - {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; +static const int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1}, + {7, 8}, {1, 9}, {14, 3}, {15, 12}, + {-1, -1}, {-1, -1} }; + +static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1}, + {7, 8}, {1, 9}, {14, 11}, {15, 10}, + {-1, -1}, {-1, -1} }; #ifdef CONFIG_PPC_B4420 static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; #endif -static const int8_t vsc16_rx_aurora[8][2] = { {12, 3}, {13, 12}, {-1, -1}, +static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} }; -static const int8_t vsc08_tx_sfp[4][2] = { {2, 6}, {3, 7}, {7, 1}, {1, 0} }; +static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} }; static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} }; -static const int8_t vsc08_rx_sfp[4][2] = { {6, 3}, {7, 4}, {1, 7}, {0, 1} }; +static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} }; #endif diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index dd4c0f69e..b82b3d409 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -13,6 +13,7 @@ #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h> #include <asm/fsl_law.h> +#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h> DECLARE_GLOBAL_DATA_PTR; @@ -188,3 +189,74 @@ phys_size_t initdram(int board_type) puts(" DDR: "); return dram_size; } + +unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, + unsigned int dbw_cap_adj[]) +{ + int i, j; + unsigned long long total_mem, current_mem_base, total_ctlr_mem; + unsigned long long rank_density, ctlr_density = 0; + + current_mem_base = 0ull; + total_mem = 0; + /* + * This board has soldered DDR chips. DDRC1 has two rank. + * DDRC2 has only one rank. + * Assigning DDRC2 to lower address and DDRC1 to higher address. + */ + if (pinfo->memctl_opts[0].memctl_interleaving) { + rank_density = pinfo->dimm_params[0][0].rank_density >> + dbw_cap_adj[0]; + ctlr_density = rank_density; + + debug("rank density is 0x%llx, ctlr density is 0x%llx\n", + rank_density, ctlr_density); + for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) { + switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { + case FSL_DDR_CACHE_LINE_INTERLEAVING: + case FSL_DDR_PAGE_INTERLEAVING: + case FSL_DDR_BANK_INTERLEAVING: + case FSL_DDR_SUPERBANK_INTERLEAVING: + total_ctlr_mem = 2 * ctlr_density; + break; + default: + panic("Unknown interleaving mode"); + } + pinfo->common_timing_params[i].base_address = + current_mem_base; + pinfo->common_timing_params[i].total_mem = + total_ctlr_mem; + total_mem = current_mem_base + total_ctlr_mem; + debug("ctrl %d base 0x%llx\n", i, current_mem_base); + debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); + } + } else { + /* + * Simple linear assignment if memory + * controllers are not interleaved. + */ + for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) { + total_ctlr_mem = 0; + pinfo->common_timing_params[i].base_address = + current_mem_base; + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + /* Compute DIMM base addresses. */ + unsigned long long cap = + pinfo->dimm_params[i][j].capacity; + pinfo->dimm_params[i][j].base_address = + current_mem_base; + debug("ctrl %d dimm %d base 0x%llx\n", + i, j, current_mem_base); + current_mem_base += cap; + total_ctlr_mem += cap; + } + debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); + pinfo->common_timing_params[i].total_mem = + total_ctlr_mem; + total_mem += total_ctlr_mem; + } + } + debug("Total mem by %s is 0x%llx\n", __func__, total_mem); + + return total_mem; +} diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index 68e2725fc..3bcda6d13 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -275,6 +275,24 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); break; + case 0x98: + /* XAUI in Slot1 and Slot2 */ + debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n", + CONFIG_SYS_FM1_10GEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC1, + CONFIG_SYS_FM1_10GEC1_PHY_ADDR); + debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n", + CONFIG_SYS_FM1_10GEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC2, + CONFIG_SYS_FM1_10GEC2_PHY_ADDR); + break; + case 0x9E: + /* XAUI in Slot2 */ + debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n", + CONFIG_SYS_FM1_10GEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC2, + CONFIG_SYS_FM1_10GEC2_PHY_ADDR); + break; default: printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", serdes2_prtcl); @@ -300,6 +318,23 @@ int board_eth_init(bd_t *bis) } } + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + int idx = i - FM1_10GEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + fm_info_set_mdio(i, + miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); + break; + default: + printf("Fman1: 10GSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + } + + cpu_eth_init(bis); #endif diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c index 4142e014d..b26725b2f 100644 --- a/board/freescale/b4860qds/law.c +++ b/board/freescale/b4860qds/law.c @@ -33,8 +33,12 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_MAPLE_MEM_PHYS + SET_LAW(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_MAPLE), +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CONFIG_SYS_NAND_BASE_PHYS SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c index 6d634bf69..29cc41bfa 100644 --- a/board/freescale/b4860qds/tlb.c +++ b/board/freescale/b4860qds/tlb.c @@ -106,7 +106,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_4M, 1), + 0, 10, BOOKE_PAGESZ_32M, 1), #endif #ifdef CONFIG_SYS_NAND_BASE /* diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 8d914d548..2cf87383d 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -78,7 +78,11 @@ struct qixis { u8 trig_stat; u8 res12[3]; u8 trig_ctr[4]; - u8 res13[48]; + u8 res13[16]; + u8 clk_freq[6]; /* Clock Measurement Registers */ + u8 res_c6[8]; + u8 clk_base[2]; /* Clock Frequency Base Reg */ + u8 res_d0[16]; u8 aux2[4]; /* Auxiliary Registers,0xE0 */ u8 res14[10]; u8 aux_ad; diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c index ef9de25bd..ae0707353 100644 --- a/board/freescale/corenet_ds/eth_superhydra.c +++ b/board/freescale/corenet_ds/eth_superhydra.c @@ -605,8 +605,8 @@ int board_eth_init(bd_t *bis) lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) { debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); - mdio_mux[FM1_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK; - mdio_mux[FM1_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT2; + mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; + mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT2; super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO", mdio_mux[i].mask, mdio_mux[i].val); } @@ -704,8 +704,8 @@ int board_eth_init(bd_t *bis) lane = serdes_get_first_lane(XAUI_FM2); if (lane >= 0) { debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); - mdio_mux[FM2_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK; - mdio_mux[FM2_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT1; + mdio_mux[i].mask = BRDCFG1_EMI2_SEL_MASK; + mdio_mux[i].val = BRDCFG1_EMI2_SEL_SLOT1; super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO", mdio_mux[i].mask, mdio_mux[i].val); } diff --git a/board/freescale/corenet_ds/pbi.cfg b/board/freescale/corenet_ds/pbi.cfg index 50806ca8a..af1ebd6f2 100644 --- a/board/freescale/corenet_ds/pbi.cfg +++ b/board/freescale/corenet_ds/pbi.cfg @@ -19,7 +19,7 @@ # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, # MA 02110-1301 USA # -# Refer docs/README.pblimage for more details about how-to configure +# Refer doc/README.pblimage for more details about how-to configure # and create PBL boot image # diff --git a/board/freescale/corenet_ds/rcw_p5040ds.cfg b/board/freescale/corenet_ds/rcw_p5040ds.cfg new file mode 100644 index 000000000..82fa7417d --- /dev/null +++ b/board/freescale/corenet_ds/rcw_p5040ds.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for P5040DS. +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +0c580000 00000000 22121200 00000000 +089c4400 00283000 58000000 61000000 +00000000 00000000 00000000 10070000 +00000000 00000000 00000000 00000000 diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 996d788dd..bae5c2320 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -20,7 +20,7 @@ * Foundation Inc. 51 Franklin Street Fifth Floor Boston, * MA 02110-1301 USA * - * Refer docs/README.imxmage for more details about how-to configure + * Refer doc/README.imximage for more details about how-to configure * and create imximage boot image * * The syntax is taken as close as possible with the kwbimage diff --git a/board/freescale/mx25pdk/imximage.cfg b/board/freescale/mx25pdk/imximage.cfg index c42a2836f..8cc8bde6c 100644 --- a/board/freescale/mx25pdk/imximage.cfg +++ b/board/freescale/mx25pdk/imximage.cfg @@ -15,7 +15,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * Refer docs/README.imxmage for more details about how-to configure + * Refer doc/README.imximage for more details about how-to configure * and create imximage boot image * * The syntax is taken as close as possible with the kwbimage diff --git a/board/freescale/mx51evk/imximage.cfg b/board/freescale/mx51evk/imximage.cfg index 3e141eef3..aaa490a74 100644 --- a/board/freescale/mx51evk/imximage.cfg +++ b/board/freescale/mx51evk/imximage.cfg @@ -20,7 +20,7 @@ * Foundation Inc. 51 Franklin Street Fifth Floor Boston, * MA 02110-1301 USA * - * Refer docs/README.imxmage for more details about how-to configure + * Refer doc/README.imximage for more details about how-to configure * and create imximage boot image * * The syntax is taken as close as possible with the kwbimage diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg index 4633e4d38..a103d9553 100644 --- a/board/freescale/mx53ard/imximage_dd3.cfg +++ b/board/freescale/mx53ard/imximage_dd3.cfg @@ -20,7 +20,7 @@ * Foundation Inc. 51 Franklin Street Fifth Floor Boston, * MA 02110-1301 USA * - * Refer docs/README.imxmage for more details about how-to configure + * Refer doc/README.imximage for more details about how-to configure * and create imximage boot image * * The syntax is taken as close as possible with the kwbimage diff --git a/board/freescale/mx53evk/imximage.cfg b/board/freescale/mx53evk/imximage.cfg index 1cd61d56c..c1cfddaf4 100644 --- a/board/freescale/mx53evk/imximage.cfg +++ b/board/freescale/mx53evk/imximage.cfg @@ -20,7 +20,7 @@ * Foundation Inc. 51 Franklin Street Fifth Floor Boston, * MA 02110-1301 USA * - * Refer docs/README.imxmage for more details about how-to configure + * Refer doc/README.imximage for more details about how-to configure * and create imximage boot image * * The syntax is taken as close as possible with the kwbimage diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg index e6b90c116..2f75ad051 100644 --- a/board/freescale/mx53loco/imximage.cfg +++ b/board/freescale/mx53loco/imximage.cfg @@ -20,7 +20,7 @@ * Foundation Inc. 51 Franklin Street Fifth Floor Boston, * MA 02110-1301 USA * - * Refer docs/README.imxmage for more details about how-to configure + * Refer doc/README.imximage for more details about how-to configure * and create imximage boot image * * The syntax is taken as close as possible with the kwbimage diff --git a/board/freescale/mx53smd/imximage.cfg b/board/freescale/mx53smd/imximage.cfg index 4633e4d38..a103d9553 100644 --- a/board/freescale/mx53smd/imximage.cfg +++ b/board/freescale/mx53smd/imximage.cfg @@ -20,7 +20,7 @@ * Foundation Inc. 51 Franklin Street Fifth Floor Boston, * MA 02110-1301 USA * - * Refer docs/README.imxmage for more details about how-to configure + * Refer doc/README.imximage for more details about how-to configure * and create imximage boot image * * The syntax is taken as close as possible with the kwbimage diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg index 4ed211eed..6f18b3700 100644 --- a/board/freescale/mx6qarm2/imximage.cfg +++ b/board/freescale/mx6qarm2/imximage.cfg @@ -20,7 +20,7 @@ * Foundation Inc. 51 Franklin Street Fifth Floor Boston, * MA 02110-1301 USA * - * Refer docs/README.imxmage for more details about how-to configure + * Refer doc/README.imximage for more details about how-to configure * and create imximage boot image * * The syntax is taken as close as possible with the kwbimage diff --git a/board/freescale/mx6qsabreauto/imximage.cfg b/board/freescale/mx6qsabreauto/imximage.cfg index bbff81395..e720c6b53 100644 --- a/board/freescale/mx6qsabreauto/imximage.cfg +++ b/board/freescale/mx6qsabreauto/imximage.cfg @@ -19,7 +19,7 @@ * Foundation Inc. 51 Franklin Street Fifth Floor Boston, * MA 02110-1301 USA * - * Refer docs/README.imxmage for more details about how-to configure + * Refer doc/README.imximage for more details about how-to configure * and create imximage boot image * * The syntax is taken as close as possible with the kwbimage diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index a706a6d00..44d3e0c61 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -227,6 +227,17 @@ int misc_init_r(void) "'00' is unsupported\n"); else actual[i] = freq[i][clock]; + + /* + * PC board uses a different CPLD with PB board, this CPLD + * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB + * board has cpld_ver_sub = 0, and pcba_ver = 4. + */ + if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) && + (CPLD_READ(pcba_ver) == 5)) { + /* PC board bank2 frequency */ + actual[i] = freq[i-1][clock]; + } } for (i = 0; i < NUM_SRDS_BANKS; i++) { diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 692616aed..058d62511 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -19,6 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; struct board_specific_parameters { u32 n_ranks; u32 datarate_mhz_high; + u32 rank_gb; u32 clk_adjust; u32 wrlvl_start; u32 wrlvl_ctl_2; @@ -36,16 +37,19 @@ struct board_specific_parameters { static const struct board_specific_parameters udimm0[] = { /* * memory controller 0 - * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay | + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ - {2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, - {1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, - {1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, + {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, + {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, + {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, + {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, + {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, + {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, {} }; @@ -61,19 +65,19 @@ static const struct board_specific_parameters *udimms[] = { static const struct board_specific_parameters rdimm0[] = { /* * memory controller 0 - * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay | + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ - {4, 1350, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0}, - {4, 1666, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0}, - {4, 2140, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0}, - {2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, - {1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, - {1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {4, 1350, 0, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0}, + {4, 1666, 0, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0}, + {4, 2140, 0, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0}, + {2, 1350, 0, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0}, + {2, 1666, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {2, 2140, 0, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, + {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, {} }; @@ -113,7 +117,8 @@ void fsl_ddr_board_options(memctl_options_t *popts, */ ddr_freq = get_ddr_freq(0) / 1000000; while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { if (ddr_freq <= pbsp->datarate_mhz_high) { popts->cpo_override = pbsp->cpo; popts->write_data_delay = @@ -146,6 +151,13 @@ void fsl_ddr_board_options(memctl_options_t *popts, panic("DIMM is not supported by this board"); } found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + /* * Factors to consider for half-strength driver enable: * - number of DIMMs installed diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c index a49c7d4f1..7103a0d38 100644 --- a/board/freescale/t4qds/eth.c +++ b/board/freescale/t4qds/eth.c @@ -52,7 +52,7 @@ #define EMI1_SLOT4 4 #define EMI1_SLOT5 5 #define EMI1_SLOT7 7 -#define EMI2 8 /* tmp, FIXME */ +#define EMI2 8 /* Slot6 and Slot8 do not have EMI connections */ static int mdio_mux[NUM_FM_PORTS]; @@ -71,6 +71,14 @@ static const char *mdio_names[] = { static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2}; static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4}; +static u8 slot_qsgmii_phyaddr[5][4] = { + {0, 0, 0, 0},/* not used, to make index match slot No. */ + {0, 1, 2, 3}, + {4, 5, 6, 7}, + {8, 9, 0xa, 0xb}, + {0xc, 0xd, 0xe, 0xf}, +}; +static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0}; static const char *t4240qds_mdio_name_for_muxval(u8 muxval) { @@ -180,21 +188,228 @@ static int t4240qds_mdio_init(char *realbusname, u8 muxval) void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, enum fm_port port, int offset) { - if (mdio_mux[port] == EMI1_RGMII) - fdt_set_phy_handle(blob, prop, pa, "phy_rgmii"); - - /* TODO: will do with dts */ + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + switch (port) { + case FM1_DTSEC1: + if (qsgmiiphy_fix[port]) + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy21"); + break; + case FM1_DTSEC2: + if (qsgmiiphy_fix[port]) + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy22"); + break; + case FM1_DTSEC3: + if (qsgmiiphy_fix[port]) + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy23"); + break; + case FM1_DTSEC4: + if (qsgmiiphy_fix[port]) + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy24"); + break; + case FM1_DTSEC6: + if (qsgmiiphy_fix[port]) + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy12"); + break; + case FM1_DTSEC9: + if (qsgmiiphy_fix[port]) + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy14"); + else + fdt_set_phy_handle(blob, prop, pa, + "phy_sgmii4"); + break; + case FM1_DTSEC10: + if (qsgmiiphy_fix[port]) + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy13"); + else + fdt_set_phy_handle(blob, prop, pa, + "phy_sgmii3"); + break; + case FM2_DTSEC1: + if (qsgmiiphy_fix[port]) + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy41"); + break; + case FM2_DTSEC2: + if (qsgmiiphy_fix[port]) + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy42"); + break; + case FM2_DTSEC3: + if (qsgmiiphy_fix[port]) + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy43"); + break; + case FM2_DTSEC4: + if (qsgmiiphy_fix[port]) + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy44"); + break; + case FM2_DTSEC6: + if (qsgmiiphy_fix[port]) + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy32"); + break; + case FM2_DTSEC9: + if (qsgmiiphy_fix[port]) + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy34"); + else + fdt_set_phy_handle(blob, prop, pa, + "phy_sgmii12"); + break; + case FM2_DTSEC10: + if (qsgmiiphy_fix[port]) + fdt_set_phy_handle(blob, prop, pa, + "sgmii_phy33"); + else + fdt_set_phy_handle(blob, prop, pa, + "phy_sgmii11"); + break; + default: + break; + } + } } void fdt_fixup_board_enet(void *fdt) { - /* TODO: will do with dts */ + int i; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + + prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + switch (mdio_mux[i]) { + case EMI1_SLOT1: + fdt_status_okay_by_alias(fdt, "emi1_slot1"); + break; + case EMI1_SLOT2: + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + break; + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + break; + case EMI1_SLOT4: + fdt_status_okay_by_alias(fdt, "emi1_slot4"); + break; + default: + break; + } + break; + case PHY_INTERFACE_MODE_XGMII: + /* check if it's XFI interface for 10g */ + if ((prtcl2 == 56) || (prtcl2 == 57)) { + fdt_status_okay_by_alias(fdt, "emi2_xfislot3"); + break; + } + switch (i) { + case FM1_10GEC1: + fdt_status_okay_by_alias(fdt, "emi2_xauislot1"); + break; + case FM1_10GEC2: + fdt_status_okay_by_alias(fdt, "emi2_xauislot2"); + break; + case FM2_10GEC1: + fdt_status_okay_by_alias(fdt, "emi2_xauislot3"); + break; + case FM2_10GEC2: + fdt_status_okay_by_alias(fdt, "emi2_xauislot4"); + break; + default: + break; + } + break; + default: + break; + } + } +} + +static void initialize_qsgmiiphy_fix(void) +{ + int i; + unsigned short reg; + + for (i = 1; i <= 4; i++) { + /* + * Try to read if a SGMII card is used, we do it slot by slot. + * if a SGMII PHY address is valid on a slot, then we mark + * all ports on the slot, then fix the PHY address for the + * marked port when doing dtb fixup. + */ + if (miiphy_read(mdio_names[i], + SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, ®) != 0) { + debug("Slot%d PHY ID register 2 read failed\n", i); + continue; + } + + debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg); + + if (reg == 0xFFFF) { + /* No physical device present at this address */ + continue; + } + + switch (i) { + case 1: + qsgmiiphy_fix[FM1_DTSEC5] = 1; + qsgmiiphy_fix[FM1_DTSEC6] = 1; + qsgmiiphy_fix[FM1_DTSEC9] = 1; + qsgmiiphy_fix[FM1_DTSEC10] = 1; + slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR; + slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR; + slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR; + slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR; + break; + case 2: + qsgmiiphy_fix[FM1_DTSEC1] = 1; + qsgmiiphy_fix[FM1_DTSEC2] = 1; + qsgmiiphy_fix[FM1_DTSEC3] = 1; + qsgmiiphy_fix[FM1_DTSEC4] = 1; + slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR; + slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR; + slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR; + slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR; + break; + case 3: + qsgmiiphy_fix[FM2_DTSEC5] = 1; + qsgmiiphy_fix[FM2_DTSEC6] = 1; + qsgmiiphy_fix[FM2_DTSEC9] = 1; + qsgmiiphy_fix[FM2_DTSEC10] = 1; + slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR; + slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR; + slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR; + slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR; + break; + case 4: + qsgmiiphy_fix[FM2_DTSEC1] = 1; + qsgmiiphy_fix[FM2_DTSEC2] = 1; + qsgmiiphy_fix[FM2_DTSEC3] = 1; + qsgmiiphy_fix[FM2_DTSEC4] = 1; + slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR; + slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR; + slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR; + slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR; + break; + default: + break; + } + } } int board_eth_init(bd_t *bis) { #if defined(CONFIG_FMAN_ENET) - int i; + int i, idx, lane, slot; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -236,6 +451,7 @@ int board_eth_init(bd_t *bis) t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); + initialize_qsgmiiphy_fix(); switch (srds_prtcl_s1) { case 1: @@ -248,44 +464,48 @@ int board_eth_init(bd_t *bis) case 28: case 36: /* SGMII in Slot1 and Slot2 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); + fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); + fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]); + fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); + fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); + fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC9, - SGMII_CARD_PORT4_PHY_ADDR); + slot_qsgmii_phyaddr[1][3]); fm_info_set_phy_address(FM1_DTSEC10, - SGMII_CARD_PORT3_PHY_ADDR); + slot_qsgmii_phyaddr[1][2]); } break; case 38: - fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); + fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); + fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]); + fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); + fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); + fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC9, - QSGMII_CARD_PHY_ADDR); + slot_qsgmii_phyaddr[1][3]); fm_info_set_phy_address(FM1_DTSEC10, - QSGMII_CARD_PHY_ADDR); + slot_qsgmii_phyaddr[1][2]); } break; case 40: case 46: case 48: - fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); + fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC10, - SGMII_CARD_PORT3_PHY_ADDR); + slot_qsgmii_phyaddr[1][3]); fm_info_set_phy_address(FM1_DTSEC9, - SGMII_CARD_PORT4_PHY_ADDR); + slot_qsgmii_phyaddr[1][2]); } - fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); + fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); + fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]); + fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); break; default: puts("Invalid SerDes1 protocol for T4240QDS\n"); @@ -293,7 +513,7 @@ int board_eth_init(bd_t *bis) } for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1, lane, slot; + idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: lane = serdes_get_first_lane(FSL_SRDS_1, @@ -334,8 +554,16 @@ int board_eth_init(bd_t *bis) } for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: + lane = serdes_get_first_lane(FSL_SRDS_1, + XAUI_FM1_MAC9 + idx); + if (lane < 0) + break; + slot = lane_to_slot_fsm1[lane]; + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); mdio_mux[i] = EMI2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; @@ -344,7 +572,6 @@ int board_eth_init(bd_t *bis) } } - #if (CONFIG_SYS_NUM_FMAN == 2) switch (srds_prtcl_s2) { case 1: @@ -364,68 +591,64 @@ int board_eth_init(bd_t *bis) case 26: /* XAUI/HiGig in Slot3, SGMII in Slot4 */ fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); + fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); + fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); + fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; case 28: case 36: /* SGMII in Slot3 and Slot4 */ - fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); + fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); + fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); + fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); + fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); + fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); + fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); + fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); break; case 38: /* QSGMII in Slot3 and Slot4 */ - fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); + fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); + fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); + fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); + fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); + fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); + fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); + fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); break; case 40: case 46: case 48: /* SGMII in Slot3 */ - fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); + fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); + fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); + fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); /* QSGMII in Slot4 */ - fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); + fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); + fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); + fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; case 50: case 52: case 54: fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); + fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); + fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); + fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; case 56: case 57: /* XFI in Slot3, SGMII in Slot4 */ - fm_info_set_phy_address(FM1_10GEC1, XFI_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC2, XFI_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC2, XFI_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC1, XFI_CARD_PORT4_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); + fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); + fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); + fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); break; default: puts("Invalid SerDes2 protocol for T4240QDS\n"); @@ -433,7 +656,7 @@ int board_eth_init(bd_t *bis) } for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - int idx = i - FM2_DTSEC1, lane, slot; + idx = i - FM2_DTSEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: lane = serdes_get_first_lane(FSL_SRDS_2, @@ -477,8 +700,16 @@ int board_eth_init(bd_t *bis) } for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { + idx = i - FM2_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: + lane = serdes_get_first_lane(FSL_SRDS_2, + XAUI_FM2_MAC9 + idx); + if (lane < 0) + break; + slot = lane_to_slot_fsm2[lane]; + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); mdio_mux[i] = EMI2; fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); break; diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c index 6f2c5c86b..f3848f392 100644 --- a/board/freescale/t4qds/law.c +++ b/board/freescale/t4qds/law.c @@ -37,7 +37,8 @@ struct law_entry law_table[] = { #endif SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), #ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CONFIG_SYS_NAND_BASE_PHYS SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t4qds/t4240qds_qixis.h b/board/freescale/t4qds/t4240qds_qixis.h index efb718d2c..485353d5a 100644 --- a/board/freescale/t4qds/t4240qds_qixis.h +++ b/board/freescale/t4qds/t4240qds_qixis.h @@ -42,7 +42,7 @@ #define QIXIS_DDRCLK_125 0x2 #define QIXIS_DDRCLK_133 0x3 -#define BRDCFG5_RESET 0x00 +#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */ #define BRDCFG12_SD3EN_MASK 0x20 #define BRDCFG12_SD3MX_MASK 0x08 diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg new file mode 100644 index 000000000..c598fb5af --- /dev/null +++ b/board/freescale/t4qds/t4_pbi.cfg @@ -0,0 +1,36 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#workaround for IFC bus speed +091241c0 f03f3f3f +091241c4 ff003f3f +09124010 00000101 +09124130 0000000c +#workaround for SERDES A-006031 +090ea000 064740e6 +090ea020 064740e6 +090eb000 064740e6 +090eb020 064740e6 +090ec000 064740e6 +090ec020 064740e6 +090ed000 064740e6 +090ed020 064740e6 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg new file mode 100644 index 000000000..6ac95ffd5 --- /dev/null +++ b/board/freescale/t4qds/t4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +#serdes protocol 1_28_6_12 +14180019 0c101916 00000000 00000000 +04383060 30548c00 6c020000 19000000 +00000000 ee0000ee 00000000 000187fc +00000000 00000000 00000000 00000018 diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c index 3c95f3fb7..f0f280b25 100644 --- a/board/freescale/t4qds/t4qds.c +++ b/board/freescale/t4qds/t4qds.c @@ -110,7 +110,7 @@ int checkboard(void) for (i = 0; i < MAX_SERDES; i++) { static const char *freq[] = { "100", "125", "156.25", "161.1328125"}; - unsigned int clock = (sw >> (2 * i)) & 3; + unsigned int clock = (sw >> (6 - 2 * i)) & 3; printf("SERDES%u=%sMHz ", i+1, freq[clock]); } @@ -132,6 +132,243 @@ int select_i2c_ch_pca9547(u8 ch) return 0; } +/* + * read_voltage from sensor on I2C bus + * We use average of 4 readings, waiting for 532us befor another reading + */ +#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ +#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ + +static inline int read_voltage(void) +{ + int i, ret, voltage_read = 0; + u16 vol_mon; + + for (i = 0; i < NUM_READINGS; i++) { + ret = i2c_read(I2C_VOL_MONITOR_ADDR, + I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2); + if (ret) { + printf("VID: failed to read core voltage\n"); + return ret; + } + if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { + printf("VID: Core voltage sensor error\n"); + return -1; + } + debug("VID: bus voltage reads 0x%04x\n", vol_mon); + /* LSB = 4mv */ + voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; + udelay(WAIT_FOR_ADC); + } + /* calculate the average */ + voltage_read /= NUM_READINGS; + + return voltage_read; +} + +/* + * We need to calculate how long before the voltage starts to drop or increase + * It returns with the loop count. Each loop takes several readings (532us) + */ +static inline int wait_for_voltage_change(int vdd_last) +{ + int timeout, vdd_current; + + vdd_current = read_voltage(); + /* wait until voltage starts to drop */ + for (timeout = 0; abs(vdd_last - vdd_current) <= 4 && + timeout < 100; timeout++) { + vdd_current = read_voltage(); + } + if (timeout >= 100) { + printf("VID: Voltage adjustment timeout\n"); + return -1; + } + return timeout; +} + +/* + * argument 'wait' is the time we know the voltage difference can be measured + * this function keeps reading the voltage until it is stable + */ +static inline int wait_for_voltage_stable(int wait) +{ + int timeout, vdd_current, vdd_last; + + vdd_last = read_voltage(); + udelay(wait * NUM_READINGS * WAIT_FOR_ADC); + /* wait until voltage is stable */ + vdd_current = read_voltage(); + for (timeout = 0; abs(vdd_last - vdd_current) >= 4 && + timeout < 100; timeout++) { + vdd_last = vdd_current; + udelay(wait * NUM_READINGS * WAIT_FOR_ADC); + vdd_current = read_voltage(); + } + if (timeout >= 100) { + printf("VID: Voltage adjustment timeout\n"); + return -1; + } + + return vdd_current; +} + +static inline int set_voltage(u8 vid) +{ + int wait, vdd_last; + + vdd_last = read_voltage(); + QIXIS_WRITE(brdcfg[6], vid); + wait = wait_for_voltage_change(vdd_last); + if (wait < 0) + return -1; + debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC); + wait = wait ? wait : 1; + + vdd_last = wait_for_voltage_stable(wait); + if (vdd_last < 0) + return -1; + debug("VID: Current voltage is %d mV\n", vdd_last); + + return vdd_last; +} + + +static int adjust_vdd(ulong vdd_override) +{ + int re_enable = disable_interrupts(); + ccsr_gur_t __iomem *gur = + (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 fusesr; + u8 vid, vid_current; + int vdd_target, vdd_current, vdd_last; + int ret; + unsigned long vdd_string_override; + char *vdd_string; + static const uint16_t vdd[32] = { + 0, /* unused */ + 9875, /* 0.9875V */ + 9750, + 9625, + 9500, + 9375, + 9250, + 9125, + 9000, + 8875, + 8750, + 8625, + 8500, + 8375, + 8250, + 8125, + 10000, /* 1.0000V */ + 10125, + 10250, + 10375, + 10500, + 10625, + 10750, + 10875, + 11000, + 0, /* reserved */ + }; + struct vdd_drive { + u8 vid; + unsigned voltage; + }; + + ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR); + if (ret) { + debug("VID: I2c failed to switch channel\n"); + ret = -1; + goto exit; + } + + /* get the voltage ID from fuse status register */ + fusesr = in_be32(&gur->dcfg_fusesr); + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_VID_MASK; + if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) { + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; + } + vdd_target = vdd[vid]; + + /* check override variable for overriding VDD */ + vdd_string = getenv("t4240qds_vdd_mv"); + if (vdd_override == 0 && vdd_string && + !strict_strtoul(vdd_string, 10, &vdd_string_override)) + vdd_override = vdd_string_override; + if (vdd_override >= 819 && vdd_override <= 1212) { + vdd_target = vdd_override * 10; /* convert to 1/10 mV */ + debug("VDD override is %lu\n", vdd_override); + } else if (vdd_override != 0) { + printf("Invalid value.\n"); + } + + if (vdd_target == 0) { + debug("VID: VID not used\n"); + ret = 0; + goto exit; + } else { + /* round up and divice by 10 to get a value in mV */ + vdd_target = DIV_ROUND_UP(vdd_target, 10); + debug("VID: vid = %d mV\n", vdd_target); + } + + /* + * Check current board VID setting + * Voltage regulator support output to 6.250mv step + * The highes voltage allowed for this board is (vid=0x40) 1.21250V + * the lowest is (vid=0x7f) 0.81875V + */ + vid_current = QIXIS_READ(brdcfg[6]); + vdd_current = 121250 - (vid_current - 0x40) * 625; + debug("VID: Current vid setting is (0x%x) %d mV\n", + vid_current, vdd_current/100); + + /* + * Read voltage monitor to check real voltage. + * Voltage monitor LSB is 4mv. + */ + vdd_last = read_voltage(); + if (vdd_last < 0) { + printf("VID: Could not read voltage sensor abort VID adjustment\n"); + ret = -1; + goto exit; + } + debug("VID: Core voltage is at %d mV\n", vdd_last); + /* + * Adjust voltage to at or 8mV above target. + * Each step of adjustment is 6.25mV. + * Stepping down too fast may cause over current. + */ + while (vdd_last > 0 && vid_current < 0x80 && + vdd_last > (vdd_target + 8)) { + vid_current++; + vdd_last = set_voltage(vid_current); + } + /* + * Check if we need to step up + * This happens when board voltage switch was set too low + */ + while (vdd_last > 0 && vid_current >= 0x40 && + vdd_last < vdd_target + 2) { + vid_current--; + vdd_last = set_voltage(vid_current); + } + if (vdd_last > 0) + printf("VID: Core voltage %d mV\n", vdd_last); + else + ret = -1; + +exit: + if (re_enable) + enable_interrupts(); + return ret; +} + /* Configure Crossbar switches for Front-Side SerDes Ports */ int config_frontside_crossbar_vsc3316(void) { @@ -282,8 +519,15 @@ int board_early_init_r(void) setup_portals(); #endif - /* Disable remote I2C connectoin */ - QIXIS_WRITE(brdcfg[5], BRDCFG5_RESET); + /* Disable remote I2C connection to qixis fpga */ + QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); + + /* + * Adjust core voltage according to voltage ID + * This function changes I2C mux to channel 2. + */ + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); /* Configure board SERDES ports crossbar */ config_frontside_crossbar_vsc3316(); @@ -296,6 +540,20 @@ int board_early_init_r(void) unsigned long get_board_sys_clk(void) { u8 sysclk_conf = QIXIS_READ(brdcfg[1]); +#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT + /* use accurate clock measurement */ + int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); + int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); + u32 val; + + val = freq * base; + if (val) { + debug("SYS Clock measurement is: %d\n", val); + return val; + } else { + printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n"); + } +#endif switch (sysclk_conf & 0x0F) { case QIXIS_SYSCLK_83: @@ -319,6 +577,20 @@ unsigned long get_board_sys_clk(void) unsigned long get_board_ddr_clk(void) { u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); +#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT + /* use accurate clock measurement */ + int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); + int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); + u32 val; + + val = freq * base; + if (val) { + debug("DDR Clock measurement is: %d\n", val); + return val; + } else { + printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n"); + } +#endif switch ((ddrclk_conf & 0x30) >> 4) { case QIXIS_DDRCLK_100: @@ -357,7 +629,7 @@ int misc_init_r(void) sw = QIXIS_READ(brdcfg[2]); for (i = 0; i < MAX_SERDES; i++) { - unsigned int clock = (sw >> (2 * i)) & 3; + unsigned int clock = (sw >> (6 - 2 * i)) & 3; switch (clock) { case 0: actual[i] = SRDS_PLLCR0_RFCK_SEL_100; @@ -414,6 +686,106 @@ void ft_board_setup(void *blob, bd_t *bd) } /* + * This function is called by bdinfo to print detail board information. + * As an exmaple for future board, we organize the messages into + * several sections. If applicable, the message is in the format of + * <name> = <value> + * It should aligned with normal output of bdinfo command. + * + * Voltage: Core, DDR and another configurable voltages + * Clock : Critical clocks which are not printed already + * RCW : RCW source if not printed already + * Misc : Other important information not in above catagories + */ +void board_detail(void) +{ + int i; + u8 brdcfg[16], dutcfg[16], rst_ctl; + int vdd, rcwsrc; + static const char * const clk[] = {"66.67", "100", "125", "133.33"}; + + for (i = 0; i < 16; i++) { + brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); + dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); + } + + /* Voltage secion */ + if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) { + vdd = read_voltage(); + if (vdd > 0) + printf("Core voltage= %d mV\n", vdd); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + } + + printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25); + + /* clock section */ + printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n", + clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]); + + /* RCW section */ + rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1); + puts("RCW source = "); + switch (rcwsrc) { + case 0x017: + case 0x01f: + puts("8-bit NOR\n"); + break; + case 0x027: + case 0x02F: + puts("16-bit NOR\n"); + break; + case 0x040: + puts("SDHC/eMMC\n"); + break; + case 0x044: + puts("SPI 16-bit addressing\n"); + break; + case 0x045: + puts("SPI 24-bit addressing\n"); + break; + case 0x048: + puts("I2C normal addressing\n"); + break; + case 0x049: + puts("I2C extended addressing\n"); + break; + case 0x108: + case 0x109: + case 0x10a: + case 0x10b: + puts("8-bit NAND, 2KB\n"); + break; + default: + if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f)) + puts("Hard-coded RCW\n"); + else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f)) + puts("8-bit NAND, 4KB\n"); + else + puts("unknown\n"); + break; + } + + /* Misc section */ + rst_ctl = QIXIS_READ(rst_ctl); + puts("HRESET_REQ = "); + switch (rst_ctl & 0x30) { + case 0x00: + puts("Ignored\n"); + break; + case 0x10: + puts("Assert HRESET\n"); + break; + case 0x30: + puts("Reset system\n"); + break; + default: + puts("N/A\n"); + break; + } +} + +/* * Reverse engineering switch settings. * Some bits cannot be figured out. They will be displayed as * underscore in binary format. mask[] has those bits. @@ -429,7 +801,7 @@ void qixis_dump_switch(void) * Any bit with 1 means that bit cannot be reverse engineered. * It will be displayed as _ in binary format. */ - static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xdf, 0x3f, 0x1f}; + static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f}; char buf[10]; u8 brdcfg[16], dutcfg[16]; @@ -460,7 +832,8 @@ void qixis_dump_switch(void) sw[5] = ((brdcfg[0] & 0x0f) << 4) | \ ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \ ((brdcfg[0] & 0x40) >> 5); - sw[6] = (brdcfg[11] & 0x20); + sw[6] = (brdcfg[11] & 0x20) | + ((brdcfg[5] & 0x02) << 3); sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \ ((brdcfg[5] & 0x10) << 2); sw[8] = ((brdcfg[12] & 0x08) << 4) | \ @@ -472,3 +845,23 @@ void qixis_dump_switch(void) i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); } } + +static int do_vdd_adjust(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ulong override; + + if (argc < 2) + return CMD_RET_USAGE; + if (!strict_strtoul(argv[1], 10, &override)) + adjust_vdd(override); /* the value is checked by callee */ + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + vdd_override, 2, 0, do_vdd_adjust, + "Override VDD", + "- override with the voltage specified in mV, eg. 1050" +); diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c index 80eb511e1..92c01cf95 100644 --- a/board/freescale/t4qds/tlb.c +++ b/board/freescale/t4qds/tlb.c @@ -115,7 +115,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 13, BOOKE_PAGESZ_4M, 1), + 0, 13, BOOKE_PAGESZ_32M, 1), #endif #ifdef CONFIG_SYS_NAND_BASE /* |