diff options
Diffstat (limited to 'board/esd/pmc440/pmc440.c')
| -rw-r--r-- | board/esd/pmc440/pmc440.c | 80 |
1 files changed, 8 insertions, 72 deletions
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index ec9255243..d0ff080fa 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -39,6 +39,8 @@ #include <miiphy.h> #endif #include <serial.h> +#include <asm/4xx_pci.h> + #include "fpga.h" #include "pmc440.h" @@ -478,7 +480,7 @@ int checkboard(void) /* * Assign interrupts to PCI devices. Some OSs rely on this. */ -void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB}; @@ -488,64 +490,6 @@ void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) #endif /* - * pci_pre_init - * - * This routine is called just prior to registering the hose and gives - * the board the opportunity to check things. Returning a value of zero - * indicates that things are bad & PCI initialization should be aborted. - * - * Different boards may wish to customize the pci controller structure - * (add regions, override default access routines, etc) or perform - * certain pre-initialization actions. - */ -#if defined(CONFIG_PCI) -int pci_pre_init(struct pci_controller *hose) -{ - unsigned long addr; - - /* - * Set priority for all PLB3 devices to 0. - * Set PLB3 arbiter to fair mode. - */ - mfsdr(SD0_AMP1, addr); - mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB3_ACR); - mtdcr(PLB3_ACR, addr | 0x80000000); - - /* - * Set priority for all PLB4 devices to 0. - */ - mfsdr(SD0_AMP0, addr); - mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ - mtdcr(PLB4_ACR, addr); - - /* - * Set Nebula PLB4 arbiter to fair mode. - */ - /* Segment0 */ - addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; - addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; - addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; - addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; - mtdcr(PLB0_ACR, addr); - - /* Segment1 */ - addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; - addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; - addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; - addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; - mtdcr(PLB1_ACR, addr); - -#ifdef CONFIG_PCI_PNP - hose->fixup_irq = pmc440_pci_fixup_irq; -#endif - - return 1; -} -#endif /* defined(CONFIG_PCI) */ - -/* * pci_target_init * * The bootstrap configuration provides default settings for the pci @@ -658,24 +602,16 @@ void pci_target_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /* - * pci_master_init + * Override weak default pci_master_init() */ #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { - unsigned short temp_short; - /* - * Write the PowerPC440 EP PCI Configuration regs. - * Enable PowerPC440 EP to be a master on the PCI bus (PMM). - * Enable PowerPC440 EP to act as a PCI memory target (PTM). + * Only configure the master in monach mode */ - if (is_monarch()) { - pci_read_config_word(0, PCI_COMMAND, &temp_short); - pci_write_config_word(0, PCI_COMMAND, - temp_short | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY); - } + if (is_monarch()) + __pci_master_init(hose); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ @@ -712,7 +648,7 @@ static void wait_for_pci_ready(void) } /* - * is_pci_host + * Override weak is_pci_host() * * This routine is called to determine if a pci scan should be * performed. With various hardware environments (especially cPCI and |