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-rw-r--r--board/davedenx/qong/Makefile2
-rw-r--r--board/davedenx/qong/fpga.c95
-rw-r--r--board/davedenx/qong/qong.c44
-rw-r--r--board/davedenx/qong/qong_fpga.h3
4 files changed, 141 insertions, 3 deletions
diff --git a/board/davedenx/qong/Makefile b/board/davedenx/qong/Makefile
index 93e198542..ada6e03a2 100644
--- a/board/davedenx/qong/Makefile
+++ b/board/davedenx/qong/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := qong.o
+COBJS := qong.o fpga.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/davedenx/qong/fpga.c b/board/davedenx/qong/fpga.c
new file mode 100644
index 000000000..f865eb422
--- /dev/null
+++ b/board/davedenx/qong/fpga.c
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+#include <mxc_gpio.h>
+#include <fpga.h>
+#include <lattice.h>
+#include "qong_fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA)
+
+static void qong_jtag_init(void)
+{
+ return;
+}
+
+static void qong_fpga_jtag_set_tdi(int value)
+{
+ mxc_gpio_set(QONG_FPGA_TDI_PIN, value);
+}
+
+static void qong_fpga_jtag_set_tms(int value)
+{
+ mxc_gpio_set(QONG_FPGA_TMS_PIN, value);
+}
+
+static void qong_fpga_jtag_set_tck(int value)
+{
+ mxc_gpio_set(QONG_FPGA_TCK_PIN, value);
+}
+
+static int qong_fpga_jtag_get_tdo(void)
+{
+ return mxc_gpio_get(QONG_FPGA_TDO_PIN);
+}
+
+lattice_board_specific_func qong_fpga_fns = {
+ qong_jtag_init,
+ qong_fpga_jtag_set_tdi,
+ qong_fpga_jtag_set_tms,
+ qong_fpga_jtag_set_tck,
+ qong_fpga_jtag_get_tdo
+};
+
+Lattice_desc qong_fpga[CONFIG_FPGA_COUNT] = {
+ {
+ Lattice_XP2,
+ lattice_jtag_mode,
+ 356519,
+ (void *) &qong_fpga_fns,
+ NULL,
+ 0,
+ "lfxp2_5e_ftbga256"
+ },
+};
+
+int qong_fpga_init(void)
+{
+ int i;
+
+ fpga_init();
+
+ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+ fpga_add(fpga_lattice, &qong_fpga[i]);
+ }
+ return 0;
+}
+
+#endif
+
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
index 9abc29c5f..8a81cfc68 100644
--- a/board/davedenx/qong/qong.c
+++ b/board/davedenx/qong/qong.c
@@ -25,6 +25,7 @@
#include <netdev.h>
#include <asm/arch/mx31.h>
#include <asm/arch/mx31-regs.h>
+#include <asm/io.h>
#include <nand.h>
#include <fsl_pmic.h>
#include <mxc_gpio.h>
@@ -73,6 +74,15 @@ int board_early_init_f (void)
/* set interrupt pin as input */
mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN);
+ /* FPGA JTAG Interface */
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
+ mxc_gpio_direction(QONG_FPGA_TCK_PIN, MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_direction(QONG_FPGA_TMS_PIN, MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_direction(QONG_FPGA_TDI_PIN, MXC_GPIO_DIRECTION_OUT);
+ mxc_gpio_direction(QONG_FPGA_TDO_PIN, MXC_GPIO_DIRECTION_IN);
#endif
/* setup pins for UART1 */
@@ -88,6 +98,38 @@ int board_early_init_f (void)
mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+ /* Setup pins for USB2 Host */
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC));
+ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC));
+
+#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+ mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
+ mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
+ mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
+ mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
+ mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
+ mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
+ mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
+ mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
+ mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
+ mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
+ mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
+ mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
+
+ writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8);
+
return 0;
}
@@ -146,6 +188,8 @@ int board_init (void)
gd->bd->bi_arch_number = MACH_TYPE_QONG;
gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
+ qong_fpga_init();
+
return 0;
}
diff --git a/board/davedenx/qong/qong_fpga.h b/board/davedenx/qong/qong_fpga.h
index 4e11f5a1c..4e79ac2cf 100644
--- a/board/davedenx/qong/qong_fpga.h
+++ b/board/davedenx/qong/qong_fpga.h
@@ -24,7 +24,6 @@
#ifndef QONG_FPGA_H
#define QONG_FPGA_H
-#ifdef CONFIG_QONG_FPGA
#define QONG_FPGA_CTRL_BASE CONFIG_FPGA_BASE
#define QONG_FPGA_CTRL_VERSION (QONG_FPGA_CTRL_BASE + 0x00000000)
#define QONG_FPGA_PERIPH_SIZE (1 << 24)
@@ -35,6 +34,6 @@
#define QONG_FPGA_TDO_PIN 7
#define QONG_FPGA_RST_PIN 48
#define QONG_FPGA_IRQ_PIN 40
-#endif
+int qong_fpga_init(void);
#endif /* QONG_FPGA_H */
generated by cgit v1.2.3-70-g09d2 (git 2.51.2) at 2025-10-30 22:03:18 +0000