diff options
Diffstat (limited to 'arch')
91 files changed, 1026 insertions, 695 deletions
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c index b4dc4a6e2..bd6a5b120 100644 --- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c +++ b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c @@ -148,7 +148,7 @@ unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer) /* Command 16 to read aBlocks from the MMC/SD - caed */ unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF}; - /* The addres on the MMC/SD-card is in bytes, + /* The address on the MMC/SD-card is in bytes, addr is transformed from blocks to bytes and the result is placed into the command */ @@ -173,7 +173,7 @@ unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer) /* Command 24 to write a block to the MMC/SD - card */ unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF}; - /* The addres on the MMC/SD-card is in bytes, + /* The address on the MMC/SD-card is in bytes, addr is transformed from blocks to bytes and the result is placed into the command */ diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 091b7d891..ecb92ef21 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -274,7 +274,7 @@ _dynsym_start_ofs: #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) -/* Interupt-Controller base addresses */ +/* Interrupt-Controller base addresses */ INTMR1: .word 0x80000280 @ 32 bit size INTMR2: .word 0x80001280 @ 16 bit size INTMR3: .word 0x80002280 @ 8 bit size diff --git a/arch/arm/cpu/arm920t/at91/timer.c b/arch/arm/cpu/arm920t/at91/timer.c index c321e2864..91607b525 100644 --- a/arch/arm/cpu/arm920t/at91/timer.c +++ b/arch/arm/cpu/arm920t/at91/timer.c @@ -59,7 +59,7 @@ int timer_init(void) when the value in TC_RC is reached */ writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr); - writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */ + writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */ writel(TIMER_LOAD_VAL, &tc->tc[0].rc); writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr); diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 2a536674b..0090f894d 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -142,11 +142,11 @@ copyex: # if defined(CONFIG_S3C2400) # define pWTCON 0x15300000 -# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ +# define INTMSK 0x14400008 /* Interrupt-Controller base addresses */ # define CLKDIVN 0x14800014 /* clock divisor register */ #else # define pWTCON 0x53000000 -# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ +# define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */ # define INTSUBMSK 0x4A00001C # define CLKDIVN 0x4C000014 /* clock divisor register */ # endif diff --git a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c index 09f69ce32..642e67ae8 100644 --- a/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c +++ b/arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c @@ -386,7 +386,7 @@ ixQMgrNotificationEnable (IxQMgrQId qId, &dispatchQInfo[qId].statusMask); - /* Set the interupt source is this queue is in the range 0-31 */ + /* Set the interrupt source is this queue is in the range 0-31 */ if (qId < IX_QMGR_MIN_QUEUPP_QID) { ixQMgrAqmIfIntSrcSelWrite (qId, srcSel); diff --git a/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h b/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h index 0ee412355..4e0de8235 100644 --- a/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h +++ b/arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h @@ -279,7 +279,7 @@ typedef struct BOOL portInitialized; UINT32 npeId; /**< NpeId for this port */ IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */ - IxEthAccRxDataInfo ixEthAccRxData; /**< Recieve data control structures */ + IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */ } IxEthAccPortDataInfo; extern IxEthAccPortDataInfo ixEthAccPortData[]; diff --git a/arch/arm/cpu/ixp/npe/include/IxNpeA.h b/arch/arm/cpu/ixp/npe/include/IxNpeA.h index 7427cc41c..90669c27e 100644 --- a/arch/arm/cpu/ixp/npe/include/IxNpeA.h +++ b/arch/arm/cpu/ixp/npe/include/IxNpeA.h @@ -717,7 +717,7 @@ typedef struct */ typedef struct { - UINT32 rxBitField; /**< Recieved bit field */ + UINT32 rxBitField; /**< Received bit field */ UINT32 atmCellHeader; /**< ATM Cell Header */ UINT32 rsvdWord0; /**< Reserved field */ UINT16 currMbufLen; /**< Mbuf Length */ diff --git a/arch/arm/cpu/ixp/npe/include/IxQMgr.h b/arch/arm/cpu/ixp/npe/include/IxQMgr.h index 165ed96e5..03d7e0709 100644 --- a/arch/arm/cpu/ixp/npe/include/IxQMgr.h +++ b/arch/arm/cpu/ixp/npe/include/IxQMgr.h @@ -570,7 +570,7 @@ typedef enum * @brief Queue interrupt source select. * * This enum defines the different source conditions on a queue that result in - * an interupt being fired by the AQM. Interrupt source is configurable for + * an interrupt being fired by the AQM. Interrupt source is configurable for * queues 0-31 only. The interrupt source for queues 32-63 is hardwired to the * NE(Nearly Empty) status flag. * diff --git a/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h b/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h index f7194e72e..b65d621e3 100644 --- a/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h +++ b/arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h @@ -404,7 +404,7 @@ * * @def IX_ETH_ACC_RX_FRAME_ETH_Q * -* @brief Eth0/Eth1 NPE Frame Recieve Q. +* @brief Eth0/Eth1 NPE Frame Receive Q. * * @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration * diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S index 61bce5f18..14e985457 100644 --- a/arch/arm/cpu/lh7a40x/start.S +++ b/arch/arm/cpu/lh7a40x/start.S @@ -124,7 +124,7 @@ reset: msr cpsr,r0 #define pWDTCTL 0x80001400 /* Watchdog Timer control register */ -#define pINTENC 0x8000050C /* Interupt-Controller enable clear register */ +#define pINTENC 0x8000050C /* Interrupt-Controller enable clear register */ #define pCLKSET 0x80000420 /* clock divisor register */ /* disable watchdog, set watchdog control register to diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index c3acf7aae..7223c471b 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -263,7 +263,7 @@ _dynsym_start_ofs: */ -/* Interupt-Controller base address */ +/* Interrupt-Controller base address */ IC_BASE: .word 0x90050000 #define ICMR 0x04 diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index 390402701..d3308f7a8 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -57,21 +57,10 @@ void dram_init_banksize (void); void setup_serial_tag (struct tag **params); void setup_revision_tag (struct tag **params); -/* ------------------------------------------------------------ */ -/* Here is a list of some prototypes which are incompatible to */ -/* the U-Boot implementation */ -/* To be fixed! */ -/* ------------------------------------------------------------ */ -/* common/cmd_nvedit.c */ -int setenv (char *, char *); - /* cpu/.../interrupt.c */ int arch_interrupt_init (void); void reset_timer_masked (void); ulong get_timer_masked (void); void udelay_masked (unsigned long usec); -/* cpu/.../timer.c */ -int timer_init (void); - #endif /* _U_BOOT_ARM_H_ */ diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index bcbf697b5..90709d075 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -42,7 +42,6 @@ #include <command.h> #include <malloc.h> #include <stdio_dev.h> -#include <timestamp.h> #include <version.h> #include <net.h> #include <serial.h> @@ -70,13 +69,6 @@ extern int AT91F_DataflashInit(void); extern void dataflash_print_info(void); #endif -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - -const char version_string[] = - U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"CONFIG_IDENT_STRING; - #ifdef CONFIG_DRIVER_RTL8019 extern void rtl8019_get_enetaddr (uchar * addr); #endif diff --git a/arch/avr32/include/asm/initcalls.h b/arch/avr32/include/asm/initcalls.h deleted file mode 100644 index 57a278b6a..000000000 --- a/arch/avr32/include/asm/initcalls.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2005, 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_INITCALLS_H__ -#define __ASM_AVR32_INITCALLS_H__ - -#include <config.h> - -extern int cpu_init(void); -extern int timer_init(void); - -#endif /* __ASM_AVR32_INITCALLS_H__ */ diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index 5edef8fd3..65473a107 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -23,7 +23,6 @@ #include <command.h> #include <malloc.h> #include <stdio_dev.h> -#include <timestamp.h> #include <version.h> #include <net.h> @@ -31,7 +30,6 @@ #include <miiphy.h> #endif -#include <asm/initcalls.h> #include <asm/sections.h> #include <asm/arch/mmu.h> @@ -41,9 +39,6 @@ DECLARE_GLOBAL_DATA_PTR; -const char version_string[] = - U_BOOT_VERSION " ("U_BOOT_DATE" - "U_BOOT_TIME") " CONFIG_IDENT_STRING; - unsigned long monitor_flash_len; /* Weak aliases for optional board functions */ diff --git a/arch/blackfin/cpu/.gitignore b/arch/blackfin/cpu/.gitignore index 0ec9d5672..ba986d8ba 100644 --- a/arch/blackfin/cpu/.gitignore +++ b/arch/blackfin/cpu/.gitignore @@ -1 +1,4 @@ bootrom-asm-offsets.[chs] + +init.lds +init.elf diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile index df10f1bc6..5deaa9e6a 100644 --- a/arch/blackfin/cpu/Makefile +++ b/arch/blackfin/cpu/Makefile @@ -13,7 +13,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).o -EXTRA := +EXTRA := init.elf CEXTRA := initcode.o SEXTRA := start.o SOBJS := interrupt.o cache.o @@ -61,6 +61,11 @@ ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) fi endif +$(obj)init.lds: init.lds.S + $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P $^ -o $@ +$(obj)init.elf: $(obj)init.lds $(obj)init.o $(obj)initcode.o + $(LD) $(LDFLAGS) -T $^ -o $@ + ######################################################################### # defines $(obj).depend target diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c index 18dbdf7ab..6a0bcca9f 100644 --- a/arch/blackfin/cpu/cpu.c +++ b/arch/blackfin/cpu/cpu.c @@ -19,6 +19,7 @@ #include "cpu.h" #include "serial.h" +#include "initcode.h" ulong bfin_poweron_retx; @@ -44,13 +45,16 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[]; memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len); } -#if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) - /* The BF537 bootrom will reset the EBIU_AMGCTL register on us - * after it has finished loading the LDR. So configure it again. + + /* + * Make sure our async settings are committed. Some bootroms + * (like the BF537) will reset some registers on us after it + * has finished loading the LDR. Or if we're booting over + * JTAG, the initcode never got a chance to run. Or if we + * aren't booting from parallel flash, the initcode skipped + * this step completely. */ - else - bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); -#endif + program_async_controller(NULL); /* Save RETX so we can pass it while booting Linux */ bfin_poweron_retx = bootflag; diff --git a/arch/blackfin/cpu/gpio.c b/arch/blackfin/cpu/gpio.c index cb96721cf..5674d42b6 100644 --- a/arch/blackfin/cpu/gpio.c +++ b/arch/blackfin/cpu/gpio.c @@ -665,6 +665,7 @@ int bfin_gpio_request(unsigned gpio, const char *label) return 0; } +#ifdef CONFIG_BFIN_GPIO_TRACK void bfin_gpio_free(unsigned gpio) { if (check_gpio(gpio) < 0) @@ -679,6 +680,7 @@ void bfin_gpio_free(unsigned gpio) set_label(gpio, "free"); } +#endif #ifdef BFIN_SPECIAL_GPIO_BANKS DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES)); diff --git a/arch/blackfin/cpu/init.S b/arch/blackfin/cpu/init.S new file mode 100644 index 000000000..f48c11320 --- /dev/null +++ b/arch/blackfin/cpu/init.S @@ -0,0 +1,9 @@ +#include <asm/blackfin.h> +ENTRY(_start) + sp.l = LO(L1_SRAM_SCRATCH_END - 20); + sp.h = HI(L1_SRAM_SCRATCH_END - 20); + call _initcode; +1: + emuexcpt; + jump 1b; +END(_start) diff --git a/arch/blackfin/cpu/init.lds.S b/arch/blackfin/cpu/init.lds.S new file mode 100644 index 000000000..602e7c879 --- /dev/null +++ b/arch/blackfin/cpu/init.lds.S @@ -0,0 +1,25 @@ +/* + * linker script for simple init.elf + * + * Copyright (c) 2005-2011 Analog Device Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <config.h> +#include <asm/blackfin.h> +#undef ALIGN +#undef ENTRY + +OUTPUT_ARCH(bfin) + +MEMORY +{ + l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE +} + +ENTRY(_start) +SECTIONS +{ + .text.l1 : { *(.text .text.*) } >l1_code +} diff --git a/arch/blackfin/cpu/initcode.c b/arch/blackfin/cpu/initcode.c index 750add06b..fb3a101c7 100644 --- a/arch/blackfin/cpu/initcode.c +++ b/arch/blackfin/cpu/initcode.c @@ -4,7 +4,7 @@ * cannot make any function calls as it may be executed all by itself by * the Blackfin's bootrom in LDR format. * - * Copyright (c) 2004-2008 Analog Devices Inc. + * Copyright (c) 2004-2011 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -19,11 +19,15 @@ #include <asm/mach-common/bits/pll.h> #include <asm/mach-common/bits/uart.h> +#define BUG() while (1) { asm volatile("emuexcpt;"); } + #include "serial.h" __attribute__((always_inline)) static inline void serial_init(void) { + uint32_t uart_base = UART_DLL; + #ifdef __ADSPBF54x__ # ifdef BFIN_BOOT_UART_USE_RTS # define BFIN_UART_USE_RTS 1 @@ -65,13 +69,13 @@ static inline void serial_init(void) if (BFIN_DEBUG_EARLY_SERIAL) { int ucen = bfin_read16(&pUART->gctl) & UCEN; - serial_early_init(); + serial_early_init(uart_base); /* If the UART is off, that means we need to program * the baud rate ourselves initially. */ if (ucen != UCEN) - serial_early_set_baud(CONFIG_BAUDRATE); + serial_early_set_baud(uart_base, CONFIG_BAUDRATE); } } @@ -79,6 +83,8 @@ __attribute__((always_inline)) static inline void serial_deinit(void) { #ifdef __ADSPBF54x__ + uint32_t uart_base = UART_DLL; + if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) { /* clear forced RTS rather than relying on auto RTS */ bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL); @@ -89,6 +95,8 @@ static inline void serial_deinit(void) __attribute__((always_inline)) static inline void serial_putc(char c) { + uint32_t uart_base = UART_DLL; + if (!BFIN_DEBUG_EARLY_SERIAL) return; @@ -101,6 +109,8 @@ static inline void serial_putc(char c) continue; } +#include "initcode.h" + __attribute__((always_inline)) static inline void program_nmi_handler(void) { @@ -166,21 +176,6 @@ program_nmi_handler(void) # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF) #endif -#ifndef CONFIG_EBIU_RSTCTL_VAL -# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */ -#endif -#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0) -# error invalid EBIU_RSTCTL value: must not set reserved bits -#endif - -#ifndef CONFIG_EBIU_MBSCTL_VAL -# define CONFIG_EBIU_MBSCTL_VAL 0 -#endif - -#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0) -# error invalid EBIU_DDRQUE value: must not set reserved bits -#endif - /* Make sure our voltage value is sane so we don't blow up! */ #ifndef CONFIG_VR_CTL_VAL # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV) @@ -519,7 +514,7 @@ update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB) unsigned int quotient; for (quotient = 0; dividend > 0; ++quotient) dividend -= divisor; - serial_early_put_div(quotient - ANOMALY_05000230); + serial_early_put_div(UART_DLL, quotient - ANOMALY_05000230); serial_putc('c'); } @@ -636,34 +631,6 @@ check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs) serial_putc('e'); } -__attribute__((always_inline)) static inline void -program_async_controller(ADI_BOOT_DATA *bs) -{ - serial_putc('a'); - - /* Program the async banks controller. */ - bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL); - bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL); - bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); - - serial_putc('b'); - - /* Not all parts have these additional MMRs. */ -#ifdef EBIU_MBSCTL - bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL); -#endif -#ifdef EBIU_MODE -# ifdef CONFIG_EBIU_MODE_VAL - bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL); -# endif -# ifdef CONFIG_EBIU_FCTL_VAL - bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL); -# endif -#endif - - serial_putc('c'); -} - BOOTROM_CALLED_FUNC_ATTR void initcode(ADI_BOOT_DATA *bs) { diff --git a/arch/blackfin/cpu/initcode.h b/arch/blackfin/cpu/initcode.h new file mode 100644 index 000000000..e0aad6de0 --- /dev/null +++ b/arch/blackfin/cpu/initcode.h @@ -0,0 +1,71 @@ +/* + * Code for early processor initialization + * + * Copyright (c) 2004-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_INITCODE_H__ +#define __BFIN_INITCODE_H__ + +#include <asm/mach-common/bits/bootrom.h> + +#ifndef BFIN_IN_INITCODE +# define serial_putc(c) +#endif + +#ifndef CONFIG_EBIU_RSTCTL_VAL +# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */ +#endif +#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0) +# error invalid EBIU_RSTCTL value: must not set reserved bits +#endif + +#ifndef CONFIG_EBIU_MBSCTL_VAL +# define CONFIG_EBIU_MBSCTL_VAL 0 +#endif + +#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0) +# error invalid EBIU_DDRQUE value: must not set reserved bits +#endif + +__attribute__((always_inline)) static inline void +program_async_controller(ADI_BOOT_DATA *bs) +{ +#ifdef BFIN_IN_INITCODE + /* + * We really only need to setup the async banks early if we're + * booting out of it. Otherwise, do it later on in cpu_init. + */ + if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && + CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_PARA) + return; +#endif + + serial_putc('a'); + + /* Program the async banks controller. */ + bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL); + bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL); + bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); + + serial_putc('b'); + + /* Not all parts have these additional MMRs. */ +#ifdef EBIU_MBSCTL + bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL); +#endif +#ifdef EBIU_MODE +# ifdef CONFIG_EBIU_MODE_VAL + bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL); +# endif +# ifdef CONFIG_EBIU_FCTL_VAL + bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL); +# endif +#endif + + serial_putc('c'); +} + +#endif diff --git a/arch/blackfin/cpu/jtag-console.c b/arch/blackfin/cpu/jtag-console.c index e0f297560..a77358a88 100644 --- a/arch/blackfin/cpu/jtag-console.c +++ b/arch/blackfin/cpu/jtag-console.c @@ -48,11 +48,11 @@ static inline uint32_t bfin_read_emudat(void) static bool jtag_write_emudat(uint32_t emudat) { static bool overflowed = false; - ulong timeout = get_timer(0) + CONFIG_JTAG_CONSOLE_TIMEOUT; + ulong timeout = get_timer(0); while (bfin_read_DBGSTAT() & 0x1) { if (overflowed) return overflowed; - if (timeout < get_timer(0)) + if (get_timer(timeout) > CONFIG_JTAG_CONSOLE_TIMEOUT) overflowed = true; } overflowed = false; diff --git a/arch/blackfin/cpu/reset.c b/arch/blackfin/cpu/reset.c index e23dcc7ba..ff39035de 100644 --- a/arch/blackfin/cpu/reset.c +++ b/arch/blackfin/cpu/reset.c @@ -51,7 +51,9 @@ static void bfin_reset(void) /* The BF526 ROM will crash during reset */ #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) - bfin_read_SWRST(); + /* Seems to be fixed with newer parts though ... */ + if (__SILICON_REVISION__ < 1 && bfin_revid() < 1) + bfin_read_SWRST(); #endif /* Wait for the SWRST write to complete. Cannot rely on SSYNC diff --git a/arch/blackfin/cpu/serial.c b/arch/blackfin/cpu/serial.c index 650202e24..030160f41 100644 --- a/arch/blackfin/cpu/serial.c +++ b/arch/blackfin/cpu/serial.c @@ -39,6 +39,8 @@ #include <common.h> #include <watchdog.h> +#include <serial.h> +#include <linux/compiler.h> #include <asm/blackfin.h> #include <asm/mach-common/bits/uart.h> @@ -49,9 +51,9 @@ DECLARE_GLOBAL_DATA_PTR; #include "serial.h" #ifdef CONFIG_DEBUG_SERIAL -uint16_t cached_lsr[256]; -uint16_t cached_rbr[256]; -size_t cache_count; +static uint16_t cached_lsr[256]; +static uint16_t cached_rbr[256]; +static size_t cache_count; /* The LSR is read-to-clear on some parts, so we have to make sure status * bits aren't inadvertently lost when doing various tests. This also @@ -59,68 +61,34 @@ size_t cache_count; * tally of all the status bits. */ static uint16_t uart_lsr_save; -static uint16_t uart_lsr_read(void) +static uint16_t uart_lsr_read(uint32_t uart_base) { - uint16_t lsr = bfin_read16(&pUART->lsr); + uint16_t lsr = bfin_read(&pUART->lsr); uart_lsr_save |= (lsr & (OE|PE|FE|BI)); return lsr | uart_lsr_save; } /* Just do the clear for everyone since it can't hurt. */ -static void uart_lsr_clear(void) +static void uart_lsr_clear(uint32_t uart_base) { uart_lsr_save = 0; - bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1); + bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1); } #else /* When debugging is disabled, we only care about the DR bit, so if other * bits get set/cleared, we don't really care since we don't read them * anyways (and thus anomaly 05000099 is irrelevant). */ -static uint16_t uart_lsr_read(void) +static inline uint16_t uart_lsr_read(uint32_t uart_base) { - return bfin_read16(&pUART->lsr); + return bfin_read(&pUART->lsr); } -static void uart_lsr_clear(void) +static void uart_lsr_clear(uint32_t uart_base) { - bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1); + bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1); } #endif -/* Symbol for our assembly to call. */ -void serial_set_baud(uint32_t baud) -{ - serial_early_set_baud(baud); -} - -/* Symbol for common u-boot code to call. - * Setup the baudrate (brg: baudrate generator). - */ -void serial_setbrg(void) -{ - serial_set_baud(gd->baudrate); -} - -/* Symbol for our assembly to call. */ -void serial_initialize(void) -{ - serial_early_init(); -} - -/* Symbol for common u-boot code to call. */ -int serial_init(void) -{ - serial_initialize(); - serial_setbrg(); - uart_lsr_clear(); -#ifdef CONFIG_DEBUG_SERIAL - cache_count = 0; - memset(cached_lsr, 0x00, sizeof(cached_lsr)); - memset(cached_rbr, 0x00, sizeof(cached_rbr)); -#endif - return 0; -} - -void serial_putc(const char c) +static void uart_putc(uint32_t uart_base, const char c) { /* send a \r for compatibility */ if (c == '\n') @@ -129,36 +97,36 @@ void serial_putc(const char c) WATCHDOG_RESET(); /* wait for the hardware fifo to clear up */ - while (!(uart_lsr_read() & THRE)) + while (!(uart_lsr_read(uart_base) & THRE)) continue; /* queue the character for transmission */ - bfin_write16(&pUART->thr, c); + bfin_write(&pUART->thr, c); SSYNC(); WATCHDOG_RESET(); } -int serial_tstc(void) +static int uart_tstc(uint32_t uart_base) { WATCHDOG_RESET(); - return (uart_lsr_read() & DR) ? 1 : 0; + return (uart_lsr_read(uart_base) & DR) ? 1 : 0; } -int serial_getc(void) +static int uart_getc(uint32_t uart_base) { uint16_t uart_rbr_val; /* wait for data ! */ - while (!serial_tstc()) + while (!uart_tstc(uart_base)) continue; /* grab the new byte */ - uart_rbr_val = bfin_read16(&pUART->rbr); + uart_rbr_val = bfin_read(&pUART->rbr); #ifdef CONFIG_DEBUG_SERIAL /* grab & clear the LSR */ - uint16_t uart_lsr_val = uart_lsr_read(); + uint16_t uart_lsr_val = uart_lsr_read(uart_base); cached_lsr[cache_count] = uart_lsr_val; cached_rbr[cache_count] = uart_rbr_val; @@ -168,23 +136,171 @@ int serial_getc(void) uint16_t dll, dlh; printf("\n[SERIAL ERROR]\n"); ACCESS_LATCH(); - dll = bfin_read16(&pUART->dll); - dlh = bfin_read16(&pUART->dlh); + dll = bfin_read(&pUART->dll); + dlh = bfin_read(&pUART->dlh); ACCESS_PORT_IER(); printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh); do { --cache_count; - printf("\t%3i: RBR=0x%02x LSR=0x%02x\n", cache_count, + printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count, cached_rbr[cache_count], cached_lsr[cache_count]); } while (cache_count > 0); return -1; } #endif - uart_lsr_clear(); + uart_lsr_clear(uart_base); return uart_rbr_val; } +#ifdef CONFIG_SYS_BFIN_UART + +static void uart_puts(uint32_t uart_base, const char *s) +{ + while (*s) + uart_putc(uart_base, *s++); +} + +#define DECL_BFIN_UART(n) \ +static int uart##n##_init(void) \ +{ \ + const unsigned short pins[] = { _P_UART(n, RX), _P_UART(n, TX), 0, }; \ + peripheral_request_list(pins, "bfin-uart"); \ + uart_init(MMR_UART(n)); \ + serial_early_set_baud(MMR_UART(n), gd->baudrate); \ + uart_lsr_clear(MMR_UART(n)); \ + return 0; \ +} \ +\ +static int uart##n##_uninit(void) \ +{ \ + return serial_early_uninit(MMR_UART(n)); \ +} \ +\ +static void uart##n##_setbrg(void) \ +{ \ + serial_early_set_baud(MMR_UART(n), gd->baudrate); \ +} \ +\ +static int uart##n##_getc(void) \ +{ \ + return uart_getc(MMR_UART(n)); \ +} \ +\ +static int uart##n##_tstc(void) \ +{ \ + return uart_tstc(MMR_UART(n)); \ +} \ +\ +static void uart##n##_putc(const char c) \ +{ \ + uart_putc(MMR_UART(n), c); \ +} \ +\ +static void uart##n##_puts(const char *s) \ +{ \ + uart_puts(MMR_UART(n), s); \ +} \ +\ +struct serial_device bfin_serial##n##_device = { \ + .name = "bfin_uart"#n, \ + .init = uart##n##_init, \ + .uninit = uart##n##_uninit, \ + .setbrg = uart##n##_setbrg, \ + .getc = uart##n##_getc, \ + .tstc = uart##n##_tstc, \ + .putc = uart##n##_putc, \ + .puts = uart##n##_puts, \ +}; + +#ifdef UART0_DLL +DECL_BFIN_UART(0) +#endif +#ifdef UART1_DLL +DECL_BFIN_UART(1) +#endif +#ifdef UART2_DLL +DECL_BFIN_UART(2) +#endif +#ifdef UART3_DLL +DECL_BFIN_UART(3) +#endif + +__weak struct serial_device *default_serial_console(void) +{ +#if CONFIG_UART_CONSOLE == 0 + return &bfin_serial0_device; +#elif CONFIG_UART_CONSOLE == 1 + return &bfin_serial1_device; +#elif CONFIG_UART_CONSOLE == 2 + return &bfin_serial2_device; +#elif CONFIG_UART_CONSOLE == 3 + return &bfin_serial3_device; +#endif +} + +void serial_register_bfin_uart(void) +{ +#ifdef UART0_DLL + serial_register(&bfin_serial0_device); +#endif +#ifdef UART1_DLL + serial_register(&bfin_serial1_device); +#endif +#ifdef UART2_DLL + serial_register(&bfin_serial2_device); +#endif +#ifdef UART3_DLL + serial_register(&bfin_serial3_device); +#endif +} + +#else + +/* Symbol for our assembly to call. */ +void serial_set_baud(uint32_t baud) +{ + serial_early_set_baud(UART_DLL, baud); +} + +/* Symbol for common u-boot code to call. + * Setup the baudrate (brg: baudrate generator). + */ +void serial_setbrg(void) +{ + serial_set_baud(gd->baudrate); +} + +/* Symbol for our assembly to call. */ +void serial_initialize(void) +{ + serial_early_init(UART_DLL); +} + +/* Symbol for common u-boot code to call. */ +int serial_init(void) +{ + serial_initialize(); + serial_setbrg(); + uart_lsr_clear(UART_DLL); + return 0; +} + +int serial_tstc(void) +{ + return uart_tstc(UART_DLL); +} + +int serial_getc(void) +{ + return uart_getc(UART_DLL); +} + +void serial_putc(const char c) +{ + uart_putc(UART_DLL, c); +} + void serial_puts(const char *s) { while (*s) @@ -192,3 +308,5 @@ void serial_puts(const char *s) } #endif + +#endif diff --git a/arch/blackfin/cpu/serial.h b/arch/blackfin/cpu/serial.h index 7999a1933..8a076ddc9 100644 --- a/arch/blackfin/cpu/serial.h +++ b/arch/blackfin/cpu/serial.h @@ -82,26 +82,28 @@ struct bfin_mmr_serial { #define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx #define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx) -#define MMR_UART(mmr) _PASTE_UART(CONFIG_UART_CONSOLE, UART, DLL) -#define P_UART(pin) _PASTE_UART(CONFIG_UART_CONSOLE, P_UART, pin) +#define MMR_UART(n) _PASTE_UART(n, UART, DLL) +#define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin) +#define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin) #ifndef UART_DLL -# define UART_DLL MMR_UART(DLL) +# define UART_DLL MMR_UART(CONFIG_UART_CONSOLE) #else +# define UART0_DLL UART_DLL # if CONFIG_UART_CONSOLE != 0 # error CONFIG_UART_CONSOLE must be 0 on parts with only one UART # endif #endif -#define pUART ((volatile struct bfin_mmr_serial *)UART_DLL) +#define pUART ((volatile struct bfin_mmr_serial *)uart_base) #if BFIN_UART_HW_VER == 2 # define ACCESS_LATCH() # define ACCESS_PORT_IER() #else # define ACCESS_LATCH() \ - bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) | DLAB) + bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) | DLAB) # define ACCESS_PORT_IER() \ - bfin_write16(&pUART->lcr, bfin_read16(&pUART->lcr) & ~DLAB) + bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) & ~DLAB) #endif __attribute__((always_inline)) @@ -168,30 +170,47 @@ static inline void serial_do_portmux(void) } __attribute__((always_inline)) -static inline void serial_early_init(void) +static inline int uart_init(uint32_t uart_base) { - /* handle portmux crap on different Blackfins */ - serial_do_portmux(); - /* always enable UART -- avoids anomalies 05000309 and 05000350 */ - bfin_write16(&pUART->gctl, UCEN); + bfin_write(&pUART->gctl, UCEN); /* Set LCR to Word Lengh 8-bit word select */ - bfin_write16(&pUART->lcr, WLS_8); + bfin_write(&pUART->lcr, WLS_8); SSYNC(); + + return 0; } __attribute__((always_inline)) -static inline void serial_early_put_div(uint16_t divisor) +static inline int serial_early_init(uint32_t uart_base) +{ + /* handle portmux crap on different Blackfins */ + serial_do_portmux(); + + return uart_init(uart_base); +} + +__attribute__((always_inline)) +static inline int serial_early_uninit(uint32_t uart_base) +{ + /* disable the UART by clearing UCEN */ + bfin_write(&pUART->gctl, 0); + + return 0; +} + +__attribute__((always_inline)) +static inline void serial_early_put_div(uint32_t uart_base, uint16_t divisor) { /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH(); SSYNC(); /* Program the divisor to get the baud rate we want */ - bfin_write16(&pUART->dll, LOB(divisor)); - bfin_write16(&pUART->dlh, HIB(divisor)); + bfin_write(&pUART->dll, LOB(divisor)); + bfin_write(&pUART->dlh, HIB(divisor)); SSYNC(); /* Clear DLAB in LCR to Access THR RBR IER */ @@ -202,12 +221,14 @@ static inline void serial_early_put_div(uint16_t divisor) __attribute__((always_inline)) static inline uint16_t serial_early_get_div(void) { + uint32_t uart_base = UART_DLL; + /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH(); SSYNC(); - uint8_t dll = bfin_read16(&pUART->dll); - uint8_t dlh = bfin_read16(&pUART->dlh); + uint8_t dll = bfin_read(&pUART->dll); + uint8_t dlh = bfin_read(&pUART->dlh); uint16_t divisor = (dlh << 8) | dll; /* Clear DLAB in LCR to Access THR RBR IER */ @@ -223,13 +244,14 @@ static inline uint16_t serial_early_get_div(void) #endif __attribute__((always_inline)) -static inline void serial_early_set_baud(uint32_t baud) +static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) { /* Translate from baud into divisor in terms of SCLK. The * weird multiplication is to make sure we over sample just * a little rather than under sample the incoming signals. */ - serial_early_put_div((get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230); + serial_early_put_div(uart_base, + (get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230); } #ifndef BFIN_IN_INITCODE @@ -266,16 +288,16 @@ static inline void serial_early_puts(const char *s) */ #ifdef CONFIG_DEBUG_EARLY_SERIAL # define serial_early_puts(str) \ - call _get_pc; \ - jump 1f; \ + .section .rodata; \ + 7: \ .ascii "Early:"; \ .ascii __FILE__; \ .ascii ": "; \ .ascii str; \ .asciz "\n"; \ - .align 4; \ -1: \ - R0 += 2; \ + .previous; \ + R0.L = 7b; \ + R0.H = 7b; \ call _serial_puts; #else # define serial_early_puts(str) diff --git a/arch/blackfin/cpu/start.S b/arch/blackfin/cpu/start.S index 15ecb1e8e..90b4d1ae9 100644 --- a/arch/blackfin/cpu/start.S +++ b/arch/blackfin/cpu/start.S @@ -33,7 +33,6 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mach-common/bits/core.h> -#include <asm/mach-common/bits/dma.h> #include <asm/mach-common/bits/pll.h> #include "serial.h" diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h index 48f793a4c..27034d3d0 100644 --- a/arch/blackfin/include/asm/blackfin_local.h +++ b/arch/blackfin/include/asm/blackfin_local.h @@ -93,65 +93,61 @@ extern void blackfin_dcache_flush_invalidate_range(const void *, const void *); # define NOP_PAD_ANOMALY_05000198 #endif -#define bfin_read8(addr) ({ \ - uint8_t __v; \ +#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \ + u32 __v; \ __asm__ __volatile__( \ NOP_PAD_ANOMALY_05000198 \ - "%0 = b[%1] (z);" \ + "%0 = " #asm_size "[%1]" #asm_ext ";" \ : "=d" (__v) \ : "a" (addr) \ ); \ __v; }) - -#define bfin_read16(addr) ({ \ - uint16_t __v; \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - "%0 = w[%1] (z);" \ - : "=d" (__v) \ - : "a" (addr) \ - ); \ - __v; }) - -#define bfin_read32(addr) ({ \ - uint32_t __v; \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - "%0 = [%1];" \ - : "=d" (__v) \ - : "a" (addr) \ - ); \ - __v; }) - -#define bfin_readPTR(addr) bfin_read32(addr) - -#define bfin_write8(addr, val) \ +#define _bfin_writeX(addr, val, size, asm_size) \ __asm__ __volatile__( \ NOP_PAD_ANOMALY_05000198 \ - "b[%0] = %1;" \ + #asm_size "[%0] = %1;" \ : \ - : "a" (addr), "d" (val) \ + : "a" (addr), "d" ((u##size)(val)) \ : "memory" \ ) -#define bfin_write16(addr, val) \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - "w[%0] = %1;" \ - : \ - : "a" (addr), "d" (val) \ - : "memory" \ - ) +#define bfin_read8(addr) _bfin_readX(addr, 8, b, (z)) +#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z)) +#define bfin_read32(addr) _bfin_readX(addr, 32, , ) +#define bfin_write8(addr, val) _bfin_writeX(addr, val, 8, b) +#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w) +#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, ) -#define bfin_write32(addr, val) \ - __asm__ __volatile__( \ - NOP_PAD_ANOMALY_05000198 \ - "[%0] = %1;" \ - : \ - : "a" (addr), "d" (val) \ - : "memory" \ - ) +#define bfin_read(addr) \ +({ \ + sizeof(*(addr)) == 1 ? bfin_read8(addr) : \ + sizeof(*(addr)) == 2 ? bfin_read16(addr) : \ + sizeof(*(addr)) == 4 ? bfin_read32(addr) : \ + ({ BUG(); 0; }); \ +}) +#define bfin_write(addr, val) \ +do { \ + switch (sizeof(*(addr))) { \ + case 1: bfin_write8(addr, val); break; \ + case 2: bfin_write16(addr, val); break; \ + case 4: bfin_write32(addr, val); break; \ + default: BUG(); \ + } \ +} while (0) +#define bfin_write_or(addr, bits) \ +do { \ + typeof(addr) __addr = (addr); \ + bfin_write(__addr, bfin_read(__addr) | (bits)); \ +} while (0) + +#define bfin_write_and(addr, bits) \ +do { \ + typeof(addr) __addr = (addr); \ + bfin_write(__addr, bfin_read(__addr) & (bits)); \ +} while (0) + +#define bfin_readPTR(addr) bfin_read32(addr) #define bfin_writePTR(addr, val) bfin_write32(addr, val) /* SSYNC implementation for C file */ diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h index 89814cd58..bc3c25215 100644 --- a/arch/blackfin/include/asm/config.h +++ b/arch/blackfin/include/asm/config.h @@ -121,6 +121,9 @@ #ifndef CONFIG_SYS_MEMTEST_END # define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4) #endif +#ifndef CONFIG_SYS_POST_WORD_ADDR +# define CONFIG_SYS_POST_WORD_ADDR (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE - 4) +#endif /* Check to make sure everything fits in external RAM */ #if CONFIG_SYS_MAX_RAM_SIZE && \ diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h index 9c0e5d195..224688fc5 100644 --- a/arch/blackfin/include/asm/gpio.h +++ b/arch/blackfin/include/asm/gpio.h @@ -142,8 +142,10 @@ struct gpio_port_t { #ifdef CONFIG_BFIN_GPIO_TRACK void bfin_gpio_labels(void); +void bfin_gpio_free(unsigned gpio); #else #define bfin_gpio_labels() +#define bfin_gpio_free(gpio) #define bfin_gpio_request(gpio, label) bfin_gpio_request(gpio) #define bfin_special_gpio_request(gpio, label) bfin_special_gpio_request(gpio) #endif @@ -154,7 +156,6 @@ int bfin_special_gpio_request(unsigned gpio, const char *label); #endif int bfin_gpio_request(unsigned gpio, const char *label); -void bfin_gpio_free(unsigned gpio); int bfin_gpio_direction_input(unsigned gpio); int bfin_gpio_direction_output(unsigned gpio, int value); int bfin_gpio_get_value(unsigned gpio); diff --git a/arch/blackfin/include/asm/mach-bf506/anomaly.h b/arch/blackfin/include/asm/mach-bf506/anomaly.h index e76723322..5b3227a8e 100644 --- a/arch/blackfin/include/asm/mach-bf506/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf506/anomaly.h @@ -5,12 +5,13 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: + * - Revision A, 02/18/2011; ADSP-BF504/BF504F/BF506F Blackfin Processor Anomaly List */ #if __SILICON_REVISION__ < 0 @@ -36,8 +37,6 @@ #define ANOMALY_05000310 (1) /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ #define ANOMALY_05000366 (1) -/* Speculative Fetches Can Cause Undesired External FIFO Operations */ -#define ANOMALY_05000416 (1) /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ #define ANOMALY_05000426 (1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ @@ -52,12 +51,28 @@ #define ANOMALY_05000472 (1) /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) +/* SPORT0 Data Transmit Error in Multi-Channel Mode with Internal Clock */ +#define ANOMALY_05000476 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) +/* Disabling ACM During an Ongoing Transfer Can Lead to Undefined ACM Behavior */ +#define ANOMALY_05000478 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* TWI Vbus Minimum Specification Can Be Violated under Certain Conditions */ +#define ANOMALY_05000486 (1) +/* SPI Master Boot Can Fail Under Certain Conditions */ +#define ANOMALY_05000490 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* Maximum Idd-deepsleep Specifications Can Be Exceeded under Certain Conditions */ +#define ANOMALY_05000495 (1) +/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ +#define ANOMALY_05000498 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -109,6 +124,7 @@ #define ANOMALY_05000364 (0) #define ANOMALY_05000371 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000386 (0) #define ANOMALY_05000389 (0) #define ANOMALY_05000400 (0) @@ -123,6 +139,7 @@ #define ANOMALY_05000467 (0) #define ANOMALY_05000474 (0) #define ANOMALY_05000475 (0) +#define ANOMALY_05000480 (0) #define ANOMALY_05000485 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf518/anomaly.h b/arch/blackfin/include/asm/mach-bf518/anomaly.h index 24918c5f7..56383f7cb 100644 --- a/arch/blackfin/include/asm/mach-bf518/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf518/anomaly.h @@ -5,16 +5,15 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List + * - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List */ -/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */ #if __SILICON_REVISION__ < 0 # error will not work on BF518 silicon version #endif @@ -77,19 +76,29 @@ /* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ -#define ANOMALY_05000462 (1) -/* PLL Latches Incorrect Settings During Reset */ -#define ANOMALY_05000469 (1) +#define ANOMALY_05000462 (__SILICON_REVISION__ < 2) /* Incorrect Default MSEL Value in PLL_CTL */ -#define ANOMALY_05000472 (1) +#define ANOMALY_05000472 (__SILICON_REVISION__ < 2) /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL Latches Incorrect Settings During Reset */ +#define ANOMALY_05000482 (__SILICON_REVISION__ < 2) +/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ +#define ANOMALY_05000485 (__SILICON_REVISION__ < 2) +/* SPI Master Boot Can Fail Under Certain Conditions */ +#define ANOMALY_05000490 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ +#define ANOMALY_05000498 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -141,6 +150,7 @@ #define ANOMALY_05000364 (0) #define ANOMALY_05000371 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000386 (0) #define ANOMALY_05000389 (0) #define ANOMALY_05000400 (0) @@ -155,6 +165,6 @@ #define ANOMALY_05000467 (0) #define ANOMALY_05000474 (0) #define ANOMALY_05000475 (0) -#define ANOMALY_05000485 (0) +#define ANOMALY_05000480 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf527/anomaly.h b/arch/blackfin/include/asm/mach-bf527/anomaly.h index 72a63694e..688470611 100644 --- a/arch/blackfin/include/asm/mach-bf527/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf527/anomaly.h @@ -5,14 +5,14 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List - * - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List + * - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List + * - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -57,7 +57,7 @@ /* Incorrect Access of OTP_STATUS During otp_write() Function */ #define ANOMALY_05000328 (_ANOMALY_BF527(< 2)) /* Host DMA Boot Modes Are Not Functional */ -#define ANOMALY_05000330 (__SILICON_REVISION__ < 2) +#define ANOMALY_05000330 (_ANOMALY_BF527(< 2)) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ #define ANOMALY_05000337 (_ANOMALY_BF527(< 2)) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ @@ -135,7 +135,7 @@ /* Incorrect Default Internal Voltage Regulator Setting */ #define ANOMALY_05000410 (_ANOMALY_BF527(< 2)) /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ -#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2)) +#define ANOMALY_05000411 (_ANOMALY_BF526(< 1)) /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ #define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2)) /* DEB2_URGENT Bit Not Functional */ @@ -181,11 +181,11 @@ /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) /* The WURESET Bit in the SYSCR Register is not Functional */ -#define ANOMALY_05000445 (1) -/* USB DMA Mode 1 Short Packet Data Corruption */ +#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0)) +/* USB DMA Short Packet Data Corruption */ #define ANOMALY_05000450 (1) /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ -#define ANOMALY_05000451 (1) +#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0)) /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ #define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0)) /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ @@ -198,19 +198,19 @@ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ #define ANOMALY_05000462 (1) -/* USB Rx DMA hang */ +/* USB Rx DMA Hang */ #define ANOMALY_05000465 (1) /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ #define ANOMALY_05000466 (1) -/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ +/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */ #define ANOMALY_05000467 (1) /* PLL Latches Incorrect Settings During Reset */ #define ANOMALY_05000469 (1) /* Incorrect Default MSEL Value in PLL_CTL */ #define ANOMALY_05000472 (_ANOMALY_BF526(>= 0)) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) @@ -219,11 +219,19 @@ /* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */ #define ANOMALY_05000483 (1) /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ -#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3)) +#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0)) /* The CODEC Zero-Cross Detect Feature is not Functional */ #define ANOMALY_05000487 (1) -/* IFLUSH sucks at life */ +/* SPI Master Boot Can Fail Under Certain Conditions */ +#define ANOMALY_05000490 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ +#define ANOMALY_05000498 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -270,11 +278,13 @@ #define ANOMALY_05000323 (0) #define ANOMALY_05000362 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000400 (0) #define ANOMALY_05000402 (0) #define ANOMALY_05000412 (0) #define ANOMALY_05000447 (0) #define ANOMALY_05000448 (0) #define ANOMALY_05000474 (0) +#define ANOMALY_05000480 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf533/anomaly.h b/arch/blackfin/include/asm/mach-bf533/anomaly.h index 30e0eba22..03f2b4091 100644 --- a/arch/blackfin/include/asm/mach-bf533/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf533/anomaly.h @@ -5,13 +5,13 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List + * - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -152,7 +152,7 @@ #define ANOMALY_05000277 (__SILICON_REVISION__ < 6) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 6) -/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* False Hardware Error when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 6) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 6) @@ -210,18 +210,25 @@ #define ANOMALY_05000462 (1) /* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ #define ANOMALY_05000471 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) -/* These anomalies have been "phased" out of analog.com anomaly sheets and are +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are * here to show running on older silicon just isn't feasible. */ @@ -355,6 +362,7 @@ #define ANOMALY_05000362 (1) #define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000386 (1) #define ANOMALY_05000389 (0) #define ANOMALY_05000412 (0) @@ -369,6 +377,7 @@ #define ANOMALY_05000465 (0) #define ANOMALY_05000467 (0) #define ANOMALY_05000474 (0) +#define ANOMALY_05000480 (0) #define ANOMALY_05000485 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf537/anomaly.h b/arch/blackfin/include/asm/mach-bf537/anomaly.h index d3a29665a..543cd3fb3 100644 --- a/arch/blackfin/include/asm/mach-bf537/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf537/anomaly.h @@ -5,13 +5,13 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List + * - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -44,18 +44,12 @@ #define ANOMALY_05000119 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ -#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */ #define ANOMALY_05000180 (1) -/* Instruction Cache Is Not Functional */ -#define ANOMALY_05000237 (__SILICON_REVISION__ < 2) /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ #define ANOMALY_05000244 (__SILICON_REVISION__ < 3) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) -/* Buffered CLKIN Output Is Disabled by Default */ -#define ANOMALY_05000247 (1) /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */ #define ANOMALY_05000250 (__SILICON_REVISION__ < 3) /* EMAC TX DMA Error After an Early Frame Abort */ @@ -98,7 +92,7 @@ #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2)) /* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */ #define ANOMALY_05000280 (1) -/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* False Hardware Error when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 3) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 3) @@ -162,9 +156,9 @@ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ #define ANOMALY_05000462 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) @@ -172,8 +166,26 @@ #define ANOMALY_05000480 (__SILICON_REVISION__ < 3) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) + +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ + +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ +#define ANOMALY_05000157 (__SILICON_REVISION__ < 2) +/* Instruction Cache Is Not Functional */ +#define ANOMALY_05000237 (__SILICON_REVISION__ < 2) +/* Buffered CLKIN Output Is Disabled by Default */ +#define ANOMALY_05000247 (__SILICON_REVISION__ < 2) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -208,6 +220,7 @@ #define ANOMALY_05000363 (0) #define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000386 (1) #define ANOMALY_05000389 (0) #define ANOMALY_05000400 (0) diff --git a/arch/blackfin/include/asm/mach-bf538/anomaly.h b/arch/blackfin/include/asm/mach-bf538/anomaly.h index 4bc1f4a3d..b6ca99788 100644 --- a/arch/blackfin/include/asm/mach-bf538/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf538/anomaly.h @@ -5,14 +5,14 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List - * - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List + * - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List + * - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -56,25 +56,21 @@ #define ANOMALY_05000229 (1) /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ #define ANOMALY_05000233 (1) -/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ -#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Maximum External Clock Speed for Timers */ #define ANOMALY_05000253 (1) -/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ -#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ #define ANOMALY_05000270 (__SILICON_REVISION__ < 4) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ -#define ANOMALY_05000272 (1) +#define ANOMALY_05000272 (ANOMALY_BF538) /* Writes to Synchronous SDRAM Memory May Be Lost */ #define ANOMALY_05000273 (__SILICON_REVISION__ < 4) /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ #define ANOMALY_05000277 (__SILICON_REVISION__ < 4) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 4) -/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* False Hardware Error when ISR Context Is Not Restored */ #define ANOMALY_05000281 (__SILICON_REVISION__ < 4) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ #define ANOMALY_05000282 (__SILICON_REVISION__ < 4) @@ -102,8 +98,10 @@ #define ANOMALY_05000313 (__SILICON_REVISION__ < 4) /* Killed System MMR Write Completes Erroneously on Next System MMR Access */ #define ANOMALY_05000315 (__SILICON_REVISION__ < 4) +/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */ +#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */ /* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */ -#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4) +#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */ /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ #define ANOMALY_05000355 (__SILICON_REVISION__ < 5) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ @@ -134,16 +132,32 @@ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ #define ANOMALY_05000462 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) + +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ + +/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ +#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) +/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */ +#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -179,6 +193,7 @@ #define ANOMALY_05000363 (0) #define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000386 (1) #define ANOMALY_05000389 (0) #define ANOMALY_05000400 (0) @@ -194,6 +209,7 @@ #define ANOMALY_05000465 (0) #define ANOMALY_05000467 (0) #define ANOMALY_05000474 (0) +#define ANOMALY_05000480 (0) #define ANOMALY_05000485 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf548/anomaly.h b/arch/blackfin/include/asm/mach-bf548/anomaly.h index b9f4ecc95..021fb1977 100644 --- a/arch/blackfin/include/asm/mach-bf548/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf548/anomaly.h @@ -5,13 +5,13 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision J, 06/03/2010; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List + * - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -31,111 +31,37 @@ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */ -#define ANOMALY_05000220 (1) +#define ANOMALY_05000220 (__SILICON_REVISION__ < 4) /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) -/* False Hardware Error Exception when ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) -/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ -#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) -/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (__SILICON_REVISION__ < 1) -/* TWI Slave Boot Mode Is Not Functional */ -#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) /* FIFO Boot Mode Not Functional */ #define ANOMALY_05000325 (__SILICON_REVISION__ < 2) -/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ -#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) -/* Incorrect Access of OTP_STATUS During otp_write() Function */ -#define ANOMALY_05000328 (__SILICON_REVISION__ < 1) -/* Synchronous Burst Flash Boot Mode Is Not Functional */ -#define ANOMALY_05000329 (__SILICON_REVISION__ < 1) -/* Host DMA Boot Modes Are Not Functional */ -#define ANOMALY_05000330 (__SILICON_REVISION__ < 1) -/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ -#define ANOMALY_05000334 (__SILICON_REVISION__ < 1) -/* Inadequate Rotary Debounce Logic Duration */ -#define ANOMALY_05000335 (__SILICON_REVISION__ < 1) -/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ -#define ANOMALY_05000336 (__SILICON_REVISION__ < 1) -/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000337 (__SILICON_REVISION__ < 1) -/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ -#define ANOMALY_05000338 (__SILICON_REVISION__ < 1) -/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ -#define ANOMALY_05000340 (__SILICON_REVISION__ < 1) -/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ -#define ANOMALY_05000344 (__SILICON_REVISION__ < 1) -/* USB Calibration Value Is Not Initialized */ -#define ANOMALY_05000346 (__SILICON_REVISION__ < 1) -/* USB Calibration Value to use */ -#define ANOMALY_05000346_value 0x5411 -/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ -#define ANOMALY_05000347 (__SILICON_REVISION__ < 1) -/* Data Lost when Core Reads SDH Data FIFO */ -#define ANOMALY_05000349 (__SILICON_REVISION__ < 1) -/* PLL Status Register Is Inaccurate */ -#define ANOMALY_05000351 (__SILICON_REVISION__ < 1) /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ -#define ANOMALY_05000353 (__SILICON_REVISION__ < 2) -/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ -#define ANOMALY_05000355 (__SILICON_REVISION__ < 1) -/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ -#define ANOMALY_05000356 (__SILICON_REVISION__ < 1) +/* + * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing + * shows that the fix itself does not cover all cases. + */ +#define ANOMALY_05000353 (1) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ #define ANOMALY_05000357 (1) /* External Memory Read Access Hangs Core With PLL Bypass */ #define ANOMALY_05000360 (1) /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ #define ANOMALY_05000365 (1) -/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */ -#define ANOMALY_05000367 (__SILICON_REVISION__ < 1) /* Addressing Conflict between Boot ROM and Asynchronous Memory */ #define ANOMALY_05000369 (1) -/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */ -#define ANOMALY_05000370 (__SILICON_REVISION__ < 1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (__SILICON_REVISION__ < 2) -/* USB DP/DM Data Pins May Lose State When Entering Hibernate */ -#define ANOMALY_05000372 (__SILICON_REVISION__ < 1) /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ #define ANOMALY_05000378 (__SILICON_REVISION__ < 2) /* 16-Bit NAND FLASH Boot Mode Is Not Functional */ #define ANOMALY_05000379 (1) -/* 8-Bit NAND Flash Boot Mode Not Functional */ -#define ANOMALY_05000382 (__SILICON_REVISION__ < 1) -/* Boot from OTP Memory Not Functional */ -#define ANOMALY_05000385 (__SILICON_REVISION__ < 1) -/* bfrom_SysControl() Firmware Routine Not Functional */ -#define ANOMALY_05000386 (__SILICON_REVISION__ < 1) -/* Programmable Preboot Settings Not Functional */ -#define ANOMALY_05000387 (__SILICON_REVISION__ < 1) -/* CRC32 Checksum Support Not Functional */ -#define ANOMALY_05000388 (__SILICON_REVISION__ < 1) -/* Reset Vector Must Not Be in SDRAM Memory Space */ -#define ANOMALY_05000389 (__SILICON_REVISION__ < 1) -/* Changed Meaning of BCODE Field in SYSCR Register */ -#define ANOMALY_05000390 (__SILICON_REVISION__ < 1) -/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */ -#define ANOMALY_05000391 (__SILICON_REVISION__ < 1) -/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000392 (__SILICON_REVISION__ < 1) -/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000393 (__SILICON_REVISION__ < 1) -/* Log Buffer Not Functional */ -#define ANOMALY_05000394 (__SILICON_REVISION__ < 1) -/* Hook Routine Not Functional */ -#define ANOMALY_05000395 (__SILICON_REVISION__ < 1) -/* Header Indirect Bit Not Functional */ -#define ANOMALY_05000396 (__SILICON_REVISION__ < 1) -/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ -#define ANOMALY_05000397 (__SILICON_REVISION__ < 1) /* Lockbox SESR Disallows Certain User Interrupts */ #define ANOMALY_05000404 (__SILICON_REVISION__ < 2) /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ @@ -157,7 +83,7 @@ /* Speculative Fetches Can Cause Undesired External FIFO Operations */ #define ANOMALY_05000416 (1) /* Multichannel SPORT Channel Misalignment Under Specific Configuration */ -#define ANOMALY_05000425 (1) +#define ANOMALY_05000425 (__SILICON_REVISION__ < 4) /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ #define ANOMALY_05000426 (1) /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ @@ -170,8 +96,6 @@ #define ANOMALY_05000431 (__SILICON_REVISION__ < 3) /* SW Breakpoints Ignored Upon Return From Lockbox Authentication */ #define ANOMALY_05000434 (1) -/* OTP Write Accesses Not Supported */ -#define ANOMALY_05000442 (__SILICON_REVISION__ < 1) /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ #define ANOMALY_05000443 (1) /* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */ @@ -182,34 +106,32 @@ #define ANOMALY_05000448 (__SILICON_REVISION__ == 1) /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ #define ANOMALY_05000449 (__SILICON_REVISION__ == 1) -/* USB DMA Mode 1 Short Packet Data Corruption */ +/* USB DMA Short Packet Data Corruption */ #define ANOMALY_05000450 (1) -/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ -#define ANOMALY_05000452 (__SILICON_REVISION__ < 1) /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ #define ANOMALY_05000456 (1) /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ #define ANOMALY_05000457 (1) /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */ -#define ANOMALY_05000460 (1) +#define ANOMALY_05000460 (__SILICON_REVISION__ < 4) /* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */ -#define ANOMALY_05000462 (1) +#define ANOMALY_05000462 (__SILICON_REVISION__ < 4) /* USB DMA RX Data Corruption */ -#define ANOMALY_05000463 (1) +#define ANOMALY_05000463 (__SILICON_REVISION__ < 4) /* USB TX DMA Hang */ -#define ANOMALY_05000464 (1) -/* USB Rx DMA hang */ +#define ANOMALY_05000464 (__SILICON_REVISION__ < 4) +/* USB Rx DMA Hang */ #define ANOMALY_05000465 (1) /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */ -#define ANOMALY_05000466 (1) -/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ -#define ANOMALY_05000467 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000466 (__SILICON_REVISION__ < 4) +/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */ +#define ANOMALY_05000467 (__SILICON_REVISION__ < 4) +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */ -#define ANOMALY_05000474 (1) +/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */ +#define ANOMALY_05000474 (__SILICON_REVISION__ < 4) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ @@ -219,9 +141,111 @@ /* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */ #define ANOMALY_05000484 (__SILICON_REVISION__ < 3) /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */ -#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2) -/* IFLUSH sucks at life */ +#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4) +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* SPI Master Boot Can Fail Under Certain Conditions */ +#define ANOMALY_05000490 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */ +#define ANOMALY_05000498 (1) +/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */ +#define ANOMALY_05000500 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) +/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */ +#define ANOMALY_05000502 (1) + +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ + +/* False Hardware Error when ISR Context Is Not Restored */ +#define ANOMALY_05000281 (__SILICON_REVISION__ < 1) +/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ +#define ANOMALY_05000304 (__SILICON_REVISION__ < 1) +/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ +#define ANOMALY_05000312 (__SILICON_REVISION__ < 1) +/* TWI Slave Boot Mode Is Not Functional */ +#define ANOMALY_05000324 (__SILICON_REVISION__ < 1) +/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ +#define ANOMALY_05000327 (__SILICON_REVISION__ < 1) +/* Incorrect Access of OTP_STATUS During otp_write() Function */ +#define ANOMALY_05000328 (__SILICON_REVISION__ < 1) +/* Synchronous Burst Flash Boot Mode Is Not Functional */ +#define ANOMALY_05000329 (__SILICON_REVISION__ < 1) +/* Host DMA Boot Modes Are Not Functional */ +#define ANOMALY_05000330 (__SILICON_REVISION__ < 1) +/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ +#define ANOMALY_05000334 (__SILICON_REVISION__ < 1) +/* Inadequate Rotary Debounce Logic Duration */ +#define ANOMALY_05000335 (__SILICON_REVISION__ < 1) +/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */ +#define ANOMALY_05000336 (__SILICON_REVISION__ < 1) +/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ +#define ANOMALY_05000337 (__SILICON_REVISION__ < 1) +/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */ +#define ANOMALY_05000338 (__SILICON_REVISION__ < 1) +/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */ +#define ANOMALY_05000340 (__SILICON_REVISION__ < 1) +/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */ +#define ANOMALY_05000344 (__SILICON_REVISION__ < 1) +/* USB Calibration Value Is Not Initialized */ +#define ANOMALY_05000346 (__SILICON_REVISION__ < 1) +/* USB Calibration Value to use */ +#define ANOMALY_05000346_value 0x5411 +/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ +#define ANOMALY_05000347 (__SILICON_REVISION__ < 1) +/* Data Lost when Core Reads SDH Data FIFO */ +#define ANOMALY_05000349 (__SILICON_REVISION__ < 1) +/* PLL Status Register Is Inaccurate */ +#define ANOMALY_05000351 (__SILICON_REVISION__ < 1) +/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ +#define ANOMALY_05000355 (__SILICON_REVISION__ < 1) +/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ +#define ANOMALY_05000356 (__SILICON_REVISION__ < 1) +/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */ +#define ANOMALY_05000367 (__SILICON_REVISION__ < 1) +/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */ +#define ANOMALY_05000370 (__SILICON_REVISION__ < 1) +/* USB DP/DM Data Pins May Lose State When Entering Hibernate */ +#define ANOMALY_05000372 (__SILICON_REVISION__ < 1) +/* 8-Bit NAND Flash Boot Mode Not Functional */ +#define ANOMALY_05000382 (__SILICON_REVISION__ < 1) +/* Boot from OTP Memory Not Functional */ +#define ANOMALY_05000385 (__SILICON_REVISION__ < 1) +/* bfrom_SysControl() Firmware Routine Not Functional */ +#define ANOMALY_05000386 (__SILICON_REVISION__ < 1) +/* Programmable Preboot Settings Not Functional */ +#define ANOMALY_05000387 (__SILICON_REVISION__ < 1) +/* CRC32 Checksum Support Not Functional */ +#define ANOMALY_05000388 (__SILICON_REVISION__ < 1) +/* Reset Vector Must Not Be in SDRAM Memory Space */ +#define ANOMALY_05000389 (__SILICON_REVISION__ < 1) +/* Changed Meaning of BCODE Field in SYSCR Register */ +#define ANOMALY_05000390 (__SILICON_REVISION__ < 1) +/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */ +#define ANOMALY_05000391 (__SILICON_REVISION__ < 1) +/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000392 (__SILICON_REVISION__ < 1) +/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000393 (__SILICON_REVISION__ < 1) +/* Log Buffer Not Functional */ +#define ANOMALY_05000394 (__SILICON_REVISION__ < 1) +/* Hook Routine Not Functional */ +#define ANOMALY_05000395 (__SILICON_REVISION__ < 1) +/* Header Indirect Bit Not Functional */ +#define ANOMALY_05000396 (__SILICON_REVISION__ < 1) +/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ +#define ANOMALY_05000397 (__SILICON_REVISION__ < 1) +/* OTP Write Accesses Not Supported */ +#define ANOMALY_05000442 (__SILICON_REVISION__ < 1) +/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ +#define ANOMALY_05000452 (__SILICON_REVISION__ < 1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000099 (0) @@ -274,5 +298,6 @@ #define ANOMALY_05000435 (0) #define ANOMALY_05000440 (0) #define ANOMALY_05000475 (0) +#define ANOMALY_05000480 (0) #endif diff --git a/arch/blackfin/include/asm/mach-bf561/anomaly.h b/arch/blackfin/include/asm/mach-bf561/anomaly.h index 9313c27f4..b27173cf0 100644 --- a/arch/blackfin/include/asm/mach-bf561/anomaly.h +++ b/arch/blackfin/include/asm/mach-bf561/anomaly.h @@ -5,13 +5,13 @@ * and can be replaced with that version at any time * DO NOT EDIT THIS FILE * - * Copyright 2004-2010 Analog Devices Inc. + * Copyright 2004-2011 Analog Devices Inc. * Licensed under the ADI BSD license. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: - * - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List + * - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -26,62 +26,16 @@ #define ANOMALY_05000074 (1) /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ #define ANOMALY_05000099 (__SILICON_REVISION__ < 5) -/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ -#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) /* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */ #define ANOMALY_05000120 (1) /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) -/* Erroneous Exception when Enabling Cache */ -#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) /* SIGNBITS Instruction Not Functional under Certain Conditions */ #define ANOMALY_05000127 (1) -/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ -#define ANOMALY_05000134 (__SILICON_REVISION__ < 3) -/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */ -#define ANOMALY_05000135 (__SILICON_REVISION__ < 3) -/* Stall in multi-unit DMA operations */ -#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) -/* Allowing the SPORT RX FIFO to fill will cause an overflow */ -#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) -/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ -#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) -/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ -#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) -/* DMA and TESTSET conflict when both are accessing external memory */ -#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) -/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ -#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) -/* MDMA may lose the first few words of a descriptor chain */ -#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) -/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ -#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) /* IMDMA S1/D1 Channel May Stall */ #define ANOMALY_05000149 (1) -/* DMA engine may lose data due to incorrect handshaking */ -#define ANOMALY_05000150 (__SILICON_REVISION__ < 3) -/* DMA stalls when all three controllers read data from the same source */ -#define ANOMALY_05000151 (__SILICON_REVISION__ < 3) -/* Execution stall when executing in L2 and doing external accesses */ -#define ANOMALY_05000152 (__SILICON_REVISION__ < 3) -/* Frame Delay in SPORT Multichannel Mode */ -#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) -/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ -#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) /* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */ #define ANOMALY_05000156 (__SILICON_REVISION__ < 4) -/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ -#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) -/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ -#define ANOMALY_05000159 (__SILICON_REVISION__ < 3) -/* A read from external memory may return a wrong value with data cache enabled */ -#define ANOMALY_05000160 (__SILICON_REVISION__ < 3) -/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */ -#define ANOMALY_05000161 (__SILICON_REVISION__ < 3) -/* DMEM_CONTROL<12> is not set on Reset */ -#define ANOMALY_05000162 (__SILICON_REVISION__ < 3) -/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ -#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */ #define ANOMALY_05000166 (1) /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ @@ -92,10 +46,6 @@ #define ANOMALY_05000169 (__SILICON_REVISION__ < 5) /* Boot-ROM Modifies SICA_IWRx Wakeup Registers */ #define ANOMALY_05000171 (__SILICON_REVISION__ < 5) -/* DSPID register values incorrect */ -#define ANOMALY_05000172 (__SILICON_REVISION__ < 3) -/* DMA vs Core accesses to external memory */ -#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) /* Cache Fill Buffer Data lost */ #define ANOMALY_05000174 (__SILICON_REVISION__ < 5) /* Overlapping Sequencer and Memory Stalls */ @@ -124,8 +74,6 @@ #define ANOMALY_05000189 (__SILICON_REVISION__ < 5) /* PPI Not Functional at Core Voltage < 1Volt */ #define ANOMALY_05000190 (1) -/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ -#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */ #define ANOMALY_05000193 (__SILICON_REVISION__ < 5) /* Restarting SPORT in Specific Modes May Cause Data Corruption */ @@ -213,10 +161,10 @@ /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ #define ANOMALY_05000276 (__SILICON_REVISION__ < 5) /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ -#define ANOMALY_05000277 (__SILICON_REVISION__ < 3) +#define ANOMALY_05000277 (__SILICON_REVISION__ < 5) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) -/* False Hardware Error Exception when ISR Context Is Not Restored */ +/* False Hardware Error when ISR Context Is Not Restored */ /* Temporarily walk around for bug 5423 till this issue is confirmed by * official anomaly document. It looks 05000281 still exists on bf561 * v0.5. @@ -270,8 +218,6 @@ #define ANOMALY_05000366 (1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ #define ANOMALY_05000371 (1) -/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ == 4) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) /* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ @@ -294,16 +240,82 @@ #define ANOMALY_05000462 (1) /* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */ #define ANOMALY_05000471 (1) -/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */ #define ANOMALY_05000473 (1) -/* Possible Lockup Condition whem Modifying PLL from External Memory */ +/* Possible Lockup Condition when Modifying PLL from External Memory */ #define ANOMALY_05000475 (1) /* TESTSET Instruction Cannot Be Interrupted */ #define ANOMALY_05000477 (1) /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */ #define ANOMALY_05000481 (1) -/* IFLUSH sucks at life */ +/* PLL May Latch Incorrect Values Coming Out of Reset */ +#define ANOMALY_05000489 (1) +/* Instruction Memory Stalls Can Cause IFLUSH to Fail */ #define ANOMALY_05000491 (1) +/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */ +#define ANOMALY_05000494 (1) +/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */ +#define ANOMALY_05000501 (1) + +/* + * These anomalies have been "phased" out of analog.com anomaly sheets and are + * here to show running on older silicon just isn't feasible. + */ + +/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */ +#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) +/* Erroneous Exception when Enabling Cache */ +#define ANOMALY_05000125 (__SILICON_REVISION__ < 3) +/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */ +#define ANOMALY_05000134 (__SILICON_REVISION__ < 3) +/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */ +#define ANOMALY_05000135 (__SILICON_REVISION__ < 3) +/* Stall in multi-unit DMA operations */ +#define ANOMALY_05000136 (__SILICON_REVISION__ < 3) +/* Allowing the SPORT RX FIFO to fill will cause an overflow */ +#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) +/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */ +#define ANOMALY_05000141 (__SILICON_REVISION__ < 3) +/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */ +#define ANOMALY_05000142 (__SILICON_REVISION__ < 3) +/* DMA and TESTSET conflict when both are accessing external memory */ +#define ANOMALY_05000144 (__SILICON_REVISION__ < 3) +/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */ +#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) +/* MDMA may lose the first few words of a descriptor chain */ +#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) +/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ +#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) +/* DMA engine may lose data due to incorrect handshaking */ +#define ANOMALY_05000150 (__SILICON_REVISION__ < 3) +/* DMA stalls when all three controllers read data from the same source */ +#define ANOMALY_05000151 (__SILICON_REVISION__ < 3) +/* Execution stall when executing in L2 and doing external accesses */ +#define ANOMALY_05000152 (__SILICON_REVISION__ < 3) +/* Frame Delay in SPORT Multichannel Mode */ +#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) +/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ +#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) +/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */ +#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) +/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ +#define ANOMALY_05000159 (__SILICON_REVISION__ < 3) +/* A read from external memory may return a wrong value with data cache enabled */ +#define ANOMALY_05000160 (__SILICON_REVISION__ < 3) +/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */ +#define ANOMALY_05000161 (__SILICON_REVISION__ < 3) +/* DMEM_CONTROL<12> is not set on Reset */ +#define ANOMALY_05000162 (__SILICON_REVISION__ < 3) +/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */ +#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) +/* DSPID register values incorrect */ +#define ANOMALY_05000172 (__SILICON_REVISION__ < 3) +/* DMA vs Core accesses to external memory */ +#define ANOMALY_05000173 (__SILICON_REVISION__ < 3) +/* PPI does not invert the Driving PPICLK edge in Transmit Modes */ +#define ANOMALY_05000191 (__SILICON_REVISION__ < 3) +/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ +#define ANOMALY_05000402 (__SILICON_REVISION__ == 4) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000119 (0) @@ -316,6 +328,7 @@ #define ANOMALY_05000353 (1) #define ANOMALY_05000364 (0) #define ANOMALY_05000380 (0) +#define ANOMALY_05000383 (0) #define ANOMALY_05000386 (1) #define ANOMALY_05000389 (0) #define ANOMALY_05000400 (0) @@ -330,6 +343,7 @@ #define ANOMALY_05000465 (0) #define ANOMALY_05000467 (0) #define ANOMALY_05000474 (0) +#define ANOMALY_05000480 (0) #define ANOMALY_05000485 (0) #endif diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h index b17207fbd..300ef44fd 100644 --- a/arch/blackfin/include/asm/portmux.h +++ b/arch/blackfin/include/asm/portmux.h @@ -22,11 +22,15 @@ #define peripheral_request_list(per, label) peripheral_request_list(per) #endif +#ifndef __ASSEMBLY__ + int peripheral_request(unsigned short per, const char *label); void peripheral_free(unsigned short per); int peripheral_request_list(const unsigned short per[], const char *label); void peripheral_free_list(const unsigned short per[]); +#endif + #include <asm/blackfin.h> #ifndef P_SPORT2_TFS diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 362b8c47e..bfdb586b3 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -12,11 +12,11 @@ #include <common.h> #include <command.h> #include <stdio_dev.h> +#include <serial.h> #include <environment.h> #include <malloc.h> #include <mmc.h> #include <net.h> -#include <timestamp.h> #include <status_led.h> #include <version.h> @@ -39,8 +39,6 @@ int post_flag; DECLARE_GLOBAL_DATA_PTR; -const char version_string[] = U_BOOT_VERSION " ("U_BOOT_DATE" - "U_BOOT_TIME")"; - __attribute__((always_inline)) static inline void serial_early_puts(const char *s) { @@ -52,7 +50,7 @@ static inline void serial_early_puts(const char *s) static int display_banner(void) { - printf("\n\n%s\n\n", version_string); + display_options(); printf("CPU: ADSP %s " "(Detected Rev: 0.%d) " "(%s boot)\n", @@ -265,6 +263,9 @@ void board_init_f(ulong bootflag) init_baudrate(); serial_early_puts("Serial init\n"); serial_init(); +#ifdef CONFIG_SERIAL_MULTI + serial_initialize(); +#endif serial_early_puts("Console init flash\n"); console_init_f(); serial_early_puts("End of early debugging\n"); diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S index d09d49274..c5096a80c 100644 --- a/arch/m68k/cpu/mcf5227x/start.S +++ b/arch/m68k/cpu/mcf5227x/start.S @@ -23,7 +23,6 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> #include "version.h" #include <asm/cache.h> @@ -508,7 +507,5 @@ _int_handler: .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S index a726b5984..e6a69ab47 100644 --- a/arch/m68k/cpu/mcf523x/start.S +++ b/arch/m68k/cpu/mcf523x/start.S @@ -23,7 +23,6 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> #include "version.h" #include <asm/cache.h> @@ -270,7 +269,5 @@ _int_handler: .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S index f0cfa6ffe..ee17792cb 100644 --- a/arch/m68k/cpu/mcf52x2/start.S +++ b/arch/m68k/cpu/mcf52x2/start.S @@ -23,7 +23,6 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> #include "version.h" #include <asm/cache.h> @@ -330,7 +329,5 @@ _int_handler: .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S index 53ac471a4..fe98d7647 100644 --- a/arch/m68k/cpu/mcf532x/start.S +++ b/arch/m68k/cpu/mcf532x/start.S @@ -26,7 +26,6 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> #include "version.h" #include <asm/cache.h> @@ -283,7 +282,5 @@ _int_handler: /*------------------------------------------------------------------------------*/ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index 5255f374d..99060141d 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -23,7 +23,6 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> #include "version.h" #include <asm/cache.h> @@ -540,7 +539,5 @@ _int_handler: .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S index e30923fac..ec65cae3d 100644 --- a/arch/m68k/cpu/mcf547x_8x/start.S +++ b/arch/m68k/cpu/mcf547x_8x/start.S @@ -23,7 +23,6 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> #include "version.h" #include <asm/cache.h> @@ -277,7 +276,5 @@ _int_handler: .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 4 diff --git a/arch/m68k/include/asm/fec.h b/arch/m68k/include/asm/fec.h index cecec59ff..e8cea45ed 100644 --- a/arch/m68k/include/asm/fec.h +++ b/arch/m68k/include/asm/fec.h @@ -39,7 +39,7 @@ typedef struct cpm_buf_desc { uint cbd_bufaddr; /* Buffer address in host memory */ } cbd_t; -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index c5f7ac473..d97543b2d 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -27,7 +27,6 @@ #include <common.h> #include <command.h> #include <malloc.h> -#include <timestamp.h> #include <version.h> #include <watchdog.h> #include <stdio_dev.h> @@ -35,8 +34,6 @@ DECLARE_GLOBAL_DATA_PTR; -const char version_string[] = U_BOOT_VERSION " ("U_BOOT_DATE" - "U_BOOT_TIME")"; - #ifdef CONFIG_SYS_GPIO_0 extern int gpio_init (void); #endif diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 5d7467d02..9c1b2f76d 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -27,6 +27,10 @@ #include <asm/regdef.h> #include <asm/mipsregs.h> +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + /* * For the moment disable interrupts, mark the kernel mode and * set ST0_KX so that the CPU does not spit fire when using @@ -64,9 +68,16 @@ _start: RVECENT(reset,0) # U-boot entry point RVECENT(reset,1) # software reboot -#ifdef CONFIG_INCA_IP - .word INFINEON_EBU_BOOTCFG # EBU init code, fetched during - .word 0x00000000 # booting phase of the flash +#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG + /* + * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to + * access external NOR flashes. If the board boots from NOR flash the + * internal BootROM does a blind read at address 0xB0000010 to read the + * initial configuration for that EBU in order to access the flash + * device with correct parameters. This config option is board-specific. + */ + .word CONFIG_SYS_XWAY_EBU_BOOTCFG + .word 0x00000000 #else RVECENT(romReserved,2) #endif @@ -242,7 +253,7 @@ reset: nop /* ... and enable them */ - li t0, CONF_CM_CACHABLE_NONCOHERENT + li t0, CONFIG_SYS_MIPS_CACHE_MODE mtc0 t0, CP0_CONFIG #endif diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index 623c4d7f0..4f85bbdab 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -25,7 +25,6 @@ #include <command.h> #include <malloc.h> #include <stdio_dev.h> -#include <timestamp.h> #include <version.h> #include <net.h> #include <environment.h> @@ -50,9 +49,6 @@ extern ulong uboot_end; ulong monitor_flash_len; -const char version_string[] = - U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"; - static char *failed = "*** failed ***\n"; /* diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index bf5d67249..0f4ab286b 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -23,7 +23,6 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> #include <version.h> /************************************************************************* @@ -196,14 +195,8 @@ dly_clks: bge r4, r0, dly_clks ret - -#if !defined(CONFIG_IDENT_STRING) -#define CONFIG_IDENT_STRING "" -#endif .data .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" diff --git a/arch/powerpc/cpu/74xx_7xx/start.S b/arch/powerpc/cpu/74xx_7xx/start.S index f6011fcaa..75fb77389 100644 --- a/arch/powerpc/cpu/74xx_7xx/start.S +++ b/arch/powerpc/cpu/74xx_7xx/start.S @@ -35,7 +35,6 @@ #include <asm-offsets.h> #include <config.h> #include <74xx_7xx.h> -#include <timestamp.h> #include <version.h> #include <ppc_asm.tmpl> @@ -52,10 +51,6 @@ #include <galileo/gt64260R.h> #endif -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -89,9 +84,7 @@ .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" . = EXC_OFF_SYS_RESET .globl _start diff --git a/arch/powerpc/cpu/mpc512x/start.S b/arch/powerpc/cpu/mpc512x/start.S index 9c2e4885d..ed362d87a 100644 --- a/arch/powerpc/cpu/mpc512x/start.S +++ b/arch/powerpc/cpu/mpc512x/start.S @@ -31,7 +31,9 @@ #include <asm-offsets.h> #include <config.h> -#include <timestamp.h> +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "MPC512X" +#endif #include <version.h> #define CONFIG_521X 1 /* needed for Linux kernel header files*/ @@ -46,10 +48,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "MPC512X" -#endif - /* * Floating Point enable, Machine Check and Recoverable Interr. */ @@ -89,9 +87,7 @@ .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii " ", CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" /* * Vector Table diff --git a/arch/powerpc/cpu/mpc5xx/start.S b/arch/powerpc/cpu/mpc5xx/start.S index cc11c8fc5..cc4c33ebb 100644 --- a/arch/powerpc/cpu/mpc5xx/start.S +++ b/arch/powerpc/cpu/mpc5xx/start.S @@ -33,7 +33,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc5xx.h> -#include <timestamp.h> #include <version.h> #define CONFIG_5xx 1 /* needed for Linux kernel header files */ @@ -46,10 +45,6 @@ #include <asm/processor.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* We don't have a MMU. */ #undef MSR_KERNEL @@ -82,9 +77,7 @@ .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" . = EXC_OFF_SYS_RESET .globl _start diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S index 192aa506a..51cc4e2a1 100644 --- a/arch/powerpc/cpu/mpc5xxx/start.S +++ b/arch/powerpc/cpu/mpc5xxx/start.S @@ -28,7 +28,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc5xxx.h> -#include <timestamp.h> #include <version.h> #define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */ @@ -41,10 +40,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -80,9 +75,7 @@ .data .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" /* * Exception vectors diff --git a/arch/powerpc/cpu/mpc8220/start.S b/arch/powerpc/cpu/mpc8220/start.S index 300b35c0c..a1a2dc5ac 100644 --- a/arch/powerpc/cpu/mpc8220/start.S +++ b/arch/powerpc/cpu/mpc8220/start.S @@ -28,7 +28,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc8220.h> -#include <timestamp.h> #include <version.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ @@ -40,10 +39,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -79,9 +74,7 @@ .data .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" /* * Exception vectors diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S index fc4e922d6..70db73e15 100644 --- a/arch/powerpc/cpu/mpc824x/start.S +++ b/arch/powerpc/cpu/mpc824x/start.S @@ -40,7 +40,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc824x.h> -#include <timestamp.h> #include <version.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ @@ -52,10 +51,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -92,9 +87,7 @@ .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" . = EXC_OFF_SYS_RESET .globl _start diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S index 702546eec..3299d7292 100644 --- a/arch/powerpc/cpu/mpc8260/start.S +++ b/arch/powerpc/cpu/mpc8260/start.S @@ -28,7 +28,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc8260.h> -#include <timestamp.h> #include <version.h> #define CONFIG_8260 1 /* needed for Linux kernel header files */ @@ -41,10 +40,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -87,9 +82,7 @@ .data .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" /* * Hard Reset Configuration Word (HRCW) table diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 7e60315c3..b70b4ca12 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -30,7 +30,9 @@ #include <asm-offsets.h> #include <config.h> #include <mpc83xx.h> -#include <timestamp.h> +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "MPC83XX" +#endif #include <version.h> #define CONFIG_83XX 1 /* needed for Linux kernel header files*/ @@ -43,10 +45,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "MPC83XX" -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -107,9 +105,7 @@ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii " ", CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 2 diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 8a0a8e95e..7026bca60 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -78,8 +78,8 @@ COBJS-$(CONFIG_PCI) += pci.o COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o # various SoC specific assignments -COBJS-$(CONFIG_PPC_P2040) += p2040_ids.o -COBJS-$(CONFIG_PPC_P2041) += p2040_ids.o +COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o +COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o @@ -111,7 +111,7 @@ COBJS-$(CONFIG_P1024) += p1021_serdes.o COBJS-$(CONFIG_P1025) += p1021_serdes.o COBJS-$(CONFIG_P2010) += p2020_serdes.o COBJS-$(CONFIG_P2020) += p2020_serdes.o -COBJS-$(CONFIG_PPC_P2040) += p2040_serdes.o +COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index ce59c2580..22fa4615c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -46,7 +46,6 @@ int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; - uint fam; uint ver; uint major, minor; struct cpu_type *cpu; @@ -94,30 +93,25 @@ int checkcpu (void) printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); - fam = PVR_FAM(pvr); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); - if (PVR_FAM(PVR_85xx)) { - switch(PVR_MEM(pvr)) { - case 0x1: - case 0x2: - puts("E500"); - break; - case 0x3: - puts("E500MC"); - break; - case 0x4: - puts("E5500"); - break; - default: - puts("Unknown"); - break; - } - } else { + switch(ver) { + case PVR_VER_E500_V1: + case PVR_VER_E500_V2: + puts("E500"); + break; + case PVR_VER_E500MC: + puts("E500MC"); + break; + case PVR_VER_E5500: + puts("E5500"); + break; + default: puts("Unknown"); + break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); @@ -358,7 +352,7 @@ phys_size_t initdram(int board_type) lbc_sdram_init(); #endif - puts("DDR: "); + debug("DDR: "); return dram_size; } #endif /* CONFIG_SYS_RAMBOOT */ diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index b3da970d4..6aca166a9 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -222,6 +222,10 @@ static void corenet_tb_init(void) void cpu_init_f (void) { extern void m8560_cpm_reset (void); +#ifdef CONFIG_SYS_DCSRBAR_PHYS + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif + #ifdef CONFIG_MPC8548 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); uint svr = get_svr(); @@ -262,6 +266,13 @@ void cpu_init_f (void) /* Invalidate the CPC before DDR gets enabled */ invalidate_cpc(); + + #ifdef CONFIG_SYS_DCSRBAR_PHYS + /* set DCSRCR so that DCSR space is 1G */ + setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); + in_be32(&gur->dcsrcr); +#endif + } /* Implement a dummy function for those platforms w/o SERDES */ @@ -381,6 +392,12 @@ int cpu_init_r(void) puts("enabled\n"); } #elif defined(CONFIG_BACKSIDE_L2_CACHE) + if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || + (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) { + puts("N/A\n"); + goto skip_l2; + } + u32 l2cfg0 = mfspr(SPRN_L2CFG0); /* invalidate the L2 cache */ @@ -401,6 +418,8 @@ int cpu_init_r(void) ; printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); } + +skip_l2: #else puts("disabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 812bb3f87..8f13cd8eb 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -228,6 +228,12 @@ static inline void ft_fixup_l2cache(void *blob) u32 *ph; u32 l2cfg0 = mfspr(SPRN_L2CFG0); u32 size, line_size, num_ways, num_sets; + int has_l2 = 1; + + /* P2040/P2040E has no L2, so dont set any L2 props */ + if ((SVR_SOC_VER(get_svr()) == SVR_P2040) || + (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) + has_l2 = 0; size = (l2cfg0 & 0x3fff) * 64 * 1024; num_ways = ((l2cfg0 >> 14) & 0x1f) + 1; @@ -250,21 +256,22 @@ static inline void ft_fixup_l2cache(void *blob) goto next; } + if (has_l2) { #ifdef CONFIG_SYS_CACHE_STASHING - { u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); if (reg) fdt_setprop_cell(blob, l2_off, "cache-stash-id", (*reg * 2) + 32 + 1); - } #endif - fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); - fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size); - fdt_setprop_cell(blob, l2_off, "cache-size", size); - fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); - fdt_setprop_cell(blob, l2_off, "cache-level", 2); - fdt_setprop(blob, l2_off, "compatible", "cache", 6); + fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, l2_off, "cache-block-size", + line_size); + fdt_setprop_cell(blob, l2_off, "cache-size", size); + fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets); + fdt_setprop_cell(blob, l2_off, "cache-level", 2); + fdt_setprop(blob, l2_off, "compatible", "cache", 6); + } if (l3_off < 0) { ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0); @@ -628,4 +635,79 @@ void ft_cpu_setup(void *blob, bd_t *bd) */ do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer", "timer-frequency", gd->bus_clk/2, 1); + + do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", + "clock_freq", gd->bus_clk, 1); +} + +/* + * For some CCSR devices, we only have the virtual address, not the physical + * address. This is because we map CCSR as a whole, so we typically don't need + * a macro for the physical address of any device within CCSR. In this case, + * we calculate the physical address of that device using it's the difference + * between the virtual address of the device and the virtual address of the + * beginning of CCSR. + */ +#define CCSR_VIRT_TO_PHYS(x) \ + (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) + +/* + * Verify the device tree + * + * This function compares several CONFIG_xxx macros that contain physical + * addresses with the corresponding nodes in the device tree, to see if + * the physical addresses are all correct. For example, if + * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address + * of the first UART. We convert this to a physical address and compare + * that with the physical address of the first ns16550-compatible node + * in the device tree. If they don't match, then we display a warning. + * + * Returns 1 on success, 0 on failure + */ +int ft_verify_fdt(void *fdt) +{ + uint64_t ccsr = 0; + int aliases; + int off; + + /* First check the CCSR base address */ + off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4); + if (off > 0) + ccsr = fdt_get_base_address(fdt, off); + + if (!ccsr) { + printf("Warning: could not determine base CCSR address in " + "device tree\n"); + /* No point in checking anything else */ + return 0; + } + + if (ccsr != CONFIG_SYS_CCSRBAR_PHYS) { + printf("Warning: U-Boot configured CCSR at address %llx,\n" + "but the device tree has it at %llx\n", + (uint64_t) CONFIG_SYS_CCSRBAR_PHYS, ccsr); + /* No point in checking anything else */ + return 0; + } + + /* + * Get the 'aliases' node. If there isn't one, then there's nothing + * left to do. + */ + aliases = fdt_path_offset(fdt, "/aliases"); + if (aliases > 0) { +#ifdef CONFIG_SYS_NS16550_COM1 + if (!fdt_verify_alias_address(fdt, aliases, "serial0", + CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1))) + return 0; +#endif + +#ifdef CONFIG_SYS_NS16550_COM2 + if (!fdt_verify_alias_address(fdt, aliases, "serial1", + CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2))) + return 0; +#endif + } + + return 1; } diff --git a/arch/powerpc/cpu/mpc85xx/p2040_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 112ea56cd..112ea56cd 100644 --- a/arch/powerpc/cpu/mpc85xx/p2040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c diff --git a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c index 83bc82fee..f68f28191 100644 --- a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c @@ -37,8 +37,8 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, [0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, - PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, - NONE, NONE, NONE, NONE, NONE, NONE, }, + PCIE2, PCIE2, PCIE2, NONE, NONE, XAUI_FM1, XAUI_FM1, + XAUI_FM1, XAUI_FM1, NONE, NONE, NONE, NONE, }, [0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, NONE, NONE, }, @@ -53,8 +53,8 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, [0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3, - SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, NONE, - NONE, NONE, NONE, NONE, NONE, }, + SGMII_FM1_DTSEC4, NONE, NONE, XAUI_FM1, XAUI_FM1, XAUI_FM1, + XAUI_FM1, NONE, NONE, NONE, NONE, }, [0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2, PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, }, @@ -68,19 +68,35 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { enum srds_prtcl serdes_get_prtcl(int cfg, int lane) { + enum srds_prtcl prtcl; + u32 svr = get_svr(); + u32 ver = SVR_SOC_VER(svr); + if (!serdes_lane_enabled(lane)) return NONE; - return serdes_cfg_tbl[cfg][lane]; + prtcl = serdes_cfg_tbl[cfg][lane]; + + /* P2040[e] does not support XAUI */ + if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) + prtcl = NONE; + + return prtcl; } int is_serdes_prtcl_valid(u32 prtcl) { int i; + u32 svr = get_svr(); + u32 ver = SVR_SOC_VER(svr); if (prtcl > ARRAY_SIZE(serdes_cfg_tbl)) return 0; + /* P2040[e] does not support XAUI */ + if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1)) + return 0; + for (i = 0; i < SRDS_MAX_LANES; i++) { if (serdes_cfg_tbl[prtcl][i] != NONE) return 1; diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index 56a853ee5..6678ed411 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * Kumar Gala <kumar.gala@freescale.com> * * See file CREDITS for list of people who contributed to this @@ -144,6 +144,18 @@ __secondary_start_page: #endif #ifdef CONFIG_BACKSIDE_L2_CACHE + /* skip L2 setup on P2040/P2040E as they have no L2 */ + mfspr r2,SPRN_SVR + lis r3,SVR_P2040@h + ori r3,r3,SVR_P2040@l + cmpw r2,r3 + beq 3f + + lis r3,SVR_P2040_E@h + ori r3,r3,SVR_P2040_E@l + cmpw r2,r3 + beq 3f + /* Enable/invalidate the L2 cache */ msync lis r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h @@ -169,6 +181,7 @@ __secondary_start_page: andis. r1,r3,L2CSR0_L2E@h beq 2b #endif +3: #define EPAPR_MAGIC (0x45504150) #define ENTRY_ADDR_UPPER 0 diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 57774933a..878a3d67e 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -31,7 +31,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc85xx.h> -#include <timestamp.h> #include <version.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ @@ -42,10 +41,6 @@ #include <asm/cache.h> #include <asm/mmu.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - #undef MSR_KERNEL #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ @@ -399,9 +394,7 @@ _start: .long 0x27051956 /* U-BOOT Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .align 4 .globl _start_cont @@ -683,6 +676,8 @@ mck_return: /* Cache functions. */ +.globl flush_icache +flush_icache: .globl invalidate_icache invalidate_icache: mfspr r0,L1CSR1 diff --git a/arch/powerpc/cpu/mpc86xx/start.S b/arch/powerpc/cpu/mpc86xx/start.S index 3e3c21eef..32896d49e 100644 --- a/arch/powerpc/cpu/mpc86xx/start.S +++ b/arch/powerpc/cpu/mpc86xx/start.S @@ -33,7 +33,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc86xx.h> -#include <timestamp.h> #include <version.h> #include <ppc_asm.tmpl> @@ -43,10 +42,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions */ @@ -78,9 +73,7 @@ .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" . = EXC_OFF_SYS_RESET .globl _start diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index fe3daa2b9..ebca3acba 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -40,7 +40,6 @@ #include <asm-offsets.h> #include <config.h> #include <mpc8xx.h> -#include <timestamp.h> #include <version.h> #define CONFIG_8xx 1 /* needed for Linux kernel header files */ @@ -53,10 +52,6 @@ #include <asm/mmu.h> #include <asm/u-boot.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - /* We don't want the MMU yet. */ #undef MSR_KERNEL @@ -89,9 +84,7 @@ .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" . = EXC_OFF_SYS_RESET .globl _start diff --git a/arch/powerpc/cpu/mpc8xx/video.c b/arch/powerpc/cpu/mpc8xx/video.c index c79c499b6..7725c67b4 100644 --- a/arch/powerpc/cpu/mpc8xx/video.c +++ b/arch/powerpc/cpu/mpc8xx/video.c @@ -33,7 +33,6 @@ #include <common.h> #include <config.h> #include <version.h> -#include <timestamp.h> #include <i2c.h> #include <linux/types.h> #include <stdio_dev.h> diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index d9e3e7ee1..285051d96 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -30,9 +30,8 @@ #include <asm/fsl_serdes.h> #include <phy.h> #include <hwconfig.h> -#ifdef CONFIG_HAS_FSL_DR_USB -#include <usb.h> -#endif + +#define FSL_MAX_NUM_USB_CTRLS 2 #if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) static int ft_del_cpuhandle(void *blob, int cpuhandle) @@ -135,7 +134,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) char str[5]; int i, j; - for (i = 1; i <= USB_MAX_DEVICE; i++) { + for (i = 1; i <= FSL_MAX_NUM_USB_CTRLS; i++) { int mode_idx = -1, phy_idx = -1; sprintf(str, "%s%d", "usb", i); if (hwconfig(str)) { @@ -163,8 +162,6 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) usb1_defined = 1; if (mode_idx < 0 && phy_idx < 0) printf("WARNING: invalid phy or mode\n"); - } else { - break; } } if (!usb1_defined) { diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index b43e22c8f..3b0e3644a 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -68,7 +68,6 @@ #include <asm-offsets.h> #include <config.h> #include <asm/ppc4xx.h> -#include <timestamp.h> #include <version.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ @@ -80,10 +79,6 @@ #include <asm/mmu.h> #include <asm/ppc4xx-isram.h> -#ifndef CONFIG_IDENT_STRING -#define CONFIG_IDENT_STRING "" -#endif - #ifdef CONFIG_SYS_INIT_DCACHE_CS # if (CONFIG_SYS_INIT_DCACHE_CS == 0) # define PBxAP PB1AP @@ -549,9 +544,7 @@ tlbnx2: addi r4,r4,1 /* Next TLB */ .long 0x27051956 /* U-Boot Magic Number */ .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" . = EXC_OFF_SYS_RESET .globl _start_of_vectors diff --git a/arch/powerpc/include/asm/cpm_8260.h b/arch/powerpc/include/asm/cpm_8260.h index 8302404ab..6a4a51a9a 100644 --- a/arch/powerpc/include/asm/cpm_8260.h +++ b/arch/powerpc/include/asm/cpm_8260.h @@ -117,7 +117,7 @@ typedef struct cpm_buf_desc { uint cbd_bufaddr; /* Buffer address in host memory */ } cbd_t; -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ diff --git a/arch/powerpc/include/asm/cpm_85xx.h b/arch/powerpc/include/asm/cpm_85xx.h index a74a3a115..1681ecd50 100644 --- a/arch/powerpc/include/asm/cpm_85xx.h +++ b/arch/powerpc/include/asm/cpm_85xx.h @@ -110,7 +110,7 @@ typedef struct cpm_buf_desc { uint cbd_bufaddr; /* Buffer address in host memory */ } cbd_t; -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 267a9401b..6aaade076 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1759,7 +1759,8 @@ typedef struct ccsr_gur { u32 cgencrl; /* Core general control */ u8 res31[184]; u32 sriopstecr; /* SRIO prescaler timer enable control */ - u8 res32[1788]; + u32 dcsrcr; /* DCSR Control register */ + u8 res32[1784]; u32 pmuxcr; /* Pin multiplexing control */ u8 res33[60]; u32 iovselsr; /* I/O voltage selection status */ @@ -1772,6 +1773,10 @@ typedef struct ccsr_gur { u8 res37[380]; } ccsr_gur_t; +#define FSL_CORENET_DCSR_SZ_MASK 0x00000003 +#define FSL_CORENET_DCSR_SZ_4M 0x0 +#define FSL_CORENET_DCSR_SZ_1G 0x3 + /* * On p4080 we have an LIODN for msg unit (rmu) but not maintenance * everything after has RMan thus msg unit LIODN is used for maintenance diff --git a/arch/powerpc/include/asm/ppc440ep_gr.h b/arch/powerpc/include/asm/ppc440ep_gr.h index dfd1532b0..e7909638e 100644 --- a/arch/powerpc/include/asm/ppc440ep_gr.h +++ b/arch/powerpc/include/asm/ppc440ep_gr.h @@ -182,7 +182,7 @@ #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */ #define PRADV_MASK 0x07000000 /* Primary Divisor A */ #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ @@ -192,7 +192,7 @@ #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */ #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ diff --git a/arch/powerpc/include/asm/ppc440epx_grx.h b/arch/powerpc/include/asm/ppc440epx_grx.h index 6c214726b..c841f0fa0 100644 --- a/arch/powerpc/include/asm/ppc440epx_grx.h +++ b/arch/powerpc/include/asm/ppc440epx_grx.h @@ -398,7 +398,7 @@ #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */ #define PRADV_MASK 0x07000000 /* Primary Divisor A */ #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ @@ -408,7 +408,7 @@ #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */ #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ diff --git a/arch/powerpc/include/asm/ppc440gx.h b/arch/powerpc/include/asm/ppc440gx.h index 6f8581ba7..992452569 100644 --- a/arch/powerpc/include/asm/ppc440gx.h +++ b/arch/powerpc/include/asm/ppc440gx.h @@ -71,7 +71,7 @@ #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */ #define PRADV_MASK 0x07000000 /* Primary Divisor A */ #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ @@ -81,7 +81,7 @@ #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */ #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ diff --git a/arch/powerpc/include/asm/ppc440sp.h b/arch/powerpc/include/asm/ppc440sp.h index 4387495cd..cc2ff6812 100644 --- a/arch/powerpc/include/asm/ppc440sp.h +++ b/arch/powerpc/include/asm/ppc440sp.h @@ -67,7 +67,7 @@ #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */ #define PRADV_MASK 0x07000000 /* Primary Divisor A */ #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ @@ -77,7 +77,7 @@ #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */ #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ diff --git a/arch/powerpc/include/asm/ppc440spe.h b/arch/powerpc/include/asm/ppc440spe.h index bad9a4073..d59d7d28a 100644 --- a/arch/powerpc/include/asm/ppc440spe.h +++ b/arch/powerpc/include/asm/ppc440spe.h @@ -83,7 +83,7 @@ #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */ #define PRADV_MASK 0x07000000 /* Primary Divisor A */ #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ @@ -93,7 +93,7 @@ #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */ #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 9c4651a6b..0c4cc2554 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -938,6 +938,10 @@ #define PVR_85xx 0x80200000 #define PVR_85xx_REV1 (PVR_85xx | 0x0010) #define PVR_85xx_REV2 (PVR_85xx | 0x0020) +#define PVR_VER_E500_V1 0x8020 +#define PVR_VER_E500_V2 0x8021 +#define PVR_VER_E500MC 0x8023 +#define PVR_VER_E5500 0x8024 #define PVR_86xx 0x80040000 diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 4e0cb8f3b..137547451 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -87,7 +87,7 @@ static void boot_jump_linux(bootm_headers_t *images) * r8: 0 * r9: 0 */ -#if defined(CONFIG_85xx) || defined(CONFIG_440) +#if defined(CONFIG_MPC85xx) || defined(CONFIG_440) #define EPAPR_MAGIC (0x45504150) #else #define EPAPR_MAGIC (0x65504150) @@ -226,6 +226,24 @@ static int boot_bd_t_linux(bootm_headers_t *images) return ret; } +/* + * Verify the device tree. + * + * This function is called after all device tree fix-ups have been enacted, + * so that the final device tree can be verified. The definition of "verified" + * is up to the specific implementation. However, it generally means that the + * addresses of some of the devices in the device tree are compared with the + * actual addresses at which U-Boot has placed them. + * + * Returns 1 on success, 0 on failure. If 0 is returned, U-boot will halt the + * boot process. + */ +static int __ft_verify_fdt(void *fdt) +{ + return 1; +} +__attribute__((weak, alias("__ft_verify_fdt"))) int ft_verify_fdt(void *fdt); + static int boot_body_linux(bootm_headers_t *images) { ulong rd_len; @@ -298,6 +316,9 @@ static int boot_body_linux(bootm_headers_t *images) /* fixup the initrd now that we know where it should be */ if (*initrd_start && *initrd_end) fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1); + + if (!ft_verify_fdt(*of_flat_tree)) + return -1; } #endif /* CONFIG_OF_LIBFDT */ return 0; diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index ed9164342..90fe796ef 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -22,7 +22,6 @@ #include <command.h> #include <malloc.h> #include <stdio_dev.h> -#include <timestamp.h> #include <version.h> #include <watchdog.h> #include <net.h> @@ -39,8 +38,6 @@ extern int board_init(void); extern int dram_init(void); extern int timer_init(void); -const char version_string[] = U_BOOT_VERSION" ("U_BOOT_DATE" - "U_BOOT_TIME")"; - unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; #ifndef CONFIG_SYS_NO_FLASH diff --git a/arch/sparc/cpu/leon2/start.S b/arch/sparc/cpu/leon2/start.S index f22fb7eb1..9cd6c667d 100644 --- a/arch/sparc/cpu/leon2/start.S +++ b/arch/sparc/cpu/leon2/start.S @@ -28,7 +28,6 @@ #include <asm/psr.h> #include <asm/stack.h> #include <asm/leon.h> -#include <timestamp.h> #include <version.h> /* Entry for traps which jump to a programmer-specified trap handler. */ @@ -200,9 +199,7 @@ _trap_table: .data .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .section ".text" .align 4 diff --git a/arch/sparc/cpu/leon3/start.S b/arch/sparc/cpu/leon3/start.S index 56ae88d64..1e393a56e 100644 --- a/arch/sparc/cpu/leon3/start.S +++ b/arch/sparc/cpu/leon3/start.S @@ -28,7 +28,6 @@ #include <asm/psr.h> #include <asm/stack.h> #include <asm/leon.h> -#include <timestamp.h> #include <version.h> /* Entry for traps which jump to a programmer-specified trap handler. */ @@ -201,9 +200,7 @@ _trap_table: .extern leon3_snooping_avail .globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" + .ascii U_BOOT_VERSION_STRING, "\0" .section ".text" .align 4 diff --git a/arch/sparc/cpu/leon3/usb_uhci.c b/arch/sparc/cpu/leon3/usb_uhci.c index 8f99e1db1..b1269d260 100644 --- a/arch/sparc/cpu/leon3/usb_uhci.c +++ b/arch/sparc/cpu/leon3/usb_uhci.c @@ -70,7 +70,7 @@ * * Interrupt Transfers. * -------------------- - * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They + * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They * will be inserted after the appropriate (depending the interval setting) skeleton TD. * If an interrupt has been detected the dev->irqhandler is called. The status and number * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 7ccc076fe..6c84c43f0 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -66,7 +66,7 @@ _start: movw %ax, %es movw %ax, %ss - /* Clear the interupt vectors */ + /* Clear the interrupt vectors */ lidt blank_idt_ptr /* Early platform init (setup gpio, etc ) */ diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h index be52fe40d..f33f8ed44 100644 --- a/arch/x86/include/asm/interrupt.h +++ b/arch/x86/include/asm/interrupt.h @@ -32,7 +32,7 @@ /* arch/x86/cpu/interrupts.c */ void set_vector(u8 intnum, void *routine); -/* arch/x86/lib/interupts.c */ +/* arch/x86/lib/interrupts.c */ void disable_irq(int irq); void enable_irq(int irq); diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 944e1a200..4f0d2c7e7 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -36,7 +36,6 @@ typedef void (timer_fnc_t) (void); int register_timer_isr (timer_fnc_t *isr_func); /* Architecture specific - can be in arch/x86/cpu/, arch/x86/lib/, or $(BOARD)/ */ -int timer_init(void); int dram_init_f(void); /* cpu/.../interrupts.c */ diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c index c92291bc1..af375ddb1 100644 --- a/arch/x86/lib/board.c +++ b/arch/x86/lib/board.c @@ -35,7 +35,6 @@ #include <watchdog.h> #include <command.h> #include <stdio_dev.h> -#include <timestamp.h> #include <version.h> #include <malloc.h> #include <net.h> @@ -66,9 +65,6 @@ extern ulong __rel_dyn_end; extern ulong __bss_start; extern ulong __bss_end; -const char version_string[] = - U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")"; - /************************************************************************ * Init Utilities * ************************************************************************ |