diff options
Diffstat (limited to 'arch/powerpc')
49 files changed, 471 insertions, 845 deletions
diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index b7062818b..e32d2bf40 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -29,6 +29,9 @@ PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ PLATFORM_LDFLAGS += -n +# Support generic board on PPC +__HAVE_ARCH_GENERIC_BOARD := y + # # When cross-compiling on NetBSD, we have to define __PPC__ or else we # will pick up a va_list declaration that is incompatible with the diff --git a/arch/powerpc/cpu/74xx_7xx/cpu.c b/arch/powerpc/cpu/74xx_7xx/cpu.c index b6a31b437..17694a1cf 100644 --- a/arch/powerpc/cpu/74xx_7xx/cpu.c +++ b/arch/powerpc/cpu/74xx_7xx/cpu.c @@ -229,8 +229,7 @@ soft_restart(unsigned long addr) } -#if !defined(CONFIG_PCIPPC2) && \ - !defined(CONFIG_BAB7xx) && \ +#if !defined(CONFIG_BAB7xx) && \ !defined(CONFIG_ELPPC) && \ !defined(CONFIG_PPMC7XX) /* no generic way to do board reset. simply call soft_reset. */ @@ -288,13 +287,13 @@ unsigned long get_tbclk(void) /* ------------------------------------------------------------------------- */ #if defined(CONFIG_WATCHDOG) -#if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx) +#if !defined(CONFIG_BAB7xx) void watchdog_reset(void) { } -#endif /* !CONFIG_PCIPPC2 && !CONFIG_BAB7xx */ +#endif /* !CONFIG_BAB7xx */ #endif /* CONFIG_WATCHDOG */ /* ------------------------------------------------------------------------- */ diff --git a/arch/powerpc/cpu/74xx_7xx/start.S b/arch/powerpc/cpu/74xx_7xx/start.S index 75fb77389..cd8dea841 100644 --- a/arch/powerpc/cpu/74xx_7xx/start.S +++ b/arch/powerpc/cpu/74xx_7xx/start.S @@ -72,7 +72,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT @@ -715,7 +715,7 @@ in_ram: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/74xx_7xx/u-boot.lds b/arch/powerpc/cpu/74xx_7xx/u-boot.lds index c58d97975..40b89abac 100644 --- a/arch/powerpc/cpu/74xx_7xx/u-boot.lds +++ b/arch/powerpc/cpu/74xx_7xx/u-boot.lds @@ -89,6 +89,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc512x/cpu_init.c b/arch/powerpc/cpu/mpc512x/cpu_init.c index 32ade1b0b..b308cb4be 100644 --- a/arch/powerpc/cpu/mpc512x/cpu_init.c +++ b/arch/powerpc/cpu/mpc512x/cpu_init.c @@ -26,6 +26,7 @@ #include <common.h> #include <asm/io.h> +#include <asm/mpc512x.h> #include <asm/processor.h> DECLARE_GLOBAL_DATA_PTR; @@ -43,6 +44,101 @@ void cpu_init_f (volatile immap_t * im) /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); + /* Local Window and chip select configuration */ +#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE) + out_be32(&im->sysconf.lpcs0aw, + CSAW_START(CONFIG_SYS_CS0_START) | + CSAW_STOP(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE)); + sync_law(&im->sysconf.lpcs0aw); +#endif +#if defined(CONFIG_SYS_CS0_CFG) + out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); +#endif + +#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE) + out_be32(&im->sysconf.lpcs1aw, + CSAW_START(CONFIG_SYS_CS1_START) | + CSAW_STOP(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE)); + sync_law(&im->sysconf.lpcs1aw); +#endif +#if defined(CONFIG_SYS_CS1_CFG) + out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG); +#endif + +#if defined(CONFIG_SYS_CS2_START) && (defined CONFIG_SYS_CS2_SIZE) + out_be32(&im->sysconf.lpcs2aw, + CSAW_START(CONFIG_SYS_CS2_START) | + CSAW_STOP(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE)); + sync_law(&im->sysconf.lpcs2aw); +#endif +#if defined(CONFIG_SYS_CS2_CFG) + out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); +#endif + +#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE) + out_be32(&im->sysconf.lpcs3aw, + CSAW_START(CONFIG_SYS_CS3_START) | + CSAW_STOP(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE)); + sync_law(&im->sysconf.lpcs3aw); +#endif +#if defined(CONFIG_SYS_CS3_CFG) + out_be32(&im->lpc.cs_cfg[3], CONFIG_SYS_CS3_CFG); +#endif + +#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE) + out_be32(&im->sysconf.lpcs4aw, + CSAW_START(CONFIG_SYS_CS4_START) | + CSAW_STOP(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE)); + sync_law(&im->sysconf.lpcs4aw); +#endif +#if defined(CONFIG_SYS_CS4_CFG) + out_be32(&im->lpc.cs_cfg[4], CONFIG_SYS_CS4_CFG); +#endif + +#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE) + out_be32(&im->sysconf.lpcs5aw, + CSAW_START(CONFIG_SYS_CS5_START) | + CSAW_STOP(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE)); + sync_law(&im->sysconf.lpcs5aw); +#endif +#if defined(CONFIG_SYS_CS5_CFG) + out_be32(&im->lpc.cs_cfg[5], CONFIG_SYS_CS5_CFG); +#endif + +#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE) + out_be32(&im->sysconf.lpcs6aw, + CSAW_START(CONFIG_SYS_CS6_START) | + CSAW_STOP(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE)); + sync_law(&im->sysconf.lpcs6aw); +#endif +#if defined(CONFIG_SYS_CS6_CFG) + out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG); +#endif + +#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE) + out_be32(&im->sysconf.lpcs7aw, + CSAW_START(CONFIG_SYS_CS7_START) | + CSAW_STOP(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE)); + sync_law(&im->sysconf.lpcs7aw); +#endif +#if defined(CONFIG_SYS_CS7_CFG) + out_be32(&im->lpc.cs_cfg[7], CONFIG_SYS_CS7_CFG); +#endif + +#if defined CONFIG_SYS_CS_ALETIMING + if (SVR_MJREV(in_be32(&im->sysconf.spridr)) >= 2) + out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); +#endif +#if defined CONFIG_SYS_CS_BURST + out_be32(&im->lpc.cs_bcr, CONFIG_SYS_CS_BURST); +#endif +#if defined CONFIG_SYS_CS_DEADCYCLE + out_be32(&im->lpc.cs_dccr, CONFIG_SYS_CS_DEADCYCLE); +#endif +#if defined CONFIG_SYS_CS_HOLDCYCLE + out_be32(&im->lpc.cs_hccr, CONFIG_SYS_CS_HOLDCYCLE); +#endif + /* system performance tweaking */ #ifdef CONFIG_SYS_ACR_PIPE_DEP @@ -76,6 +172,21 @@ void cpu_init_f (volatile immap_t * im) ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT; out_be32(&im->clk.scfr[0], ips_div); +#ifdef SCFR1_LPC_DIV + clrsetbits_be32(&im->clk.scfr[0], SCFR1_LPC_DIV_MASK, + SCFR1_LPC_DIV << SCFR1_LPC_DIV_SHIFT); +#endif + +#ifdef SCFR1_NFC_DIV + clrsetbits_be32(&im->clk.scfr[0], SCFR1_NFC_DIV_MASK, + SCFR1_NFC_DIV << SCFR1_NFC_DIV_SHIFT); +#endif + +#ifdef SCFR1_DIU_DIV + clrsetbits_be32(&im->clk.scfr[0], SCFR1_DIU_DIV_MASK, + SCFR1_DIU_DIV << SCFR1_DIU_DIV_SHIFT); +#endif + /* * Enable Time Base/Decrementer * @@ -84,6 +195,15 @@ void cpu_init_f (volatile immap_t * im) * during FLASH chip identification etc. */ setbits_be32(&im->sysconf.spcr, SPCR_TBEN); + + /* + * Enable clocks + */ + out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN); + out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN); +#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) + setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); +#endif } int cpu_init_r (void) diff --git a/arch/powerpc/cpu/mpc512x/fixed_sdram.c b/arch/powerpc/cpu/mpc512x/fixed_sdram.c index 550cbd0bd..6635fb036 100644 --- a/arch/powerpc/cpu/mpc512x/fixed_sdram.c +++ b/arch/powerpc/cpu/mpc512x/fixed_sdram.c @@ -99,7 +99,19 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config, sync_law(&im->sysconf.ddrlaw.ar); /* DDR Enable */ - out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN); + /* + * the "enable" combination: DRAM controller out of reset, + * clock enabled, command mode -- BUT leave CKE low for now + */ + i = MDDRC_SYS_CFG_EN & ~MDDRC_SYS_CFG_CKE_MASK; + out_be32(&im->mddrc.ddr_sys_config, i); + /* maintain 200 microseconds of stable power and clock */ + udelay(200); + /* apply a NOP, it shouldn't harm */ + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_DDRCMD_NOP); + /* now assert CKE (high) */ + i |= MDDRC_SYS_CFG_CKE_MASK; + out_be32(&im->mddrc.ddr_sys_config, i); /* Initialize DDR Priority Manager */ out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1); @@ -148,6 +160,9 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config, out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0); out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config); + /* Allow for the DLL to startup before accessing data */ + udelay(10); + msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE); /* Fix DDR Local Window for new size */ out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1); diff --git a/arch/powerpc/cpu/mpc512x/iopin.c b/arch/powerpc/cpu/mpc512x/iopin.c index be2094762..1a3910162 100644 --- a/arch/powerpc/cpu/mpc512x/iopin.c +++ b/arch/powerpc/cpu/mpc512x/iopin.c @@ -47,3 +47,57 @@ void iopin_initialize(iopin_t *ioregs_init, int len) } return; } + +void iopin_initialize_bits(iopin_t *ioregs_init, int len) +{ + short i, j, p; + u32 *reg, mask; + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + + reg = (u32 *)&(im->io_ctrl); + + /* iterate over table entries */ + for (i = 0; i < len; i++) { + /* iterate over pins within a table entry */ + for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long); + p < ioregs_init[i].nr_pins; p++, j++) { + if (ioregs_init[i].bit_or & IO_PIN_OVER_EACH) { + /* replace all settings at once */ + out_be32(reg + j, ioregs_init[i].val); + } else { + /* + * only replace individual parts, but + * REPLACE them instead of just ORing + * them in and "inheriting" previously + * set bits which we don't want + */ + mask = 0; + if (ioregs_init[i].bit_or & IO_PIN_OVER_FMUX) + mask |= IO_PIN_FMUX(3); + + if (ioregs_init[i].bit_or & IO_PIN_OVER_HOLD) + mask |= IO_PIN_HOLD(3); + + if (ioregs_init[i].bit_or & IO_PIN_OVER_PULL) + mask |= IO_PIN_PUD(1) | IO_PIN_PUE(1); + + if (ioregs_init[i].bit_or & IO_PIN_OVER_STRIG) + mask |= IO_PIN_ST(1); + + if (ioregs_init[i].bit_or & IO_PIN_OVER_DRVSTR) + mask |= IO_PIN_DS(3); + /* + * DON'T do the "mask, then insert" + * in place on the register, it may + * break access to external hardware + * (like boot ROMs) when configuring + * LPB related pins, while the code to + * configure the pin is read from this + * very address region + */ + clrsetbits_be32(reg + j, mask, + ioregs_init[i].val & mask); + } + } + } +} diff --git a/arch/powerpc/cpu/mpc512x/start.S b/arch/powerpc/cpu/mpc512x/start.S index ed362d87a..6d1a99ac5 100644 --- a/arch/powerpc/cpu/mpc512x/start.S +++ b/arch/powerpc/cpu/mpc512x/start.S @@ -77,7 +77,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT @@ -622,7 +622,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc512x/u-boot.lds b/arch/powerpc/cpu/mpc512x/u-boot.lds index a34501b63..0d8697901 100644 --- a/arch/powerpc/cpu/mpc512x/u-boot.lds +++ b/arch/powerpc/cpu/mpc512x/u-boot.lds @@ -84,7 +84,7 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } ENTRY(_start) diff --git a/arch/powerpc/cpu/mpc5xx/start.S b/arch/powerpc/cpu/mpc5xx/start.S index cc4c33ebb..1b275c66a 100644 --- a/arch/powerpc/cpu/mpc5xx/start.S +++ b/arch/powerpc/cpu/mpc5xx/start.S @@ -65,7 +65,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT @@ -459,7 +459,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc5xx/u-boot.lds b/arch/powerpc/cpu/mpc5xx/u-boot.lds index 0d87c8cf1..8385a29bc 100644 --- a/arch/powerpc/cpu/mpc5xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xx/u-boot.lds @@ -93,7 +93,7 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); . = env_start; .ppcenv : diff --git a/arch/powerpc/cpu/mpc5xxx/spl_boot.c b/arch/powerpc/cpu/mpc5xxx/spl_boot.c index 9f14127dc..35611cce7 100644 --- a/arch/powerpc/cpu/mpc5xxx/spl_boot.c +++ b/arch/powerpc/cpu/mpc5xxx/spl_boot.c @@ -41,13 +41,12 @@ void board_init_f(ulong bootflag) end_align = (u32)__spl_flash_end; /* - * First we need to initialize the SDRAM, so that the real - * U-Boot or the OS (Linux) can be loaded + * On MPC5200, the initial RAM (and gd) is located in the internal + * SRAM. So we can actually call the preloader console init code + * before calling initdram(). This makes serial output (printf) + * available very early, even before SDRAM init, which has been + * an U-Boot priciple from day 1. */ - initdram(0); - - /* Clear bss */ - memset(__bss_start, '\0', __bss_end__ - __bss_start); /* * Init global_data pointer. Has to be done before calling @@ -71,6 +70,15 @@ void board_init_f(ulong bootflag) preloader_console_init(); /* + * First we need to initialize the SDRAM, so that the real + * U-Boot or the OS (Linux) can be loaded + */ + initdram(0); + + /* Clear bss */ + memset(__bss_start, '\0', __bss_end - __bss_start); + + /* * Call board_init_r() (SPL framework version) to load and boot * real U-Boot or OS */ diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S index ad5bc0a17..2b6a800de 100644 --- a/arch/powerpc/cpu/mpc5xxx/start.S +++ b/arch/powerpc/cpu/mpc5xxx/start.S @@ -66,7 +66,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT #endif @@ -694,7 +694,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds index cdb36c088..590952fd1 100644 --- a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds +++ b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds @@ -91,6 +91,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds index cab9b9265..050073961 100644 --- a/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds @@ -52,6 +52,6 @@ SECTIONS __bss_start = .; *(.bss*) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } > sdram } diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds b/arch/powerpc/cpu/mpc5xxx/u-boot.lds index 6bd646b93..06ece7836 100644 --- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xxx/u-boot.lds @@ -87,6 +87,6 @@ SECTIONS *(.sbss*) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc8220/start.S b/arch/powerpc/cpu/mpc8220/start.S index a1a2dc5ac..629563191 100644 --- a/arch/powerpc/cpu/mpc8220/start.S +++ b/arch/powerpc/cpu/mpc8220/start.S @@ -64,7 +64,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT @@ -647,7 +647,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc8220/u-boot.lds b/arch/powerpc/cpu/mpc8220/u-boot.lds index 6e9967cf8..dc63d2081 100644 --- a/arch/powerpc/cpu/mpc8220/u-boot.lds +++ b/arch/powerpc/cpu/mpc8220/u-boot.lds @@ -86,6 +86,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S index 076df70a9..0b9d89828 100644 --- a/arch/powerpc/cpu/mpc824x/start.S +++ b/arch/powerpc/cpu/mpc824x/start.S @@ -72,7 +72,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) #if defined(CONFIG_FADS) GOT_ENTRY(environment) @@ -584,7 +584,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc824x/u-boot.lds b/arch/powerpc/cpu/mpc824x/u-boot.lds index 699fb8585..4590fab33 100644 --- a/arch/powerpc/cpu/mpc824x/u-boot.lds +++ b/arch/powerpc/cpu/mpc824x/u-boot.lds @@ -87,6 +87,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S index 3299d7292..bd8d7ac53 100644 --- a/arch/powerpc/cpu/mpc8260/start.S +++ b/arch/powerpc/cpu/mpc8260/start.S @@ -65,7 +65,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) #if defined(CONFIG_HYMOD) GOT_ENTRY(environment) @@ -920,7 +920,7 @@ clear_bss: */ lwz r4,GOT(environment) #else - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) #endif cmplw 0, r3, r4 diff --git a/arch/powerpc/cpu/mpc8260/u-boot.lds b/arch/powerpc/cpu/mpc8260/u-boot.lds index 2709f3766..eb1c611f9 100644 --- a/arch/powerpc/cpu/mpc8260/u-boot.lds +++ b/arch/powerpc/cpu/mpc8260/u-boot.lds @@ -86,6 +86,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 44a64b7ac..1bfc97141 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -76,7 +76,7 @@ START_GOT GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(__bss_start) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) #ifndef MINIMAL_SPL GOT_ENTRY(_FIXUP_TABLE_) @@ -980,7 +980,7 @@ clear_bss: */ lwz r4,GOT(environment) #else - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) #endif cmplw 0, r3, r4 diff --git a/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds index d140453d4..870b47d6a 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds @@ -49,7 +49,7 @@ SECTIONS .bss (NOLOAD) : { *(.*bss) } - __bss_end__ = .; + __bss_end = .; } ENTRY(_start) -ASSERT(__bss_end__ <= 0xfff01000, "NAND bootstrap too big"); +ASSERT(__bss_end <= 0xfff01000, "NAND bootstrap too big"); diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds index 905823cb9..a9d859883 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds @@ -85,7 +85,7 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } ENTRY(_start) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 5495dc59e..825a29238 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -513,7 +513,7 @@ void fsl_serdes_init(void) size_t arglen; #endif #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 - int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */ + int need_serdes_a001; /* true == need work-around for SERDES A001 */ #endif #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 char buffer[HWCONFIG_BUFFER_SIZE]; diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index fb674694e..3f76ee66c 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -70,7 +70,7 @@ #endif GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT @@ -1784,7 +1784,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0,r3,r4 beq 6f diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds index 3bb757231..65106f5e1 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -103,6 +103,6 @@ SECTIONS } :bss . = ALIGN(4); - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds index 87522b83d..80cd98093 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds @@ -80,6 +80,6 @@ SECTIONS *(.sbss*) *(.bss*) } - __bss_end__ = .; + __bss_end = .; } ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big"); diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 1c408e29f..f2b7bffda 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -83,5 +83,5 @@ SECTIONS *(.sbss*) *(.bss*) } - __bss_end__ = .; + __bss_end = .; } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 8c6e66ec1..0503dce5a 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -127,6 +127,6 @@ SECTIONS } :bss . = ALIGN(4); - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc86xx/start.S b/arch/powerpc/cpu/mpc86xx/start.S index ef80ecf6e..20dfb9e0e 100644 --- a/arch/powerpc/cpu/mpc86xx/start.S +++ b/arch/powerpc/cpu/mpc86xx/start.S @@ -61,7 +61,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT @@ -800,7 +800,7 @@ in_ram: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc86xx/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds index 81804e357..7e357baf9 100644 --- a/arch/powerpc/cpu/mpc86xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc86xx/u-boot.lds @@ -90,6 +90,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile index 0d1a12c45..ef10e2d02 100644 --- a/arch/powerpc/cpu/mpc8xx/Makefile +++ b/arch/powerpc/cpu/mpc8xx/Makefile @@ -37,7 +37,6 @@ COBJS-y += fec.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-y += i2c.o COBJS-y += interrupts.o -COBJS-y += lcd.o COBJS-y += scc.o COBJS-y += serial.o COBJS-y += speed.o diff --git a/arch/powerpc/cpu/mpc8xx/lcd.c b/arch/powerpc/cpu/mpc8xx/lcd.c deleted file mode 100644 index 4b88b21b3..000000000 --- a/arch/powerpc/cpu/mpc8xx/lcd.c +++ /dev/null @@ -1,621 +0,0 @@ -/* - * (C) Copyright 2001-2002 - * Wolfgang Denk, DENX Software Engineering -- wd@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************************************/ -/* ** HEADER FILES */ -/************************************************************************/ - -/* #define DEBUG */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <watchdog.h> -#include <version.h> -#include <stdarg.h> -#include <lcdvideo.h> -#include <linux/types.h> -#include <stdio_dev.h> -#if defined(CONFIG_POST) -#include <post.h> -#endif -#include <lcd.h> - -#ifdef CONFIG_LCD - -/************************************************************************/ -/* ** CONFIG STUFF -- should be moved to board config file */ -/************************************************************************/ -#ifndef CONFIG_LCD_INFO -#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */ -#endif - -#if defined(CONFIG_V37) || defined(CONFIG_EDT32F10) -#undef CONFIG_LCD_LOGO -#undef CONFIG_LCD_INFO -#endif - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_KYOCERA_KCS057QV1AJ -/* - * Kyocera KCS057QV1AJ-G23. Passive, color, single scan. - */ -#define LCD_BPP LCD_COLOR4 - -vidinfo_t panel_info = { - 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, - LCD_BPP, 1, 0, 1, 0, 5, 0, 0, 0 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_KYOCERA_KCS057QV1AJ */ -/*----------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_HITACHI_SP19X001_Z1A -/* - * Hitachi SP19X001-. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 154, 116, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, - LCD_COLOR8, 1, 0, 1, 0, 0, 0, 0, 0 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_HITACHI_SP19X001_Z1A */ -/*----------------------------------------------------------------------*/ - -/*----------------------------------------------------------------------*/ -#ifdef CONFIG_NEC_NL6448AC33 -/* - * NEC NL6448AC33-18. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_NEC_NL6448AC33 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_NEC_NL6448BC20 -/* - * NEC NL6448BC20-08. 6.5", 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_NEC_NL6448BC20 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_NEC_NL6448BC33_54 -/* - * NEC NL6448BC33-54. 10.4", 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 212, 158, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_NEC_NL6448BC33_54 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_LQ104V7DS01 -/* - * SHARP LQ104V7DS01. 6.5", 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 132, 99, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW, - 3, 0, 0, 1, 1, 25, 1, 0, 33 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_SHARP_LQ104V7DS01 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_16x9 -/* - * Sharp 320x240. Active, color, single scan. It isn't 16x9, and I am - * not sure what it is....... - */ -vidinfo_t panel_info = { - 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 15, 4, 0, 3 -}; -#endif /* CONFIG_SHARP_16x9 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_LQ057Q3DC02 -/* - * Sharp LQ057Q3DC02 display. Active, color, single scan. - */ -#undef LCD_DF -#define LCD_DF 12 - -vidinfo_t panel_info = { - 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 15, 4, 0, 3 - /* wbl, vpw, lcdac, wbf */ -}; -#define CONFIG_LCD_INFO_BELOW_LOGO -#endif /* CONFIG_SHARP_LQ057Q3DC02 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SHARP_LQ64D341 -/* - * Sharp LQ64D341 display, 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 128, 16, 0, 32 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_SHARP_LQ64D341 */ - -#ifdef CONFIG_SHARP_LQ065T9DR51U -/* - * Sharp LQ065T9DR51U display, 400x240. Active, color, single scan. - */ -vidinfo_t panel_info = { - 400, 240, 143, 79, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 248, 4, 0, 35 - /* wbl, vpw, lcdac, wbf */ -}; -#define CONFIG_LCD_INFO_BELOW_LOGO -#endif /* CONFIG_SHARP_LQ065T9DR51U */ - -#ifdef CONFIG_SHARP_LQ084V1DG21 -/* - * Sharp LQ084V1DG21 display, 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 171, 129, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_LOW, - 3, 0, 0, 1, 1, 160, 3, 0, 48 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_SHARP_LQ084V1DG21 */ - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_HLD1045 -/* - * HLD1045 display, 640x480. Active, color, single scan. - */ -vidinfo_t panel_info = { - 640, 480, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 160, 3, 0, 48 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_HLD1045 */ -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_PRIMEVIEW_V16C6448AC -/* - * Prime View V16C6448AC - */ -vidinfo_t panel_info = { - 640, 480, 130, 98, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, CONFIG_SYS_LOW, CONFIG_SYS_HIGH, - 3, 0, 0, 1, 1, 144, 2, 0, 35 - /* wbl, vpw, lcdac, wbf */ -}; -#endif /* CONFIG_PRIMEVIEW_V16C6448AC */ - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_OPTREX_BW -/* - * Optrex CBL50840-2 NF-FW 99 22 M5 - * or - * Hitachi LMG6912RPFC-00T - * or - * Hitachi SP14Q002 - * - * 320x240. Black & white. - */ -#define OPTREX_BPP 0 /* 0 - monochrome, 1 bpp */ - /* 1 - 4 grey levels, 2 bpp */ - /* 2 - 16 grey levels, 4 bpp */ -vidinfo_t panel_info = { - 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, - OPTREX_BPP, 0, 0, 0, 0, 0, 0, 0, 0, 4 -}; -#endif /* CONFIG_OPTREX_BW */ - -/*-----------------------------------------------------------------*/ -#ifdef CONFIG_EDT32F10 -/* - * Emerging Display Technologies 320x240. Passive, monochrome, single scan. - */ -#define LCD_BPP LCD_MONOCHROME -#define LCD_DF 10 - -vidinfo_t panel_info = { - 320, 240, 0, 0, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_HIGH, CONFIG_SYS_LOW, - LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0 -}; -#endif -/*----------------------------------------------------------------------*/ - - -int lcd_line_length; - -int lcd_color_fg; -int lcd_color_bg; - -/* - * Frame buffer memory information - */ -void *lcd_base; /* Start of framebuffer memory */ -void *lcd_console_address; /* Start of console buffer */ - -short console_col; -short console_row; - -/************************************************************************/ - -void lcd_ctrl_init (void *lcdbase); -void lcd_enable (void); -#if LCD_BPP == LCD_COLOR8 -void lcd_setcolreg (ushort regno, - ushort red, ushort green, ushort blue); -#endif -#if LCD_BPP == LCD_MONOCHROME -void lcd_initcolregs (void); -#endif - -#if defined(CONFIG_RBC823) -void lcd_disable (void); -#endif - -/************************************************************************/ - -/************************************************************************/ -/* ----------------- chipset specific functions ----------------------- */ -/************************************************************************/ - -/* - * Calculate fb size for VIDEOLFB_ATAG. - */ -ulong calc_fbsize (void) -{ - ulong size; - int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; - - size = line_length * panel_info.vl_row; - - return size; -} - -void lcd_ctrl_init (void *lcdbase) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile lcd823_t *lcdp = &immr->im_lcd; - - uint lccrtmp; - uint lchcr_hpc_tmp; - - /* Initialize the LCD control register according to the LCD - * parameters defined. We do everything here but enable - * the controller. - */ - -#ifdef CONFIG_RPXLITE - /* This is special for RPXlite_DW Software Development Platform **[Sam]** */ - panel_info.vl_dp = CONFIG_SYS_LOW; -#endif - - lccrtmp = LCDBIT (LCCR_BNUM_BIT, - (((panel_info.vl_row * panel_info.vl_col) * (1 << LCD_BPP)) / 128)); - - lccrtmp |= LCDBIT (LCCR_CLKP_BIT, panel_info.vl_clkp) | - LCDBIT (LCCR_OEP_BIT, panel_info.vl_oep) | - LCDBIT (LCCR_HSP_BIT, panel_info.vl_hsp) | - LCDBIT (LCCR_VSP_BIT, panel_info.vl_vsp) | - LCDBIT (LCCR_DP_BIT, panel_info.vl_dp) | - LCDBIT (LCCR_BPIX_BIT, panel_info.vl_bpix) | - LCDBIT (LCCR_LBW_BIT, panel_info.vl_lbw) | - LCDBIT (LCCR_SPLT_BIT, panel_info.vl_splt) | - LCDBIT (LCCR_CLOR_BIT, panel_info.vl_clor) | - LCDBIT (LCCR_TFT_BIT, panel_info.vl_tft); - -#if 0 - lccrtmp |= ((SIU_LEVEL5 / 2) << 12); - lccrtmp |= LCCR_EIEN; -#endif - - lcdp->lcd_lccr = lccrtmp; - lcdp->lcd_lcsr = 0xFF; /* Clear pending interrupts */ - - /* Initialize LCD controller bus priorities. - */ -#ifdef CONFIG_RBC823 - immr->im_siu_conf.sc_sdcr = (immr->im_siu_conf.sc_sdcr & ~0x0f) | 1; /* RAID = 01, LAID = 00 */ -#else - immr->im_siu_conf.sc_sdcr &= ~0x0f; /* RAID = LAID = 0 */ - - /* set SHFT/CLOCK division factor 4 - * This needs to be set based upon display type and processor - * speed. The TFT displays run about 20 to 30 MHz. - * I was running 64 MHz processor speed. - * The value for this divider must be chosen so the result is - * an integer of the processor speed (i.e., divide by 3 with - * 64 MHz would be bad). - */ - immr->im_clkrst.car_sccr &= ~0x1F; - immr->im_clkrst.car_sccr |= LCD_DF; /* was 8 */ - -#endif /* CONFIG_RBC823 */ - -#if defined(CONFIG_RBC823) - /* Enable LCD on port D. - */ - immr->im_ioport.iop_pddat &= 0x0300; - immr->im_ioport.iop_pdpar |= 0x1CFF; - immr->im_ioport.iop_pddir |= 0x1CFF; - - /* Configure LCD_ON, VEE_ON, CCFL_ON on port B. - */ - immr->im_cpm.cp_pbdat &= ~0x00005001; - immr->im_cpm.cp_pbpar &= ~0x00005001; - immr->im_cpm.cp_pbdir |= 0x00005001; -#elif !defined(CONFIG_EDT32F10) - /* Enable LCD on port D. - */ - immr->im_ioport.iop_pdpar |= 0x1FFF; - immr->im_ioport.iop_pddir |= 0x1FFF; - - /* Enable LCD_A/B/C on port B. - */ - immr->im_cpm.cp_pbpar |= 0x00005001; - immr->im_cpm.cp_pbdir |= 0x00005001; -#else - /* Enable LCD on port D. - */ - immr->im_ioport.iop_pdpar |= 0x1DFF; - immr->im_ioport.iop_pdpar &= ~0x0200; - immr->im_ioport.iop_pddir |= 0x1FFF; - immr->im_ioport.iop_pddat |= 0x0200; -#endif - - /* Load the physical address of the linear frame buffer - * into the LCD controller. - * BIG NOTE: This has to be modified to load A and B depending - * upon the split mode of the LCD. - */ - lcdp->lcd_lcfaa = (ulong)lcd_base; - lcdp->lcd_lcfba = (ulong)lcd_base; - - /* MORE HACKS...This must be updated according to 823 manual - * for different panels. - * Udi Finkelstein - done - see below: - * Note: You better not try unsupported combinations such as - * 4-bit wide passive dual scan LCD at 4/8 Bit color. - */ - lchcr_hpc_tmp = - (panel_info.vl_col * - (panel_info.vl_tft ? 8 : - (((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */ - /* use << to mult by: single scan = 1, dual scan = 2 */ - panel_info.vl_splt) * - (panel_info.vl_bpix | 1)))) >> 3; /* 2/4 BPP = 1, 8/16 BPP = 3 */ - - lcdp->lcd_lchcr = LCHCR_BO | - LCDBIT (LCHCR_AT_BIT, 4) | - LCDBIT (LCHCR_HPC_BIT, lchcr_hpc_tmp) | - panel_info.vl_wbl; - - lcdp->lcd_lcvcr = LCDBIT (LCVCR_VPW_BIT, panel_info.vl_vpw) | - LCDBIT (LCVCR_LCD_AC_BIT, panel_info.vl_lcdac) | - LCDBIT (LCVCR_VPC_BIT, panel_info.vl_row) | - panel_info.vl_wbf; - -} - -/*----------------------------------------------------------------------*/ - -#ifdef NOT_USED_SO_FAR -static void -lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(immr->im_cpm); - unsigned short colreg, *cmap_ptr; - - cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2]; - - colreg = *cmap_ptr; -#ifdef CONFIG_SYS_INVERT_COLORS - colreg ^= 0x0FFF; -#endif - - *red = (colreg >> 8) & 0x0F; - *green = (colreg >> 4) & 0x0F; - *blue = colreg & 0x0F; -} -#endif /* NOT_USED_SO_FAR */ - -/*----------------------------------------------------------------------*/ - -#if LCD_BPP == LCD_COLOR8 -void -lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(immr->im_cpm); - unsigned short colreg, *cmap_ptr; - - cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2]; - - colreg = ((red & 0x0F) << 8) | - ((green & 0x0F) << 4) | - (blue & 0x0F) ; -#ifdef CONFIG_SYS_INVERT_COLORS - colreg ^= 0x0FFF; -#endif - *cmap_ptr = colreg; - - debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n", - regno, &(cp->lcd_cmap[regno * 2]), - red, green, blue, - cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]); -} -#endif /* LCD_COLOR8 */ - -/*----------------------------------------------------------------------*/ - -#if LCD_BPP == LCD_MONOCHROME -static -void lcd_initcolregs (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(immr->im_cpm); - ushort regno; - - for (regno = 0; regno < 16; regno++) { - cp->lcd_cmap[regno * 2] = 0; - cp->lcd_cmap[(regno * 2) + 1] = regno & 0x0f; - } -} -#endif - -/*----------------------------------------------------------------------*/ - -void lcd_enable (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile lcd823_t *lcdp = &immr->im_lcd; - - /* Enable the LCD panel */ -#ifndef CONFIG_RBC823 - immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */ -#endif - lcdp->lcd_lccr |= LCCR_PON; - -#ifdef CONFIG_V37 - /* Turn on display backlight */ - immr->im_cpm.cp_pbpar |= 0x00008000; - immr->im_cpm.cp_pbdir |= 0x00008000; -#elif defined(CONFIG_RBC823) - /* Turn on display backlight */ - immr->im_cpm.cp_pbdat |= 0x00004000; -#endif - -#if defined(CONFIG_LWMON) - { uchar c = pic_read (0x60); -#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON) - /* Enable LCD later in sysmon test, only if temperature is OK */ -#else - c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */ -#endif - pic_write (0x60, c); - } -#endif /* CONFIG_LWMON */ - -#if defined(CONFIG_R360MPI) - { - extern void r360_i2c_lcd_write (uchar data0, uchar data1); - unsigned long bgi, ctr; - char *p; - - if ((p = getenv("lcdbgi")) != NULL) { - bgi = simple_strtoul (p, 0, 10) & 0xFFF; - } else { - bgi = 0xFFF; - } - - if ((p = getenv("lcdctr")) != NULL) { - ctr = simple_strtoul (p, 0, 10) & 0xFFF; - } else { - ctr=0x7FF; - } - - r360_i2c_lcd_write(0x10, 0x01); - r360_i2c_lcd_write(0x20, 0x01); - r360_i2c_lcd_write(0x30 | ((bgi>>8) & 0xF), bgi & 0xFF); - r360_i2c_lcd_write(0x40 | ((ctr>>8) & 0xF), ctr & 0xFF); - } -#endif /* CONFIG_R360MPI */ -#ifdef CONFIG_RBC823 - udelay(200000); /* wait 200ms */ - /* Turn VEE_ON first */ - immr->im_cpm.cp_pbdat |= 0x00000001; - udelay(200000); /* wait 200ms */ - /* Now turn on LCD_ON */ - immr->im_cpm.cp_pbdat |= 0x00001000; -#endif -#ifdef CONFIG_RRVISION - debug ("PC4->Output(1): enable LVDS\n"); - debug ("PC5->Output(0): disable PAL clock\n"); - immr->im_ioport.iop_pddir |= 0x1000; - immr->im_ioport.iop_pcpar &= ~(0x0C00); - immr->im_ioport.iop_pcdir |= 0x0C00 ; - immr->im_ioport.iop_pcdat |= 0x0800 ; - immr->im_ioport.iop_pcdat &= ~(0x0400); - debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n", - immr->im_ioport.iop_pdpar, - immr->im_ioport.iop_pddir, - immr->im_ioport.iop_pddat); - debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n", - immr->im_ioport.iop_pcpar, - immr->im_ioport.iop_pcdir, - immr->im_ioport.iop_pcdat); -#endif -} - -/*----------------------------------------------------------------------*/ - -#if defined (CONFIG_RBC823) -void lcd_disable (void) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile lcd823_t *lcdp = &immr->im_lcd; - -#if defined(CONFIG_LWMON) - { uchar c = pic_read (0x60); - c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */ - pic_write (0x60, c); - } -#elif defined(CONFIG_R360MPI) - { - extern void r360_i2c_lcd_write (uchar data0, uchar data1); - - r360_i2c_lcd_write(0x10, 0x00); - r360_i2c_lcd_write(0x20, 0x00); - r360_i2c_lcd_write(0x30, 0x00); - r360_i2c_lcd_write(0x40, 0x00); - } -#endif /* CONFIG_LWMON */ - /* Disable the LCD panel */ - lcdp->lcd_lccr &= ~LCCR_PON; -#ifdef CONFIG_RBC823 - /* Turn off display backlight, VEE and LCD_ON */ - immr->im_cpm.cp_pbdat &= ~0x00005001; -#else - immr->im_siu_conf.sc_sdcr &= ~(1 << (31 - 25)); /* LAM = 0 */ -#endif /* CONFIG_RBC823 */ -} -#endif /* NOT_USED_SO_FAR || CONFIG_RBC823 */ - - -/************************************************************************/ - -#endif /* CONFIG_LCD */ diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index ebca3acba..5aa50c512 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -72,7 +72,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT @@ -590,7 +590,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 284709428..2db90455f 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -167,6 +167,11 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) } } + if (mode_idx < 0 || phy_idx < 0) { + puts("ERROR: wrong usb mode/phy defined!!\n"); + return; + } + dr_mode_type = modes[mode_idx]; dr_phy_type = phys[phy_idx]; diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c index 8a20a2b1e..161d274df 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c @@ -88,8 +88,6 @@ void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")) #define NUMMEMTESTS 8 #define NUMMEMWORDS 8 #define MAXBXCR 4 -#define TRUE 1 -#define FALSE 0 /* * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory @@ -298,7 +296,7 @@ static void get_spd_info(unsigned long *dimm_populated, unsigned char num_of_bytes; unsigned char total_size; - dimm_found = FALSE; + dimm_found = false; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { num_of_bytes = 0; total_size = 0; @@ -307,16 +305,16 @@ static void get_spd_info(unsigned long *dimm_populated, total_size = spd_read(iic0_dimm_addr[dimm_num], 1); if ((num_of_bytes != 0) && (total_size != 0)) { - dimm_populated[dimm_num] = TRUE; - dimm_found = TRUE; + dimm_populated[dimm_num] = true; + dimm_found = true; debug("DIMM slot %lu: populated\n", dimm_num); } else { - dimm_populated[dimm_num] = FALSE; + dimm_populated[dimm_num] = false; debug("DIMM slot %lu: Not populated\n", dimm_num); } } - if (dimm_found == FALSE) { + if (dimm_found == false) { printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); spd_ddr_init_hang (); } @@ -330,7 +328,7 @@ static void check_mem_type(unsigned long *dimm_populated, unsigned char dimm_type; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); switch (dimm_type) { case 7: @@ -356,7 +354,7 @@ static void check_volt_type(unsigned long *dimm_populated, unsigned long voltage_type; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); if (voltage_type != 0x04) { printf("ERROR: DIMM %lu with unsupported voltage level.\n", @@ -398,12 +396,12 @@ static void program_cfg0(unsigned long *dimm_populated, /* * FIXME: assume the DDR SDRAMs in both banks are the same */ - ecc_enabled = TRUE; + ecc_enabled = true; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { ecc = spd_read(iic0_dimm_addr[dimm_num], 11); if (ecc != 0x02) { - ecc_enabled = FALSE; + ecc_enabled = false; } /* @@ -437,7 +435,7 @@ static void program_cfg0(unsigned long *dimm_populated, /* * program Memory Data Error Checking */ - if (ecc_enabled == TRUE) { + if (ecc_enabled == true) { cfg0 |= SDRAM_CFG0_MCHK_GEN; } else { cfg0 |= SDRAM_CFG0_MCHK_NON; @@ -493,7 +491,7 @@ static void program_rtr(unsigned long *dimm_populated, bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12); switch (refresh_rate_type) { case 0x00: @@ -585,15 +583,15 @@ static void program_tr0(unsigned long *dimm_populated, t_rp_ns = 0; t_rcd_ns = 0; t_ras_ns = 0; - cas_2_0_available = TRUE; - cas_2_5_available = TRUE; - cas_3_0_available = TRUE; + cas_2_0_available = true; + cas_2_5_available = true; + cas_3_0_available = true; tcyc_2_0_ns_x_10 = 0; tcyc_2_5_ns_x_10 = 0; tcyc_3_0_ns_x_10 = 0; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15); t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2; t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2; @@ -640,7 +638,7 @@ static void program_tr0(unsigned long *dimm_populated, if (cas_index != 0) { cas_index++; } - cas_3_0_available = FALSE; + cas_3_0_available = false; } if (((cas_bit & 0x08) != 0) || (cas_index < 3)) { @@ -650,7 +648,7 @@ static void program_tr0(unsigned long *dimm_populated, if (cas_index != 0) { cas_index++; } - cas_2_5_available = FALSE; + cas_2_5_available = false; } if (((cas_bit & 0x04) != 0) || (cas_index < 3)) { @@ -660,7 +658,7 @@ static void program_tr0(unsigned long *dimm_populated, if (cas_index != 0) { cas_index++; } - cas_2_0_available = FALSE; + cas_2_0_available = false; } break; @@ -683,13 +681,13 @@ static void program_tr0(unsigned long *dimm_populated, /* * Program SD_CASL field */ - if ((cas_2_0_available == TRUE) && + if ((cas_2_0_available == true) && (bus_period_x_10 >= tcyc_2_0_ns_x_10)) { tr0 |= SDRAM_TR0_SDCL_2_0_CLK; - } else if ((cas_2_5_available == TRUE) && + } else if ((cas_2_5_available == true) && (bus_period_x_10 >= tcyc_2_5_ns_x_10)) { tr0 |= SDRAM_TR0_SDCL_2_5_CLK; - } else if ((cas_3_0_available == TRUE) && + } else if ((cas_3_0_available == true) && (bus_period_x_10 >= tcyc_3_0_ns_x_10)) { tr0 |= SDRAM_TR0_SDCL_3_0_CLK; } else { @@ -950,9 +948,9 @@ static void program_tr1(void) current_fail_length = 0; current_start = 0; rdclt_offset = 0; - window_found = FALSE; - fail_found = FALSE; - pass_found = FALSE; + window_found = false; + fail_found = false; + pass_found = false; debug("Starting memory test "); for (k = 0; k < NUMHALFCYCLES; k++) { @@ -963,8 +961,8 @@ static void program_tr1(void) mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt))); if (short_mem_test()) { - if (fail_found == TRUE) { - pass_found = TRUE; + if (fail_found == true) { + pass_found = true; if (current_pass_length == 0) { current_start = rdclt_offset + rdclt; } @@ -983,10 +981,10 @@ static void program_tr1(void) current_fail_length++; if (current_fail_length >= (dly_val>>2)) { - if (fail_found == FALSE) { - fail_found = TRUE; - } else if (pass_found == TRUE) { - window_found = TRUE; + if (fail_found == false) { + fail_found = true; + } else if (pass_found == true) { + window_found = true; break; } } @@ -994,9 +992,8 @@ static void program_tr1(void) } debug("."); - if (window_found == TRUE) { + if (window_found == true) break; - } tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; rdclt_offset += dly_val; @@ -1006,7 +1003,7 @@ static void program_tr1(void) /* * make sure we find the window */ - if (window_found == FALSE) { + if (window_found == false) { printf("ERROR: Cannot determine a common read delay.\n"); spd_ddr_init_hang (); } @@ -1115,7 +1112,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, bank_base_addr = CONFIG_SYS_SDRAM_BASE; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3); num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4); num_banks = spd_read(iic0_dimm_addr[dimm_num], 5); diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index 85217ea27..def7ebf72 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -241,13 +241,6 @@ void board_add_ram_info(int use_default) /*-----------------------------------------------------------------------------+ * Defines *-----------------------------------------------------------------------------*/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - #define SDRAM_DDR1 1 #define SDRAM_DDR2 2 #define SDRAM_NONE 0 @@ -683,7 +676,7 @@ static void get_spd_info(unsigned long *dimm_populated, unsigned char num_of_bytes; unsigned char total_size; - dimm_found = FALSE; + dimm_found = false; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { num_of_bytes = 0; total_size = 0; @@ -696,16 +689,16 @@ static void get_spd_info(unsigned long *dimm_populated, iic0_dimm_addr[dimm_num], total_size); if ((num_of_bytes != 0) && (total_size != 0)) { - dimm_populated[dimm_num] = TRUE; - dimm_found = TRUE; + dimm_populated[dimm_num] = true; + dimm_found = true; debug("DIMM slot %lu: populated\n", dimm_num); } else { - dimm_populated[dimm_num] = FALSE; + dimm_populated[dimm_num] = false; debug("DIMM slot %lu: Not populated\n", dimm_num); } } - if (dimm_found == FALSE) { + if (dimm_found == false) { printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); spd_ddr_init_hang (); } @@ -724,7 +717,7 @@ static void check_mem_type(unsigned long *dimm_populated, unsigned long dimm_type; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); switch (dimm_type) { case 1: @@ -994,14 +987,14 @@ static void program_copt1(unsigned long *dimm_populated, unsigned long val; #ifdef CONFIG_DDR_ECC - ecc_enabled = TRUE; + ecc_enabled = true; #else - ecc_enabled = FALSE; + ecc_enabled = false; #endif - dimm_32bit = FALSE; - dimm_64bit = FALSE; - buf0 = FALSE; - buf1 = FALSE; + dimm_32bit = false; + dimm_64bit = false; + buf0 = false; + buf1 = false; /*------------------------------------------------------------------ * Set memory controller options reg 1, SDRAM_MCOPT1. @@ -1026,7 +1019,7 @@ static void program_copt1(unsigned long *dimm_populated, /* test ecc support */ ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11); if (ecc != 0x02) /* ecc not supported */ - ecc_enabled = FALSE; + ecc_enabled = false; /* test bank count */ bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17); @@ -1048,15 +1041,15 @@ static void program_copt1(unsigned long *dimm_populated, if (registered == 1) { /* DDR2 always buffered */ /* TODO: what about above comments ? */ mcopt1 |= SDRAM_MCOPT1_RDEN; - buf0 = TRUE; + buf0 = true; } else { /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */ if ((attribute & 0x02) == 0x00) { /* buffered not supported */ - buf0 = FALSE; + buf0 = false; } else { mcopt1 |= SDRAM_MCOPT1_RDEN; - buf0 = TRUE; + buf0 = true; } } } @@ -1068,14 +1061,14 @@ static void program_copt1(unsigned long *dimm_populated, if (registered == 1) { /* DDR2 always buffered */ mcopt1 |= SDRAM_MCOPT1_RDEN; - buf1 = TRUE; + buf1 = true; } else { if ((attribute & 0x02) == 0x00) { /* buffered not supported */ - buf1 = FALSE; + buf1 = false; } else { mcopt1 |= SDRAM_MCOPT1_RDEN; - buf1 = TRUE; + buf1 = true; } } } @@ -1087,11 +1080,11 @@ static void program_copt1(unsigned long *dimm_populated, switch (data_width) { case 72: case 64: - dimm_64bit = TRUE; + dimm_64bit = true; break; case 40: case 32: - dimm_32bit = TRUE; + dimm_32bit = true; break; default: printf("WARNING: Detected a DIMM with a data width of %lu bits.\n", @@ -1110,20 +1103,19 @@ static void program_copt1(unsigned long *dimm_populated, } } - if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) { + if ((dimm_64bit == true) && (dimm_32bit == true)) { printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n"); spd_ddr_init_hang (); - } - else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) { + } else if ((dimm_64bit == true) && (dimm_32bit == false)) { mcopt1 |= SDRAM_MCOPT1_DMWD_64; - } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) { + } else if ((dimm_64bit == false) && (dimm_32bit == true)) { mcopt1 |= SDRAM_MCOPT1_DMWD_32; } else { printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n"); spd_ddr_init_hang (); } - if (ecc_enabled == TRUE) + if (ecc_enabled == true) mcopt1 |= SDRAM_MCOPT1_MCHK_GEN; else mcopt1 |= SDRAM_MCOPT1_MCHK_NON; @@ -1171,14 +1163,14 @@ static void program_codt(unsigned long *dimm_populated, total_rank += dimm_rank; total_dimm++; if ((dimm_num == 0) && (total_dimm == 1)) - firstSlot = TRUE; + firstSlot = true; else - firstSlot = FALSE; + firstSlot = false; } } if (dimm_type == SDRAM_DDR2) { codt |= SDRAM_CODT_DQS_1_8_V_DDR2; - if ((total_dimm == 1) && (firstSlot == TRUE)) { + if ((total_dimm == 1) && (firstSlot == true)) { if (total_rank == 1) { /* PUUU */ codt |= CALC_ODT_R(0); modt0 = CALC_ODT_W(0); @@ -1193,7 +1185,7 @@ static void program_codt(unsigned long *dimm_populated, modt2 = 0x00000000; modt3 = 0x00000000; } - } else if ((total_dimm == 1) && (firstSlot != TRUE)) { + } else if ((total_dimm == 1) && (firstSlot != true)) { if (total_rank == 1) { /* UUPU */ codt |= CALC_ODT_R(2); modt0 = 0x00000000; @@ -1467,26 +1459,26 @@ static void program_mode(unsigned long *dimm_populated, * the dimm modules installed. *-----------------------------------------------------------------*/ t_wr_ns = 0; - cas_2_0_available = TRUE; - cas_2_5_available = TRUE; - cas_3_0_available = TRUE; - cas_4_0_available = TRUE; - cas_5_0_available = TRUE; + cas_2_0_available = true; + cas_2_5_available = true; + cas_3_0_available = true; + cas_4_0_available = true; + cas_5_0_available = true; max_2_0_tcyc_ns_x_100 = 10; max_2_5_tcyc_ns_x_100 = 10; max_3_0_tcyc_ns_x_100 = 10; max_4_0_tcyc_ns_x_100 = 10; max_5_0_tcyc_ns_x_100 = 10; - sdram_ddr1 = TRUE; + sdram_ddr1 = true; /* loop through all the DIMM slots on the board */ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_populated[dimm_num] != SDRAM_NONE) { if (dimm_populated[dimm_num] == SDRAM_DDR1) - sdram_ddr1 = TRUE; + sdram_ddr1 = true; else - sdram_ddr1 = FALSE; + sdram_ddr1 = false; cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit); @@ -1543,7 +1535,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_4_0_available = FALSE; + cas_4_0_available = false; } if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && @@ -1554,7 +1546,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_3_0_available = FALSE; + cas_3_0_available = false; } if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && @@ -1565,7 +1557,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_2_5_available = FALSE; + cas_2_5_available = false; } if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) && @@ -1576,7 +1568,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_2_0_available = FALSE; + cas_2_0_available = false; } } else { /* @@ -1592,7 +1584,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_5_0_available = FALSE; + cas_5_0_available = false; } if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && @@ -1603,7 +1595,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_4_0_available = FALSE; + cas_4_0_available = false; } if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && @@ -1614,7 +1606,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_3_0_available = FALSE; + cas_3_0_available = false; } } } @@ -1636,14 +1628,17 @@ static void program_mode(unsigned long *dimm_populated, debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk); debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk); - if (sdram_ddr1 == TRUE) { /* DDR1 */ - if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) { + if (sdram_ddr1 == true) { /* DDR1 */ + if ((cas_2_0_available == true) && + (sdram_freq <= cycle_2_0_clk)) { mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK; *selected_cas = DDR_CAS_2; - } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) { + } else if ((cas_2_5_available == true) && + (sdram_freq <= cycle_2_5_clk)) { mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK; *selected_cas = DDR_CAS_2_5; - } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) { + } else if ((cas_3_0_available == true) && + (sdram_freq <= cycle_3_0_clk)) { mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK; *selected_cas = DDR_CAS_3; } else { @@ -1656,13 +1651,16 @@ static void program_mode(unsigned long *dimm_populated, debug("cas_3_0_available=%d\n", cas_3_0_available); debug("cas_4_0_available=%d\n", cas_4_0_available); debug("cas_5_0_available=%d\n", cas_5_0_available); - if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) { + if ((cas_3_0_available == true) && + (sdram_freq <= cycle_3_0_clk)) { mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK; *selected_cas = DDR_CAS_3; - } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) { + } else if ((cas_4_0_available == true) && + (sdram_freq <= cycle_4_0_clk)) { mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK; *selected_cas = DDR_CAS_4; - } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) { + } else if ((cas_5_0_available == true) && + (sdram_freq <= cycle_5_0_clk)) { mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK; *selected_cas = DDR_CAS_5; } else { @@ -1677,7 +1675,7 @@ static void program_mode(unsigned long *dimm_populated, } } - if (sdram_ddr1 == TRUE) + if (sdram_ddr1 == true) mmode |= SDRAM_MMODE_WR_DDR1; else { @@ -1851,16 +1849,16 @@ static void program_tr(unsigned long *dimm_populated, t_wpc_ns = 0; t_wtr_ns = 0; t_rpc_ns = 0; - sdram_ddr1 = TRUE; + sdram_ddr1 = true; /* loop through all the DIMM slots on the board */ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_populated[dimm_num] != SDRAM_NONE) { if (dimm_populated[dimm_num] == SDRAM_DDR2) - sdram_ddr1 = TRUE; + sdram_ddr1 = true; else - sdram_ddr1 = FALSE; + sdram_ddr1 = false; t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2); t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2); @@ -1925,7 +1923,7 @@ static void program_tr(unsigned long *dimm_populated, break; } - if (sdram_ddr1 == TRUE) { /* DDR1 */ + if (sdram_ddr1 == true) { /* DDR1 */ if (sdram_freq < 200000000) { sdtr2 |= SDRAM_SDTR2_WTR_1_CLK; sdtr2 |= SDRAM_SDTR2_WPC_2_CLK; @@ -2548,8 +2546,8 @@ calibration_loop: current_pass_length = 0; current_fail_length = 0; current_start = 0; - fail_found = FALSE; - pass_found = FALSE; + fail_found = false; + pass_found = false; /* * get the delay line calibration register value @@ -2570,8 +2568,8 @@ calibration_loop: * See if the rffd value passed. *-----------------------------------------------------------------*/ if (short_mem_test()) { - if (fail_found == TRUE) { - pass_found = TRUE; + if (fail_found == true) { + pass_found = true; if (current_pass_length == 0) current_start = rffd; @@ -2589,11 +2587,10 @@ calibration_loop: current_fail_length++; if (current_fail_length >= (dly_val >> 2)) { - if (fail_found == FALSE) { - fail_found = TRUE; - } else if (pass_found == TRUE) { + if (fail_found == false) + fail_found = true; + else if (pass_found == true) break; - } } } } /* for rffd */ @@ -2618,9 +2615,9 @@ calibration_loop: current_pass_length = 0; current_fail_length = 0; current_start = 0; - window_found = FALSE; - fail_found = FALSE; - pass_found = FALSE; + window_found = false; + fail_found = false; + pass_found = false; for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) { mfsdram(SDRAM_RQDC, rqdc_reg); @@ -2635,8 +2632,8 @@ calibration_loop: * See if the rffd value passed. *-----------------------------------------------------------------*/ if (short_mem_test()) { - if (fail_found == TRUE) { - pass_found = TRUE; + if (fail_found == true) { + pass_found = true; if (current_pass_length == 0) current_start = rqfd; @@ -2653,10 +2650,10 @@ calibration_loop: current_pass_length = 0; current_fail_length++; - if (fail_found == FALSE) { - fail_found = TRUE; - } else if (pass_found == TRUE) { - window_found = TRUE; + if (fail_found == false) { + fail_found = true; + } else if (pass_found == true) { + window_found = true; break; } } @@ -2667,7 +2664,7 @@ calibration_loop: /*------------------------------------------------------------------ * Make sure we found the valid read passing window. Halt if not *-----------------------------------------------------------------*/ - if (window_found == FALSE) { + if (window_found == false) { if (rqfd_start < SDRAM_RQDC_RQFD_MAX) { putc('\b'); putc(slash[loopi++ % 8]); @@ -2769,13 +2766,13 @@ static void test(void) mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_NON); - window_found = FALSE; - begin_found[0] = FALSE; - end_found[0] = FALSE; - search_end[0] = FALSE; - begin_found[1] = FALSE; - end_found[1] = FALSE; - search_end[1] = FALSE; + window_found = false; + begin_found[0] = false; + end_found[0] = false; + search_end[0] = false; + begin_found[1] = false; + end_found[1] = false; + search_end[1] = false; for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]); @@ -2812,32 +2809,32 @@ static void test(void) * See if the rffd value passed. *-----------------------------------------------------------------*/ if (i < NUMMEMTESTS) { - if ((end_found[dimm_num] == FALSE) && - (search_end[dimm_num] == TRUE)) { - end_found[dimm_num] = TRUE; + if ((end_found[dimm_num] == false) && + (search_end[dimm_num] == true)) { + end_found[dimm_num] = true; } - if ((end_found[0] == TRUE) && - (end_found[1] == TRUE)) + if ((end_found[0] == true) && + (end_found[1] == true)) break; } else { - if (begin_found[dimm_num] == FALSE) { - begin_found[dimm_num] = TRUE; - search_end[dimm_num] = TRUE; + if (begin_found[dimm_num] == false) { + begin_found[dimm_num] = true; + search_end[dimm_num] = true; } } } else { - begin_found[dimm_num] = TRUE; - end_found[dimm_num] = TRUE; + begin_found[dimm_num] = true; + end_found[dimm_num] = true; } } - if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE)) - window_found = TRUE; + if ((begin_found[0] == true) && (begin_found[1] == true)) + window_found = true; /*------------------------------------------------------------------ * Make sure we found the valid read passing window. Halt if not *-----------------------------------------------------------------*/ - if (window_found == FALSE) { + if (window_found == false) { printf("ERROR: Cannot determine a common read delay for the " "DIMM(s) installed.\n"); spd_ddr_init_hang (); diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c index ce769a715..3ceab32e4 100644 --- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c @@ -53,13 +53,6 @@ /*-----------------------------------------------------------------------------+ * Defines *-----------------------------------------------------------------------------*/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - #define MAXDIMMS 2 #define MAXRANKS 2 @@ -279,7 +272,7 @@ static void get_spd_info(unsigned long dimm_ranks[], unsigned long num_dimm_banks) { unsigned long dimm_num; - unsigned long dimm_found = FALSE; + unsigned long dimm_found = false; unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1; unsigned char num_of_bytes; unsigned char total_size; @@ -334,7 +327,7 @@ static void get_spd_info(unsigned long dimm_ranks[], "\n\n"); spd_ddr_init_hang(); } - dimm_found = TRUE; + dimm_found = true; debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM" "\n", dimm_num, ranks_on_dimm); if (ranks_on_dimm > max_ranks_per_dimm) { @@ -355,7 +348,7 @@ static void get_spd_info(unsigned long dimm_ranks[], debug("DIMM slot %lu: Not populated\n", dimm_num); } } - if (dimm_found == FALSE) { + if (dimm_found == false) { printf("ERROR: No memory installed.\n"); printf("Install at least one DDR2 DIMM.\n\n"); spd_ddr_init_hang(); @@ -882,7 +875,7 @@ static void program_ddr0_22(unsigned long dimm_ranks[], /* Check for ECC */ if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) & 0x02)) { - ecc_available = FALSE; + ecc_available = false; } } } diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 7aef43b21..52f262337 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -243,7 +243,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT #endif /* CONFIG_NAND_SPL */ @@ -1509,7 +1509,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 7f diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds index 2cadcc94d..06010d6b1 100644 --- a/arch/powerpc/cpu/ppc4xx/u-boot.lds +++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds @@ -142,6 +142,6 @@ SECTIONS } :bss . = ALIGN(4); - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h index f763a5413..d96e53646 100644 --- a/arch/powerpc/include/asm/immap_512x.h +++ b/arch/powerpc/include/asm/immap_512x.h @@ -227,7 +227,9 @@ typedef struct clk512x { #define CLOCK_SCCR2_IIM_EN 0x00080000 /* SCFR1 System Clock Frequency Register 1 */ +#ifndef SCFR1_IPS_DIV #define SCFR1_IPS_DIV 0x3 +#endif #define SCFR1_IPS_DIV_MASK 0x03800000 #define SCFR1_IPS_DIV_SHIFT 23 @@ -238,6 +240,12 @@ typedef struct clk512x { #define SCFR1_LPC_DIV_MASK 0x00003800 #define SCFR1_LPC_DIV_SHIFT 11 +#define SCFR1_NFC_DIV_MASK 0x00000700 +#define SCFR1_NFC_DIV_SHIFT 8 + +#define SCFR1_DIU_DIV_MASK 0x000000FF +#define SCFR1_DIU_DIV_SHIFT 0 + /* SCFR2 System Clock Frequency Register 2 */ #define SCFR2_SYS_DIV 0xFC000000 #define SCFR2_SYS_DIV_SHIFT 26 @@ -343,6 +351,7 @@ typedef struct ddr512x { /* MDDRC SYS CFG and Timing CFG0 Registers */ #define MDDRC_SYS_CFG_EN 0xF0000000 +#define MDDRC_SYS_CFG_CKE_MASK 0x40000000 #define MDDRC_SYS_CFG_CMD_MASK 0x10000000 #define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF @@ -871,6 +880,19 @@ typedef struct iopin_t { void iopin_initialize(iopin_t *,int); /* + * support to adjust individual parts of the IO pin setup + */ + +#define IO_PIN_OVER_EACH (1 << 0) /* for compatibility */ +#define IO_PIN_OVER_FMUX (1 << 1) +#define IO_PIN_OVER_HOLD (1 << 2) +#define IO_PIN_OVER_PULL (1 << 3) +#define IO_PIN_OVER_STRIG (1 << 4) +#define IO_PIN_OVER_DRVSTR (1 << 5) + +void iopin_initialize_bits(iopin_t *, int); + +/* * IIM */ typedef struct iim512x { diff --git a/arch/powerpc/include/asm/sections.h b/arch/powerpc/include/asm/sections.h new file mode 100644 index 000000000..0a94102de --- /dev/null +++ b/arch/powerpc/include/asm/sections.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_POWERPC_SECTIONS_H +#define __ASM_POWERPC_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif diff --git a/arch/powerpc/include/asm/spl.h b/arch/powerpc/include/asm/spl.h index f43bc23c9..7d5f9a0a3 100644 --- a/arch/powerpc/include/asm/spl.h +++ b/arch/powerpc/include/asm/spl.h @@ -26,6 +26,6 @@ #define BOOT_DEVICE_NOR 1 /* Linker symbols */ -extern char __bss_start[], __bss_end__[]; +extern char __bss_start[], __bss_end[]; #endif diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index 7229a98ea..cf972d20c 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -34,6 +34,11 @@ * include/asm-ppc/u-boot.h */ +#ifdef CONFIG_SYS_GENERIC_BOARD +/* Use the generic board which requires a unified bd_info */ +#include <asm-generic/u-boot.h> +#else + #ifndef __ASSEMBLY__ typedef struct bd_info { @@ -144,6 +149,8 @@ typedef struct bd_info { #endif /* __ASSEMBLY__ */ +#endif /* !CONFIG_SYS_GENERIC_BOARD */ + /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_PPC diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 86cf02ace..59c723b07 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -59,8 +59,10 @@ SOBJS-y += reloc.o COBJS-$(CONFIG_BAT_RW) += bat_rw.o ifndef CONFIG_SPL_BUILD +ifndef CONFIG_SYS_GENERIC_BOARD COBJS-y += board.o endif +endif COBJS-y += bootm.o COBJS-y += cache.o COBJS-y += extable.o diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 12270a453..422b4a39b 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -123,7 +123,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif extern ulong __init_end; -extern ulong __bss_end__; +extern ulong __bss_end; ulong monitor_flash_len; #if defined(CONFIG_CMD_BEDBUG) @@ -237,25 +237,18 @@ static int init_func_spi(void) /***********************************************************************/ #if defined(CONFIG_WATCHDOG) -static int init_func_watchdog_init(void) +int init_func_watchdog_init(void) { puts(" Watchdog enabled\n"); WATCHDOG_RESET(); return 0; } -#define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init, - -static int init_func_watchdog_reset(void) +int init_func_watchdog_reset(void) { WATCHDOG_RESET(); return 0; } - -#define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset, -#else -#define INIT_FUNC_WATCHDOG_INIT /* undef */ -#define INIT_FUNC_WATCHDOG_RESET /* undef */ #endif /* CONFIG_WATCHDOG */ /* @@ -326,7 +319,8 @@ static init_fnc_t *init_sequence[] = { #ifdef CONFIG_POST post_init_f, #endif - INIT_FUNC_WATCHDOG_RESET init_func_ram, + INIT_FUNC_WATCHDOG_RESET + init_func_ram, #if defined(CONFIG_SYS_DRAM_TEST) testdram, #endif /* CONFIG_SYS_DRAM_TEST */ @@ -419,7 +413,7 @@ void board_init_f(ulong bootflag) * - monitor code * - board info struct */ - len = (ulong)&__bss_end__ - CONFIG_SYS_MONITOR_BASE; + len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; /* * Subtract specified amount of memory to hide so that it won't diff --git a/arch/powerpc/lib/ticks.S b/arch/powerpc/lib/ticks.S index 17810395b..63114bb0c 100644 --- a/arch/powerpc/lib/ticks.S +++ b/arch/powerpc/lib/ticks.S @@ -50,19 +50,24 @@ wait_ticks: stwu r1, -16(r1) mflr r0 /* save link register */ stw r0, 20(r1) /* Use r0 or GDB will be unhappy */ - mr r7, r3 /* save tick count */ + stw r14, 12(r1) /* save used registers */ + stw r15, 8(r1) + mr r14, r3 /* save tick count */ bl get_ticks /* Get start time */ /* Calculate end time */ - addc r7, r4, r7 /* Compute end time lower */ - addze r6, r3 /* and end time upper */ + addc r14, r4, r14 /* Compute end time lower */ + addze r15, r3 /* and end time upper */ WATCHDOG_RESET /* Trigger watchdog, if needed */ 1: bl get_ticks /* Get current time */ - subfc r4, r4, r7 /* Subtract current time from end time */ - subfe. r3, r3, r6 + subfc r4, r4, r14 /* Subtract current time from end time */ + subfe. r3, r3, r15 bge 1b /* Loop until time expired */ - mtlr r0 /* restore link register */ + lwz r15, 8(r1) /* restore saved registers */ + lwz r14, 12(r1) + lwz r0, 20(r1) addi r1,r1,16 + mtlr r0 blr |