diff options
Diffstat (limited to 'arch/powerpc/include/asm/ppc4xx-sdram.h')
| -rw-r--r-- | arch/powerpc/include/asm/ppc4xx-sdram.h | 12 | 
1 files changed, 6 insertions, 6 deletions
| diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index ac150c268..d570d7915 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -292,7 +292,7 @@   */  #if defined(CONFIG_440SPE) || \      defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ -    defined(CONFIG_460SX) +    defined(CONFIG_460SX) || defined(CONFIG_APM821XX)  #define SDRAM_RXBAS_SDBA_MASK		0xFFE00000	/* Base address	*/  #define SDRAM_RXBAS_SDBA_ENCODE(n)	((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000))  #define SDRAM_RXBAS_SDBA_DECODE(n)	((((phys_size_t)(n)) & 0xFFE00000) << 2) @@ -365,7 +365,7 @@  /*   * Memory controller registers   */ -#ifdef CONFIG_405EX +#if defined(CONFIG_405EX) || defined(CONFIG_APM821XX)  #define SDRAM_BESR	0x00	/* PLB bus error status (read/clear)         */  #define SDRAM_BESRT	0x01	/* PLB bus error status (test/set)           */  #define SDRAM_BEARL	0x02	/* PLB bus error address low                 */ @@ -375,9 +375,9 @@  #define SDRAM_PLBOPT	0x08	/* PLB slave options                         */  #define SDRAM_PUABA	0x09	/* PLB upper address base                    */  #define SDRAM_MCSTAT	0x1F	/* memory controller status                  */ -#else /* CONFIG_405EX */ +#else /* CONFIG_405EX || CONFIG_APM821XX */  #define SDRAM_MCSTAT	0x14	/* memory controller status                  */ -#endif /* CONFIG_405EX */ +#endif /* CONFIG_405EX || CONFIG_APM821XX */  #define SDRAM_MCOPT1	0x20	/* memory controller options 1               */  #define SDRAM_MCOPT2	0x21	/* memory controller options 2               */  #define SDRAM_MODT0	0x22	/* on die termination for bank 0             */ @@ -423,12 +423,12 @@  #define SDRAM_MEMODE	0x89	/* memory extended mode                      */  #define SDRAM_ECCES	0x98	/* ECC error status                          */  #define SDRAM_CID	0xA4	/* core ID                                   */ -#ifndef CONFIG_405EX +#if !defined(CONFIG_405EX) && !defined(CONFIG_APM821XX)  #define SDRAM_RID	0xA8	/* revision ID                               */  #endif  #define SDRAM_FCSR	0xB0	/* feedback calibration status               */  #define SDRAM_RTSR	0xB1	/* run time status tracking                  */ -#ifdef CONFIG_405EX +#if  defined(CONFIG_405EX) || defined(CONFIG_APM821XX)  #define SDRAM_RID	0xF8	/* revision ID                               */  #endif |