diff options
Diffstat (limited to 'arch/powerpc/include/asm/immap_85xx.h')
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 84 |
1 files changed, 39 insertions, 45 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 5b205d1c2..4e665d399 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -266,50 +266,6 @@ typedef struct ccsr_duart { } ccsr_duart_t; #endif -/* Local Bus Controller Registers */ -typedef struct ccsr_lbc { - u32 br0; /* LBC Base 0 */ - u32 or0; /* LBC Options 0 */ - u32 br1; /* LBC Base 1 */ - u32 or1; /* LBC Options 1 */ - u32 br2; /* LBC Base 2 */ - u32 or2; /* LBC Options 2 */ - u32 br3; /* LBC Base 3 */ - u32 or3; /* LBC Options 3 */ - u32 br4; /* LBC Base 4 */ - u32 or4; /* LBC Options 4 */ - u32 br5; /* LBC Base 5 */ - u32 or5; /* LBC Options 5 */ - u32 br6; /* LBC Base 6 */ - u32 or6; /* LBC Options 6 */ - u32 br7; /* LBC Base 7 */ - u32 or7; /* LBC Options 7 */ - u8 res1[40]; - u32 mar; /* LBC UPM Addr */ - u8 res2[4]; - u32 mamr; /* LBC UPMA Mode */ - u32 mbmr; /* LBC UPMB Mode */ - u32 mcmr; /* LBC UPMC Mode */ - u8 res3[8]; - u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */ - u32 mdr; /* LBC UPM Data */ - u8 res4[8]; - u32 lsdmr; /* LBC SDRAM Mode */ - u8 res5[8]; - u32 lurt; /* LBC UPM Refresh Timer */ - u32 lsrt; /* LBC SDRAM Refresh Timer */ - u8 res6[8]; - u32 ltesr; /* LBC Transfer Error Status */ - u32 ltedr; /* LBC Transfer Error Disable */ - u32 lteir; /* LBC Transfer Error IRQ */ - u32 lteatr; /* LBC Transfer Error Attrs */ - u32 ltear; /* LBC Transfer Error Addr */ - u8 res7[12]; - u32 lbcr; /* LBC Configuration */ - u32 lcrr; /* LBC Clock Ratio */ - u8 res8[3880]; -} ccsr_lbc_t; - /* eSPI Registers */ typedef struct ccsr_espi { u32 mode; /* eSPI mode */ @@ -2045,6 +2001,41 @@ enum { FSL_SRDS_B3_LANE_D = 23, }; +/* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 +typedef struct ccsr_sec { + u8 res1[0xfa0]; + u32 crnr_ms; /* CHA Revision Number Register, MS */ + u32 crnr_ls; /* CHA Revision Number Register, LS */ + u32 ctpr_ms; /* Compile Time Parameters Register, MS */ +#define SEC_CTPR_MS_AXI_LIODN 0x08000000 +#define SEC_CTPR_MS_QI 0x02000000 + u32 ctpr_ls; /* Compile Time Parameters Register, LS */ + u8 res2[0x10]; + u32 far_ms; /* Fault Address Register, MS */ + u32 far_ls; /* Fault Address Register, LS */ + u32 falr; /* Fault Address LIODN Register */ + u32 fadr; /* Fault Address Detail Register */ + u8 res3[0x4]; + u32 csta; /* CAAM Status Register */ + u8 res4[0x8]; + u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ +#define SEC_RVID_MA 0x0f000000 + u32 ccbvid; /* CHA Cluster Block Version ID Register */ + u32 chavid_ms; /* CHA Version ID Register, MS */ + u32 chavid_ls; /* CHA Version ID Register, LS */ + u32 chanum_ms; /* CHA Number Register, MS */ +#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000 +#define SEC_CHANUM_MS_JQNUM_SHIFT 28 +#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 +#define SEC_CHANUM_MS_DECONUM_SHIFT 24 + u32 chanum_ls; /* CHA Number Register, LS */ + u32 caamvid_ms; /* CAAM Version ID Register, MS */ + u32 caamvid_ls; /* CAAM Version ID Register, LS */ + u8 res5[0xf000]; +} ccsr_sec_t; +#endif + #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 @@ -2059,6 +2050,7 @@ enum { #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000 +#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 #define CONFIG_SYS_TSEC1_OFFSET 0x4e0000 /* FM1@DTSEC0 */ @@ -2111,7 +2103,7 @@ enum { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) #define CONFIG_SYS_MPC85xx_DDR2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) -#define CONFIG_SYS_MPC85xx_LBC_ADDR \ +#define CONFIG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) #define CONFIG_SYS_MPC85xx_ESPI_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) @@ -2143,6 +2135,8 @@ enum { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) +#define CONFIG_SYS_FSL_SEC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) |