diff options
Diffstat (limited to 'arch/powerpc/include/asm/immap_85xx.h')
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 19 | 
1 files changed, 17 insertions, 2 deletions
| diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index e0efc7eba..edd7888c4 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2495,6 +2495,7 @@ typedef struct serdes_corenet {  #define SRDS_RSTCTL_SDEN	0x00000020  #define SRDS_RSTCTL_SDRST_B	0x00000040  #define SRDS_RSTCTL_PLLRST_B	0x00000080 +#define SRDS_RSTCTL_RSTERR_SHIFT  29  		u32	pllcr0; /* PLL Control Register 0 */  #define SRDS_PLLCR0_POFF		0x80000000  #define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000 @@ -2504,6 +2505,7 @@ typedef struct serdes_corenet {  #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000  #define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000  #define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000 +#define SRDS_PLLCR0_DCBIAS_OUT_EN      0x02000000  #define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000  #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000  #define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000 @@ -2511,9 +2513,22 @@ typedef struct serdes_corenet {  #define SRDS_PLLCR0_FRATE_SEL_4		0x00070000  #define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000  #define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000 +#define SRDS_PLLCR0_DCBIAS_OVRD		0x000000F0 +#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT	4  		u32	pllcr1; /* PLL Control Register 1 */ -#define SRDS_PLLCR1_PLL_BWSEL	0x08000000 -		u32	res_0c;	/* 0x00c */ +#define SRDS_PLLCR1_BCAP_EN		0x20000000 +#define SRDS_PLLCR1_BCAP_OVD		0x10000000 +#define SRDS_PLLCR1_PLL_FCAP		0x001F8000 +#define SRDS_PLLCR1_PLL_FCAP_SHIFT	15 +#define SRDS_PLLCR1_PLL_BWSEL		0x08000000 +#define SRDS_PLLCR1_BYP_CAL		0x02000000 +		u32	pllsr2;	/* At 0x00c, PLL Status Register 2 */ +#define SRDS_PLLSR2_BCAP_EN		0x00800000 +#define SRDS_PLLSR2_BCAP_EN_SHIFT	23 +#define SRDS_PLLSR2_FCAP		0x003F0000 +#define SRDS_PLLSR2_FCAP_SHIFT		16 +#define SRDS_PLLSR2_DCBIAS		0x000F0000 +#define SRDS_PLLSR2_DCBIAS_SHIFT	16  		u32	pllcr3;  		u32	pllcr4;  		u8	res_18[0x20-0x18]; |