diff options
Diffstat (limited to 'arch/powerpc/cpu')
36 files changed, 216 insertions, 179 deletions
diff --git a/arch/powerpc/cpu/mpc512x/cpu.c b/arch/powerpc/cpu/mpc512x/cpu.c index a1a3bd4ad..bb03c6d88 100644 --- a/arch/powerpc/cpu/mpc512x/cpu.c +++ b/arch/powerpc/cpu/mpc512x/cpu.c @@ -68,8 +68,8 @@ int checkcpu (void) } printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n", strmhz(buf1, clock), - strmhz(buf2, gd->csb_clk), - gd->reset_status & 0xffff); + strmhz(buf2, gd->arch.csb_clk), + gd->arch.reset_status & 0xffff); return 0; } diff --git a/arch/powerpc/cpu/mpc512x/cpu_init.c b/arch/powerpc/cpu/mpc512x/cpu_init.c index fe6beaf84..32ade1b0b 100644 --- a/arch/powerpc/cpu/mpc512x/cpu_init.c +++ b/arch/powerpc/cpu/mpc512x/cpu_init.c @@ -62,7 +62,7 @@ void cpu_init_f (volatile immap_t * im) #endif /* RSR - Reset Status Register - clear all status */ - gd->reset_status = im->reset.rsr; + gd->arch.reset_status = im->reset.rsr; out_be32(&im->reset.rsr, ~RSR_RES); /* diff --git a/arch/powerpc/cpu/mpc512x/i2c.c b/arch/powerpc/cpu/mpc512x/i2c.c index 0ea12806b..59040f83c 100644 --- a/arch/powerpc/cpu/mpc512x/i2c.c +++ b/arch/powerpc/cpu/mpc512x/i2c.c @@ -250,7 +250,7 @@ static int mpc_get_fdr (int speed) {126, 128} }; - ips = gd->ips_clk; + ips = gd->arch.ips_clk; for (i = 7; i >= 0; i--) { for (j = 7; j >= 0; j--) { scl = 2 * (scltap[j].scl2tap + diff --git a/arch/powerpc/cpu/mpc512x/ide.c b/arch/powerpc/cpu/mpc512x/ide.c index dd6b2f467..7a496734e 100644 --- a/arch/powerpc/cpu/mpc512x/ide.c +++ b/arch/powerpc/cpu/mpc512x/ide.c @@ -100,7 +100,7 @@ int ide_preinit (void) ide_set_reset(0); /* Init timings : we use PIO mode 0 timings */ - t = 1000000000 / gd->ips_clk; /* period in ns */ + t = 1000000000 / gd->arch.ips_clk; /* period in ns */ cfg.bytes.field1 = 3; cfg.bytes.field2 = 3; cfg.bytes.field3 = (pio_specs.t1 + t) / t; diff --git a/arch/powerpc/cpu/mpc512x/serial.c b/arch/powerpc/cpu/mpc512x/serial.c index 58587fd5b..3afbe8101 100644 --- a/arch/powerpc/cpu/mpc512x/serial.c +++ b/arch/powerpc/cpu/mpc512x/serial.c @@ -140,7 +140,7 @@ void serial_setbrg_dev(unsigned int idx) } /* calculate divisor for setting PSC CTUR and CTLR registers */ - baseclk = (gd->ips_clk + 8) / 16; + baseclk = (gd->arch.ips_clk + 8) / 16; div = (baseclk + (baudrate / 2)) / baudrate; out_8(&psc->ctur, (div >> 8) & 0xff); diff --git a/arch/powerpc/cpu/mpc512x/speed.c b/arch/powerpc/cpu/mpc512x/speed.c index 9d749f22e..9a8f315d8 100644 --- a/arch/powerpc/cpu/mpc512x/speed.c +++ b/arch/powerpc/cpu/mpc512x/speed.c @@ -113,9 +113,9 @@ int get_clocks (void) pci_clk = 333333; } - gd->ips_clk = ips_clk; + gd->arch.ips_clk = ips_clk; gd->pci_clk = pci_clk; - gd->csb_clk = csb_clk; + gd->arch.csb_clk = csb_clk; gd->cpu_clk = core_clk; gd->bus_clk = csb_clk; return 0; @@ -128,7 +128,7 @@ int get_clocks (void) *********************************************/ ulong get_bus_freq (ulong dummy) { - return gd->csb_clk; + return gd->arch.csb_clk; } int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) @@ -137,10 +137,13 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) printf("Clock configuration:\n"); printf(" CPU: %-4s MHz\n", strmhz(buf, gd->cpu_clk)); - printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk)); - printf(" IPS Bus: %-4s MHz\n", strmhz(buf, gd->ips_clk)); + printf(" Coherent System Bus: %-4s MHz\n", + strmhz(buf, gd->arch.csb_clk)); + printf(" IPS Bus: %-4s MHz\n", + strmhz(buf, gd->arch.ips_clk)); printf(" PCI: %-4s MHz\n", strmhz(buf, gd->pci_clk)); - printf(" DDR: %-4s MHz\n", strmhz(buf, 2*gd->csb_clk)); + printf(" DDR: %-4s MHz\n", + strmhz(buf, 2 * gd->arch.csb_clk)); return 0; } diff --git a/arch/powerpc/cpu/mpc5xxx/i2c.c b/arch/powerpc/cpu/mpc5xxx/i2c.c index b423d2fe3..8d5f47b1b 100644 --- a/arch/powerpc/cpu/mpc5xxx/i2c.c +++ b/arch/powerpc/cpu/mpc5xxx/i2c.c @@ -310,7 +310,7 @@ static int mpc_get_fdr(int speed) {126, 128} }; - ipb = gd->ipb_clk; + ipb = gd->arch.ipb_clk; for (i = 7; i >= 0; i--) { for (j = 7; j >= 0; j--) { scl = 2 * (scltap[j].scl2tap + diff --git a/arch/powerpc/cpu/mpc5xxx/ide.c b/arch/powerpc/cpu/mpc5xxx/ide.c index d337abb1c..094f62b6b 100644 --- a/arch/powerpc/cpu/mpc5xxx/ide.c +++ b/arch/powerpc/cpu/mpc5xxx/ide.c @@ -75,7 +75,7 @@ int ide_preinit (void) psdma->PtdCntrl |= 1; /* Init timings : we use PIO mode 0 timings */ - period = 1000000000 / gd->ipb_clk; /* period in ns */ + period = 1000000000 / gd->arch.ipb_clk; /* period in ns */ t0 = CALC_TIMING (600); t2_8 = CALC_TIMING (290); diff --git a/arch/powerpc/cpu/mpc5xxx/serial.c b/arch/powerpc/cpu/mpc5xxx/serial.c index eb141619b..1ccb4e35d 100644 --- a/arch/powerpc/cpu/mpc5xxx/serial.c +++ b/arch/powerpc/cpu/mpc5xxx/serial.c @@ -89,7 +89,7 @@ int serial_init_dev (unsigned long dev_base) /* select clock sources */ psc->psc_clock_select = 0; - baseclk = (gd->ipb_clk + 16) / 32; + baseclk = (gd->arch.ipb_clk + 16) / 32; /* switch to UART mode */ psc->sicr = 0; @@ -169,7 +169,7 @@ void serial_setbrg_dev (unsigned long dev_base) volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base; unsigned long baseclk, div; - baseclk = (gd->ipb_clk + 16) / 32; + baseclk = (gd->arch.ipb_clk + 16) / 32; /* set up UART divisor */ div = (baseclk + (gd->baudrate/2)) / gd->baudrate; diff --git a/arch/powerpc/cpu/mpc5xxx/speed.c b/arch/powerpc/cpu/mpc5xxx/speed.c index 8027d3e08..5353e3d53 100644 --- a/arch/powerpc/cpu/mpc5xxx/speed.c +++ b/arch/powerpc/cpu/mpc5xxx/speed.c @@ -66,14 +66,20 @@ int get_clocks (void) val = *(vu_long *)MPC5XXX_CDM_CFG; if (val & (1 << 8)) { - gd->ipb_clk = gd->bus_clk / 2; + gd->arch.ipb_clk = gd->bus_clk / 2; } else { - gd->ipb_clk = gd->bus_clk; + gd->arch.ipb_clk = gd->bus_clk; } switch (val & 3) { - case 0: gd->pci_clk = gd->ipb_clk; break; - case 1: gd->pci_clk = gd->ipb_clk / 2; break; - default: gd->pci_clk = gd->bus_clk / 4; break; + case 0: + gd->pci_clk = gd->arch.ipb_clk; + break; + case 1: + gd->pci_clk = gd->arch.ipb_clk / 2; + break; + default: + gd->pci_clk = gd->bus_clk / 4; + break; } return (0); @@ -85,7 +91,7 @@ int prt_mpc5xxx_clks (void) printf (" Bus %s MHz, IPB %s MHz, PCI %s MHz\n", strmhz(buf1, gd->bus_clk), - strmhz(buf2, gd->ipb_clk), + strmhz(buf2, gd->arch.ipb_clk), strmhz(buf3, gd->pci_clk) ); return (0); diff --git a/arch/powerpc/cpu/mpc8220/fec.c b/arch/powerpc/cpu/mpc8220/fec.c index aaf9be107..43fa802ca 100644 --- a/arch/powerpc/cpu/mpc8220/fec.c +++ b/arch/powerpc/cpu/mpc8220/fec.c @@ -288,9 +288,11 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis) * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. */ - /* tbd - rtm */ - /*fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); */ - /* No MII for 7-wire mode */ + /* + * tbd - rtm + * fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1); + * No MII for 7-wire mode + */ fec->eth->mii_speed = 0x00000030; } diff --git a/arch/powerpc/cpu/mpc8220/speed.c b/arch/powerpc/cpu/mpc8220/speed.c index 62ac845b7..bb72e5ce1 100644 --- a/arch/powerpc/cpu/mpc8220/speed.c +++ b/arch/powerpc/cpu/mpc8220/speed.c @@ -71,7 +71,7 @@ int get_clocks (void) #error clock measuring not implemented yet - define CONFIG_SYS_MPC8220_CLKIN #endif - gd->inp_clk = CONFIG_SYS_MPC8220_CLKIN; + gd->arch.inp_clk = CONFIG_SYS_MPC8220_CLKIN; /* Read XLB to PCI(INP) clock multiplier */ pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) & @@ -85,7 +85,7 @@ int get_clocks (void) /* FlexBus is temporary set as the same as input clock */ /* will do dynamic in the future */ - gd->flb_clk = CONFIG_SYS_MPC8220_CLKIN; + gd->arch.flb_clk = CONFIG_SYS_MPC8220_CLKIN; /* CPU Clock - Read HID1 */ asm volatile ("mfspr %0, 1009":"=r" (hid1):); @@ -97,12 +97,14 @@ int get_clocks (void) for (i = 0; i < size; i++) if (hid1 == bus2core[i].hid1) { gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1; - gd->vco_clk = CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2; + gd->arch.vco_clk = + CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER * + (gd->pci_clk * bus2core[i].vco_div) / 2; break; } /* hardcoded 81MHz for now */ - gd->pev_clk = 81000000; + gd->arch.pev_clk = 81000000; return (0); } @@ -115,7 +117,7 @@ int prt_mpc8220_clks (void) strmhz(buf1, gd->bus_clk), strmhz(buf2, gd->cpu_clk), strmhz(buf3, gd->pci_clk), - strmhz(buf4, gd->vco_clk) + strmhz(buf4, gd->arch.vco_clk) ); return (0); } diff --git a/arch/powerpc/cpu/mpc8260/commproc.c b/arch/powerpc/cpu/mpc8260/commproc.c index 082957ee0..22cef3e98 100644 --- a/arch/powerpc/cpu/mpc8260/commproc.c +++ b/arch/powerpc/cpu/mpc8260/commproc.c @@ -30,8 +30,8 @@ m8260_cpm_reset(void) /* Reclaim the DP memory for our use. */ - gd->dp_alloc_base = CPM_DATAONLY_BASE; - gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE; + gd->arch.dp_alloc_base = CPM_DATAONLY_BASE; + gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE; /* * Reset CPM @@ -60,21 +60,22 @@ m8260_cpm_dpalloc(uint size, uint align) uint savebase; align_mask = align - 1; - savebase = gd->dp_alloc_base; + savebase = gd->arch.dp_alloc_base; - if ((off = (gd->dp_alloc_base & align_mask)) != 0) - gd->dp_alloc_base += (align - off); + off = gd->arch.dp_alloc_base & align_mask; + if (off != 0) + gd->arch.dp_alloc_base += (align - off); if ((off = size & align_mask) != 0) size += align - off; - if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) { - gd->dp_alloc_base = savebase; + if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) { + gd->arch.dp_alloc_base = savebase; panic("m8260_cpm_dpalloc: ran out of dual port ram!"); } - retloc = gd->dp_alloc_base; - gd->dp_alloc_base += size; + retloc = gd->arch.dp_alloc_base; + gd->arch.dp_alloc_base += size; memset((void *)&immr->im_dprambase[retloc], 0, size); @@ -101,7 +102,7 @@ m8260_cpm_hostalloc(uint size, uint align) * Baud rate clocks are zero-based in the driver code (as that maps * to port numbers). Documentation uses 1-based numbering. */ -#define BRG_INT_CLK gd->brg_clk +#define BRG_INT_CLK gd->arch.brg_clk #define BRG_UART_CLK (BRG_INT_CLK / 16) /* This function is used by UARTs, or anything else that uses a 16x diff --git a/arch/powerpc/cpu/mpc8260/cpu_init.c b/arch/powerpc/cpu/mpc8260/cpu_init.c index acd48a9f5..3964e607d 100644 --- a/arch/powerpc/cpu/mpc8260/cpu_init.c +++ b/arch/powerpc/cpu/mpc8260/cpu_init.c @@ -120,7 +120,7 @@ void cpu_init_f (volatile immap_t * immr) memset ((void *) gd, 0, sizeof (gd_t)); /* RSR - Reset Status Register - clear all status (5-4) */ - gd->reset_status = immr->im_clkrst.car_rsr; + gd->arch.reset_status = immr->im_clkrst.car_rsr; immr->im_clkrst.car_rsr = RSR_ALLBITS; /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */ @@ -274,7 +274,7 @@ int prt_8260_rsr (void) RSR_EHRS, "External Hard"} }; static int n = sizeof bits / sizeof bits[0]; - ulong rsr = gd->reset_status; + ulong rsr = gd->arch.reset_status; int i; char *sep; diff --git a/arch/powerpc/cpu/mpc8260/i2c.c b/arch/powerpc/cpu/mpc8260/i2c.c index 7382cbadc..b720b1fb8 100644 --- a/arch/powerpc/cpu/mpc8260/i2c.c +++ b/arch/powerpc/cpu/mpc8260/i2c.c @@ -259,7 +259,7 @@ void i2c_init(int speed, int slaveadd) * divide BRGCLK by 1) */ debug("[I2C] Setting rate...\n"); - i2c_setrate(gd->brg_clk, CONFIG_SYS_I2C_SPEED); + i2c_setrate(gd->arch.brg_clk, CONFIG_SYS_I2C_SPEED); /* Set I2C controller in master mode */ i2c->i2c_i2com = 0x01; diff --git a/arch/powerpc/cpu/mpc8260/speed.c b/arch/powerpc/cpu/mpc8260/speed.c index bb50dee96..7841e8a89 100644 --- a/arch/powerpc/cpu/mpc8260/speed.c +++ b/arch/powerpc/cpu/mpc8260/speed.c @@ -135,17 +135,17 @@ int get_clocks (void) (get_pvr () == PVR_8260_HIP7R1) || (get_pvr () == PVR_8260_HIP7RA)) { pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT; - gd->vco_out = clkin * (pllmf + 1); + gd->arch.vco_out = clkin * (pllmf + 1); } else { /* HiP3, HiP4 */ pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; plldf = (scmr & SCMR_PLLDF) ? 1 : 0; - gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1); + gd->arch.vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1); } - gd->cpm_clk = gd->vco_out / 2; + gd->arch.cpm_clk = gd->arch.vco_out / 2; gd->bus_clk = clkin; - gd->scc_clk = gd->vco_out / 4; - gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); + gd->arch.scc_clk = gd->arch.vco_out / 4; + gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); if (cp->b2c_mult > 0) { gd->cpu_clk = (clkin * cp->b2c_mult) / 2; @@ -173,7 +173,7 @@ int get_clocks (void) pci_div = pcidf + 1; } - gd->pci_clk = (gd->cpm_clk * 2) / pci_div; + gd->pci_clk = (gd->arch.cpm_clk * 2) / pci_div; } #endif @@ -231,10 +231,10 @@ int prt_8260_clks (void) plldf, pllmf, pcidf); printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n", - gd->vco_out, gd->scc_clk, gd->brg_clk); + gd->arch.vco_out, gd->arch.scc_clk, gd->arch.brg_clk); printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n", - gd->cpu_clk, gd->cpm_clk, gd->bus_clk); + gd->cpu_clk, gd->arch.cpm_clk, gd->bus_clk); #ifdef CONFIG_PCI printf (" - pci_clk %10ld\n", gd->pci_clk); #endif diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index e64b0c341..cc2023429 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -122,7 +122,7 @@ int checkcpu(void) printf(" at %s MHz, ", strmhz(buf, clock)); - printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk)); + printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk)); return 0; } diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 20d06003e..515335196 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -232,12 +232,12 @@ void cpu_init_f (volatile immap_t * im) clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val); /* RSR - Reset Status Register - clear all status (4.6.1.3) */ - gd->reset_status = __raw_readl(&im->reset.rsr); + gd->arch.reset_status = __raw_readl(&im->reset.rsr); __raw_writel(~(RSR_RES), &im->reset.rsr); /* AER - Arbiter Event Register - store status */ - gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr); - gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr); + gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr); + gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr); /* * RMR - Reset Mode Register @@ -440,42 +440,44 @@ static int print_83xx_arb_event(int force) "reserved" }; - int etype = (gd->arbiter_event_attributes & AEATR_EVENT) + int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT) >> AEATR_EVENT_SHIFT; - int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID) + int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID) >> AEATR_MSTR_ID_SHIFT; - int tbst = (gd->arbiter_event_attributes & AEATR_TBST) + int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST) >> AEATR_TBST_SHIFT; - int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE) + int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE) >> AEATR_TSIZE_SHIFT; - int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE) + int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE) >> AEATR_TTYPE_SHIFT; - if (!force && !gd->arbiter_event_address) + if (!force && !gd->arch.arbiter_event_address) return 0; puts("Arbiter Event Status:\n"); - printf(" Event Address: 0x%08lX\n", gd->arbiter_event_address); + printf(" Event Address: 0x%08lX\n", + gd->arch.arbiter_event_address); printf(" Event Type: 0x%1x = %s\n", etype, event[etype]); printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]); printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize, tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize); printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]); - return gd->arbiter_event_address; + return gd->arch.arbiter_event_address; } #elif defined(CONFIG_DISPLAY_AER_BRIEF) static int print_83xx_arb_event(int force) { - if (!force && !gd->arbiter_event_address) + if (!force && !gd->arch.arbiter_event_address) return 0; printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n", - gd->arbiter_event_attributes, gd->arbiter_event_address); + gd->arch.arbiter_event_attributes, + gd->arch.arbiter_event_address); - return gd->arbiter_event_address; + return gd->arch.arbiter_event_address; } #endif /* CONFIG_DISPLAY_AER_xxxx */ @@ -499,7 +501,7 @@ int prt_83xx_rsr(void) RSR_HRS, "External/Internal Hard"} }; static int n = sizeof bits / sizeof bits[0]; - ulong rsr = gd->reset_status; + ulong rsr = gd->arch.reset_status; int i; char *sep; diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index 1f54781b7..fe553a74f 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -118,7 +118,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "clock-frequency", gd->core_clk, 1); + "clock-frequency", gd->arch.core_clk, 1); do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,soc", diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index 52d446175..609b13321 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -286,8 +286,8 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) get_clocks(); /* Configure the PCIE controller core clock ratio */ out_le32(hose_cfg_base + PEX_GCLK_RATIO, - (((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16) - / 333); + (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk) + / 1000000) * 16) / 333); udelay(1000000); /* Do Type 1 bridge configuration */ diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index b8c05d159..6be0e3a2e 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -462,53 +462,53 @@ int get_clocks(void) brg_clk = qe_clk / 2; #endif - gd->csb_clk = csb_clk; + gd->arch.csb_clk = csb_clk; #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) - gd->tsec1_clk = tsec1_clk; - gd->tsec2_clk = tsec2_clk; - gd->usbdr_clk = usbdr_clk; + gd->arch.tsec1_clk = tsec1_clk; + gd->arch.tsec2_clk = tsec2_clk; + gd->arch.usbdr_clk = usbdr_clk; #elif defined(CONFIG_MPC8309) - gd->usbdr_clk = usbdr_clk; + gd->arch.usbdr_clk = usbdr_clk; #endif #if defined(CONFIG_MPC834x) - gd->usbmph_clk = usbmph_clk; + gd->arch.usbmph_clk = usbmph_clk; #endif #if defined(CONFIG_MPC8315) - gd->tdm_clk = tdm_clk; + gd->arch.tdm_clk = tdm_clk; #endif #if defined(CONFIG_FSL_ESDHC) - gd->sdhc_clk = sdhc_clk; + gd->arch.sdhc_clk = sdhc_clk; #endif - gd->core_clk = core_clk; - gd->i2c1_clk = i2c1_clk; + gd->arch.core_clk = core_clk; + gd->arch.i2c1_clk = i2c1_clk; #if !defined(CONFIG_MPC832x) - gd->i2c2_clk = i2c2_clk; + gd->arch.i2c2_clk = i2c2_clk; #endif #if !defined(CONFIG_MPC8309) - gd->enc_clk = enc_clk; + gd->arch.enc_clk = enc_clk; #endif - gd->lbiu_clk = lbiu_clk; - gd->lclk_clk = lclk_clk; + gd->arch.lbiu_clk = lbiu_clk; + gd->arch.lclk_clk = lclk_clk; gd->mem_clk = mem_clk; #if defined(CONFIG_MPC8360) - gd->mem_sec_clk = mem_sec_clk; + gd->arch.mem_sec_clk = mem_sec_clk; #endif #if defined(CONFIG_QE) - gd->qe_clk = qe_clk; - gd->brg_clk = brg_clk; + gd->arch.qe_clk = qe_clk; + gd->arch.brg_clk = brg_clk; #endif #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) - gd->pciexp1_clk = pciexp1_clk; - gd->pciexp2_clk = pciexp2_clk; + gd->arch.pciexp1_clk = pciexp1_clk; + gd->arch.pciexp2_clk = pciexp2_clk; #endif #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) - gd->sata_clk = sata_clk; + gd->arch.sata_clk = sata_clk; #endif gd->pci_clk = pci_sync_in; - gd->cpu_clk = gd->core_clk; - gd->bus_clk = gd->csb_clk; + gd->cpu_clk = gd->arch.core_clk; + gd->bus_clk = gd->arch.csb_clk; return 0; } @@ -519,7 +519,7 @@ int get_clocks(void) *********************************************/ ulong get_bus_freq(ulong dummy) { - return gd->csb_clk; + return gd->arch.csb_clk; } /******************************************** @@ -536,49 +536,69 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char buf[32]; printf("Clock configuration:\n"); - printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk)); - printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk)); + printf(" Core: %-4s MHz\n", + strmhz(buf, gd->arch.core_clk)); + printf(" Coherent System Bus: %-4s MHz\n", + strmhz(buf, gd->arch.csb_clk)); #if defined(CONFIG_QE) - printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk)); - printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk)); + printf(" QE: %-4s MHz\n", + strmhz(buf, gd->arch.qe_clk)); + printf(" BRG: %-4s MHz\n", + strmhz(buf, gd->arch.brg_clk)); #endif - printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk)); - printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk)); + printf(" Local Bus Controller:%-4s MHz\n", + strmhz(buf, gd->arch.lbiu_clk)); + printf(" Local Bus: %-4s MHz\n", + strmhz(buf, gd->arch.lclk_clk)); printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk)); #if defined(CONFIG_MPC8360) - printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk)); + printf(" DDR Secondary: %-4s MHz\n", + strmhz(buf, gd->arch.mem_sec_clk)); #endif #if !defined(CONFIG_MPC8309) - printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk)); + printf(" SEC: %-4s MHz\n", + strmhz(buf, gd->arch.enc_clk)); #endif - printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk)); + printf(" I2C1: %-4s MHz\n", + strmhz(buf, gd->arch.i2c1_clk)); #if !defined(CONFIG_MPC832x) - printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk)); + printf(" I2C2: %-4s MHz\n", + strmhz(buf, gd->arch.i2c2_clk)); #endif #if defined(CONFIG_MPC8315) - printf(" TDM: %-4s MHz\n", strmhz(buf, gd->tdm_clk)); + printf(" TDM: %-4s MHz\n", + strmhz(buf, gd->arch.tdm_clk)); #endif #if defined(CONFIG_FSL_ESDHC) - printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk)); + printf(" SDHC: %-4s MHz\n", + strmhz(buf, gd->arch.sdhc_clk)); #endif #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) - printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk)); - printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk)); - printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk)); + printf(" TSEC1: %-4s MHz\n", + strmhz(buf, gd->arch.tsec1_clk)); + printf(" TSEC2: %-4s MHz\n", + strmhz(buf, gd->arch.tsec2_clk)); + printf(" USB DR: %-4s MHz\n", + strmhz(buf, gd->arch.usbdr_clk)); #elif defined(CONFIG_MPC8309) - printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk)); + printf(" USB DR: %-4s MHz\n", + strmhz(buf, gd->arch.usbdr_clk)); #endif #if defined(CONFIG_MPC834x) - printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk)); + printf(" USB MPH: %-4s MHz\n", + strmhz(buf, gd->arch.usbmph_clk)); #endif #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ defined(CONFIG_MPC837x) - printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk)); - printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk)); + printf(" PCIEXP1: %-4s MHz\n", + strmhz(buf, gd->arch.pciexp1_clk)); + printf(" PCIEXP2: %-4s MHz\n", + strmhz(buf, gd->arch.pciexp2_clk)); #endif #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315) - printf(" SATA: %-4s MHz\n", strmhz(buf, gd->sata_clk)); + printf(" SATA: %-4s MHz\n", + strmhz(buf, gd->arch.sata_clk)); #endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/commproc.c b/arch/powerpc/cpu/mpc85xx/commproc.c index 292b723dc..37e706238 100644 --- a/arch/powerpc/cpu/mpc85xx/commproc.c +++ b/arch/powerpc/cpu/mpc85xx/commproc.c @@ -43,8 +43,8 @@ m8560_cpm_reset(void) /* Reclaim the DP memory for our use. */ - gd->dp_alloc_base = CPM_DATAONLY_BASE; - gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE; + gd->arch.dp_alloc_base = CPM_DATAONLY_BASE; + gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE; /* * Reset CPM @@ -69,21 +69,22 @@ m8560_cpm_dpalloc(uint size, uint align) uint savebase; align_mask = align - 1; - savebase = gd->dp_alloc_base; + savebase = gd->arch.dp_alloc_base; - if ((off = (gd->dp_alloc_base & align_mask)) != 0) - gd->dp_alloc_base += (align - off); + off = gd->arch.dp_alloc_base & align_mask; + if (off != 0) + gd->arch.dp_alloc_base += (align - off); if ((off = size & align_mask) != 0) size += align - off; - if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) { - gd->dp_alloc_base = savebase; + if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) { + gd->arch.dp_alloc_base = savebase; panic("m8560_cpm_dpalloc: ran out of dual port ram!"); } - retloc = gd->dp_alloc_base; - gd->dp_alloc_base += size; + retloc = gd->arch.dp_alloc_base; + gd->arch.dp_alloc_base += size; memset((void *)&(cpm->im_dprambase[retloc]), 0, size); @@ -110,7 +111,7 @@ m8560_cpm_hostalloc(uint size, uint align) * Baud rate clocks are zero-based in the driver code (as that maps * to port numbers). Documentation uses 1-based numbering. */ -#define BRG_INT_CLK gd->brg_clk +#define BRG_INT_CLK gd->arch.brg_clk #define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16) /* This function is used by UARTS, or anything else that uses a 16x diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 9b9832cfc..df2ab6d73 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -104,7 +104,7 @@ int checkcpu (void) puts("CPU: "); } - cpu = gd->cpu; + cpu = gd->arch.cpu; puts(cpu->name); if (IS_E_PROCESSOR(svr)) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 3a268aa0a..d381cf9da 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -637,9 +637,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_compat_u32(blob, "fsl,pq3-localbus", - "bus-frequency", gd->lbc_clk, 1); + "bus-frequency", gd->arch.lbc_clk, 1); do_fixup_by_compat_u32(blob, "fsl,elbc", - "bus-frequency", gd->lbc_clk, 1); + "bus-frequency", gd->arch.lbc_clk, 1); #ifdef CONFIG_QE ft_qe_setup(blob); ft_fixup_qe_snum(blob); diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 801ee078c..297f2ed47 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -391,11 +391,11 @@ int get_clocks (void) gd->cpu_clk = sys_info.freqProcessor[0]; gd->bus_clk = sys_info.freqSystemBus; gd->mem_clk = sys_info.freqDDRBus; - gd->lbc_clk = sys_info.freqLocalBus; + gd->arch.lbc_clk = sys_info.freqLocalBus; #ifdef CONFIG_QE - gd->qe_clk = sys_info.freqQE; - gd->brg_clk = gd->qe_clk / 2; + gd->arch.qe_clk = sys_info.freqQE; + gd->arch.brg_clk = gd->arch.qe_clk / 2; #endif /* * The base clock for I2C depends on the actual SOC. Unfortunately, @@ -406,7 +406,7 @@ int get_clocks (void) */ #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) - gd->i2c1_clk = sys_info.freqSystemBus; + gd->arch.i2c1_clk = sys_info.freqSystemBus; #elif defined(CONFIG_MPC8544) /* * On the 8544, the I2C clock is the same as the SEC clock. This can be @@ -416,29 +416,29 @@ int get_clocks (void) * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. */ if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) - gd->i2c1_clk = sys_info.freqSystemBus / 3; + gd->arch.i2c1_clk = sys_info.freqSystemBus / 3; else - gd->i2c1_clk = sys_info.freqSystemBus / 2; + gd->arch.i2c1_clk = sys_info.freqSystemBus / 2; #else /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ - gd->i2c1_clk = sys_info.freqSystemBus / 2; + gd->arch.i2c1_clk = sys_info.freqSystemBus / 2; #endif - gd->i2c2_clk = gd->i2c1_clk; + gd->arch.i2c2_clk = gd->arch.i2c1_clk; #if defined(CONFIG_FSL_ESDHC) #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\ defined(CONFIG_P1014) - gd->sdhc_clk = gd->bus_clk; + gd->arch.sdhc_clk = gd->bus_clk; #else - gd->sdhc_clk = gd->bus_clk / 2; + gd->arch.sdhc_clk = gd->bus_clk / 2; #endif #endif /* defined(CONFIG_FSL_ESDHC) */ #if defined(CONFIG_CPM2) - gd->vco_out = 2*sys_info.freqSystemBus; - gd->cpm_clk = gd->vco_out / 2; - gd->scc_clk = gd->vco_out / 4; - gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1))); + gd->arch.vco_out = 2*sys_info.freqSystemBus; + gd->arch.cpm_clk = gd->arch.vco_out / 2; + gd->arch.scc_clk = gd->arch.vco_out / 4; + gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1))); #endif if(gd->cpu_clk != 0) return (0); diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 23d33574a..0dff37f77 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -99,7 +99,7 @@ static inline void use_tlb_cam(u8 idx) int i = idx / 32; int bit = idx % 32; - gd->used_tlb_cams[i] |= (1 << bit); + gd->arch.used_tlb_cams[i] |= (1 << bit); } static inline void free_tlb_cam(u8 idx) @@ -107,7 +107,7 @@ static inline void free_tlb_cam(u8 idx) int i = idx / 32; int bit = idx % 32; - gd->used_tlb_cams[i] &= ~(1 << bit); + gd->arch.used_tlb_cams[i] &= ~(1 << bit); } void init_used_tlb_cams(void) @@ -116,7 +116,7 @@ void init_used_tlb_cams(void) unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) - gd->used_tlb_cams[i] = 0; + gd->arch.used_tlb_cams[i] = 0; /* walk all the entries */ for (i = 0; i < num_cam; i++) { @@ -133,7 +133,7 @@ int find_free_tlbcam(void) u32 idx; for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) { - idx = ffz(gd->used_tlb_cams[i]); + idx = ffz(gd->arch.used_tlb_cams[i]); if (idx != 32) break; diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c index d2c8c78e8..c553415b5 100644 --- a/arch/powerpc/cpu/mpc86xx/cpu.c +++ b/arch/powerpc/cpu/mpc86xx/cpu.c @@ -67,7 +67,7 @@ checkcpu(void) } puts("CPU: "); - cpu = gd->cpu; + cpu = gd->arch.cpu; puts(cpu->name); diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index 2f955fe93..26a65c586 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -34,10 +34,10 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_MPC8641) do_fixup_by_compat_u32(blob, "fsl,mpc8641-localbus", - "bus-frequency", gd->lbc_clk, 1); + "bus-frequency", gd->arch.lbc_clk, 1); #endif do_fixup_by_compat_u32(blob, "fsl,elbc", - "bus-frequency", gd->lbc_clk, 1); + "bus-frequency", gd->arch.lbc_clk, 1); fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c index a2d0a8ac6..18c1eea0c 100644 --- a/arch/powerpc/cpu/mpc86xx/speed.c +++ b/arch/powerpc/cpu/mpc86xx/speed.c @@ -120,7 +120,7 @@ int get_clocks(void) get_sys_info(&sys_info); gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; - gd->lbc_clk = sys_info.freqLocalBus; + gd->arch.lbc_clk = sys_info.freqLocalBus; /* * The base clock for I2C depends on the actual SOC. Unfortunately, @@ -130,11 +130,11 @@ int get_clocks(void) * AN2919. */ #ifdef CONFIG_MPC8610 - gd->i2c1_clk = sys_info.freqSystemBus; + gd->arch.i2c1_clk = sys_info.freqSystemBus; #else - gd->i2c1_clk = sys_info.freqSystemBus / 2; + gd->arch.i2c1_clk = sys_info.freqSystemBus / 2; #endif - gd->i2c2_clk = gd->i2c1_clk; + gd->arch.i2c2_clk = gd->arch.i2c1_clk; if (gd->cpu_clk != 0) return 0; diff --git a/arch/powerpc/cpu/mpc8xx/commproc.c b/arch/powerpc/cpu/mpc8xx/commproc.c index 5fe01fffa..a36478209 100644 --- a/arch/powerpc/cpu/mpc8xx/commproc.c +++ b/arch/powerpc/cpu/mpc8xx/commproc.c @@ -31,8 +31,8 @@ DECLARE_GLOBAL_DATA_PTR; int dpram_init (void) { /* Reclaim the DP memory for our use. */ - gd->dp_alloc_base = CPM_DATAONLY_BASE; - gd->dp_alloc_top = CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE; + gd->arch.dp_alloc_base = CPM_DATAONLY_BASE; + gd->arch.dp_alloc_top = CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE; return (0); } @@ -43,19 +43,19 @@ int dpram_init (void) */ uint dpram_alloc (uint size) { - uint addr = gd->dp_alloc_base; + uint addr = gd->arch.dp_alloc_base; - if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) + if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) return (CPM_DP_NOSPACE); - gd->dp_alloc_base += size; + gd->arch.dp_alloc_base += size; return addr; } uint dpram_base (void) { - return gd->dp_alloc_base; + return gd->arch.dp_alloc_base; } /* Allocate some memory from the dual ported ram. We may want to @@ -66,12 +66,12 @@ uint dpram_alloc_align (uint size, uint align) { uint addr, mask = align - 1; - addr = (gd->dp_alloc_base + mask) & ~mask; + addr = (gd->arch.dp_alloc_base + mask) & ~mask; - if ((addr + size) >= gd->dp_alloc_top) + if ((addr + size) >= gd->arch.dp_alloc_top) return (CPM_DP_NOSPACE); - gd->dp_alloc_base = addr + size; + gd->arch.dp_alloc_base = addr + size; return addr; } @@ -80,6 +80,6 @@ uint dpram_base_align (uint align) { uint mask = align - 1; - return (gd->dp_alloc_base + mask) & ~mask; + return (gd->arch.dp_alloc_base + mask) & ~mask; } #endif /* CONFIG_SYS_ALLOC_DPRAM */ diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c index 7130983ff..7edd7e420 100644 --- a/arch/powerpc/cpu/mpc8xx/fdt.c +++ b/arch/powerpc/cpu/mpc8xx/fdt.c @@ -37,7 +37,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", bd->bi_intfreq, 1); do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", - gd->brg_clk, 1); + gd->arch.brg_clk, 1); /* Fixup ethernet MAC addresses */ fdt_fixup_ethernet(blob); diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c index 6e13e5de0..091b49f24 100644 --- a/arch/powerpc/cpu/mpc8xx/speed.c +++ b/arch/powerpc/cpu/mpc8xx/speed.c @@ -192,7 +192,7 @@ void get_brgclk(uint sccr) divider = 64; break; } - gd->brg_clk = gd->cpu_clk/divider; + gd->arch.brg_clk = gd->cpu_clk/divider; } #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index ab454f50d..39525fb29 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -148,7 +148,7 @@ struct cpu_type *identify_cpu(u32 ver) u32 cpu_mask(void) { ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; - struct cpu_type *cpu = gd->cpu; + struct cpu_type *cpu = gd->arch.cpu; /* better to query feature reporting register than just assume 1 */ if (cpu == &cpu_type_unknown) @@ -166,7 +166,7 @@ u32 cpu_mask(void) */ int cpu_numcores(void) { - struct cpu_type *cpu = gd->cpu; + struct cpu_type *cpu = gd->arch.cpu; /* * Report # of cores in terms of the cpu_mask if we haven't @@ -196,7 +196,7 @@ int probecpu (void) svr = get_svr(); ver = SVR_SOC_VER(svr); - gd->cpu = identify_cpu(ver); + gd->arch.cpu = identify_cpu(ver); return 0; } @@ -204,7 +204,7 @@ int probecpu (void) /* Once in memory, compute mask & # cores once and save them off */ int fixup_cpu(void) { - struct cpu_type *cpu = gd->cpu; + struct cpu_type *cpu = gd->arch.cpu; if (cpu->num_cores == 0) { cpu->mask = cpu_mask(); diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index ce1d71e30..6f9d5683a 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -69,7 +69,7 @@ static inline void set_law_base_addr(int idx, phys_addr_t addr) void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { - gd->used_laws |= (1 << idx); + gd->arch.used_laws |= (1 << idx); out_be32(LAWAR_ADDR(idx), 0); set_law_base_addr(idx, addr); @@ -81,7 +81,7 @@ void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) void disable_law(u8 idx) { - gd->used_laws &= ~(1 << idx); + gd->arch.used_laws &= ~(1 << idx); out_be32(LAWAR_ADDR(idx), 0); set_law_base_addr(idx, 0); @@ -112,7 +112,7 @@ static int get_law_entry(u8 i, struct law_entry *e) int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { - u32 idx = ffz(gd->used_laws); + u32 idx = ffz(gd->arch.used_laws); if (idx >= FSL_HW_NUM_LAWS) return -1; @@ -128,11 +128,11 @@ int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) u32 idx; /* we have no LAWs free */ - if (gd->used_laws == -1) + if (gd->arch.used_laws == -1) return -1; /* grab the last free law */ - idx = __ilog2(~(gd->used_laws)); + idx = __ilog2(~(gd->arch.used_laws)); if (idx >= FSL_HW_NUM_LAWS) return -1; @@ -240,9 +240,9 @@ void init_laws(void) int i; #if FSL_HW_NUM_LAWS < 32 - gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); + gd->arch.used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); #elif FSL_HW_NUM_LAWS == 32 - gd->used_laws = 0; + gd->arch.used_laws = 0; #else #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes #endif @@ -255,7 +255,7 @@ void init_laws(void) u32 lawar = in_be32(LAWAR_ADDR(i)); if (lawar & LAW_EN) - gd->used_laws |= (1 << i); + gd->arch.used_laws |= (1 << i); } #if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \ diff --git a/arch/powerpc/cpu/ppc4xx/4xx_uart.c b/arch/powerpc/cpu/ppc4xx/4xx_uart.c index 38ba60bb0..2ab185f0f 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_uart.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_uart.c @@ -296,10 +296,10 @@ int get_serial_clock(void) * the UART divisor is available */ #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK - gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK; + gd->arch.uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK; #else get_sys_info(&sys_info); - gd->uart_clk = sys_info.freqUART / udiv; + gd->arch.uart_clk = sys_info.freqUART / udiv; #endif return clk; diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c index 5ddb88024..37f5817f2 100644 --- a/arch/powerpc/cpu/ppc4xx/fdt.c +++ b/arch/powerpc/cpu/ppc4xx/fdt.c @@ -141,7 +141,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) /* * Fixup all UART clocks for CPU internal UARTs - * (only these UARTs are definitely clocked by gd->uart_clk) + * (only these UARTs are definitely clocked by gd->arch.uart_clk) * * These UARTs are direct childs of /plb/opb. This code * does not touch any UARTs that are connected to the ebc. @@ -160,7 +160,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) (fdt_node_check_compatible(blob, off, "ns16550") == 0)) fdt_setprop(blob, off, "clock-frequency", - (void*)&(gd->uart_clk), 4); + (void *)&gd->arch.uart_clk, 4); } /* |