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-rw-r--r--arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c20
-rw-r--r--arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c4
-rw-r--r--arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c32
-rw-r--r--arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c15
-rw-r--r--arch/powerpc/cpu/ppc4xx/4xx_pcie.c11
-rw-r--r--arch/powerpc/cpu/ppc4xx/cmd_ecctest.c9
-rw-r--r--arch/powerpc/cpu/ppc4xx/iop480_uart.c3
-rw-r--r--arch/powerpc/cpu/ppc4xx/usb_ohci.c3
8 files changed, 27 insertions, 70 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
index a31b17e9e..48aa75391 100644
--- a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
+++ b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
@@ -116,26 +116,25 @@ long int spd_sdram(int(read_spd)(uint addr))
{
int tmp,row,col;
int total_size,bank_size,bank_code;
- int ecc_on;
int mode;
int bank_cnt;
int sdram0_pmit=0x07c00000;
+ int sdram0_b0cr;
+ int sdram0_b1cr = 0;
#ifndef CONFIG_405EP /* not on PPC405EP */
+ int sdram0_b2cr = 0;
+ int sdram0_b3cr = 0;
int sdram0_besr0 = -1;
int sdram0_besr1 = -1;
int sdram0_eccesr = -1;
-#endif
int sdram0_ecccfg;
+ int ecc_on;
+#endif
int sdram0_rtr=0;
int sdram0_tr=0;
- int sdram0_b0cr;
- int sdram0_b1cr;
- int sdram0_b2cr;
- int sdram0_b3cr;
-
int sdram0_cfg=0;
int t_rp;
@@ -295,6 +294,7 @@ long int spd_sdram(int(read_spd)(uint addr))
if (bank_cnt > 4) /* we only have 4 banks to work with */
SPD_ERR("SDRAM - unsupported module rows for this width\n");
+#ifndef CONFIG_405EP /* not on PPC405EP */
/* now check for ECC ability of module. We only support ECC
* on 32 bit wide devices with 8 bit ECC.
*/
@@ -305,6 +305,7 @@ long int spd_sdram(int(read_spd)(uint addr))
sdram0_ecccfg = 0;
ecc_on = 0;
}
+#endif
/*------------------------------------------------------------------
* calculate total size
@@ -378,9 +379,6 @@ long int spd_sdram(int(read_spd)(uint addr))
* using the calculated values, compute the bank
* config register values.
* -------------------------------------------------------------------*/
- sdram0_b1cr = 0;
- sdram0_b2cr = 0;
- sdram0_b3cr = 0;
/* compute the size of each bank */
bank_size = total_size / bank_cnt;
@@ -444,8 +442,10 @@ long int spd_sdram(int(read_spd)(uint addr))
/* SDRAM have a power on delay, 500 micro should do */
udelay(500);
sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
+#ifndef CONFIG_405EP /* not on PPC405EP */
if (ecc_on)
sdram0_cfg |= SDRAM0_CFG_MEMCHK;
+#endif
mtsdram(SDRAM0_CFG, sdram0_cfg);
return (total_size);
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
index e05daf23b..8a20a2b1e 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
@@ -380,8 +380,6 @@ static void program_cfg0(unsigned long *dimm_populated,
unsigned char ecc;
unsigned char attributes;
unsigned long data_width;
- unsigned long dimm_32bit;
- unsigned long dimm_64bit;
/*
* get Memory Controller Options 0 data
@@ -423,10 +421,8 @@ static void program_cfg0(unsigned long *dimm_populated,
(unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
(((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
if (data_width == 64 || data_width == 72) {
- dimm_64bit = TRUE;
cfg0 |= SDRAM_CFG0_DMWD_64;
} else if (data_width == 32 || data_width == 40) {
- dimm_32bit = TRUE;
cfg0 |= SDRAM_CFG0_DMWD_32;
} else {
printf("WARNING: DIMM with datawidth of %lu bits.\n",
diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
index 4a2f33744..85217ea27 100644
--- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
@@ -445,9 +445,6 @@ static unsigned char spd_read(uchar chip, uint addr)
phys_size_t initdram(int board_type)
{
unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
- unsigned char spd0[MAX_SPD_BYTES];
- unsigned char spd1[MAX_SPD_BYTES];
- unsigned char *dimm_spd[MAXDIMMS];
unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
unsigned long num_dimm_banks; /* on board dimm banks */
unsigned long val;
@@ -458,12 +455,6 @@ phys_size_t initdram(int board_type)
num_dimm_banks = sizeof(iic0_dimm_addr);
/*------------------------------------------------------------------
- * Set up an array of SPD matrixes.
- *-----------------------------------------------------------------*/
- dimm_spd[0] = spd0;
- dimm_spd[1] = spd1;
-
- /*------------------------------------------------------------------
* Reset the DDR-SDRAM controller.
*-----------------------------------------------------------------*/
mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
@@ -1000,7 +991,6 @@ static void program_copt1(unsigned long *dimm_populated,
unsigned long attribute = 0;
unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
unsigned long bankcount;
- unsigned long ddrtype;
unsigned long val;
#ifdef CONFIG_DDR_ECC
@@ -1045,8 +1035,6 @@ static void program_copt1(unsigned long *dimm_populated,
else /* bank count = 8 */
mcopt1 |= SDRAM_MCOPT1_8_BANKS;
- /* test DDR type */
- ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
/* test for buffered/unbuffered, registered, differential clocks */
registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
@@ -1500,7 +1488,6 @@ static void program_mode(unsigned long *dimm_populated,
else
sdram_ddr1 = FALSE;
- /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
@@ -2490,12 +2477,6 @@ static void DQS_calibration_process(void)
unsigned long val;
long rffd_average;
long max_start;
- long min_end;
- unsigned long begin_rqfd[MAXRANKS];
- unsigned long begin_rffd[MAXRANKS];
- unsigned long end_rqfd[MAXRANKS];
- unsigned long end_rffd[MAXRANKS];
- char window_found;
unsigned long dlycal;
unsigned long dly_val;
unsigned long max_pass_length;
@@ -2506,6 +2487,7 @@ static void DQS_calibration_process(void)
unsigned char fail_found;
unsigned char pass_found;
#if !defined(CONFIG_DDR_RQDC_FIXED)
+ int window_found;
u32 rqdc_reg;
u32 rqfd;
u32 rqfd_start;
@@ -2559,16 +2541,6 @@ calibration_loop:
#endif /* CONFIG_DDR_RQDC_FIXED */
max_start = 0;
- min_end = 0;
- begin_rqfd[0] = 0;
- begin_rffd[0] = 0;
- begin_rqfd[1] = 0;
- begin_rffd[1] = 0;
- end_rqfd[0] = 0;
- end_rffd[0] = 0;
- end_rqfd[1] = 0;
- end_rffd[1] = 0;
- window_found = FALSE;
max_pass_length = 0;
max_start = 0;
@@ -2576,7 +2548,6 @@ calibration_loop:
current_pass_length = 0;
current_fail_length = 0;
current_start = 0;
- window_found = FALSE;
fail_found = FALSE;
pass_found = FALSE;
@@ -2621,7 +2592,6 @@ calibration_loop:
if (fail_found == FALSE) {
fail_found = TRUE;
} else if (pass_found == TRUE) {
- window_found = TRUE;
break;
}
}
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index 4b8e65a51..3c87bfb60 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -154,18 +154,20 @@ u32 ddr_rdss_opt(ulong) __attribute__((weak, alias("__ddr_rdss_opt")));
static u32 *get_membase(int bxcr_num)
{
- ulong bxcf;
u32 *membase;
#if defined(SDRAM_R0BAS)
/* BAS from Memory Queue rank reg. */
membase =
(u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
- bxcf = 0; /* just to satisfy the compiler */
#else
- /* BAS from SDRAM_MBxCF mem rank reg. */
- mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
- membase = (u32 *)((bxcf & 0xfff80000) << 3);
+ {
+ ulong bxcf;
+
+ /* BAS from SDRAM_MBxCF mem rank reg. */
+ mfsdram(SDRAM_MB0CF + (bxcr_num<<2), bxcf);
+ membase = (u32 *)((bxcf & 0xfff80000) << 3);
+ }
#endif
return membase;
@@ -719,7 +721,9 @@ static u32 program_DQS_calibration_methodB(struct ddrautocal *ddrcal)
static u32 DQS_calibration_methodB(struct ddrautocal *cal)
{
ulong rfdc_reg;
+#ifndef CONFIG_DDR_RFDC_FIXED
ulong rffd;
+#endif
ulong rqdc_reg;
ulong rqfd;
@@ -837,7 +841,6 @@ static u32 DQS_calibration_methodB(struct ddrautocal *cal)
mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
#endif /* CONFIG_DDR_RFDC_FIXED */
- rffd = rffd_average;
in_window = 0;
curr_win_min = curr_win_max = 0;
diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
index a87e93b80..43b972fbb 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
@@ -227,7 +227,6 @@ static void pcie_dmer_enable(void)
static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
int offset, int len, u32 *val) {
- u8 *address;
*val = 0;
if (validate_endpoint(hose))
@@ -255,7 +254,7 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
return 0;
- address = pcie_get_base(hose, devfn);
+ pcie_get_base(hose, devfn);
offset += devfn << 4;
/*
@@ -287,8 +286,6 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
int offset, int len, u32 val) {
- u8 *address;
-
if (validate_endpoint(hose))
return 0; /* No upstream config access */
@@ -307,7 +304,7 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
return 0;
- address = pcie_get_base(hose, devfn);
+ pcie_get_base(hose, devfn);
offset += devfn << 4;
/*
@@ -1063,7 +1060,6 @@ int ppc4xx_init_pcie_endport(int port)
void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
{
volatile void *mbase = NULL;
- volatile void *rmbase = NULL;
pci_set_ops(hose,
pcie_read_config_byte,
@@ -1076,18 +1072,15 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
switch (port) {
case 0:
mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
- rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE;
hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
break;
case 1:
mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
- rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE;
hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
break;
#if CONFIG_SYS_PCIE_NR_PORTS > 2
case 2:
mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
- rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE;
hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
break;
#endif
diff --git a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
index 542ab69a1..231f69ebd 100644
--- a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
+++ b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c
@@ -113,8 +113,6 @@ static force_inline void set_mcopt1_mchk(u32 bits)
*/
static void inject_ecc_error(void *ptr, int par)
{
- u32 val;
-
/*
* Taken from PPC460EX/EXr/GT users manual (Rev 1.21)
* 22.2.17.13 ECC Diagnostics
@@ -124,7 +122,7 @@ static void inject_ecc_error(void *ptr, int par)
*/
out_be32(ptr, 0x00000000);
- val = in_be32(ptr);
+ in_be32(ptr);
/* 6. Set memory controller to no error checking */
set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_NON);
@@ -136,7 +134,7 @@ static void inject_ecc_error(void *ptr, int par)
out_be32(ptr, in_be32(ptr) ^ 0x00000003);
/* 8. Wait for SDRAM idle */
- val = in_be32(ptr);
+ in_be32(ptr);
set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP);
/* Wait for SDRAM idle */
@@ -151,7 +149,6 @@ static void rewrite_ecc_parity(void *ptr, int par)
u32 end_address;
u32 address_increment;
u32 mcopt1;
- u32 val;
/*
* Fill ECC parity byte again. Otherwise further accesses to
@@ -159,7 +156,7 @@ static void rewrite_ecc_parity(void *ptr, int par)
*/
/* Wait for SDRAM idle */
- val = in_be32(0x00000000);
+ in_be32(0x00000000);
set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_GEN);
/* ECC bit set method for non-cached memory */
diff --git a/arch/powerpc/cpu/ppc4xx/iop480_uart.c b/arch/powerpc/cpu/ppc4xx/iop480_uart.c
index 0e3423f7a..027ca30c2 100644
--- a/arch/powerpc/cpu/ppc4xx/iop480_uart.c
+++ b/arch/powerpc/cpu/ppc4xx/iop480_uart.c
@@ -134,7 +134,6 @@ DECLARE_GLOBAL_DATA_PTR;
int serial_init (void)
{
- volatile char val;
unsigned short br_reg;
br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
@@ -149,7 +148,7 @@ int serial_init (void)
out_8((u8 *)SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
out_8((u8 *)SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
- val = in_8((u8 *)SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
+ in_8((u8 *)SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
return (0);
}
diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/ppc4xx/usb_ohci.c
index fe091e3fa..065730d88 100644
--- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c
+++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.c
@@ -753,10 +753,9 @@ static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buf
static void dl_transfer_length(td_t * td)
{
- __u32 tdINFO, tdBE, tdCBP;
+ __u32 tdBE, tdCBP;
urb_priv_t *lurb_priv = &urb_priv;
- tdINFO = ohci_cpu_to_le32 (td->hwINFO);
tdBE = ohci_cpu_to_le32 (td->hwBE);
tdCBP = ohci_cpu_to_le32 (td->hwCBP);
generated by cgit v1.2.3-70-g09d2 (git 2.51.2) at 2025-11-01 11:44:33 +0000