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-rw-r--r--arch/powerpc/cpu/ppc4xx/cpu_init.c8
-rw-r--r--arch/powerpc/cpu/ppc4xx/interrupts.c7
-rw-r--r--arch/powerpc/cpu/ppc4xx/start.S25
-rw-r--r--arch/powerpc/cpu/ppc4xx/traps.c11
4 files changed, 18 insertions, 33 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index 2a727b1df..bf208adfe 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -342,7 +342,7 @@ cpu_init_f (void)
#endif
#if defined(CONFIG_WATCHDOG)
- val = mfspr(tcr);
+ val = mfspr(SPRN_TCR);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
val |= 0xb8000000; /* generate system reset after 1.34 seconds */
#elif defined(CONFIG_440EPX)
@@ -354,11 +354,11 @@ cpu_init_f (void)
val &= ~0x30000000; /* clear WRC bits */
val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */
#endif
- mtspr(tcr, val);
+ mtspr(SPRN_TCR, val);
- val = mfspr(tsr);
+ val = mfspr(SPRN_TSR);
val |= 0x80000000; /* enable watchdog timer */
- mtspr(tsr, val);
+ mtspr(SPRN_TSR, val);
reset_4xx_watchdog();
#endif /* CONFIG_WATCHDOG */
diff --git a/arch/powerpc/cpu/ppc4xx/interrupts.c b/arch/powerpc/cpu/ppc4xx/interrupts.c
index c2d497398..d0bca92f9 100644
--- a/arch/powerpc/cpu/ppc4xx/interrupts.c
+++ b/arch/powerpc/cpu/ppc4xx/interrupts.c
@@ -67,13 +67,6 @@ static __inline__ void set_pit(unsigned long val)
asm volatile("mtpit %0" : : "r" (val));
}
-
-static __inline__ void set_tcr(unsigned long val)
-{
- asm volatile("mttcr %0" : : "r" (val));
-}
-
-
static __inline__ void set_evpr(unsigned long val)
{
asm volatile("mtevpr %0" : : "r" (val));
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 87caea19b..363becc80 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -63,6 +63,7 @@
* board_init will change CS0 to be positioned at the correct
* address and (s)dram will be positioned at address 0
*/
+#include <asm-offsets.h>
#include <config.h>
#include <asm/ppc4xx.h>
#include <timestamp.h>
@@ -182,8 +183,8 @@
# endif
#endif /* CONFIG_SYS_INIT_DCACHE_CS */
-#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
-#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
+#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
+#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
#endif
/*
@@ -656,8 +657,8 @@ _start:
/* Clear Dcache to use as RAM */
addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
- addis r4,r0,CONFIG_SYS_INIT_RAM_END@h
- ori r4,r4,CONFIG_SYS_INIT_RAM_END@l
+ addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
+ ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
rlwinm. r5,r4,0,27,31
rlwinm r5,r4,27,5,31
beq ..d_ran
@@ -1091,8 +1092,8 @@ _start:
lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
- lis r4, CONFIG_SYS_INIT_RAM_END@h
- ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
+ lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
+ ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
/*
* Convert the size, in bytes, to the number of cache lines/blocks
@@ -1119,12 +1120,12 @@ _start:
lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
- lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
- ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
+ lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
+ ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
mtctr r4
lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
- ori r2, r2, CONFIG_SYS_INIT_RAM_END@l
+ ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
@@ -1399,7 +1400,7 @@ relocate_code:
/* Flush initial global data range */
mr r3, r4
- addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
+ addi r4, r4, GENERATED_GBL_DATA_SIZE@l
bl flush_dcache_range
#if defined(CONFIG_SYS_INIT_DCACHE_CS)
@@ -1414,8 +1415,8 @@ relocate_code:
lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
- lis r4, CONFIG_SYS_INIT_RAM_END@h
- ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
+ lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
+ ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
add r4, r4, r3
bl invalidate_dcache_range
diff --git a/arch/powerpc/cpu/ppc4xx/traps.c b/arch/powerpc/cpu/ppc4xx/traps.c
index b5562ad97..9baa7a16d 100644
--- a/arch/powerpc/cpu/ppc4xx/traps.c
+++ b/arch/powerpc/cpu/ppc4xx/traps.c
@@ -46,15 +46,6 @@ extern unsigned long search_exception_table(unsigned long);
*/
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
-static __inline__ void set_tsr(unsigned long val)
-{
-#if defined(CONFIG_440)
- asm volatile("mtspr 0x150, %0" : : "r" (val));
-#else
- asm volatile("mttsr %0" : : "r" (val));
-#endif
-}
-
static __inline__ unsigned long get_esr(void)
{
unsigned long val;
@@ -364,7 +355,7 @@ DecrementerPITException(struct pt_regs *regs)
/*
* Reset PIT interrupt
*/
- set_tsr(0x08000000);
+ mtspr(SPRN_TSR, 0x08000000);
/*
* Call timer_interrupt routine in interrupts.c