diff options
Diffstat (limited to 'arch/m68k')
31 files changed, 1149 insertions, 914 deletions
diff --git a/arch/m68k/cpu/mcf5227x/cpu.c b/arch/m68k/cpu/mcf5227x/cpu.c index 09ef1d2cf..3a0ab9746 100644 --- a/arch/m68k/cpu/mcf5227x/cpu.c +++ b/arch/m68k/cpu/mcf5227x/cpu.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -30,14 +30,15 @@ #include <command.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM); + rcm_t *rcm = (rcm_t *) (MMAP_RCM); udelay(1000); - rcm->rcr |= RCM_RCR_SOFTRST; + setbits_8(&rcm->rcr, RCM_RCR_SOFTRST); /* we don't return! */ return 0; @@ -45,14 +46,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int checkcpu(void) { - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + ccm_t *ccm = (ccm_t *) MMAP_CCM; u16 msk; u16 id = 0; u8 ver; puts("CPU: "); - msk = (ccm->cir >> 6); - ver = (ccm->cir & 0x003f); + msk = (in_be16(&ccm->cir) >> 6); + ver = (in_be16(&ccm->cir) & 0x003f); switch (msk) { case 0x6c: id = 52277; diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c b/arch/m68k/cpu/mcf5227x/cpu_init.c index beb78f583..e23b20df9 100644 --- a/arch/m68k/cpu/mcf5227x/cpu_init.c +++ b/arch/m68k/cpu/mcf5227x/cpu_init.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. + * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -29,6 +29,7 @@ #include <watchdog.h> #include <asm/immap.h> +#include <asm/io.h> #include <asm/rtc.h> /* @@ -40,70 +41,70 @@ */ void cpu_init_f(void) { - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + pll_t *pll = (pll_t *)MMAP_PLL; #if !defined(CONFIG_CF_SBF) /* Workaround, must place before fbcs */ - pll->psr = 0x12; + out_be32(&pll->psr, 0x12); - scm1->mpr = 0x77777777; - scm1->pacra = 0; - scm1->pacrb = 0; - scm1->pacrc = 0; - scm1->pacrd = 0; - scm1->pacre = 0; - scm1->pacrf = 0; - scm1->pacrg = 0; - scm1->pacri = 0; + out_be32(&scm1->mpr, 0x77777777); + out_be32(&scm1->pacra, 0); + out_be32(&scm1->pacrb, 0); + out_be32(&scm1->pacrc, 0); + out_be32(&scm1->pacrd, 0); + out_be32(&scm1->pacre, 0); + out_be32(&scm1->pacrf, 0); + out_be32(&scm1->pacrg, 0); + out_be32(&scm1->pacri, 0); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #endif /* CONFIG_CF_SBF */ #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ && defined(CONFIG_SYS_CS1_CTRL)) - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ && defined(CONFIG_SYS_CS4_CTRL)) - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ && defined(CONFIG_SYS_CS5_CTRL)) - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #ifdef CONFIG_FSL_I2C - gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA; + out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA); #endif icache_enable(); @@ -115,11 +116,11 @@ void cpu_init_f(void) int cpu_init_r(void) { #ifdef CONFIG_MCFRTC - volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE); - volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; + rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE); + rtcex_t *rtcex = (rtcex_t *)&rtc->extended; - rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF; - rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF; + out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff); + out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff); #endif return (0); @@ -127,27 +128,27 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->par_uart &= - (GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK); - gpio->par_uart |= - (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + clrbits_be16(&gpio->par_uart, + ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK)); + setbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); break; case 1: - gpio->par_uart &= - (GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK); - gpio->par_uart |= - (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); + clrbits_be16(&gpio->par_uart, + ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK)); + setbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); break; case 2: - gpio->par_dspi &= - (GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK); - gpio->par_dspi = - (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD); + clrbits_8(&gpio->par_dspi, + ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK)); + out_8(&gpio->par_dspi, + GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD); break; } } @@ -155,32 +156,32 @@ void uart_port_conf(int port) #ifdef CONFIG_CF_DSPI void cfspi_port_conf(void) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; - gpio->par_dspi = - GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | - GPIO_PAR_DSPI_SCK_SCK; + out_8(&gpio->par_dspi, + GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | + GPIO_PAR_DSPI_SCK_SCK); } int cfspi_claim_bus(uint bus, uint cs) { - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + dspi_t *dspi = (dspi_t *) MMAP_DSPI; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; - if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) + if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) return -1; /* Clear FIFO and resume transfer */ - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); switch (cs) { case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_UNMASK; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK); + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); break; case 2: - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK; - gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2; + clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); + setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2); break; } @@ -189,17 +190,18 @@ int cfspi_claim_bus(uint bus, uint cs) void cfspi_release_bus(uint bus, uint cs) { - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + dspi_t *dspi = (dspi_t *) MMAP_DSPI; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */ + /* Clear FIFO */ + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); switch (cs) { case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); break; case 2: - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK; + clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK); break; } } diff --git a/arch/m68k/cpu/mcf5227x/interrupts.c b/arch/m68k/cpu/mcf5227x/interrupts.c index 85828a67b..a2cf51933 100644 --- a/arch/m68k/cpu/mcf5227x/interrupts.c +++ b/arch/m68k/cpu/mcf5227x/interrupts.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,14 +28,15 @@ /* CPU specific interrupt routine */ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ - intp->imrh0 |= 0xFFFFFFFF; - intp->imrl0 |= 0xFFFFFFFF; + setbits_be32(&intp->imrh0, 0xffffffff); + setbits_be32(&intp->imrl0, 0xffffffff); enable_interrupts(); return 0; @@ -44,9 +45,9 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; - intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK; + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/cpu/mcf5227x/speed.c b/arch/m68k/cpu/mcf5227x/speed.c index 7e385d399..b94a9eda4 100644 --- a/arch/m68k/cpu/mcf5227x/speed.c +++ b/arch/m68k/cpu/mcf5227x/speed.c @@ -1,6 +1,6 @@ /* * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -26,6 +26,7 @@ #include <asm/processor.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -44,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR; void clock_enter_limp(int lpdiv) { - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + ccm_t *ccm = (ccm_t *)MMAP_CCM; int i, j; /* Check bounds of divider */ @@ -57,10 +58,10 @@ void clock_enter_limp(int lpdiv) for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ; /* Apply the divider to the system clock */ - ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i); + clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); /* Enable Limp Mode */ - ccm->misccr |= CCM_MISCCR_LIMP; + setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); } /* @@ -69,14 +70,15 @@ void clock_enter_limp(int lpdiv) */ void clock_exit_limp(void) { - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + ccm_t *ccm = (ccm_t *)MMAP_CCM; + pll_t *pll = (pll_t *)MMAP_PLL; /* Exit Limp mode */ - ccm->misccr &= ~CCM_MISCCR_LIMP; + clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); /* Wait for the PLL to lock */ - while (!(pll->psr & PLL_PSR_LOCK)) ; + while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) + ; } /* @@ -85,12 +87,12 @@ void clock_exit_limp(void) int get_clocks(void) { - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + ccm_t *ccm = (ccm_t *)MMAP_CCM; + pll_t *pll = (pll_t *)MMAP_PLL; int vco, temp, pcrvalue, pfdr; u8 bootmode; - pcrvalue = pll->pcr & 0xFF0F0FFF; + pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF; pfdr = pcrvalue >> 24; if (pfdr == 0x1E) @@ -102,32 +104,32 @@ int get_clocks(void) if (bootmode == 0) { /* Normal mode */ - vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; + vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { /* Default value */ - pcrvalue = (pll->pcr & 0x00FFFFFF); + pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); pcrvalue |= 0x1E << 24; - pll->pcr = pcrvalue; + out_be32(&pll->pcr, pcrvalue); vco = - ((pll->pcr & 0xFF000000) >> 24) * + ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; } gd->vco_clk = vco; /* Vco clock */ } else if (bootmode == 3) { /* serial mode */ - vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; + vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; gd->vco_clk = vco; /* Vco clock */ } - if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { + if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { /* Limp mode */ } else { gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */ - temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1; + temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1; gd->cpu_clk = vco / temp; /* cpu clock */ - temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; + temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; gd->flb_clk = vco / temp; /* flexbus clock */ gd->bus_clk = gd->flb_clk; } diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c index 2376f970d..a3f568403 100644 --- a/arch/m68k/cpu/mcf523x/cpu.c +++ b/arch/m68k/cpu/mcf523x/cpu.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -31,28 +31,29 @@ #include <netdev.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + ccm_t *ccm = (ccm_t *) MMAP_CCM; - ccm->rcr = CCM_RCR_SOFTRST; + out_8(&ccm->rcr, CCM_RCR_SOFTRST); /* we don't return! */ return 0; -}; +} int checkcpu(void) { - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + ccm_t *ccm = (ccm_t *) MMAP_CCM; u16 msk; u16 id = 0; u8 ver; puts("CPU: "); - msk = (ccm->cir >> 6); - ver = (ccm->cir & 0x003f); + msk = (in_be16(&ccm->cir) >> 6); + ver = (in_be16(&ccm->cir) & 0x003f); switch (msk) { case 0x31: id = 5235; @@ -76,19 +77,21 @@ int checkcpu(void) /* Called by macro WATCHDOG_RESET */ void watchdog_reset(void) { - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + wdog_t *wdp = (wdog_t *) (MMAP_WDOG); - wdp->sr = 0x5555; /* Count register */ + /* Count register */ + out_be16(&wdp->sr, 0x5555); asm("nop"); - wdp->sr = 0xAAAA; /* Count register */ + out_be16(&wdp->sr, 0xaaaa); } int watchdog_disable(void) { - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + wdog_t *wdp = (wdog_t *) (MMAP_WDOG); /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */ - wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */ + /* halted watchdog timer */ + setbits_be16(&wdp->cr, WTM_WCR_HALTED); puts("WATCHDOG:disabled\n"); return (0); @@ -96,15 +99,15 @@ int watchdog_disable(void) int watchdog_init(void) { - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + wdog_t *wdp = (wdog_t *) (MMAP_WDOG); u32 wdog_module = 0; /* set timeout and enable watchdog */ wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT); wdog_module |= (wdog_module / 8192); - wdp->mr = wdog_module; + out_be16(&wdp->mr, wdog_module); - wdp->cr = WTM_WCR_EN; + out_be16(&wdp->cr, WTM_WCR_EN); puts("WATCHDOG:enabled\n"); return (0); diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c index 0f299f0c3..d1c0b401c 100644 --- a/arch/m68k/cpu/mcf523x/cpu_init.c +++ b/arch/m68k/cpu/mcf523x/cpu_init.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2007 Freescale Semiconductor, Inc. + * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,7 @@ #include <common.h> #include <watchdog.h> #include <asm/immap.h> +#include <asm/io.h> #if defined(CONFIG_CMD_NET) #include <config.h> @@ -44,74 +45,74 @@ */ void cpu_init_f(void) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG; - volatile scm_t *scm = (scm_t *) MMAP_SCM; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + wdog_t *wdog = (wdog_t *) MMAP_WDOG; + scm_t *scm = (scm_t *) MMAP_SCM; /* watchdog is enabled by default - disable the watchdog */ #ifndef CONFIG_WATCHDOG - wdog->cr = 0; + out_be16(&wdog->cr, 0); #endif - scm->rambar = (CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE); + out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE); /* Port configuration */ - gpio->par_cs = 0; + out_8(&gpio->par_cs, 0); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS1; - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1); + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS2; - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2); + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS3; - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3); + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS4; - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4); + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS5; - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5); + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS6; - fbcs->csar6 = CONFIG_SYS_CS6_BASE; - fbcs->cscr6 = CONFIG_SYS_CS6_CTRL; - fbcs->csmr6 = CONFIG_SYS_CS6_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6); + out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE); + out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL); + out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK); #endif #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL)) - gpio->par_cs |= GPIO_PAR_CS_CS7; - fbcs->csar7 = CONFIG_SYS_CS7_BASE; - fbcs->cscr7 = CONFIG_SYS_CS7_CTRL; - fbcs->csmr7 = CONFIG_SYS_CS7_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7); + out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE); + out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL); + out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK); #endif #ifdef CONFIG_FSL_I2C @@ -132,29 +133,33 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->par_uart &= ~(GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); - gpio->par_uart |= (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); + clrbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); + setbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); break; case 1: - gpio->par_uart &= - ~(GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK); - gpio->par_uart |= - (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); + clrbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK); + setbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); break; case 2: #ifdef CONFIG_SYS_UART2_PRI_GPIO - gpio->par_uart &= ~(GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); - gpio->par_uart |= (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); + clrbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); + setbits_be16(&gpio->par_uart, + GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); #elif defined(CONFIG_SYS_UART2_ALT1_GPIO) - gpio->feci2c &= - ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); - gpio->feci2c |= - (GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD); + clrbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD); #endif break; } @@ -163,15 +168,16 @@ void uart_port_conf(int port) #if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; if (setclear) { - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_EMDC_FECEMDC | - GPIO_PAR_FECI2C_EMDIO_FECEMDIO); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_EMDC_FECEMDC | + GPIO_PAR_FECI2C_EMDIO_FECEMDIO); } else { - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); + clrbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_EMDC_MASK | + GPIO_PAR_FECI2C_EMDIO_MASK); } return 0; diff --git a/arch/m68k/cpu/mcf523x/interrupts.c b/arch/m68k/cpu/mcf523x/interrupts.c index db5ccdf6d..76115a401 100644 --- a/arch/m68k/cpu/mcf523x/interrupts.c +++ b/arch/m68k/cpu/mcf523x/interrupts.c @@ -1,6 +1,6 @@ /* * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -25,13 +25,14 @@ /* CPU specific interrupt routine */ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ - intp->imrl0 |= 0x1; + setbits_be32(&intp->imrl0, 0x1); enable_interrupts(); return 0; @@ -40,10 +41,10 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; - intp->imrl0 &= ~INTC_IPRL_INT0; - intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK; + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrl0, INTC_IPRL_INT0); + clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/cpu/mcf523x/speed.c b/arch/m68k/cpu/mcf523x/speed.c index 6096ba414..e2a6ae3a5 100644 --- a/arch/m68k/cpu/mcf523x/speed.c +++ b/arch/m68k/cpu/mcf523x/speed.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -29,6 +29,7 @@ #include <asm/processor.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; /* @@ -36,11 +37,12 @@ DECLARE_GLOBAL_DATA_PTR; */ int get_clocks(void) { - volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + pll_t *pll = (pll_t *)(MMAP_PLL); - pll->syncr = PLL_SYNCR_MFD(1); + out_be32(&pll->syncr, PLL_SYNCR_MFD(1)); - while (!(pll->synsr & PLL_SYNSR_LOCK)); + while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK)) + ; gd->bus_clk = CONFIG_SYS_CLK; gd->cpu_clk = (gd->bus_clk * 2); diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c index 571d078f8..7c6100c52 100644 --- a/arch/m68k/cpu/mcf52x2/cpu.c +++ b/arch/m68k/cpu/mcf52x2/cpu.c @@ -9,6 +9,8 @@ * MCF5275 additions * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) * + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * * See file CREDITS for list of people who contributed to this * project. * @@ -32,6 +34,7 @@ #include <watchdog.h> #include <command.h> #include <asm/immap.h> +#include <asm/io.h> #include <netdev.h> #include "cpu.h" @@ -40,11 +43,11 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_M5208 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM); + rcm_t *rcm = (rcm_t *)(MMAP_RCM); udelay(1000); - rcm->rcr = RCM_RCR_SOFTRST; + out_8(&rcm->rcr, RCM_RCR_SOFTRST); /* we don't return! */ return 0; @@ -65,18 +68,21 @@ int checkcpu(void) /* Called by macro WATCHDOG_RESET */ void watchdog_reset(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - wdt->sr = 0x5555; - wdt->sr = 0xAAAA; + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); + + out_be16(&wdt->sr, 0x5555); + out_be16(&wdt->sr, 0xaaaa); } int watchdog_disable(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - wdt->sr = 0x5555; /* reset watchdog counter */ - wdt->sr = 0xAAAA; - wdt->cr = 0; /* disable watchdog timer */ + /* reset watchdog counter */ + out_be16(&wdt->sr, 0x5555); + out_be16(&wdt->sr, 0xaaaa); + /* disable watchdog timer */ + out_be16(&wdt->cr, 0); puts("WATCHDOG:disabled\n"); return (0); @@ -84,15 +90,18 @@ int watchdog_disable(void) int watchdog_init(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - wdt->cr = 0; /* disable watchdog */ + /* disable watchdog */ + out_be16(&wdt->cr, 0); /* set timeout and enable watchdog */ - wdt->mr = - ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1; - wdt->sr = 0x5555; /* reset watchdog counter */ - wdt->sr = 0xAAAA; + out_be16(&wdt->mr, + (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); + + /* reset watchdog counter */ + out_be16(&wdt->sr, 0x5555); + out_be16(&wdt->sr, 0xaaaa); puts("WATCHDOG:enabled\n"); return (0); @@ -178,13 +187,13 @@ int watchdog_init(void) #ifdef CONFIG_M5272 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + wdog_t *wdp = (wdog_t *) (MMAP_WDOG); - wdp->wdog_wrrr = 0; + out_be16(&wdp->wdog_wrrr, 0); udelay(1000); /* enable watchdog, set timeout to 0 and wait */ - wdp->wdog_wrrr = 1; + out_be16(&wdp->wdog_wrrr, 1); while (1) ; /* we don't return! */ @@ -193,12 +202,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int checkcpu(void) { - volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG); + sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG); uchar msk; char *suf; puts("CPU: "); - msk = (sysctrl->sc_dir > 28) & 0xf; + msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf; switch (msk) { case 0x2: suf = "1K75N"; @@ -221,17 +230,21 @@ int checkcpu(void) /* Called by macro WATCHDOG_RESET */ void watchdog_reset(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - wdt->wdog_wcr = 0; + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); + + out_be16(&wdt->wdog_wcr, 0); } int watchdog_disable(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - wdt->wdog_wcr = 0; /* reset watchdog counter */ - wdt->wdog_wirr = 0; /* disable watchdog interrupt */ - wdt->wdog_wrrr = 0; /* disable watchdog timer */ + /* reset watchdog counter */ + out_be16(&wdt->wdog_wcr, 0); + /* disable watchdog interrupt */ + out_be16(&wdt->wdog_wirr, 0); + /* disable watchdog timer */ + out_be16(&wdt->wdog_wrrr, 0); puts("WATCHDOG:disabled\n"); return (0); @@ -239,14 +252,17 @@ int watchdog_disable(void) int watchdog_init(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - wdt->wdog_wirr = 0; /* disable watchdog interrupt */ + /* disable watchdog interrupt */ + out_be16(&wdt->wdog_wirr, 0); /* set timeout and enable watchdog */ - wdt->wdog_wrrr = - ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1; - wdt->wdog_wcr = 0; /* reset watchdog counter */ + out_be16(&wdt->wdog_wrrr, + (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); + + /* reset watchdog counter */ + out_be16(&wdt->wdog_wcr, 0); puts("WATCHDOG:enabled\n"); return (0); @@ -258,11 +274,11 @@ int watchdog_init(void) #ifdef CONFIG_M5275 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM); + rcm_t *rcm = (rcm_t *)(MMAP_RCM); udelay(1000); - rcm->rcr = RCM_RCR_SOFTRST; + out_8(&rcm->rcr, RCM_RCR_SOFTRST); /* we don't return! */ return 0; @@ -282,18 +298,22 @@ int checkcpu(void) /* Called by macro WATCHDOG_RESET */ void watchdog_reset(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); - wdt->wsr = 0x5555; - wdt->wsr = 0xAAAA; + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); + + out_be16(&wdt->wsr, 0x5555); + out_be16(&wdt->wsr, 0xaaaa); } int watchdog_disable(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - wdt->wsr = 0x5555; /* reset watchdog counter */ - wdt->wsr = 0xAAAA; - wdt->wcr = 0; /* disable watchdog timer */ + /* reset watchdog counter */ + out_be16(&wdt->wsr, 0x5555); + out_be16(&wdt->wsr, 0xaaaa); + + /* disable watchdog timer */ + out_be16(&wdt->wcr, 0); puts("WATCHDOG:disabled\n"); return (0); @@ -301,15 +321,18 @@ int watchdog_disable(void) int watchdog_init(void) { - volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG); + wdog_t *wdt = (wdog_t *)(MMAP_WDOG); - wdt->wcr = 0; /* disable watchdog */ + /* disable watchdog */ + out_be16(&wdt->wcr, 0); /* set timeout and enable watchdog */ - wdt->wmr = - ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1; - wdt->wsr = 0x5555; /* reset watchdog counter */ - wdt->wsr = 0xAAAA; + out_be16(&wdt->wmr, + (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); + + /* reset watchdog counter */ + out_be16(&wdt->wsr, 0x5555); + out_be16(&wdt->wsr, 0xaaaa); puts("WATCHDOG:enabled\n"); return (0); diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c index a98a9262e..5d0e9f06f 100644 --- a/arch/m68k/cpu/mcf52x2/cpu_init.c +++ b/arch/m68k/cpu/mcf52x2/cpu_init.c @@ -8,7 +8,7 @@ * (c) Copyright 2010 * Arcturus Networks Inc. <www.arcturusnetworks.com> * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * Hayden Fraser (Hayden.Fraser@freescale.com) * @@ -37,6 +37,7 @@ #include <common.h> #include <watchdog.h> #include <asm/immap.h> +#include <asm/io.h> #if defined(CONFIG_CMD_NET) #include <config.h> @@ -48,57 +49,57 @@ /* Only 5272 Flexbus chipselect is different from the rest */ void init_fbcs(void) { - volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS); + fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #else #warning "Chip Select 0 are not initialized/used" #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ && defined(CONFIG_SYS_CS1_CTRL)) - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ && defined(CONFIG_SYS_CS4_CTRL)) - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ && defined(CONFIG_SYS_CS5_CTRL)) - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \ && defined(CONFIG_SYS_CS6_CTRL)) - fbcs->csar6 = CONFIG_SYS_CS6_BASE; - fbcs->cscr6 = CONFIG_SYS_CS6_CTRL; - fbcs->csmr6 = CONFIG_SYS_CS6_MASK; + out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE); + out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL); + out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK); #endif #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \ && defined(CONFIG_SYS_CS7_CTRL)) - fbcs->csar7 = CONFIG_SYS_CS7_BASE; - fbcs->cscr7 = CONFIG_SYS_CS7_CTRL; - fbcs->csmr7 = CONFIG_SYS_CS7_MASK; + out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE); + out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL); + out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK); #endif } #endif @@ -106,22 +107,22 @@ void init_fbcs(void) #if defined(CONFIG_M5208) void cpu_init_f(void) { - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + scm1_t *scm1 = (scm1_t *) MMAP_SCM1; #ifndef CONFIG_WATCHDOG - volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG; + wdog_t *wdg = (wdog_t *) MMAP_WDOG; /* Disable the watchdog if we aren't using it */ - wdg->cr = 0; + out_be16(&wdg->cr, 0); #endif - scm1->mpr = 0x77777777; - scm1->pacra = 0; - scm1->pacrb = 0; - scm1->pacrc = 0; - scm1->pacrd = 0; - scm1->pacre = 0; - scm1->pacrf = 0; + out_be32(&scm1->mpr, 0x77777777); + out_be32(&scm1->pacra, 0); + out_be32(&scm1->pacrb, 0); + out_be32(&scm1->pacrc, 0); + out_be32(&scm1->pacrd, 0); + out_be32(&scm1->pacre, 0); + out_be32(&scm1->pacrf, 0); /* FlexBus Chipselect */ init_fbcs(); @@ -137,36 +138,36 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->par_uart &= GPIO_PAR_UART0_UNMASK; - gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); + clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK); + setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); break; case 1: - gpio->par_uart &= GPIO_PAR_UART0_UNMASK; - gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD); + clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK); + setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD); break; case 2: #ifdef CONFIG_SYS_UART2_PRI_GPIO - gpio->par_timer &= - (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK); - gpio->par_timer |= - (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD); + clrbits_8(&gpio->par_timer, + ~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK)); + setbits_8(&gpio->par_timer, + GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD); #endif #ifdef CONFIG_SYS_UART2_ALT1_GPIO - gpio->par_feci2c &= - (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK); - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD); + clrbits_8(&gpio->par_feci2c, + ~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK)); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD); #endif #ifdef CONFIG_SYS_UART2_ALT1_GPIO - gpio->par_feci2c &= - (GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK); - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); + clrbits_8(&gpio->par_feci2c, + ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK)); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); #endif break; } @@ -175,17 +176,17 @@ void uart_port_conf(int port) #if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; if (setclear) { - gpio->par_fec |= - GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO; + setbits_8(&gpio->par_fec, + GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO); } else { - gpio->par_fec &= - (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK); - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK; + clrbits_8(&gpio->par_fec, + ~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK)); + clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK); } return 0; } @@ -249,17 +250,17 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile u32 *par = (u32 *) MMAP_PAR; + u32 *par = (u32 *) MMAP_PAR; /* Setup Ports: */ switch (port) { case 1: - *par &= 0xFFE7FFFF; - *par |= 0x00180000; + clrbits_be32(par, 0x00180000); + setbits_be32(par, 0x00180000); break; case 2: - *par &= 0xFFFFFFFC; - *par &= 0x00000003; + clrbits_be32(par, 0x00000003); + clrbits_be32(par, 0xFFFFFFFC); break; } } @@ -332,7 +333,20 @@ int fecpin_setclear(struct eth_device *dev, int setclear) return 0; } #endif /* CONFIG_CMD_NET */ -#endif + +#if defined(CONFIG_CF_QSPI) + +/* Configure PIOs for SIN, SOUT, and SCK */ +void cfspi_port_conf(void) +{ + mbar_writeByte(MCF_GPIO_PAR_QSPI, + MCF_GPIO_PAR_QSPI_SIN_SIN | + MCF_GPIO_PAR_QSPI_SOUT_SOUT | + MCF_GPIO_PAR_QSPI_SCK_SCK); +} +#endif /* CONFIG_CF_QSPI */ + +#endif /* CONFIG_M5271 */ #if defined(CONFIG_M5272) /* @@ -348,59 +362,59 @@ void cpu_init_f(void) * already initialized. */ #ifndef CONFIG_MONITOR_IS_IN_RAM - volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR); - volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO); - volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); + sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR); + gpio_t *gpio = (gpio_t *) (MMAP_GPIO); + csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); - sysctrl->sc_scr = CONFIG_SYS_SCR; - sysctrl->sc_spr = CONFIG_SYS_SPR; + out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR); + out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR); /* Setup Ports: */ - gpio->gpio_pacnt = CONFIG_SYS_PACNT; - gpio->gpio_paddr = CONFIG_SYS_PADDR; - gpio->gpio_padat = CONFIG_SYS_PADAT; - gpio->gpio_pbcnt = CONFIG_SYS_PBCNT; - gpio->gpio_pbddr = CONFIG_SYS_PBDDR; - gpio->gpio_pbdat = CONFIG_SYS_PBDAT; - gpio->gpio_pdcnt = CONFIG_SYS_PDCNT; + out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT); + out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR); + out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT); + out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT); + out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR); + out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT); + out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT); /* Memory Controller: */ - csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM; - csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM; + out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM); + out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM); #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM)) - csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM; - csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM; + out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM); + out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM); #endif #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) - csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM; - csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM; + out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM); + out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM); #endif #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) - csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM; - csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM; + out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM); + out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM); #endif #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM) - csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM; - csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM; + out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM); + out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM); #endif #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM) - csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM; - csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM; + out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM); + out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM); #endif #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM) - csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM; - csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM; + out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM); + out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM); #endif #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM) - csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM; - csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM; + out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM); + out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM); #endif #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ @@ -420,17 +434,21 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); - gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); + clrbits_be32(&gpio->gpio_pbcnt, + GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); + setbits_be32(&gpio->gpio_pbcnt, + GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); break; case 1: - gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK); - gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD); + clrbits_be32(&gpio->gpio_pdcnt, + GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK); + setbits_be32(&gpio->gpio_pdcnt, + GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD); break; } } @@ -438,13 +456,14 @@ void uart_port_conf(int port) #if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; if (setclear) { - gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | - GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | - GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | - GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3; + setbits_be32(&gpio->gpio_pbcnt, + GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | + GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | + GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | + GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3); } else { } return 0; @@ -469,11 +488,11 @@ void cpu_init_f(void) */ #ifndef CONFIG_MONITOR_IS_IN_RAM - volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG); - volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO); + wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG); + gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO); /* Kill watchdog so we can initialize the PLL */ - wdog_reg->wcr = 0; + out_be16(&wdog_reg->wcr, 0); /* FlexBus Chipselect */ init_fbcs(); @@ -498,21 +517,21 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->par_uart &= ~UART0_ENABLE_MASK; - gpio->par_uart |= UART0_ENABLE_MASK; + clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK); + setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK); break; case 1: - gpio->par_uart &= ~UART1_ENABLE_MASK; - gpio->par_uart |= UART1_ENABLE_MASK; + clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK); + setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK); break; case 2: - gpio->par_uart &= ~UART2_ENABLE_MASK; - gpio->par_uart |= UART2_ENABLE_MASK; + clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK); + setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK); break; } } @@ -521,24 +540,24 @@ void uart_port_conf(int port) int fecpin_setclear(struct eth_device *dev, int setclear) { struct fec_info_s *info = (struct fec_info_s *) dev->priv; - volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO; + gpio_t *gpio = (gpio_t *)MMAP_GPIO; if (setclear) { /* Enable Ethernet pins */ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { - gpio->par_feci2c |= 0x0F00; - gpio->par_fec0hl |= 0xC0; + setbits_be16(&gpio->par_feci2c, 0x0f00); + setbits_8(&gpio->par_fec0hl, 0xc0); } else { - gpio->par_feci2c |= 0x00A0; - gpio->par_fec1hl |= 0xC0; + setbits_be16(&gpio->par_feci2c, 0x00a0); + setbits_8(&gpio->par_fec1hl, 0xc0); } } else { if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { - gpio->par_feci2c &= ~0x0F00; - gpio->par_fec0hl &= ~0xC0; + clrbits_be16(&gpio->par_feci2c, 0x0f00); + clrbits_8(&gpio->par_fec0hl, 0xc0); } else { - gpio->par_feci2c &= ~0x00A0; - gpio->par_fec1hl &= ~0xC0; + clrbits_be16(&gpio->par_feci2c, 0x00a0); + clrbits_8(&gpio->par_fec1hl, 0xc0); } } diff --git a/arch/m68k/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c index dff8c6aa8..915eb7023 100644 --- a/arch/m68k/cpu/mcf52x2/interrupts.c +++ b/arch/m68k/cpu/mcf52x2/interrupts.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,20 +28,22 @@ #include <watchdog.h> #include <asm/processor.h> #include <asm/immap.h> +#include <asm/io.h> #ifdef CONFIG_M5272 int interrupt_init(void) { - volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC); + intctrl_t *intp = (intctrl_t *) (MMAP_INTC); /* disable all external interrupts */ - intp->int_icr1 = 0x88888888; - intp->int_icr2 = 0x88888888; - intp->int_icr3 = 0x88888888; - intp->int_icr4 = 0x88888888; - intp->int_pitr = 0x00000000; + out_be32(&intp->int_icr1, 0x88888888); + out_be32(&intp->int_icr2, 0x88888888); + out_be32(&intp->int_icr3, 0x88888888); + out_be32(&intp->int_icr4, 0x88888888); + out_be32(&intp->int_pitr, 0x00000000); + /* initialize vector register */ - intp->int_pivr = 0x40; + out_8(&intp->int_pivr, 0x40); enable_interrupts(); @@ -51,10 +53,10 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE); + intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE); - intp->int_icr1 &= ~INT_ICR1_TMR3MASK; - intp->int_icr1 |= CONFIG_SYS_TMRINTR_PRI; + clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK); + setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI); } #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5272 */ @@ -63,14 +65,14 @@ void dtimer_intr_setup(void) defined(CONFIG_M5271) || defined(CONFIG_M5275) int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ #if defined(CONFIG_M5208) - intp->imrl0 = 0xFFFFFFFF; - intp->imrh0 = 0xFFFFFFFF; + out_be32(&intp->imrl0, 0xffffffff); + out_be32(&intp->imrh0, 0xffffffff); #else - intp->imrl0 |= 0x1; + setbits_be32(&intp->imrl0, 0x1); #endif enable_interrupts(); @@ -80,11 +82,11 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; - intp->imrl0 &= 0xFFFFFFFE; - intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK; + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrl0, 0x00000001); + clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK); } #endif /* CONFIG_MCFTMR */ #endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */ diff --git a/arch/m68k/cpu/mcf52x2/speed.c b/arch/m68k/cpu/mcf52x2/speed.c index b485e1ccc..70abed25c 100644 --- a/arch/m68k/cpu/mcf52x2/speed.c +++ b/arch/m68k/cpu/mcf52x2/speed.c @@ -2,7 +2,7 @@ * (C) Copyright 2003 * Josef Baumgartner <josef.baumgartner@telex.de> * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * Hayden Fraser (Hayden.Fraser@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -27,6 +27,7 @@ #include <common.h> #include <asm/processor.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -34,10 +35,10 @@ DECLARE_GLOBAL_DATA_PTR; int get_clocks (void) { #if defined(CONFIG_M5208) - volatile pll_t *pll = (pll_t *) MMAP_PLL; + pll_t *pll = (pll_t *) MMAP_PLL; - pll->odr = CONFIG_SYS_PLL_ODR; - pll->fdr = CONFIG_SYS_PLL_FDR; + out_8(&pll->odr, CONFIG_SYS_PLL_ODR); + out_8(&pll->fdr, CONFIG_SYS_PLL_FDR); #endif #if defined(CONFIG_M5249) || defined(CONFIG_M5253) @@ -70,14 +71,14 @@ int get_clocks (void) #endif /* CONFIG_M5249 || CONFIG_M5253 */ #if defined(CONFIG_M5275) - volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + pll_t *pll = (pll_t *)(MMAP_PLL); /* Setup PLL */ - pll->syncr = 0x01080000; - while (!(pll->synsr & FMPLL_SYNSR_LOCK)) + out_be32(&pll->syncr, 0x01080000); + while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) ; - pll->syncr = 0x01000000; - while (!(pll->synsr & FMPLL_SYNSR_LOCK)) + out_be32(&pll->syncr, 0x01000000); + while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) ; #endif diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c index 3346784c8..4f160a664 100644 --- a/arch/m68k/cpu/mcf532x/cpu.c +++ b/arch/m68k/cpu/mcf532x/cpu.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -31,15 +31,16 @@ #include <netdev.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM); + rcm_t *rcm = (rcm_t *) (MMAP_RCM); udelay(1000); - rcm->rcr |= RCM_RCR_SOFTRST; + setbits_8(&rcm->rcr, RCM_RCR_SOFTRST); /* we don't return! */ return 0; @@ -47,14 +48,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int checkcpu(void) { - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + ccm_t *ccm = (ccm_t *) MMAP_CCM; u16 msk; u16 id = 0; u8 ver; puts("CPU: "); - msk = (ccm->cir >> 6); - ver = (ccm->cir & 0x003f); + msk = (in_be16(&ccm->cir) >> 6); + ver = (in_be16(&ccm->cir) & 0x003f); switch (msk) { #ifdef CONFIG_MCF5301x case 0x78: @@ -115,18 +116,20 @@ int checkcpu(void) /* Called by macro WATCHDOG_RESET */ void watchdog_reset(void) { - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + wdog_t *wdp = (wdog_t *) (MMAP_WDOG); - wdp->sr = 0x5555; /* Count register */ - wdp->sr = 0xAAAA; /* Count register */ + /* Count register */ + out_be16(&wdp->sr, 0x5555); + out_be16(&wdp->sr, 0xaaaa); } int watchdog_disable(void) { - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + wdog_t *wdp = (wdog_t *) (MMAP_WDOG); /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */ - wdp->cr |= WTM_WCR_HALTED; /* halted watchdog timer */ + /* halted watchdog timer */ + setbits_be16(&wdp->cr, WTM_WCR_HALTED); puts("WATCHDOG:disabled\n"); return (0); @@ -134,18 +137,18 @@ int watchdog_disable(void) int watchdog_init(void) { - volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); + wdog_t *wdp = (wdog_t *) (MMAP_WDOG); u32 wdog_module = 0; /* set timeout and enable watchdog */ wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); #ifdef CONFIG_M5329 - wdp->mr = (wdog_module / 8192); + out_be16(&wdp->mr, wdog_module / 8192); #else - wdp->mr = (wdog_module / 4096); + out_be16(&wdp->mr, wdog_module / 4096); #endif - wdp->cr = WTM_WCR_EN; + out_be16(&wdp->cr, WTM_WCR_EN); puts("WATCHDOG:enabled\n"); return (0); diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c index 6f551b60c..f571fadc3 100644 --- a/arch/m68k/cpu/mcf532x/cpu_init.c +++ b/arch/m68k/cpu/mcf532x/cpu_init.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2004-2008 Freescale Semiconductor, Inc. + * (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,7 @@ #include <common.h> #include <watchdog.h> #include <asm/immap.h> +#include <asm/io.h> #if defined(CONFIG_CMD_NET) #include <config.h> @@ -38,72 +39,68 @@ #ifdef CONFIG_MCF5301x void cpu_init_f(void) { - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - /* watchdog is enabled by default - disable the watchdog */ -#ifndef CONFIG_WATCHDOG - /*wdog->cr = 0; */ -#endif - - scm1->mpr = 0x77777777; - scm1->pacra = 0; - scm1->pacrb = 0; - scm1->pacrc = 0; - scm1->pacrd = 0; - scm1->pacre = 0; - scm1->pacrf = 0; - scm1->pacrg = 0; + out_be32(&scm1->mpr, 0x77777777); + out_be32(&scm1->pacra, 0); + out_be32(&scm1->pacrb, 0); + out_be32(&scm1->pacrc, 0); + out_be32(&scm1->pacrd, 0); + out_be32(&scm1->pacre, 0); + out_be32(&scm1->pacrf, 0); + out_be32(&scm1->pacrg, 0); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ && defined(CONFIG_SYS_CS0_CTRL)) - gpio->par_cs |= GPIO_PAR_CS0_CS0; - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0); + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ && defined(CONFIG_SYS_CS1_CTRL)) - gpio->par_cs |= GPIO_PAR_CS1_CS1; - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1); + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ && defined(CONFIG_SYS_CS4_CTRL)) - gpio->par_cs |= GPIO_PAR_CS4; - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS4); + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ && defined(CONFIG_SYS_CS5_CTRL)) - gpio->par_cs |= GPIO_PAR_CS5; - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS5); + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #ifdef CONFIG_FSL_I2C - gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL; + out_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL); #endif icache_enable(); @@ -113,21 +110,21 @@ void cpu_init_f(void) int cpu_init_r(void) { #ifdef CONFIG_MCFFEC - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + ccm_t *ccm = (ccm_t *) MMAP_CCM; #endif #ifdef CONFIG_MCFRTC - volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); - volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended; + rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); + rtcex_t *rtcex = (rtcex_t *) &rtc->extended; - rtcex->gocu = CONFIG_SYS_RTC_CNT; - rtcex->gocl = CONFIG_SYS_RTC_SETUP; + out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT); + out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP); #endif #ifdef CONFIG_MCFFEC if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE) - ccm->misccr |= CCM_MISCCR_FECM; + setbits_be16(&ccm->misccr, CCM_MISCCR_FECM); else - ccm->misccr &= ~CCM_MISCCR_FECM; + clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM); #endif return (0); @@ -135,41 +132,52 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->par_uart &= ~(GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); - gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); + clrbits_8(&gpio->par_uart, + GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); + setbits_8(&gpio->par_uart, + GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD); break; case 1: #ifdef CONFIG_SYS_UART1_ALT1_GPIO - gpio->par_simp1h &= - ~(GPIO_PAR_SIMP1H_DATA1_UNMASK | - GPIO_PAR_SIMP1H_VEN1_UNMASK); - gpio->par_simp1h |= - (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD); + clrbits_8(&gpio->par_simp1h, + GPIO_PAR_SIMP1H_DATA1_UNMASK | + GPIO_PAR_SIMP1H_VEN1_UNMASK); + setbits_8(&gpio->par_simp1h, + GPIO_PAR_SIMP1H_DATA1_U1TXD | + GPIO_PAR_SIMP1H_VEN1_U1RXD); #elif defined(CONFIG_SYS_UART1_ALT2_GPIO) - gpio->par_ssih &= - ~(GPIO_PAR_SSIH_RXD_UNMASK | GPIO_PAR_SSIH_TXD_UNMASK); - gpio->par_ssih |= - (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD); + clrbits_8(&gpio->par_ssih, + GPIO_PAR_SSIH_RXD_UNMASK | + GPIO_PAR_SSIH_TXD_UNMASK); + setbits_8(&gpio->par_ssih, + GPIO_PAR_SSIH_RXD_U1RXD | + GPIO_PAR_SSIH_TXD_U1TXD); #endif break; case 2: #ifdef CONFIG_SYS_UART2_PRI_GPIO - gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD); + setbits_8(&gpio->par_uart, + GPIO_PAR_UART_U2TXD | + GPIO_PAR_UART_U2RXD); #elif defined(CONFIG_SYS_UART2_ALT1_GPIO) - gpio->par_dspih &= - ~(GPIO_PAR_DSPIH_SIN_UNMASK | GPIO_PAR_DSPIH_SOUT_UNMASK); - gpio->par_dspih |= - (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD); + clrbits_8(&gpio->par_dspih, + GPIO_PAR_DSPIH_SIN_UNMASK | + GPIO_PAR_DSPIH_SOUT_UNMASK); + setbits_8(&gpio->par_dspih, + GPIO_PAR_DSPIH_SIN_U2RXD | + GPIO_PAR_DSPIH_SOUT_U2TXD); #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK); - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD); + clrbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_SDA_UNMASK | + GPIO_PAR_FECI2C_SCL_UNMASK); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_SDA_U2TXD | + GPIO_PAR_FECI2C_SCL_U2RXD); #endif break; } @@ -178,30 +186,30 @@ void uart_port_conf(int port) #if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; struct fec_info_s *info = (struct fec_info_s *)dev->priv; if (setclear) { if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { - gpio->par_fec |= - GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0; + setbits_8(&gpio->par_fec, + GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0); } else { - gpio->par_fec |= - GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1; + setbits_8(&gpio->par_fec, + GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1); } } else { if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { - gpio->par_fec &= - ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_UNMASK; + clrbits_8(&gpio->par_fec, + GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC); + clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK); } else { - gpio->par_fec &= - ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); - gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_UNMASK; + clrbits_8(&gpio->par_fec, + GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC); + clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK); } } return 0; @@ -212,80 +220,81 @@ int fecpin_setclear(struct eth_device *dev, int setclear) #ifdef CONFIG_MCF532x void cpu_init_f(void) { - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG; + scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + scm2_t *scm2 = (scm2_t *) MMAP_SCM2; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + wdog_t *wdog = (wdog_t *) MMAP_WDOG; /* watchdog is enabled by default - disable the watchdog */ #ifndef CONFIG_WATCHDOG - wdog->cr = 0; + out_be16(&wdog->cr, 0); #endif - scm1->mpr0 = 0x77777777; - scm2->pacra = 0; - scm2->pacrb = 0; - scm2->pacrc = 0; - scm2->pacrd = 0; - scm2->pacre = 0; - scm2->pacrf = 0; - scm2->pacrg = 0; - scm1->pacrh = 0; + out_be32(&scm1->mpr0, 0x77777777); + out_be32(&scm2->pacra, 0); + out_be32(&scm2->pacrb, 0); + out_be32(&scm2->pacrc, 0); + out_be32(&scm2->pacrd, 0); + out_be32(&scm2->pacre, 0); + out_be32(&scm2->pacrf, 0); + out_be32(&scm2->pacrg, 0); + out_be32(&scm1->pacrh, 0); /* Port configuration */ - gpio->par_cs = 0; + out_8(&gpio->par_cs, 0); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ && defined(CONFIG_SYS_CS1_CTRL)) /* Latch chipselect */ - gpio->par_cs |= GPIO_PAR_CS1; - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS1); + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ && defined(CONFIG_SYS_CS2_CTRL)) - gpio->par_cs |= GPIO_PAR_CS2; - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS2); + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ && defined(CONFIG_SYS_CS3_CTRL)) - gpio->par_cs |= GPIO_PAR_CS3; - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS3); + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ && defined(CONFIG_SYS_CS4_CTRL)) - gpio->par_cs |= GPIO_PAR_CS4; - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS4); + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ && defined(CONFIG_SYS_CS5_CTRL)) - gpio->par_cs |= GPIO_PAR_CS5; - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + setbits_8(&gpio->par_cs, GPIO_PAR_CS5); + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #ifdef CONFIG_FSL_I2C - gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; + out_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); #endif icache_enable(); @@ -301,30 +310,35 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->par_uart &= ~(GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); - gpio->par_uart |= (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); + clrbits_be16(&gpio->par_uart, + GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); + setbits_be16(&gpio->par_uart, + GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0); break; case 1: - gpio->par_uart &= - ~(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); - gpio->par_uart |= - (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); + clrbits_be16(&gpio->par_uart, + GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); + setbits_be16(&gpio->par_uart, + GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3)); break; case 2: #ifdef CONFIG_SYS_UART2_ALT1_GPIO - gpio->par_timer &= 0x0F; - gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); + clrbits_8(&gpio->par_timer, 0xf0); + setbits_8(&gpio->par_timer, + GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2); #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) - gpio->par_feci2c &= 0xFF00; - gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); + clrbits_8(&gpio->par_feci2c, 0x00ff); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); #elif defined(CONFIG_SYS_UART2_ALT3_GPIO) - gpio->par_ssi &= 0xF0FF; - gpio->par_ssi |= (GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); + clrbits_be16(&gpio->par_ssi, 0x0f00); + setbits_be16(&gpio->par_ssi, + GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); #endif break; } @@ -333,16 +347,18 @@ void uart_port_conf(int port) #if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; if (setclear) { - gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; + setbits_8(&gpio->par_fec, + GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); + setbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); } else { - gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); + clrbits_8(&gpio->par_fec, + GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); + clrbits_8(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); } return 0; } diff --git a/arch/m68k/cpu/mcf532x/interrupts.c b/arch/m68k/cpu/mcf532x/interrupts.c index d6c820545..d1ea2ff5a 100644 --- a/arch/m68k/cpu/mcf532x/interrupts.c +++ b/arch/m68k/cpu/mcf532x/interrupts.c @@ -1,6 +1,6 @@ /* * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -25,14 +25,15 @@ /* CPU specific interrupt routine */ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ - intp->imrh0 |= 0xFFFFFFFF; - intp->imrl0 |= 0xFFFFFFFF; + setbits_be32(&intp->imrh0, 0xffffffff); + setbits_be32(&intp->imrl0, 0xffffffff); enable_interrupts(); return 0; @@ -41,9 +42,9 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; - intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK; + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c index 5a29e2567..cfdcc8b80 100644 --- a/arch/m68k/cpu/mcf532x/speed.c +++ b/arch/m68k/cpu/mcf532x/speed.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -29,6 +29,7 @@ #include <asm/processor.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -65,13 +66,13 @@ DECLARE_GLOBAL_DATA_PTR; /* Get the value of the current system clock */ int get_sys_clock(void) { - volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); - volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + ccm_t *ccm = (ccm_t *)(MMAP_CCM); + pll_t *pll = (pll_t *)(MMAP_PLL); int divider; /* Test to see if device is in LIMP mode */ - if (ccm->misccr & CCM_MISCCR_LIMP) { - divider = ccm->cdr & CCM_CDR_LPDIV(0xF); + if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) { + divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); #ifdef CONFIG_MCF5301x return (FREF / (3 * (1 << divider))); #endif @@ -80,14 +81,14 @@ int get_sys_clock(void) #endif } else { #ifdef CONFIG_MCF5301x - u32 pfdr = (pll->pcr & 0x3F) + 1; - u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8)); - u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1; + u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; + u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); + u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1; return (((FREF * pfdr) / refdiv) / busdiv); #endif #ifdef CONFIG_MCF532x - return ((FREF * pll->pfdr) / (BUSDIV * 4)); + return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4); #endif } } @@ -103,7 +104,7 @@ int get_sys_clock(void) */ int clock_limp(int div) { - volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + ccm_t *ccm = (ccm_t *)(MMAP_CCM); u32 temp; /* Check bounds of divider */ @@ -113,12 +114,12 @@ int clock_limp(int div) div = MAX_LPD; /* Save of the current value of the SSIDIV so we don't overwrite the value */ - temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF)); + temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF)); /* Apply the divider to the system clock */ - ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); + out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); - ccm->misccr |= CCM_MISCCR_LIMP; + setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); return (FREF / (3 * (1 << div))); } @@ -126,14 +127,15 @@ int clock_limp(int div) /* Exit low power LIMP mode */ int clock_exit_limp(void) { - volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM); + ccm_t *ccm = (ccm_t *)(MMAP_CCM); int fout; /* Exit LIMP mode */ - ccm->misccr &= (~CCM_MISCCR_LIMP); + clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); /* Wait for PLL to lock */ - while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ; + while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK)) + ; fout = get_sys_clock(); @@ -153,10 +155,10 @@ int clock_exit_limp(void) int clock_pll(int fsys, int flags) { #ifdef CONFIG_MCF532x - volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80); + u32 *sdram_workaround = (u32 *)(MMAP_SDRAM + 0x80); #endif - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); - volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); + pll_t *pll = (pll_t *)(MMAP_PLL); int fref, temp, fout, mfd; u32 i; @@ -165,13 +167,13 @@ int clock_pll(int fsys, int flags) if (fsys == 0) { /* Return current PLL output */ #ifdef CONFIG_MCF5301x - u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1; - mfd = (pll->pcr & 0x3F) + 1; + u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1; + mfd = (in_be32(&pll->pcr) & 0x3F) + 1; return (fref * mfd) / busdiv; #endif #ifdef CONFIG_MCF532x - mfd = pll->pfdr; + mfd = in_8(&pll->pfdr); return (fref * mfd / (BUSDIV * 4)); #endif @@ -211,8 +213,8 @@ int clock_pll(int fsys, int flags) * If it has then the SDRAM needs to be put into self refresh * mode before reprogramming the PLL. */ - if (sdram->ctrl & SDRAMC_SDCR_REF) - sdram->ctrl &= ~SDRAMC_SDCR_CKE; + if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) + clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE); /* * Initialize the PLL to generate the new system clock frequency. @@ -223,35 +225,36 @@ int clock_pll(int fsys, int flags) clock_limp(DEFAULT_LPD); #ifdef CONFIG_MCF5301x - pll->pdr = - PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) | - PLL_PDR_OUTDIV2(BUSDIV - 1) | - PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) | - PLL_PDR_OUTDIV4(USBDIV - 1); + out_be32(&pll->pdr, + PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) | + PLL_PDR_OUTDIV2(BUSDIV - 1) | + PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) | + PLL_PDR_OUTDIV4(USBDIV - 1)); - pll->pcr &= PLL_PCR_FBDIV_UNMASK; - pll->pcr |= PLL_PCR_FBDIV(mfd - 1); + clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK); + setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1)); #endif #ifdef CONFIG_MCF532x /* Reprogram PLL for desired fsys */ - pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV)); + out_8(&pll->podr, + PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV)); - pll->pfdr = mfd; + out_8(&pll->pfdr, mfd); #endif /* Exit LIMP mode */ clock_exit_limp(); /* Return the SDRAM to normal operation if it is in use. */ - if (sdram->ctrl & SDRAMC_SDCR_REF) - sdram->ctrl |= SDRAMC_SDCR_CKE; + if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) + setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE); #ifdef CONFIG_MCF532x /* * software workaround for SDRAM opeartion after exiting LIMP * mode errata */ - *sdram_workaround = CONFIG_SYS_SDRAM_BASE; + out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE); #endif /* wait for DQS logic to relock */ diff --git a/arch/m68k/cpu/mcf5445x/cpu.c b/arch/m68k/cpu/mcf5445x/cpu.c index 323a54eab..adfc708c3 100644 --- a/arch/m68k/cpu/mcf5445x/cpu.c +++ b/arch/m68k/cpu/mcf5445x/cpu.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -31,14 +31,15 @@ #include <netdev.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM); + rcm_t *rcm = (rcm_t *) (MMAP_RCM); udelay(1000); - rcm->rcr |= RCM_RCR_SOFTRST; + setbits_8(&rcm->rcr, RCM_RCR_SOFTRST); /* we don't return! */ return 0; @@ -46,14 +47,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int checkcpu(void) { - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + ccm_t *ccm = (ccm_t *) MMAP_CCM; u16 msk; u16 id = 0; u8 ver; puts("CPU: "); - msk = (ccm->cir >> 6); - ver = (ccm->cir & 0x003f); + msk = (in_be16(&ccm->cir) >> 6); + ver = (in_be16(&ccm->cir) & 0x003f); switch (msk) { case 0x48: id = 54455; diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index fdcd18585..3f9209ff1 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. + * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -30,6 +30,7 @@ #include <asm/immap.h> #include <asm/processor.h> #include <asm/rtc.h> +#include <asm/io.h> #if defined(CONFIG_CMD_NET) #include <config.h> @@ -46,64 +47,64 @@ */ void cpu_init_f(void) { - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - scm1->mpr = 0x77777777; - scm1->pacra = 0; - scm1->pacrb = 0; - scm1->pacrc = 0; - scm1->pacrd = 0; - scm1->pacre = 0; - scm1->pacrf = 0; - scm1->pacrg = 0; + out_be32(&scm1->mpr, 0x77777777); + out_be32(&scm1->pacra, 0); + out_be32(&scm1->pacrb, 0); + out_be32(&scm1->pacrc, 0); + out_be32(&scm1->pacrd, 0); + out_be32(&scm1->pacre, 0); + out_be32(&scm1->pacrf, 0); + out_be32(&scm1->pacrg, 0); /* FlexBus */ - gpio->par_be = - GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 | - GPIO_PAR_BE_BE0_BE0; - gpio->par_fbctl = - GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW | - GPIO_PAR_FBCTL_TS_TS; + out_8(&gpio->par_be, + GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | + GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0); + out_8(&gpio->par_fbctl, + GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | + GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS); #if !defined(CONFIG_CF_SBF) #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) /* Latch chipselect */ - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif /* @@ -115,7 +116,8 @@ void cpu_init_f(void) setvbr(CONFIG_SYS_CS0_BASE); #ifdef CONFIG_FSL_I2C - gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA; + out_be16(&gpio->par_feci2c, + GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA); #endif icache_enable(); @@ -127,11 +129,11 @@ void cpu_init_f(void) int cpu_init_r(void) { #ifdef CONFIG_MCFRTC - volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE); - volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; + rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE); + rtcex_t *rtcex = (rtcex_t *)&rtc->extended; - rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF; - rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF; + out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff); + out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff); #endif return (0); @@ -139,40 +141,40 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ switch (port) { case 0: - gpio->par_uart &= - ~(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); - gpio->par_uart |= - (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + clrbits_8(&gpio->par_uart, + GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + setbits_8(&gpio->par_uart, + GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); break; case 1: #ifdef CONFIG_SYS_UART1_PRI_GPIO - gpio->par_uart &= - ~(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); - gpio->par_uart |= - (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); + clrbits_8(&gpio->par_uart, + GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); + setbits_8(&gpio->par_uart, + GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); #elif defined(CONFIG_SYS_UART1_ALT1_GPIO) - gpio->par_ssi &= - (GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK); - gpio->par_ssi |= - (GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD); + clrbits_be16(&gpio->par_ssi, + ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK)); + setbits_be16(&gpio->par_ssi, + GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD); #endif break; case 2: #if defined(CONFIG_SYS_UART2_ALT1_GPIO) - gpio->par_timer &= - (GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK); - gpio->par_timer |= - (GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD); + clrbits_8(&gpio->par_timer, + ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK)); + setbits_8(&gpio->par_timer, + GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD); #elif defined(CONFIG_SYS_UART2_ALT2_GPIO) - gpio->par_timer &= - (GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK); - gpio->par_timer |= - (GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD); + clrbits_8(&gpio->par_timer, + ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK)); + setbits_8(&gpio->par_timer, + GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD); #endif break; } @@ -181,43 +183,43 @@ void uart_port_conf(int port) #if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; struct fec_info_s *info = (struct fec_info_s *)dev->priv; if (setclear) { #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_MDC0_MDC0 | - GPIO_PAR_FECI2C_MDIO0_MDIO0); + setbits_be16(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC0_MDC0 | + GPIO_PAR_FECI2C_MDIO0_MDIO0); else - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_MDC1_MDC1 | - GPIO_PAR_FECI2C_MDIO1_MDIO1); + setbits_be16(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC1_MDC1 | + GPIO_PAR_FECI2C_MDIO1_MDIO1); #else - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + setbits_be16(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); #endif if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO; + setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO); else - gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA; + setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA); } else { - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); + clrbits_be16(&gpio->par_feci2c, + GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); if (info->iobase == CONFIG_SYS_FEC0_IOBASE) { #ifdef CONFIG_SYS_FEC_FULL_MII - gpio->par_fec |= GPIO_PAR_FEC_FEC0_MII; + setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII); #else - gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK; + clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK); #endif } else { #ifdef CONFIG_SYS_FEC_FULL_MII - gpio->par_fec |= GPIO_PAR_FEC_FEC1_MII; + setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII); #else - gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK; + clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK); #endif } } @@ -228,43 +230,45 @@ int fecpin_setclear(struct eth_device *dev, int setclear) #ifdef CONFIG_CF_DSPI void cfspi_port_conf(void) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; - gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | - GPIO_PAR_DSPI_SCK_SCK; + out_8(&gpio->par_dspi, + GPIO_PAR_DSPI_SIN_SIN | + GPIO_PAR_DSPI_SOUT_SOUT | + GPIO_PAR_DSPI_SCK_SCK); } int cfspi_claim_bus(uint bus, uint cs) { - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + dspi_t *dspi = (dspi_t *) MMAP_DSPI; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; - if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) + if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) return -1; /* Clear FIFO and resume transfer */ - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); switch (cs) { case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); break; case 1: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); break; case 2: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); break; case 3: - gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK; - gpio->par_dma |= GPIO_PAR_DMA_DACK0_PCS3; + clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); + setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3); break; case 5: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5; - gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); break; } @@ -273,26 +277,27 @@ int cfspi_claim_bus(uint bus, uint cs) void cfspi_release_bus(uint bus, uint cs) { - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + dspi_t *dspi = (dspi_t *) MMAP_DSPI; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */ + /* Clear FIFO */ + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF); switch (cs) { case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0); break; case 1: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1); break; case 2: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2); break; case 3: - gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK; + clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK); break; case 5: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5; + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5); break; } } diff --git a/arch/m68k/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c index 85828a67b..a2cf51933 100644 --- a/arch/m68k/cpu/mcf5445x/interrupts.c +++ b/arch/m68k/cpu/mcf5445x/interrupts.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,14 +28,15 @@ /* CPU specific interrupt routine */ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ - intp->imrh0 |= 0xFFFFFFFF; - intp->imrl0 |= 0xFFFFFFFF; + setbits_be32(&intp->imrh0, 0xffffffff); + setbits_be32(&intp->imrl0, 0xffffffff); enable_interrupts(); return 0; @@ -44,9 +45,9 @@ int interrupt_init(void) #if defined(CONFIG_MCFTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; - intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK; + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/cpu/mcf5445x/pci.c b/arch/m68k/cpu/mcf5445x/pci.c index 7f9784c3c..c32fcee7f 100644 --- a/arch/m68k/cpu/mcf5445x/pci.c +++ b/arch/m68k/cpu/mcf5445x/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -60,78 +60,82 @@ PCI_OP(write, dword, u32, out_le32, 0) void pci_mcf5445x_init(struct pci_controller *hose) { - volatile pci_t *pci = (volatile pci_t *)MMAP_PCI; - volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + pci_t *pci = (pci_t *)MMAP_PCI; + pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; u32 barEn = 0; - pciarb->acr = 0x001F001F; + out_be32(&pciarb->acr, 0x001f001f); /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT, PCIREQ2, PCIGNT2 */ - gpio->par_pci = - GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 | - GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 | - GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0; + out_be16(&gpio->par_pci, + GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | + GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 | + GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 | + GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0); /* Assert reset bit */ - pci->gscr |= PCI_GSCR_PR; + setbits_be32(&pci->gscr, PCI_GSCR_PR); - pci->tcr1 |= PCI_TCR1_P; + setbits_be32(&pci->tcr1, PCI_TCR1_P); /* Initiator windows */ - pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16); - pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16); - pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16); + out_be32(&pci->iw0btar, + CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16)); + out_be32(&pci->iw1btar, + CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16)); + out_be32(&pci->iw2btar, + CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16)); - pci->iwcr = - PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | - PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO; + out_be32(&pci->iwcr, + PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | + PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO); - pci->icr = 0; + out_be32(&pci->icr, 0); /* Enable bus master and mem access */ - pci->scr = PCI_SCR_B | PCI_SCR_M; + out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M); /* Cache line size and master latency */ - pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8); - pci->cr2 = 0; + out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8)); + out_be32(&pci->cr2, 0); #ifdef CONFIG_SYS_PCI_BAR0 - pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0); - pci->tbatr0 = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN; + out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0)); + out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN); barEn |= PCI_TCR2_B0E; #endif #ifdef CONFIG_SYS_PCI_BAR1 - pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1); - pci->tbatr1 = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN; + out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1)); + out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN); barEn |= PCI_TCR2_B1E; #endif #ifdef CONFIG_SYS_PCI_BAR2 - pci->bar2 = PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2); - pci->tbatr2 = CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN; + out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2)); + out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN); barEn |= PCI_TCR2_B2E; #endif #ifdef CONFIG_SYS_PCI_BAR3 - pci->bar3 = PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3); - pci->tbatr3 = CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN; + out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3)); + out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN); barEn |= PCI_TCR2_B3E; #endif #ifdef CONFIG_SYS_PCI_BAR4 - pci->bar4 = PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4); - pci->tbatr4 = CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN; + out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4)); + out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN); barEn |= PCI_TCR2_B4E; #endif #ifdef CONFIG_SYS_PCI_BAR5 - pci->bar5 = PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5); - pci->tbatr5 = CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN; + out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5)); + out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN); barEn |= PCI_TCR2_B5E; #endif - pci->tcr2 = barEn; + out_be32(&pci->tcr2, barEn); /* Deassert reset bit */ - pci->gscr &= ~PCI_GSCR_PR; + clrbits_be32(&pci->gscr, PCI_GSCR_PR); udelay(1000); /* Enable PCI bus master support */ diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c index 9c0c07733..073b7efaf 100644 --- a/arch/m68k/cpu/mcf5445x/speed.c +++ b/arch/m68k/cpu/mcf5445x/speed.c @@ -1,6 +1,6 @@ /* * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -26,6 +26,7 @@ #include <asm/processor.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -44,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR; void clock_enter_limp(int lpdiv) { - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + ccm_t *ccm = (ccm_t *)MMAP_CCM; int i, j; /* Check bounds of divider */ @@ -57,10 +58,10 @@ void clock_enter_limp(int lpdiv) for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ; /* Apply the divider to the system clock */ - ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i); + clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i)); /* Enable Limp Mode */ - ccm->misccr |= CCM_MISCCR_LIMP; + setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); } /* @@ -69,14 +70,15 @@ void clock_enter_limp(int lpdiv) */ void clock_exit_limp(void) { - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + ccm_t *ccm = (ccm_t *)MMAP_CCM; + pll_t *pll = (pll_t *)MMAP_PLL; /* Exit Limp mode */ - ccm->misccr &= ~CCM_MISCCR_LIMP; + clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); /* Wait for the PLL to lock */ - while (!(pll->psr & PLL_PSR_LOCK)) ; + while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) + ; } /* @@ -85,8 +87,8 @@ void clock_exit_limp(void) int get_clocks(void) { - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + ccm_t *ccm = (ccm_t *)MMAP_CCM; + pll_t *pll = (pll_t *)MMAP_PLL; int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 }; int pllmult_pci[] = { 12, 6, 16, 8 }; int vco = 0, bPci, temp, fbtemp, pcrvalue; @@ -94,13 +96,13 @@ int get_clocks(void) u16 fbpll_mask; #ifdef CONFIG_M54455EVB - volatile u8 *cpld = (volatile u8 *)(CONFIG_SYS_CS2_BASE + 3); + u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3); #endif u8 bootmode; /* To determine PCI is present or not */ - if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) || - ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) { + if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) || + ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) { pPllmult = &pllmult_pci[0]; fbpll_mask = 3; /* 11b */ bPci = 1; @@ -114,7 +116,7 @@ int get_clocks(void) } #ifdef CONFIG_M54455EVB - bootmode = (*cpld & 0x03); + bootmode = (in_8(cpld) & 0x03); if (bootmode != 3) { /* Temporary read from CCR- fixed fb issue, must be the same clock @@ -122,11 +124,11 @@ int get_clocks(void) fbtemp = pPllmult[ccm->ccr & fbpll_mask]; /* Break down into small pieces, code still in flex bus */ - pcrvalue = pll->pcr & 0xFFFFF0FF; + pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF; temp = fbtemp - 1; pcrvalue |= PLL_PCR_OUTDIV3(temp); - pll->pcr = pcrvalue; + out_be32(&pll->pcr, pcrvalue); } #endif #ifdef CONFIG_M54451EVB @@ -137,9 +139,10 @@ int get_clocks(void) bootmode = 2; /* default value is 16 mul, set to 20 mul */ - pcrvalue = (pll->pcr & 0x00FFFFFF) | 0x14000000; - pll->pcr = pcrvalue; - while ((pll->psr & PLL_PSR_LOCK) != PLL_PSR_LOCK); + pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000; + out_be32(&pll->pcr, pcrvalue); + while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK) + ; #endif #endif @@ -149,10 +152,10 @@ int get_clocks(void) if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { /* invaild range, re-set in PCR */ - int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; + int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; int i, j, bus; - j = (pll->pcr & 0xFF000000) >> 24; + j = (in_be32(&pll->pcr) & 0xFF000000) >> 24; for (i = j; i < 0xFF; i++) { vco = i * CONFIG_SYS_INPUT_CLKSRC; if (vco >= CLOCK_PLL_FVCO_MIN) { @@ -163,47 +166,47 @@ int get_clocks(void) break; } } - pcrvalue = pll->pcr & 0x00FF00FF; + pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF; fbtemp = ((i - 1) << 8) | ((i - 1) << 12); pcrvalue |= ((i << 24) | fbtemp); - pll->pcr = pcrvalue; + out_be32(&pll->pcr, pcrvalue); } gd->vco_clk = vco; /* Vco clock */ } else if (bootmode == 2) { /* Normal mode */ - vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; + vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { /* Default value */ - pcrvalue = (pll->pcr & 0x00FFFFFF); - pcrvalue |= pPllmult[ccm->ccr & fbpll_mask] << 24; - pll->pcr = pcrvalue; - vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; + pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); + pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24; + out_be32(&pll->pcr, pcrvalue); + vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; } gd->vco_clk = vco; /* Vco clock */ } else if (bootmode == 3) { /* serial mode */ - vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; + vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; gd->vco_clk = vco; /* Vco clock */ } - if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { + if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { /* Limp mode */ } else { gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */ - temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1; + temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1; gd->cpu_clk = vco / temp; /* cpu clock */ - temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; + temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; gd->bus_clk = vco / temp; /* bus clock */ - temp = ((pll->pcr & PLL_PCR_OUTDIV3_MASK) >> 8) + 1; + temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1; gd->flb_clk = vco / temp; /* FlexBus clock */ #ifdef CONFIG_PCI if (bPci) { - temp = ((pll->pcr & PLL_PCR_OUTDIV4_MASK) >> 12) + 1; + temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1; gd->pci_clk = vco / temp; /* PCI clock */ } #endif diff --git a/arch/m68k/cpu/mcf547x_8x/cpu.c b/arch/m68k/cpu/mcf547x_8x/cpu.c index 7590f2c1c..157a8e41a 100644 --- a/arch/m68k/cpu/mcf547x_8x/cpu.c +++ b/arch/m68k/cpu/mcf547x_8x/cpu.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -31,19 +31,20 @@ #include <netdev.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); - gptmr->pre = 10; - gptmr->cnt = 1; + out_be16(&gptmr->pre, 10); + out_be16(&gptmr->cnt, 1); /* enable watchdog, set timeout to 0 and wait */ - gptmr->mode = GPT_TMS_SGPIO; - gptmr->ctrl = GPT_CTRL_WDEN | GPT_CTRL_CE; + out_8(&gptmr->mode, GPT_TMS_SGPIO); + out_8(&gptmr->ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE); /* we don't return! */ return 1; @@ -51,12 +52,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int checkcpu(void) { - volatile siu_t *siu = (siu_t *) MMAP_SIU; + siu_t *siu = (siu_t *) MMAP_SIU; u16 id = 0; puts("CPU: "); - switch ((siu->jtagid & 0x000FF000) >> 12) { + switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) { case 0x0C: id = 5485; break; @@ -111,18 +112,18 @@ int checkcpu(void) /* Called by macro WATCHDOG_RESET */ void hw_watchdog_reset(void) { - volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); - gptmr->ocpw = 0xa5; + out_8(&gptmr->ocpw, 0xa5); } int watchdog_disable(void) { - volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */ - gptmr->mode = 0; - gptmr->ctrl = 0; + out_8(&gptmr->mode, 0); + out_8(&gptmr->ctrl, 0); puts("WATCHDOG:disabled\n"); @@ -131,14 +132,13 @@ int watchdog_disable(void) int watchdog_init(void) { + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); - volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT); + out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000); - gptmr->pre = CONFIG_WATCHDOG_TIMEOUT; - gptmr->cnt = CONFIG_SYS_TIMER_PRESCALER * 1000; - - gptmr->mode = GPT_TMS_SGPIO; - gptmr->ctrl = GPT_CTRL_CE | GPT_CTRL_WDEN; + out_8(&gptmr->mode, GPT_TMS_SGPIO); + out_8(&gptmr->ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN); puts("WATCHDOG:enabled\n"); return (0); diff --git a/arch/m68k/cpu/mcf547x_8x/cpu_init.c b/arch/m68k/cpu/mcf547x_8x/cpu_init.c index 60c91267a..4eb8a7c18 100644 --- a/arch/m68k/cpu/mcf547x_8x/cpu_init.c +++ b/arch/m68k/cpu/mcf547x_8x/cpu_init.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2007 Freescale Semiconductor, Inc. + * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,7 @@ #include <common.h> #include <MCD_dma.h> #include <asm/immap.h> +#include <asm/io.h> #if defined(CONFIG_CMD_NET) #include <config.h> @@ -44,58 +45,59 @@ */ void cpu_init_f(void) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB; - xlbarb->adrto = 0x2000; - xlbarb->datto = 0x2500; - xlbarb->busto = 0x3000; + out_be32(&xlbarb->adrto, 0x2000); + out_be32(&xlbarb->datto, 0x2500); + out_be32(&xlbarb->busto, 0x3000); - xlbarb->cfg = XARB_CFG_AT | XARB_CFG_DT; + out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT); /* Master Priority Enable */ - xlbarb->prien = 0xff; - xlbarb->pri = 0; + out_be32(&xlbarb->prien, 0xff); + out_be32(&xlbarb->pri, 0); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #ifdef CONFIG_FSL_I2C - gpio->par_feci2cirq = GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA; + out_be16(&gpio->par_feci2cirq, + GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA); #endif icache_enable(); @@ -115,44 +117,44 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); /* Setup Ports: */ switch (port) { case 0: - gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); + out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); break; case 1: - gpio->par_psc1 = (GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1); + out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1); break; case 2: - gpio->par_psc2 = (GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2); + out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2); break; case 3: - gpio->par_psc3 = (GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3); + out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3); break; } - *pscsicr &= 0xF8; + clrbits_8(pscsicr, 0x07); } #if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; struct fec_info_dma *info = (struct fec_info_dma *)dev->priv; if (setclear) { if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_feci2cirq |= 0xF000; + setbits_be16(&gpio->par_feci2cirq, 0xf000); else - gpio->par_feci2cirq |= 0x0FC0; + setbits_be16(&gpio->par_feci2cirq, 0x0fc0); } else { if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_feci2cirq &= 0x0FFF; + clrbits_be16(&gpio->par_feci2cirq, 0xf000); else - gpio->par_feci2cirq &= 0xF03F; + clrbits_be16(&gpio->par_feci2cirq, 0x0fc0); } return 0; } diff --git a/arch/m68k/cpu/mcf547x_8x/interrupts.c b/arch/m68k/cpu/mcf547x_8x/interrupts.c index 76be876aa..d21543801 100644 --- a/arch/m68k/cpu/mcf547x_8x/interrupts.c +++ b/arch/m68k/cpu/mcf547x_8x/interrupts.c @@ -1,6 +1,6 @@ /* * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -25,14 +25,15 @@ /* CPU specific interrupt routine */ #include <common.h> #include <asm/immap.h> +#include <asm/io.h> int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ - intp->imrh0 |= 0xFFFFFFFF; - intp->imrl0 |= 0xFFFFFFFF; + setbits_be32(&intp->imrh0, 0xffffffff); + setbits_be32(&intp->imrl0, 0xffffffff); enable_interrupts(); @@ -42,9 +43,9 @@ int interrupt_init(void) #if defined(CONFIG_SLTTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; - intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK; + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/cpu/mcf547x_8x/pci.c b/arch/m68k/cpu/mcf547x_8x/pci.c index f867dc127..1a81e3f04 100644 --- a/arch/m68k/cpu/mcf547x_8x/pci.c +++ b/arch/m68k/cpu/mcf547x_8x/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -88,53 +88,56 @@ int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev, void pci_mcf547x_8x_init(struct pci_controller *hose) { - volatile pci_t *pci = (volatile pci_t *) MMAP_PCI; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + pci_t *pci = (pci_t *) MMAP_PCI; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Port configuration */ - gpio->par_pcibg = - GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) | - GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) | - GPIO_PAR_PCIBG_PCIBG4(3); - gpio->par_pcibr = - GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) | - GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) | - GPIO_PAR_PCIBR_PCIBR4(3); + out_be16(&gpio->par_pcibg, + GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) | + GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) | + GPIO_PAR_PCIBG_PCIBG4(3)); + out_be16(&gpio->par_pcibr, + GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) | + GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) | + GPIO_PAR_PCIBR_PCIBR4(3)); /* Assert reset bit */ - pci->gscr |= PCI_GSCR_PR; + setbits_be32(&pci->gscr, PCI_GSCR_PR); - pci->tcr1 = PCI_TCR1_P; + out_be32(&pci->tcr1, PCI_TCR1_P); /* Initiator windows */ - pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16); - pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16); - pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16); + out_be32(&pci->iw0btar, + CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16)); + out_be32(&pci->iw1btar, + CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16)); + out_be32(&pci->iw2btar, + CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16)); - pci->iwcr = - PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | - PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO; + out_be32(&pci->iwcr, + PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | + PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO); - pci->icr = 0; + out_be32(&pci->icr, 0); /* Enable bus master and mem access */ - pci->scr = PCI_SCR_B | PCI_SCR_M; + out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M); /* Cache line size and master latency */ - pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8); - pci->cr2 = 0; + out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8)); + out_be32(&pci->cr2, 0); #ifdef CONFIG_SYS_PCI_BAR0 - pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0); - pci->tbatr0a = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN; + out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0)); + out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN); #endif #ifdef CONFIG_SYS_PCI_BAR1 - pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1); - pci->tbatr1a = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN; + out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1)); + out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN); #endif /* Deassert reset bit */ - pci->gscr &= ~PCI_GSCR_PR; + clrbits_be32(&pci->gscr, PCI_GSCR_PR); udelay(1000); /* Enable PCI bus master support */ diff --git a/arch/m68k/cpu/mcf547x_8x/slicetimer.c b/arch/m68k/cpu/mcf547x_8x/slicetimer.c index ee2e35bd5..25dd2aed5 100644 --- a/arch/m68k/cpu/mcf547x_8x/slicetimer.c +++ b/arch/m68k/cpu/mcf547x_8x/slicetimer.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 Freescale Semiconductor, Inc. + * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -25,6 +25,7 @@ #include <asm/timer.h> #include <asm/immap.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -42,31 +43,32 @@ extern void dtimer_intr_setup(void); void __udelay(unsigned long usec) { - volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE); + slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE); u32 now, freq; /* 1 us period */ freq = CONFIG_SYS_TIMER_PRESCALER; - timerp->cr = 0; /* Disable */ - timerp->tcnt = usec * freq; - timerp->cr = SLT_CR_TEN; + /* Disable */ + out_be32(&timerp->cr, 0); + out_be32(&timerp->tcnt, usec * freq); + out_be32(&timerp->cr, SLT_CR_TEN); - now = timerp->cnt; + now = in_be32(&timerp->cnt); while (now != 0) - now = timerp->cnt; + now = in_be32(&timerp->cnt); - timerp->sr |= SLT_SR_ST; - timerp->cr = 0; + setbits_be32(&timerp->sr, SLT_SR_ST); + out_be32(&timerp->cr, 0); } void dtimer_interrupt(void *not_used) { - volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); + slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); /* check for timer interrupt asserted */ if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) { - timerp->sr |= SLT_SR_ST; + setbits_be32(&timerp->sr, SLT_SR_ST); timestamp++; return; } @@ -74,25 +76,27 @@ void dtimer_interrupt(void *not_used) int timer_init(void) { - volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); + slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); timestamp = 0; - timerp->cr = 0; /* disable timer */ - timerp->tcnt = 0; - timerp->sr = SLT_SR_BE | SLT_SR_ST; /* clear status */ + /* disable timer */ + out_be32(&timerp->cr, 0); + out_be32(&timerp->tcnt, 0); + /* clear status */ + out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST); /* initialize and enable timer interrupt */ irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0); /* Interrupt every ms */ - timerp->tcnt = 1000 * CONFIG_SYS_TIMER_PRESCALER; + out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER); dtimer_intr_setup(); /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ - timerp->cr = SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN; + out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN); return 0; } diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h index ad971b4f3..525d90ccb 100644 --- a/arch/m68k/include/asm/bitops.h +++ b/arch/m68k/include/asm/bitops.h @@ -17,41 +17,36 @@ extern int test_and_change_bit(int nr, volatile void *addr); #ifdef __KERNEL__ -/* - * ffs: find first bit set. This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ -extern __inline__ int ffs(int x) + +extern inline int test_bit(int nr, __const__ volatile void *addr) +{ + __const__ unsigned int *p = (__const__ unsigned int *) addr; + + return (p[nr >> 5] & (1UL << (nr & 31))) != 0; +} + +extern inline int test_and_set_bit(int nr, volatile void *vaddr) { - int r = 1; + char retval; + + volatile char *p = &((volatile char *)vaddr)[(nr^31) >> 3]; + __asm__ __volatile__ ("bset %2,(%4); sne %0" + : "=d" (retval), "=m" (*p) + : "di" (nr & 7), "m" (*p), "a" (p)); - if (!x) - return 0; - if (!(x & 0xffff)) { - x >>= 16; - r += 16; - } - if (!(x & 0xff)) { - x >>= 8; - r += 8; - } - if (!(x & 0xf)) { - x >>= 4; - r += 4; - } - if (!(x & 3)) { - x >>= 2; - r += 2; - } - if (!(x & 1)) { - x >>= 1; - r += 1; - } - return r; + return retval; } + #define __ffs(x) (ffs(x) - 1) -#define PLATFORM_FFS + +/* + * * hweightN: returns the hamming weight (i.e. the number + * * of bits set) of a N-bit word + * */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) #endif /* __KERNEL__ */ diff --git a/arch/m68k/include/asm/coldfire/flexbus.h b/arch/m68k/include/asm/coldfire/flexbus.h index 51cbbd8b2..9a3078a14 100644 --- a/arch/m68k/include/asm/coldfire/flexbus.h +++ b/arch/m68k/include/asm/coldfire/flexbus.h @@ -29,7 +29,57 @@ /********************************************************************* * FlexBus Chip Selects (FBCS) *********************************************************************/ +#ifdef CONFIG_M5235 +typedef struct fbcs { + u16 csar0; /* Chip-select Address */ + u16 res1; + u32 csmr0; /* Chip-select Mask */ + u16 res2; + u16 cscr0; /* Chip-select Control */ + + u16 csar1; + u16 res3; + u32 csmr1; + u16 res4; + u16 cscr1; + + u16 csar2; + u16 res5; + u32 csmr2; + u16 res6; + u16 cscr2; + + u16 csar3; + u16 res7; + u32 csmr3; + u16 res8; + u16 cscr3; + + u16 csar4; + u16 res9; + u32 csmr4; + u16 res10; + u16 cscr4; + + u16 csar5; + u16 res11; + u32 csmr5; + u16 res12; + u16 cscr5; + u16 csar6; + u16 res13; + u32 csmr6; + u16 res14; + u16 cscr6; + + u16 csar7; + u16 res15; + u32 csmr7; + u16 res16; + u16 cscr7; +} fbcs_t; +#else typedef struct fbcs { u32 csar0; /* Chip-select Address */ u32 csmr0; /* Chip-select Mask */ @@ -56,6 +106,7 @@ typedef struct fbcs { u32 csmr7; u32 cscr7; } fbcs_t; +#endif #define FBCS_CSAR_BA(x) ((x) & 0xFFFF0000) @@ -94,6 +145,22 @@ typedef struct fbcs { #endif #define FBCS_CSMR_V (0x00000001) /* Valid bit */ +#ifdef CONFIG_M5235 +#define FBCS_CSCR_SRWS(x) (((x) & 0x3) << 14) +#define FBCS_CSCR_IWS(x) (((x) & 0xF) << 10) +#define FBCS_CSCR_AA_ON (1 << 8) +#define FBCS_CSCR_AA_OFF (0 << 8) +#define FBCS_CSCR_PS_32 (0 << 6) +#define FBCS_CSCR_PS_16 (2 << 6) +#define FBCS_CSCR_PS_8 (1 << 6) +#define FBCS_CSCR_BEM_ON (1 << 5) +#define FBCS_CSCR_BEM_OFF (0 << 5) +#define FBCS_CSCR_BSTR_ON (1 << 4) +#define FBCS_CSCR_BSTR_OFF (0 << 4) +#define FBCS_CSCR_BSTW_ON (1 << 3) +#define FBCS_CSCR_BSTW_OFF (0 << 3) +#define FBCS_CSCR_SWWS(x) (((x) & 0x7) << 0) +#else #define FBCS_CSCR_SWS(x) (((x) & 0x3F) << 26) #define FBCS_CSCR_SWS_MASK (0x03FFFFFF) #define FBCS_CSCR_SWSEN (0x00800000) @@ -116,5 +183,6 @@ typedef struct fbcs { #define FBCS_CSCR_PS_16 (0x00000080) #define FBCS_CSCR_PS_8 (0x00000040) #define FBCS_CSCR_PS_32 (0x00000000) +#endif #endif /* __FLEXBUS_H */ diff --git a/arch/m68k/include/asm/coldfire/qspi.h b/arch/m68k/include/asm/coldfire/qspi.h index 8bcd2e4db..9fd98f6c0 100644 --- a/arch/m68k/include/asm/coldfire/qspi.h +++ b/arch/m68k/include/asm/coldfire/qspi.h @@ -98,7 +98,7 @@ typedef struct qspi_ctrl { #define QSPI_QAR_RECV (0x0010) #define QSPI_QAR_CMD (0x0020) -/* DR */ +/* DR with RAM command word definitions */ #define QSPI_QDR_CONT (0x8000) #define QSPI_QDR_BITSE (0x4000) #define QSPI_QDR_DT (0x2000) diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h index d86eaf95e..50ed74989 100644 --- a/arch/m68k/include/asm/io.h +++ b/arch/m68k/include/asm/io.h @@ -1,7 +1,7 @@ /* * IO header file * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -225,6 +225,42 @@ extern inline void out_be32(volatile unsigned *addr, int val) *addr = val; } +/* Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single call. These macros can + * also be used to set a multiple-bit bit pattern using a mask, by + * specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrbits(type, addr, clear) \ + out_##type((addr), in_##type(addr) & ~(clear)) + +#define setbits(type, addr, set) \ + out_##type((addr), in_##type(addr) | (set)) + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrbits_be32(addr, clear) clrbits(be32, addr, clear) +#define setbits_be32(addr, set) setbits(be32, addr, set) +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) + +#define clrbits_le32(addr, clear) clrbits(le32, addr, clear) +#define setbits_le32(addr, set) setbits(le32, addr, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrbits_be16(addr, clear) clrbits(be16, addr, clear) +#define setbits_be16(addr, set) setbits(be16, addr, set) +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) + +#define clrbits_le16(addr, clear) clrbits(le16, addr, clear) +#define setbits_le16(addr, set) setbits(le16, addr, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) + +#define clrbits_8(addr, clear) clrbits(8, addr, clear) +#define setbits_8(addr, set) setbits(8, addr, set) +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + static inline void sync(void) { /* This sync function is for PowerPC or other architecture instruction diff --git a/arch/m68k/include/asm/m5271.h b/arch/m68k/include/asm/m5271.h index d25261bcd..b2bc05111 100644 --- a/arch/m68k/include/asm/m5271.h +++ b/arch/m68k/include/asm/m5271.h @@ -171,6 +171,32 @@ #define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00 #define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300 +/* Bit definitions and macros for PAR_QSPI */ +#define MCF_GPIO_PAR_QSPI_PCS1_UNMASK 0x3F +#define MCF_GPIO_PAR_QSPI_PCS1_PCS1 0xC0 +#define MCF_GPIO_PAR_QSPI_PCS1_SDRAM_SCKE 0x80 +#define MCF_GPIO_PAR_QSPI_PCS1_GPIO 0x00 +#define MCF_GPIO_PAR_QSPI_PCS0_UNMASK 0xDF +#define MCF_GPIO_PAR_QSPI_PCS0_PCS0 0x20 +#define MCF_GPIO_PAR_QSPI_PCS0_GPIO 0x00 +#define MCF_GPIO_PAR_QSPI_SIN_UNMASK 0xE7 +#define MCF_GPIO_PAR_QSPI_SIN_SIN 0x18 +#define MCF_GPIO_PAR_QSPI_SIN_I2C_SDA 0x10 +#define MCF_GPIO_PAR_QSPI_SIN_GPIO 0x00 +#define MCF_GPIO_PAR_QSPI_SOUT_UNMASK 0xFB +#define MCF_GPIO_PAR_QSPI_SOUT_SOUT 0x04 +#define MCF_GPIO_PAR_QSPI_SOUT_GPIO 0x00 +#define MCF_GPIO_PAR_QSPI_SCK_UNMASK 0xFC +#define MCF_GPIO_PAR_QSPI_SCK_SCK 0x03 +#define MCF_GPIO_PAR_QSPI_SCK_I2C_SCL 0x02 +#define MCF_GPIO_PAR_QSPI_SCK_GPIO 0x00 + +/* Bit definitions and macros for PAR_TIMER for QSPI */ +#define MCF_GPIO_PAR_TIMER_T3IN_UNMASK 0x3FFF +#define MCF_GPIO_PAR_TIMER_T3IN_QSPI_PCS2 0x4000 +#define MCF_GPIO_PAR_TIMER_T3OUT_UNMASK 0xFF3F +#define MCF_GPIO_PAR_TIMER_T3OUT_QSPI_PCS3 0x0040 + #define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6) #define MCF_SDRAMC_DCR 0x000040 |