8 files changed, 123 insertions, 7 deletions
diff --git a/arch/arm/cpu/arm920t/s3c24x0/Makefile b/arch/arm/cpu/arm920t/s3c24x0/Makefile
index bd53724b5..0029700e4 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/Makefile
+++ b/arch/arm/cpu/arm920t/s3c24x0/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(SOC).o
 
 COBJS-$(CONFIG_USE_IRQ) += interrupts.o
+COBJS-$(CONFIG_DISPLAY_CPUINFO)	+= cpu_info.o
 COBJS-y	+= speed.o
 COBJS-y	+= timer.o
 COBJS-y	+= usb.o
diff --git a/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c b/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c
new file mode 100644
index 000000000..14c5c6a00
--- /dev/null
+++ b/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2010
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+typedef ulong (*getfreq)(void);
+
+static const getfreq freq_f[] = {
+	get_FCLK,
+	get_HCLK,
+	get_PCLK,
+};
+
+static const char freq_c[] = { 'F', 'H', 'P' };
+
+int print_cpuinfo(void)
+{
+	int i;
+	char buf[32];
+/* the S3C2400 seems to be lacking a CHIP ID register */
+#ifndef CONFIG_S3C2400
+	ulong cpuid;
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	cpuid = readl(&gpio->gstatus1);
+	printf("CPUID: %8lX\n", cpuid);
+#endif
+	for (i = 0; i < ARRAY_SIZE(freq_f); i++)
+		printf("%cCLK: %8s MHz\n", freq_c[i], strmhz(buf, freq_f[i]()));
+
+	return 0;
+}
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 441564203..ee90ab719 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -38,11 +38,6 @@ void invalidate_dcache_all(void)
 	dcache_noop();
 }
 
-void flush_dcache_all(void)
-{
-	dcache_noop();
-}
-
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
 	dcache_noop();
diff --git a/arch/arm/cpu/arm926ejs/davinci/timer.c b/arch/arm/cpu/arm926ejs/davinci/timer.c
index a06d44955..93c9e60b7 100644
--- a/arch/arm/cpu/arm926ejs/davinci/timer.c
+++ b/arch/arm/cpu/arm926ejs/davinci/timer.c
@@ -108,7 +108,7 @@ void __udelay(unsigned long usec)
  */
 ulong get_tbclk(void)
 {
-	return CONFIG_SYS_HZ;
+	return gd->timer_rate_hz;
 }
 
 #ifdef CONFIG_HW_WATCHDOG
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 6a77c71e1..ef08a55ab 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -132,6 +132,7 @@ reset:
 	orr	r0, r0, #0xd3
 	msr	cpsr,r0
 
+#if !defined(CONFIG_TEGRA2)
 /*
  * Setup vector:
  * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
@@ -147,6 +148,7 @@ reset:
 	ldr	r0, =_start
 	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
 #endif
+#endif	/* !Tegra2 */
 
 	/* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/arch/arm/include/asm/arch-davinci/da8xx-fb.h b/arch/arm/include/asm/arch-davinci/da8xx-fb.h
index 6d2327c8c..a9181d89c 100644
--- a/arch/arm/include/asm/arch-davinci/da8xx-fb.h
+++ b/arch/arm/include/asm/arch-davinci/da8xx-fb.h
@@ -123,4 +123,3 @@ struct lcd_sync_arg {
 void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel);
 
 #endif  /* ifndef DA8XX_FB_H */
-
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index c2a9b46cf..cd304e868 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -470,6 +470,47 @@ struct omap4_prcm_regs {
 
 };
 
+struct omap4_scrm_regs {
+	u32 revision;		/* 0x0000 */
+	u32 pad00[63];
+	u32 clksetuptime;	/* 0x0100 */
+	u32 pmicsetuptime;	/* 0x0104 */
+	u32 pad01[2];
+	u32 altclksrc;		/* 0x0110 */
+	u32 pad02[2];
+	u32 c2cclkm;		/* 0x011c */
+	u32 pad03[56];
+	u32 extclkreq;		/* 0x0200 */
+	u32 accclkreq;		/* 0x0204 */
+	u32 pwrreq;		/* 0x0208 */
+	u32 pad04[1];
+	u32 auxclkreq0;		/* 0x0210 */
+	u32 auxclkreq1;		/* 0x0214 */
+	u32 auxclkreq2;		/* 0x0218 */
+	u32 auxclkreq3;		/* 0x021c */
+	u32 auxclkreq4;		/* 0x0220 */
+	u32 auxclkreq5;		/* 0x0224 */
+	u32 pad05[3];
+	u32 c2cclkreq;		/* 0x0234 */
+	u32 pad06[54];
+	u32 auxclk0;		/* 0x0310 */
+	u32 auxclk1;		/* 0x0314 */
+	u32 auxclk2;		/* 0x0318 */
+	u32 auxclk3;		/* 0x031c */
+	u32 auxclk4;		/* 0x0320 */
+	u32 auxclk5;		/* 0x0324 */
+	u32 pad07[54];
+	u32 rsttime_reg;	/* 0x0400 */
+	u32 pad08[6];
+	u32 c2crstctrl;		/* 0x041c */
+	u32 extpwronrstctrl;	/* 0x0420 */
+	u32 pad09[59];
+	u32 extwarmrstst_reg;	/* 0x0510 */
+	u32 apewarmrstst_reg;	/* 0x0514 */
+	u32 pad10[1];
+	u32 c2cwarmrstst_reg;	/* 0x051C */
+};
+
 /* DPLL register offsets */
 #define CM_CLKMODE_DPLL		0
 #define CM_IDLEST_DPLL		0x4
@@ -652,6 +693,28 @@ struct omap4_prcm_regs {
 #define TPS62361_BASE_VOLT_MV	500
 #define TPS62361_VSEL0_GPIO	7
 
+/* AUXCLKx reg fields */
+#define AUXCLK_ENABLE_MASK		(1 << 8)
+#define AUXCLK_SRCSELECT_SHIFT		1
+#define AUXCLK_SRCSELECT_MASK		(3 << 1)
+#define AUXCLK_CLKDIV_SHIFT		16
+#define AUXCLK_CLKDIV_MASK		(0xF << 16)
+
+#define AUXCLK_SRCSELECT_SYS_CLK	0
+#define AUXCLK_SRCSELECT_CORE_DPLL	1
+#define AUXCLK_SRCSELECT_PER_DPLL	2
+#define AUXCLK_SRCSELECT_ALTERNATE	3
+
+#define AUXCLK_CLKDIV_2			1
+#define AUXCLK_CLKDIV_16		0xF
+
+/* ALTCLKSRC */
+#define ALTCLKSRC_MODE_MASK		3
+#define ALTCLKSRC_ENABLE_INT_MASK	4
+#define ALTCLKSRC_ENABLE_EXT_MASK	8
+
+#define ALTCLKSRC_MODE_ACTIVE		1
+
 /* Defines for DPLL setup */
 #define DPLL_LOCKED_FREQ_TOLERANCE_0		0
 #define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 802e833a2..afa0093df 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -206,6 +206,8 @@ static int bootm_linux_fdt(int machid, bootm_headers_t *images)
 
 	fixup_memory_node(*of_flat_tree);
 
+	fdt_fixup_ethernet(*of_flat_tree);
+
 	fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1);
 
 	announce_and_cleanup();