diff options
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-at91/at91_spi.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-at91/at91sam9263.h | 13 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-at91/at91sam9263_matrix.h | 146 |
3 files changed, 56 insertions, 105 deletions
diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h b/arch/arm/include/asm/arch-at91/at91_spi.h index c520e89d2..afe724d02 100644 --- a/arch/arm/include/asm/arch-at91/at91_spi.h +++ b/arch/arm/include/asm/arch-at91/at91_spi.h @@ -33,7 +33,7 @@ typedef struct at91_spi { at91_pdc_t pdc; } at91_spi_t; -#ifdef CONFIG_AT91_LEGACY +#ifdef CONFIG_ATMEL_LEGACY #define AT91_SPI_CR 0x00 /* Control Register */ #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ diff --git a/arch/arm/include/asm/arch-at91/at91sam9263.h b/arch/arm/include/asm/arch-at91/at91sam9263.h index 2a1d6ee04..bf9ff7689 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9263.h +++ b/arch/arm/include/asm/arch-at91/at91sam9263.h @@ -125,10 +125,23 @@ #define ATMEL_BASE_UHP 0x00a00000 /* USB Host controller */ /* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 /* typically NOR */ +#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 +#define ATMEL_BASE_CS6 0x70000000 +#define ATMEL_BASE_CS7 0x80000000 + +/* * Other misc defines */ #define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */ #define ATMEL_BASE_PIO ATMEL_BASE_PIOA +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP /* * Cpu Name diff --git a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h index 83aaaab77..3f6709363 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91sam9263_matrix.h @@ -15,115 +15,53 @@ #ifndef AT91SAM9263_MATRIX_H #define AT91SAM9263_MATRIX_H -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ -#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ -#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) +#ifndef __ASSEMBLY__ -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ -#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) +/* + * This struct defines access to the matrix' maximum of + * 16 masters and 16 slaves. + * Note: not all masters/slaves are available + */ +struct at91_matrix { + u32 mcfg[16]; /* Master Configuration Registers */ + u32 scfg[16]; /* Slave Configuration Registers */ + u32 pras[16][2]; /* Priority Assignment Slave Registers */ + u32 mrcr; /* Master Remap Control Register */ + u32 filler[0x06]; + u32 ebicsa; /* EBI Chip Select Assignment Register */ +}; + +#endif /* __ASSEMBLY__ */ -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ -#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ -#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ -#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ -#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ -#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) -#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_16 (5 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_16 (5 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) +#define AT91_MATRIX_M0PR_SHIFT 0 +#define AT91_MATRIX_M1PR_SHIFT 4 +#define AT91_MATRIX_M2PR_SHIFT 8 +#define AT91_MATRIX_M3PR_SHIFT 12 +#define AT91_MATRIX_M4PR_SHIFT 16 +#define AT91_MATRIX_M5PR_SHIFT 20 -#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ -#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4) -#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5) -#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_RCB0 (1 << 0) +#define AT91_MATRIX_RCB1 (1 << 1) -#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */ -#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3) -#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) #endif |