diff options
Diffstat (limited to 'arch/arm/include')
24 files changed, 1225 insertions, 1722 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index 1f597c0ee..33c9c8389 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -16,148 +16,12 @@ #ifndef MMC_HOST_DEF_H #define MMC_HOST_DEF_H +#include <asm/omap_mmc.h> + /* * OMAP HSMMC register definitions */ #define OMAP_HSMMC1_BASE 0x48060100 #define OMAP_HSMMC2_BASE 0x481D8100 -typedef struct hsmmc { - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned int sysstatus; /* 0x14 */ - unsigned char res2[0x14]; - unsigned int con; /* 0x2C */ - unsigned char res3[0xD4]; - unsigned int blk; /* 0x104 */ - unsigned int arg; /* 0x108 */ - unsigned int cmd; /* 0x10C */ - unsigned int rsp10; /* 0x110 */ - unsigned int rsp32; /* 0x114 */ - unsigned int rsp54; /* 0x118 */ - unsigned int rsp76; /* 0x11C */ - unsigned int data; /* 0x120 */ - unsigned int pstate; /* 0x124 */ - unsigned int hctl; /* 0x128 */ - unsigned int sysctl; /* 0x12C */ - unsigned int stat; /* 0x130 */ - unsigned int ie; /* 0x134 */ - unsigned char res4[0x8]; - unsigned int capa; /* 0x140 */ -} hsmmc_t; - -/* - * OMAP HS MMC Bit definitions - */ -#define MMC_SOFTRESET (0x1 << 1) -#define RESETDONE (0x1 << 0) -#define NOOPENDRAIN (0x0 << 0) -#define OPENDRAIN (0x1 << 0) -#define OD (0x1 << 0) -#define INIT_NOINIT (0x0 << 1) -#define INIT_INITSTREAM (0x1 << 1) -#define HR_NOHOSTRESP (0x0 << 2) -#define STR_BLOCK (0x0 << 3) -#define MODE_FUNC (0x0 << 4) -#define DW8_1_4BITMODE (0x0 << 5) -#define MIT_CTO (0x0 << 6) -#define CDP_ACTIVEHIGH (0x0 << 7) -#define WPP_ACTIVEHIGH (0x0 << 8) -#define RESERVED_MASK (0x3 << 9) -#define CTPL_MMC_SD (0x0 << 11) -#define BLEN_512BYTESLEN (0x200 << 0) -#define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) -#define BCE_ENABLE (0x1 << 1) -#define ACEN_DISABLE (0x0 << 2) -#define DDIR_OFFSET (4) -#define DDIR_MASK (0x1 << 4) -#define DDIR_WRITE (0x0 << 4) -#define DDIR_READ (0x1 << 4) -#define MSBS_SGLEBLK (0x0 << 5) -#define MSBS_MULTIBLK (0x1 << 5) -#define RSP_TYPE_OFFSET (16) -#define RSP_TYPE_MASK (0x3 << 16) -#define RSP_TYPE_NORSP (0x0 << 16) -#define RSP_TYPE_LGHT136 (0x1 << 16) -#define RSP_TYPE_LGHT48 (0x2 << 16) -#define RSP_TYPE_LGHT48B (0x3 << 16) -#define CCCE_NOCHECK (0x0 << 19) -#define CCCE_CHECK (0x1 << 19) -#define CICE_NOCHECK (0x0 << 20) -#define CICE_CHECK (0x1 << 20) -#define DP_OFFSET (21) -#define DP_MASK (0x1 << 21) -#define DP_NO_DATA (0x0 << 21) -#define DP_DATA (0x1 << 21) -#define CMD_TYPE_NORMAL (0x0 << 22) -#define INDEX_OFFSET (24) -#define INDEX_MASK (0x3f << 24) -#define INDEX(i) (i << 24) -#define DATI_MASK (0x1 << 1) -#define CMDI_MASK (0x1 << 0) -#define DTW_1_BITMODE (0x0 << 1) -#define DTW_4_BITMODE (0x1 << 1) -#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ -#define SDBP_PWROFF (0x0 << 8) -#define SDBP_PWRON (0x1 << 8) -#define SDVS_1V8 (0x5 << 9) -#define SDVS_3V0 (0x6 << 9) -#define ICE_MASK (0x1 << 0) -#define ICE_STOP (0x0 << 0) -#define ICS_MASK (0x1 << 1) -#define ICS_NOTREADY (0x0 << 1) -#define ICE_OSCILLATE (0x1 << 0) -#define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) -#define CEN_ENABLE (0x1 << 2) -#define CLKD_OFFSET (6) -#define CLKD_MASK (0x3FF << 6) -#define DTO_MASK (0xF << 16) -#define DTO_15THDTO (0xE << 16) -#define SOFTRESETALL (0x1 << 24) -#define CC_MASK (0x1 << 0) -#define TC_MASK (0x1 << 1) -#define BWR_MASK (0x1 << 4) -#define BRR_MASK (0x1 << 5) -#define ERRI_MASK (0x1 << 15) -#define IE_CC (0x01 << 0) -#define IE_TC (0x01 << 1) -#define IE_BWR (0x01 << 4) -#define IE_BRR (0x01 << 5) -#define IE_CTO (0x01 << 16) -#define IE_CCRC (0x01 << 17) -#define IE_CEB (0x01 << 18) -#define IE_CIE (0x01 << 19) -#define IE_DTO (0x01 << 20) -#define IE_DCRC (0x01 << 21) -#define IE_DEB (0x01 << 22) -#define IE_CERR (0x01 << 28) -#define IE_BADA (0x01 << 29) - -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE 512 -#define MMC_CARD 0 -#define SD_CARD 1 -#define BYTE_MODE 0 -#define SECTOR_MODE 1 -#define CLK_INITSEQ 0 -#define CLK_400KHZ 1 -#define CLK_MISC 2 - -#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) -#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) - -/* Clock Configurations and Macros */ -#define MMC_CLOCK_REFERENCE 96 /* MHz */ - -#define mmc_reg_out(addr, mask, val)\ - writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) - -int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max); - #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 588d8de82..97ab60d1b 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -35,5 +35,7 @@ void ddr_pll_config(unsigned int ddrpll_M); void sdelay(unsigned long); void gpmc_init(void); +void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, + u32 size); void omap_nand_switch_ecc(int); #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h index de0f1b192..b7d1932f4 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9x5.h +++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h @@ -140,12 +140,6 @@ /* * Cpu Name */ -#define CONFIG_SYS_AT91_G15_CPU_NAME "AT91SAM9G15" -#define CONFIG_SYS_AT91_G25_CPU_NAME "AT91SAM9G25" -#define CONFIG_SYS_AT91_G35_CPU_NAME "AT91SAM9G35" -#define CONFIG_SYS_AT91_X25_CPU_NAME "AT91SAM9X25" -#define CONFIG_SYS_AT91_X35_CPU_NAME "AT91SAM9X35" -#define CONFIG_SYS_AT91_UNKNOWN_CPU "Unknown CPU type" #define ATMEL_CPU_NAME get_cpu_name() /* diff --git a/arch/arm/include/asm/arch-davinci/gpio.h b/arch/arm/include/asm/arch-davinci/gpio.h index fbbb1f33c..06390c85e 100644 --- a/arch/arm/include/asm/arch-davinci/gpio.h +++ b/arch/arm/include/asm/arch-davinci/gpio.h @@ -67,7 +67,10 @@ struct davinci_gpio_bank { #define gpio_status() gpio_info() #define GPIO_NAME_SIZE 20 -#if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850) +#if defined(CONFIG_SOC_DM644X) +/* GPIO0 to GPIO53, omit the V3.3 volts one */ +#define MAX_NUM_GPIOS 70 +#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850) #define MAX_NUM_GPIOS 128 #else #define MAX_NUM_GPIOS 144 diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h index 91d11ae84..3ca4c9468 100644 --- a/arch/arm/include/asm/arch-mx35/spl.h +++ b/arch/arm/include/asm/arch-mx35/spl.h @@ -27,7 +27,7 @@ #define BOOT_DEVICE_XIP 1 #define BOOT_DEVICE_XIPWAIT 2 #define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONE_NAND 4 +#define BOOT_DEVICE_ONENAND 4 #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 7 diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h index ffaffbb3b..ae0babf17 100644 --- a/arch/arm/include/asm/arch-omap3/dss.h +++ b/arch/arm/include/asm/arch-omap3/dss.h @@ -167,6 +167,36 @@ struct venc_regs { #define VENC_OUT_SEL (1 << 6) #define DIG_LPP_SHIFT 16 +/* LCD display type */ +#define PASSIVE_DISPLAY 0 +#define ACTIVE_DISPLAY 1 + +/* TFTDATALINES */ +#define LCD_INTERFACE_12_BIT 0 +#define LCD_INTERFACE_16_BIT 1 +#define LCD_INTERFACE_18_BIT 2 +#define LCD_INTERFACE_24_BIT 3 + +/* Polarity */ +#define DSS_IVS (1 << 12) +#define DSS_IHS (1 << 13) +#define DSS_IPC (1 << 14) +#define DSS_IEO (1 << 15) + +/* GFX format */ +#define GFXFORMAT_BITMAP1 (0x0 << 1) +#define GFXFORMAT_BITMAP2 (0x1 << 1) +#define GFXFORMAT_BITMAP4 (0x2 << 1) +#define GFXFORMAT_BITMAP8 (0x3 << 1) +#define GFXFORMAT_RGB12 (0x4 << 1) +#define GFXFORMAT_ARGB16 (0x5 << 1) +#define GFXFORMAT_RGB16 (0x6 << 1) +#define GFXFORMAT_RGB24_UNPACKED (0x8 << 1) +#define GFXFORMAT_RGB24_PACKED (0x9 << 1) +#define GFXFORMAT_ARGB32 (0xC << 1) +#define GFXFORMAT_RGBA32 (0xD << 1) +#define GFXFORMAT_RGBx32 (0xE << 1) + /* Panel Configuration */ struct panel_config { u32 timing_h; @@ -178,6 +208,7 @@ struct panel_config { u32 data_lines; u32 load_mode; u32 panel_color; + u32 gfx_format; void *frame_buffer; }; diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h index 3ce1f07b8..0ba621a1b 100644 --- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h @@ -25,6 +25,8 @@ #ifndef MMC_HOST_DEF_H #define MMC_HOST_DEF_H +#include <asm/omap_mmc.h> + /* T2 Register definitions */ #define T2_BASE 0x48002000 @@ -59,142 +61,5 @@ typedef struct t2 { #define OMAP_HSMMC2_BASE 0x480B4000 #define OMAP_HSMMC3_BASE 0x480AD000 -struct hsmmc { - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned int sysstatus; /* 0x14 */ - unsigned char res2[0x14]; - unsigned int con; /* 0x2C */ - unsigned char res3[0xD4]; - unsigned int blk; /* 0x104 */ - unsigned int arg; /* 0x108 */ - unsigned int cmd; /* 0x10C */ - unsigned int rsp10; /* 0x110 */ - unsigned int rsp32; /* 0x114 */ - unsigned int rsp54; /* 0x118 */ - unsigned int rsp76; /* 0x11C */ - unsigned int data; /* 0x120 */ - unsigned int pstate; /* 0x124 */ - unsigned int hctl; /* 0x128 */ - unsigned int sysctl; /* 0x12C */ - unsigned int stat; /* 0x130 */ - unsigned int ie; /* 0x134 */ - unsigned char res4[0x8]; - unsigned int capa; /* 0x140 */ -}; - -/* - * OMAP HS MMC Bit definitions - */ -#define MMC_SOFTRESET (0x1 << 1) -#define RESETDONE (0x1 << 0) -#define NOOPENDRAIN (0x0 << 0) -#define OPENDRAIN (0x1 << 0) -#define OD (0x1 << 0) -#define INIT_NOINIT (0x0 << 1) -#define INIT_INITSTREAM (0x1 << 1) -#define HR_NOHOSTRESP (0x0 << 2) -#define STR_BLOCK (0x0 << 3) -#define MODE_FUNC (0x0 << 4) -#define DW8_1_4BITMODE (0x0 << 5) -#define MIT_CTO (0x0 << 6) -#define CDP_ACTIVEHIGH (0x0 << 7) -#define WPP_ACTIVEHIGH (0x0 << 8) -#define RESERVED_MASK (0x3 << 9) -#define CTPL_MMC_SD (0x0 << 11) -#define BLEN_512BYTESLEN (0x200 << 0) -#define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) -#define BCE_ENABLE (0x1 << 1) -#define ACEN_DISABLE (0x0 << 2) -#define DDIR_OFFSET (4) -#define DDIR_MASK (0x1 << 4) -#define DDIR_WRITE (0x0 << 4) -#define DDIR_READ (0x1 << 4) -#define MSBS_SGLEBLK (0x0 << 5) -#define MSBS_MULTIBLK (0x1 << 5) -#define RSP_TYPE_OFFSET (16) -#define RSP_TYPE_MASK (0x3 << 16) -#define RSP_TYPE_NORSP (0x0 << 16) -#define RSP_TYPE_LGHT136 (0x1 << 16) -#define RSP_TYPE_LGHT48 (0x2 << 16) -#define RSP_TYPE_LGHT48B (0x3 << 16) -#define CCCE_NOCHECK (0x0 << 19) -#define CCCE_CHECK (0x1 << 19) -#define CICE_NOCHECK (0x0 << 20) -#define CICE_CHECK (0x1 << 20) -#define DP_OFFSET (21) -#define DP_MASK (0x1 << 21) -#define DP_NO_DATA (0x0 << 21) -#define DP_DATA (0x1 << 21) -#define CMD_TYPE_NORMAL (0x0 << 22) -#define INDEX_OFFSET (24) -#define INDEX_MASK (0x3f << 24) -#define INDEX(i) (i << 24) -#define DATI_MASK (0x1 << 1) -#define CMDI_MASK (0x1 << 0) -#define DTW_1_BITMODE (0x0 << 1) -#define DTW_4_BITMODE (0x1 << 1) -#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ -#define SDBP_PWROFF (0x0 << 8) -#define SDBP_PWRON (0x1 << 8) -#define SDVS_1V8 (0x5 << 9) -#define SDVS_3V0 (0x6 << 9) -#define ICE_MASK (0x1 << 0) -#define ICE_STOP (0x0 << 0) -#define ICS_MASK (0x1 << 1) -#define ICS_NOTREADY (0x0 << 1) -#define ICE_OSCILLATE (0x1 << 0) -#define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) -#define CEN_ENABLE (0x1 << 2) -#define CLKD_OFFSET (6) -#define CLKD_MASK (0x3FF << 6) -#define DTO_MASK (0xF << 16) -#define DTO_15THDTO (0xE << 16) -#define SOFTRESETALL (0x1 << 24) -#define CC_MASK (0x1 << 0) -#define TC_MASK (0x1 << 1) -#define BWR_MASK (0x1 << 4) -#define BRR_MASK (0x1 << 5) -#define ERRI_MASK (0x1 << 15) -#define IE_CC (0x01 << 0) -#define IE_TC (0x01 << 1) -#define IE_BWR (0x01 << 4) -#define IE_BRR (0x01 << 5) -#define IE_CTO (0x01 << 16) -#define IE_CCRC (0x01 << 17) -#define IE_CEB (0x01 << 18) -#define IE_CIE (0x01 << 19) -#define IE_DTO (0x01 << 20) -#define IE_DCRC (0x01 << 21) -#define IE_DEB (0x01 << 22) -#define IE_CERR (0x01 << 28) -#define IE_BADA (0x01 << 29) - -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE 512 -#define MMC_CARD 0 -#define SD_CARD 1 -#define BYTE_MODE 0 -#define SECTOR_MODE 1 -#define CLK_INITSEQ 0 -#define CLK_400KHZ 1 -#define CLK_MISC 2 - -#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) -#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) - -/* Clock Configurations and Macros */ -#define MMC_CLOCK_REFERENCE 96 /* MHz */ - -#define mmc_reg_out(addr, mask, val)\ - writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) - -int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max); #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap3/spl.h b/arch/arm/include/asm/arch-omap3/spl.h index 404e16a5a..dec4dacba 100644 --- a/arch/arm/include/asm/arch-omap3/spl.h +++ b/arch/arm/include/asm/arch-omap3/spl.h @@ -26,7 +26,7 @@ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 #define BOOT_DEVICE_NAND 2 -#define BOOT_DEVICE_ONE_NAND 3 +#define BOOT_DEVICE_ONENAND 3 #define BOOT_DEVICE_MMC2 5 /*emmc*/ #define BOOT_DEVICE_MMC1 6 #define BOOT_DEVICE_XIPWAIT 7 diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index be20fc0ce..ed7a1c8be 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -25,6 +25,7 @@ #ifndef _CLOCKS_OMAP4_H_ #define _CLOCKS_OMAP4_H_ #include <common.h> +#include <asm/omap_common.h> /* * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per @@ -38,479 +39,6 @@ #define CM_CLKMODE_DPLL_MPU 0x4A004160 #define CM_CLKSEL_CORE 0x4A004100 -struct omap4_prcm_regs { - /* cm1.ckgen */ - u32 cm_clksel_core; - u32 pad001[1]; - u32 cm_clksel_abe; - u32 pad002[1]; - u32 cm_dll_ctrl; - u32 pad003[3]; - u32 cm_clkmode_dpll_core; - u32 cm_idlest_dpll_core; - u32 cm_autoidle_dpll_core; - u32 cm_clksel_dpll_core; - u32 cm_div_m2_dpll_core; - u32 cm_div_m3_dpll_core; - u32 cm_div_m4_dpll_core; - u32 cm_div_m5_dpll_core; - u32 cm_div_m6_dpll_core; - u32 cm_div_m7_dpll_core; - u32 cm_ssc_deltamstep_dpll_core; - u32 cm_ssc_modfreqdiv_dpll_core; - u32 cm_emu_override_dpll_core; - u32 pad004[3]; - u32 cm_clkmode_dpll_mpu; - u32 cm_idlest_dpll_mpu; - u32 cm_autoidle_dpll_mpu; - u32 cm_clksel_dpll_mpu; - u32 cm_div_m2_dpll_mpu; - u32 pad005[5]; - u32 cm_ssc_deltamstep_dpll_mpu; - u32 cm_ssc_modfreqdiv_dpll_mpu; - u32 pad006[3]; - u32 cm_bypclk_dpll_mpu; - u32 cm_clkmode_dpll_iva; - u32 cm_idlest_dpll_iva; - u32 cm_autoidle_dpll_iva; - u32 cm_clksel_dpll_iva; - u32 pad007[2]; - u32 cm_div_m4_dpll_iva; - u32 cm_div_m5_dpll_iva; - u32 pad008[2]; - u32 cm_ssc_deltamstep_dpll_iva; - u32 cm_ssc_modfreqdiv_dpll_iva; - u32 pad009[3]; - u32 cm_bypclk_dpll_iva; - u32 cm_clkmode_dpll_abe; - u32 cm_idlest_dpll_abe; - u32 cm_autoidle_dpll_abe; - u32 cm_clksel_dpll_abe; - u32 cm_div_m2_dpll_abe; - u32 cm_div_m3_dpll_abe; - u32 pad010[4]; - u32 cm_ssc_deltamstep_dpll_abe; - u32 cm_ssc_modfreqdiv_dpll_abe; - u32 pad011[4]; - u32 cm_clkmode_dpll_ddrphy; - u32 cm_idlest_dpll_ddrphy; - u32 cm_autoidle_dpll_ddrphy; - u32 cm_clksel_dpll_ddrphy; - u32 cm_div_m2_dpll_ddrphy; - u32 pad012[1]; - u32 cm_div_m4_dpll_ddrphy; - u32 cm_div_m5_dpll_ddrphy; - u32 cm_div_m6_dpll_ddrphy; - u32 pad013[1]; - u32 cm_ssc_deltamstep_dpll_ddrphy; - u32 pad014[5]; - u32 cm_shadow_freq_config1; - u32 pad0141[47]; - u32 cm_mpu_mpu_clkctrl; - - /* cm1.dsp */ - u32 pad015[55]; - u32 cm_dsp_clkstctrl; - u32 pad016[7]; - u32 cm_dsp_dsp_clkctrl; - - /* cm1.abe */ - u32 pad017[55]; - u32 cm1_abe_clkstctrl; - u32 pad018[7]; - u32 cm1_abe_l4abe_clkctrl; - u32 pad019[1]; - u32 cm1_abe_aess_clkctrl; - u32 pad020[1]; - u32 cm1_abe_pdm_clkctrl; - u32 pad021[1]; - u32 cm1_abe_dmic_clkctrl; - u32 pad022[1]; - u32 cm1_abe_mcasp_clkctrl; - u32 pad023[1]; - u32 cm1_abe_mcbsp1_clkctrl; - u32 pad024[1]; - u32 cm1_abe_mcbsp2_clkctrl; - u32 pad025[1]; - u32 cm1_abe_mcbsp3_clkctrl; - u32 pad026[1]; - u32 cm1_abe_slimbus_clkctrl; - u32 pad027[1]; - u32 cm1_abe_timer5_clkctrl; - u32 pad028[1]; - u32 cm1_abe_timer6_clkctrl; - u32 pad029[1]; - u32 cm1_abe_timer7_clkctrl; - u32 pad030[1]; - u32 cm1_abe_timer8_clkctrl; - u32 pad031[1]; - u32 cm1_abe_wdt3_clkctrl; - - /* cm2.ckgen */ - u32 pad032[3805]; - u32 cm_clksel_mpu_m3_iss_root; - u32 cm_clksel_usb_60mhz; - u32 cm_scale_fclk; - u32 pad033[1]; - u32 cm_core_dvfs_perf1; - u32 cm_core_dvfs_perf2; - u32 cm_core_dvfs_perf3; - u32 cm_core_dvfs_perf4; - u32 pad034[1]; - u32 cm_core_dvfs_current; - u32 cm_iva_dvfs_perf_tesla; - u32 cm_iva_dvfs_perf_ivahd; - u32 cm_iva_dvfs_perf_abe; - u32 pad035[1]; - u32 cm_iva_dvfs_current; - u32 pad036[1]; - u32 cm_clkmode_dpll_per; - u32 cm_idlest_dpll_per; - u32 cm_autoidle_dpll_per; - u32 cm_clksel_dpll_per; - u32 cm_div_m2_dpll_per; - u32 cm_div_m3_dpll_per; - u32 cm_div_m4_dpll_per; - u32 cm_div_m5_dpll_per; - u32 cm_div_m6_dpll_per; - u32 cm_div_m7_dpll_per; - u32 cm_ssc_deltamstep_dpll_per; - u32 cm_ssc_modfreqdiv_dpll_per; - u32 cm_emu_override_dpll_per; - u32 pad037[3]; - u32 cm_clkmode_dpll_usb; - u32 cm_idlest_dpll_usb; - u32 cm_autoidle_dpll_usb; - u32 cm_clksel_dpll_usb; - u32 cm_div_m2_dpll_usb; - u32 pad038[5]; - u32 cm_ssc_deltamstep_dpll_usb; - u32 cm_ssc_modfreqdiv_dpll_usb; - u32 pad039[1]; - u32 cm_clkdcoldo_dpll_usb; - u32 pad040[2]; - u32 cm_clkmode_dpll_unipro; - u32 cm_idlest_dpll_unipro; - u32 cm_autoidle_dpll_unipro; - u32 cm_clksel_dpll_unipro; - u32 cm_div_m2_dpll_unipro; - u32 pad041[5]; - u32 cm_ssc_deltamstep_dpll_unipro; - u32 cm_ssc_modfreqdiv_dpll_unipro; - - /* cm2.core */ - u32 pad0411[324]; - u32 cm_l3_1_clkstctrl; - u32 pad042[1]; - u32 cm_l3_1_dynamicdep; - u32 pad043[5]; - u32 cm_l3_1_l3_1_clkctrl; - u32 pad044[55]; - u32 cm_l3_2_clkstctrl; - u32 pad045[1]; - u32 cm_l3_2_dynamicdep; - u32 pad046[5]; - u32 cm_l3_2_l3_2_clkctrl; - u32 pad047[1]; - u32 cm_l3_2_gpmc_clkctrl; - u32 pad048[1]; - u32 cm_l3_2_ocmc_ram_clkctrl; - u32 pad049[51]; - u32 cm_mpu_m3_clkstctrl; - u32 cm_mpu_m3_staticdep; - u32 cm_mpu_m3_dynamicdep; - u32 pad050[5]; - u32 cm_mpu_m3_mpu_m3_clkctrl; - u32 pad051[55]; - u32 cm_sdma_clkstctrl; - u32 cm_sdma_staticdep; - u32 cm_sdma_dynamicdep; - u32 pad052[5]; - u32 cm_sdma_sdma_clkctrl; - u32 pad053[55]; - u32 cm_memif_clkstctrl; - u32 pad054[7]; - u32 cm_memif_dmm_clkctrl; - u32 pad055[1]; - u32 cm_memif_emif_fw_clkctrl; - u32 pad056[1]; - u32 cm_memif_emif_1_clkctrl; - u32 pad057[1]; - u32 cm_memif_emif_2_clkctrl; - u32 pad058[1]; - u32 cm_memif_dll_clkctrl; - u32 pad059[3]; - u32 cm_memif_emif_h1_clkctrl; - u32 pad060[1]; - u32 cm_memif_emif_h2_clkctrl; - u32 pad061[1]; - u32 cm_memif_dll_h_clkctrl; - u32 pad062[39]; - u32 cm_c2c_clkstctrl; - u32 cm_c2c_staticdep; - u32 cm_c2c_dynamicdep; - u32 pad063[5]; - u32 cm_c2c_sad2d_clkctrl; - u32 pad064[1]; - u32 cm_c2c_modem_icr_clkctrl; - u32 pad065[1]; - u32 cm_c2c_sad2d_fw_clkctrl; - u32 pad066[51]; - u32 cm_l4cfg_clkstctrl; - u32 pad067[1]; - u32 cm_l4cfg_dynamicdep; - u32 pad068[5]; - u32 cm_l4cfg_l4_cfg_clkctrl; - u32 pad069[1]; - u32 cm_l4cfg_hw_sem_clkctrl; - u32 pad070[1]; - u32 cm_l4cfg_mailbox_clkctrl; - u32 pad071[1]; - u32 cm_l4cfg_sar_rom_clkctrl; - u32 pad072[49]; - u32 cm_l3instr_clkstctrl; - u32 pad073[7]; - u32 cm_l3instr_l3_3_clkctrl; - u32 pad074[1]; - u32 cm_l3instr_l3_instr_clkctrl; - u32 pad075[5]; - u32 cm_l3instr_intrconn_wp1_clkctrl; - - - /* cm2.ivahd */ - u32 pad076[47]; - u32 cm_ivahd_clkstctrl; - u32 pad077[7]; - u32 cm_ivahd_ivahd_clkctrl; - u32 pad078[1]; - u32 cm_ivahd_sl2_clkctrl; - - /* cm2.cam */ - u32 pad079[53]; - u32 cm_cam_clkstctrl; - u32 pad080[7]; - u32 cm_cam_iss_clkctrl; - u32 pad081[1]; - u32 cm_cam_fdif_clkctrl; - - /* cm2.dss */ - u32 pad082[53]; - u32 cm_dss_clkstctrl; - u32 pad083[7]; - u32 cm_dss_dss_clkctrl; - - /* cm2.sgx */ - u32 pad084[55]; - u32 cm_sgx_clkstctrl; - u32 pad085[7]; - u32 cm_sgx_sgx_clkctrl; - - /* cm2.l3init */ - u32 pad086[55]; - u32 cm_l3init_clkstctrl; - - /* cm2.l3init */ - u32 pad087[9]; - u32 cm_l3init_hsmmc1_clkctrl; - u32 pad088[1]; - u32 cm_l3init_hsmmc2_clkctrl; - u32 pad089[1]; - u32 cm_l3init_hsi_clkctrl; - u32 pad090[7]; - u32 cm_l3init_hsusbhost_clkctrl; - u32 pad091[1]; - u32 cm_l3init_hsusbotg_clkctrl; - u32 pad092[1]; - u32 cm_l3init_hsusbtll_clkctrl; - u32 pad093[3]; - u32 cm_l3init_p1500_clkctrl; - u32 pad094[21]; - u32 cm_l3init_fsusb_clkctrl; - u32 pad095[3]; - u32 cm_l3init_usbphy_clkctrl; - - /* cm2.l4per */ - u32 pad096[7]; - u32 cm_l4per_clkstctrl; - u32 pad097[1]; - u32 cm_l4per_dynamicdep; - u32 pad098[5]; - u32 cm_l4per_adc_clkctrl; - u32 pad100[1]; - u32 cm_l4per_gptimer10_clkctrl; - u32 pad101[1]; - u32 cm_l4per_gptimer11_clkctrl; - u32 pad102[1]; - u32 cm_l4per_gptimer2_clkctrl; - u32 pad103[1]; - u32 cm_l4per_gptimer3_clkctrl; - u32 pad104[1]; - u32 cm_l4per_gptimer4_clkctrl; - u32 pad105[1]; - u32 cm_l4per_gptimer9_clkctrl; - u32 pad106[1]; - u32 cm_l4per_elm_clkctrl; - u32 pad107[1]; - u32 cm_l4per_gpio2_clkctrl; - u32 pad108[1]; - u32 cm_l4per_gpio3_clkctrl; - u32 pad109[1]; - u32 cm_l4per_gpio4_clkctrl; - u32 pad110[1]; - u32 cm_l4per_gpio5_clkctrl; - u32 pad111[1]; - u32 cm_l4per_gpio6_clkctrl; - u32 pad112[1]; - u32 cm_l4per_hdq1w_clkctrl; - u32 pad113[1]; - u32 cm_l4per_hecc1_clkctrl; - u32 pad114[1]; - u32 cm_l4per_hecc2_clkctrl; - u32 pad115[1]; - u32 cm_l4per_i2c1_clkctrl; - u32 pad116[1]; - u32 cm_l4per_i2c2_clkctrl; - u32 pad117[1]; - u32 cm_l4per_i2c3_clkctrl; - u32 pad118[1]; - u32 cm_l4per_i2c4_clkctrl; - u32 pad119[1]; - u32 cm_l4per_l4per_clkctrl; - u32 pad1191[3]; - u32 cm_l4per_mcasp2_clkctrl; - u32 pad120[1]; - u32 cm_l4per_mcasp3_clkctrl; - u32 pad121[1]; - u32 cm_l4per_mcbsp4_clkctrl; - u32 pad122[1]; - u32 cm_l4per_mgate_clkctrl; - u32 pad123[1]; - u32 cm_l4per_mcspi1_clkctrl; - u32 pad124[1]; - u32 cm_l4per_mcspi2_clkctrl; - u32 pad125[1]; - u32 cm_l4per_mcspi3_clkctrl; - u32 pad126[1]; - u32 cm_l4per_mcspi4_clkctrl; - u32 pad127[5]; - u32 cm_l4per_mmcsd3_clkctrl; - u32 pad128[1]; - u32 cm_l4per_mmcsd4_clkctrl; - u32 pad129[1]; - u32 cm_l4per_msprohg_clkctrl; - u32 pad130[1]; - u32 cm_l4per_slimbus2_clkctrl; - u32 pad131[1]; - u32 cm_l4per_uart1_clkctrl; - u32 pad132[1]; - u32 cm_l4per_uart2_clkctrl; - u32 pad133[1]; - u32 cm_l4per_uart3_clkctrl; - u32 pad134[1]; - u32 cm_l4per_uart4_clkctrl; - u32 pad135[1]; - u32 cm_l4per_mmcsd5_clkctrl; - u32 pad136[1]; - u32 cm_l4per_i2c5_clkctrl; - u32 pad137[5]; - u32 cm_l4sec_clkstctrl; - u32 cm_l4sec_staticdep; - u32 cm_l4sec_dynamicdep; - u32 pad138[5]; - u32 cm_l4sec_aes1_clkctrl; - u32 pad139[1]; - u32 cm_l4sec_aes2_clkctrl; - u32 pad140[1]; - u32 cm_l4sec_des3des_clkctrl; - u32 pad141[1]; - u32 cm_l4sec_pkaeip29_clkctrl; - u32 pad142[1]; - u32 cm_l4sec_rng_clkctrl; - u32 pad143[1]; - u32 cm_l4sec_sha2md51_clkctrl; - u32 pad144[3]; - u32 cm_l4sec_cryptodma_clkctrl; - u32 pad145[776841]; - - /* l4 wkup regs */ - u32 pad201[6211]; - u32 cm_abe_pll_ref_clksel; - u32 cm_sys_clksel; - u32 pad202[1467]; - u32 cm_wkup_clkstctrl; - u32 pad203[7]; - u32 cm_wkup_l4wkup_clkctrl; - u32 pad204; - u32 cm_wkup_wdtimer1_clkctrl; - u32 pad205; - u32 cm_wkup_wdtimer2_clkctrl; - u32 pad206; - u32 cm_wkup_gpio1_clkctrl; - u32 pad207; - u32 cm_wkup_gptimer1_clkctrl; - u32 pad208; - u32 cm_wkup_gptimer12_clkctrl; - u32 pad209; - u32 cm_wkup_synctimer_clkctrl; - u32 pad210; - u32 cm_wkup_usim_clkctrl; - u32 pad211; - u32 cm_wkup_sarram_clkctrl; - u32 pad212[5]; - u32 cm_wkup_keyboard_clkctrl; - u32 pad213; - u32 cm_wkup_rtc_clkctrl; - u32 pad214; - u32 cm_wkup_bandgap_clkctrl; - u32 pad215[197]; - u32 prm_vc_val_bypass; - u32 prm_vc_cfg_channel; - u32 prm_vc_cfg_i2c_mode; - u32 prm_vc_cfg_i2c_clk; - -}; - -struct omap4_scrm_regs { - u32 revision; /* 0x0000 */ - u32 pad00[63]; - u32 clksetuptime; /* 0x0100 */ - u32 pmicsetuptime; /* 0x0104 */ - u32 pad01[2]; - u32 altclksrc; /* 0x0110 */ - u32 pad02[2]; - u32 c2cclkm; /* 0x011c */ - u32 pad03[56]; - u32 extclkreq; /* 0x0200 */ - u32 accclkreq; /* 0x0204 */ - u32 pwrreq; /* 0x0208 */ - u32 pad04[1]; - u32 auxclkreq0; /* 0x0210 */ - u32 auxclkreq1; /* 0x0214 */ - u32 auxclkreq2; /* 0x0218 */ - u32 auxclkreq3; /* 0x021c */ - u32 auxclkreq4; /* 0x0220 */ - u32 auxclkreq5; /* 0x0224 */ - u32 pad05[3]; - u32 c2cclkreq; /* 0x0234 */ - u32 pad06[54]; - u32 auxclk0; /* 0x0310 */ - u32 auxclk1; /* 0x0314 */ - u32 auxclk2; /* 0x0318 */ - u32 auxclk3; /* 0x031c */ - u32 auxclk4; /* 0x0320 */ - u32 auxclk5; /* 0x0324 */ - u32 pad07[54]; - u32 rsttime_reg; /* 0x0400 */ - u32 pad08[6]; - u32 c2crstctrl; /* 0x041c */ - u32 extpwronrstctrl; /* 0x0420 */ - u32 pad09[59]; - u32 extwarmrstst_reg; /* 0x0510 */ - u32 apewarmrstst_reg; /* 0x0514 */ - u32 pad10[1]; - u32 c2cwarmrstst_reg; /* 0x051C */ -}; - /* DPLL register offsets */ #define CM_CLKMODE_DPLL 0 #define CM_IDLEST_DPLL 0x4 @@ -714,54 +242,44 @@ struct omap4_scrm_regs { #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 -#define NUM_SYS_CLKS 7 - -struct dpll_regs { - u32 cm_clkmode_dpll; - u32 cm_idlest_dpll; - u32 cm_autoidle_dpll; - u32 cm_clksel_dpll; - u32 cm_div_m2_dpll; - u32 cm_div_m3_dpll; - u32 cm_div_m4_dpll; - u32 cm_div_m5_dpll; - u32 cm_div_m6_dpll; - u32 cm_div_m7_dpll; -}; - -/* DPLL parameter table */ -struct dpll_params { - u32 m; - u32 n; - s8 m2; - s8 m3; - s8 m4; - s8 m5; - s8 m6; - s8 m7; +struct omap4_scrm_regs { + u32 revision; /* 0x0000 */ + u32 pad00[63]; + u32 clksetuptime; /* 0x0100 */ + u32 pmicsetuptime; /* 0x0104 */ + u32 pad01[2]; + u32 altclksrc; /* 0x0110 */ + u32 pad02[2]; + u32 c2cclkm; /* 0x011c */ + u32 pad03[56]; + u32 extclkreq; /* 0x0200 */ + u32 accclkreq; /* 0x0204 */ + u32 pwrreq; /* 0x0208 */ + u32 pad04[1]; + u32 auxclkreq0; /* 0x0210 */ + u32 auxclkreq1; /* 0x0214 */ + u32 auxclkreq2; /* 0x0218 */ + u32 auxclkreq3; /* 0x021c */ + u32 auxclkreq4; /* 0x0220 */ + u32 auxclkreq5; /* 0x0224 */ + u32 pad05[3]; + u32 c2cclkreq; /* 0x0234 */ + u32 pad06[54]; + u32 auxclk0; /* 0x0310 */ + u32 auxclk1; /* 0x0314 */ + u32 auxclk2; /* 0x0318 */ + u32 auxclk3; /* 0x031c */ + u32 auxclk4; /* 0x0320 */ + u32 auxclk5; /* 0x0324 */ + u32 pad07[54]; + u32 rsttime_reg; /* 0x0400 */ + u32 pad08[6]; + u32 c2crstctrl; /* 0x041c */ + u32 extpwronrstctrl; /* 0x0420 */ + u32 pad09[59]; + u32 extwarmrstst_reg; /* 0x0510 */ + u32 apewarmrstst_reg; /* 0x0514 */ + u32 pad10[1]; + u32 c2cwarmrstst_reg; /* 0x051C */ }; - -extern struct omap4_prcm_regs *const prcm; -extern const u32 sys_clk_array[8]; - -void scale_vcores(void); -void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv); -u32 get_offset_code(u32 offset); -u32 omap_ddr_clk(void); -void do_scale_vcore(u32 vcore_reg, u32 volt_mv); -void setup_post_dividers(u32 *const base, const struct dpll_params *params); -u32 get_sys_clk_index(void); -void enable_basic_clocks(void); -void enable_basic_uboot_clocks(void); -void enable_non_essential_clocks(void); -void do_enable_clocks(u32 *const *clk_domains, - u32 *const *clk_modules_hw_auto, - u32 *const *clk_modules_explicit_en, - u8 wait_for_enable); -const struct dpll_params *get_mpu_dpll_params(void); -const struct dpll_params *get_core_dpll_params(void); -const struct dpll_params *get_per_dpll_params(void); -const struct dpll_params *get_iva_dpll_params(void); -const struct dpll_params *get_usb_dpll_params(void); -const struct dpll_params *get_abe_dpll_params(void); #endif /* _CLOCKS_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h index 2114046e7..9c8ccb6c8 100644 --- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h @@ -25,6 +25,8 @@ #ifndef MMC_HOST_DEF_H #define MMC_HOST_DEF_H +#include <asm/omap_mmc.h> + /* * OMAP HSMMC register definitions */ @@ -33,142 +35,4 @@ #define OMAP_HSMMC2_BASE 0x480B4100 #define OMAP_HSMMC3_BASE 0x480AD100 -struct hsmmc { - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned int sysstatus; /* 0x14 */ - unsigned char res2[0x14]; - unsigned int con; /* 0x2C */ - unsigned char res3[0xD4]; - unsigned int blk; /* 0x104 */ - unsigned int arg; /* 0x108 */ - unsigned int cmd; /* 0x10C */ - unsigned int rsp10; /* 0x110 */ - unsigned int rsp32; /* 0x114 */ - unsigned int rsp54; /* 0x118 */ - unsigned int rsp76; /* 0x11C */ - unsigned int data; /* 0x120 */ - unsigned int pstate; /* 0x124 */ - unsigned int hctl; /* 0x128 */ - unsigned int sysctl; /* 0x12C */ - unsigned int stat; /* 0x130 */ - unsigned int ie; /* 0x134 */ - unsigned char res4[0x8]; - unsigned int capa; /* 0x140 */ -}; - -/* - * OMAP HS MMC Bit definitions - */ -#define MMC_SOFTRESET (0x1 << 1) -#define RESETDONE (0x1 << 0) -#define NOOPENDRAIN (0x0 << 0) -#define OPENDRAIN (0x1 << 0) -#define OD (0x1 << 0) -#define INIT_NOINIT (0x0 << 1) -#define INIT_INITSTREAM (0x1 << 1) -#define HR_NOHOSTRESP (0x0 << 2) -#define STR_BLOCK (0x0 << 3) -#define MODE_FUNC (0x0 << 4) -#define DW8_1_4BITMODE (0x0 << 5) -#define MIT_CTO (0x0 << 6) -#define CDP_ACTIVEHIGH (0x0 << 7) -#define WPP_ACTIVEHIGH (0x0 << 8) -#define RESERVED_MASK (0x3 << 9) -#define CTPL_MMC_SD (0x0 << 11) -#define BLEN_512BYTESLEN (0x200 << 0) -#define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) -#define BCE_ENABLE (0x1 << 1) -#define ACEN_DISABLE (0x0 << 2) -#define DDIR_OFFSET (4) -#define DDIR_MASK (0x1 << 4) -#define DDIR_WRITE (0x0 << 4) -#define DDIR_READ (0x1 << 4) -#define MSBS_SGLEBLK (0x0 << 5) -#define MSBS_MULTIBLK (0x1 << 5) -#define RSP_TYPE_OFFSET (16) -#define RSP_TYPE_MASK (0x3 << 16) -#define RSP_TYPE_NORSP (0x0 << 16) -#define RSP_TYPE_LGHT136 (0x1 << 16) -#define RSP_TYPE_LGHT48 (0x2 << 16) -#define RSP_TYPE_LGHT48B (0x3 << 16) -#define CCCE_NOCHECK (0x0 << 19) -#define CCCE_CHECK (0x1 << 19) -#define CICE_NOCHECK (0x0 << 20) -#define CICE_CHECK (0x1 << 20) -#define DP_OFFSET (21) -#define DP_MASK (0x1 << 21) -#define DP_NO_DATA (0x0 << 21) -#define DP_DATA (0x1 << 21) -#define CMD_TYPE_NORMAL (0x0 << 22) -#define INDEX_OFFSET (24) -#define INDEX_MASK (0x3f << 24) -#define INDEX(i) (i << 24) -#define DATI_MASK (0x1 << 1) -#define CMDI_MASK (0x1 << 0) -#define DTW_1_BITMODE (0x0 << 1) -#define DTW_4_BITMODE (0x1 << 1) -#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ -#define SDBP_PWROFF (0x0 << 8) -#define SDBP_PWRON (0x1 << 8) -#define SDVS_1V8 (0x5 << 9) -#define SDVS_3V0 (0x6 << 9) -#define ICE_MASK (0x1 << 0) -#define ICE_STOP (0x0 << 0) -#define ICS_MASK (0x1 << 1) -#define ICS_NOTREADY (0x0 << 1) -#define ICE_OSCILLATE (0x1 << 0) -#define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) -#define CEN_ENABLE (0x1 << 2) -#define CLKD_OFFSET (6) -#define CLKD_MASK (0x3FF << 6) -#define DTO_MASK (0xF << 16) -#define DTO_15THDTO (0xE << 16) -#define SOFTRESETALL (0x1 << 24) -#define CC_MASK (0x1 << 0) -#define TC_MASK (0x1 << 1) -#define BWR_MASK (0x1 << 4) -#define BRR_MASK (0x1 << 5) -#define ERRI_MASK (0x1 << 15) -#define IE_CC (0x01 << 0) -#define IE_TC (0x01 << 1) -#define IE_BWR (0x01 << 4) -#define IE_BRR (0x01 << 5) -#define IE_CTO (0x01 << 16) -#define IE_CCRC (0x01 << 17) -#define IE_CEB (0x01 << 18) -#define IE_CIE (0x01 << 19) -#define IE_DTO (0x01 << 20) -#define IE_DCRC (0x01 << 21) -#define IE_DEB (0x01 << 22) -#define IE_CERR (0x01 << 28) -#define IE_BADA (0x01 << 29) - -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE 512 -#define MMC_CARD 0 -#define SD_CARD 1 -#define BYTE_MODE 0 -#define SECTOR_MODE 1 -#define CLK_INITSEQ 0 -#define CLK_400KHZ 1 -#define CLK_MISC 2 - -#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) -#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) - -/* Clock Configurations and Macros */ -#define MMC_CLOCK_REFERENCE 96 /* MHz */ - -#define mmc_reg_out(addr, mask, val)\ - writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) - -int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max); - #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index d4b507610..5f321fe6f 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -132,34 +132,6 @@ struct s32ktimer { #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) #define DEVICE_GP 0x3 -struct omap_sys_ctrl_regs { - unsigned int pad1[129]; - unsigned int control_id_code; /* 0x4A002204 */ - unsigned int pad11[22]; - unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */ - unsigned int pad2[24]; /* 0x4a002264 */ - unsigned int control_status; /* 0x4a0022c4 */ - unsigned int pad3[22]; /* 0x4a0022c8 */ - unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */ - unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */ - unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */ - unsigned int pad4[260277]; - unsigned int control_pbiaslite; /* 0x4A100600 */ - unsigned int pad5[63]; - unsigned int control_efuse_1; /* 0x4A100700 */ - unsigned int control_efuse_2; /* 0x4A100704 */ -}; - -struct control_lpddr2io_regs { - unsigned int control_lpddr2io1_0; - unsigned int control_lpddr2io1_1; - unsigned int control_lpddr2io1_2; - unsigned int control_lpddr2io1_3; - unsigned int control_lpddr2io2_0; - unsigned int control_lpddr2io2_1; - unsigned int control_lpddr2io2_2; - unsigned int control_lpddr2io2_3; -}; #endif /* __ASSEMBLY__ */ /* @@ -178,7 +150,11 @@ struct control_lpddr2io_regs { #define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) #define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) -#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14) +#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) +#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) +#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) +#define OMAP4_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) +#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24) /* ROM code defines */ /* Boot device */ diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h index cec84dc54..4e094f9c6 100644 --- a/arch/arm/include/asm/arch-omap4/spl.h +++ b/arch/arm/include/asm/arch-omap4/spl.h @@ -27,7 +27,7 @@ #define BOOT_DEVICE_XIP 1 #define BOOT_DEVICE_XIPWAIT 2 #define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONE_NAND 4 +#define BOOT_DEVICE_ONENAND 4 #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 0xFF diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index b48f81dc3..d5f1868ee 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -44,7 +44,7 @@ void sdelay(unsigned long); void set_pl310_ctrl_reg(u32 val); void setup_clocks_for_console(void); void prcm_init(void); -void bypass_dpll(u32 *const base); +void bypass_dpll(u32 const base); void freq_update_core(void); u32 get_sys_clk_freq(void); u32 omap4_ddr_clk(void); diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 5f1a7aa77..cfde37433 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -26,6 +26,7 @@ #ifndef _CLOCKS_OMAP5_H_ #define _CLOCKS_OMAP5_H_ #include <common.h> +#include <asm/omap_common.h> /* * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per @@ -39,456 +40,6 @@ #define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160) #define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100) -struct omap5_prcm_regs { - /* cm1.ckgen */ - u32 cm_clksel_core; /* 4a004100 */ - u32 pad001[1]; /* 4a004104 */ - u32 cm_clksel_abe; /* 4a004108 */ - u32 pad002[1]; /* 4a00410c */ - u32 cm_dll_ctrl; /* 4a004110 */ - u32 pad003[3]; /* 4a004114 */ - u32 cm_clkmode_dpll_core; /* 4a004120 */ - u32 cm_idlest_dpll_core; /* 4a004124 */ - u32 cm_autoidle_dpll_core; /* 4a004128 */ - u32 cm_clksel_dpll_core; /* 4a00412c */ - u32 cm_div_m2_dpll_core; /* 4a004130 */ - u32 cm_div_m3_dpll_core; /* 4a004134 */ - u32 cm_div_h11_dpll_core; /* 4a004138 */ - u32 cm_div_h12_dpll_core; /* 4a00413c */ - u32 cm_div_h13_dpll_core; /* 4a004140 */ - u32 cm_div_h14_dpll_core; /* 4a004144 */ - u32 cm_ssc_deltamstep_dpll_core; /* 4a004148 */ - u32 cm_ssc_modfreqdiv_dpll_core; /* 4a00414c */ - u32 cm_emu_override_dpll_core; /* 4a004150 */ - - u32 cm_div_h22_dpllcore; /* 4a004154 */ - u32 cm_div_h23_dpll_core; /* 4a004158 */ - u32 pad0041[1]; /* 4a00415c */ - u32 cm_clkmode_dpll_mpu; /* 4a004160 */ - u32 cm_idlest_dpll_mpu; /* 4a004164 */ - u32 cm_autoidle_dpll_mpu; /* 4a004168 */ - u32 cm_clksel_dpll_mpu; /* 4a00416c */ - u32 cm_div_m2_dpll_mpu; /* 4a004170 */ - u32 pad005[5]; /* 4a004174 */ - u32 cm_ssc_deltamstep_dpll_mpu; /* 4a004188 */ - u32 cm_ssc_modfreqdiv_dpll_mpu; /* 4a00418c */ - u32 pad006[3]; /* 4a004190 */ - u32 cm_bypclk_dpll_mpu; /* 4a00419c */ - u32 cm_clkmode_dpll_iva; /* 4a0041a0 */ - u32 cm_idlest_dpll_iva; /* 4a0041a4 */ - u32 cm_autoidle_dpll_iva; /* 4a0041a8 */ - u32 cm_clksel_dpll_iva; /* 4a0041ac */ - u32 pad007[2]; /* 4a0041b0 */ - u32 cm_div_h11_dpll_iva; /* 4a0041b8 */ - u32 cm_div_h12_dpll_iva; /* 4a0041bc */ - u32 pad008[2]; /* 4a0041c0 */ - u32 cm_ssc_deltamstep_dpll_iva; /* 4a0041c8 */ - u32 cm_ssc_modfreqdiv_dpll_iva; /* 4a0041cc */ - u32 pad009[3]; /* 4a0041d0 */ - u32 cm_bypclk_dpll_iva; /* 4a0041dc */ - u32 cm_clkmode_dpll_abe; /* 4a0041e0 */ - u32 cm_idlest_dpll_abe; /* 4a0041e4 */ - u32 cm_autoidle_dpll_abe; /* 4a0041e8 */ - u32 cm_clksel_dpll_abe; /* 4a0041ec */ - u32 cm_div_m2_dpll_abe; /* 4a0041f0 */ - u32 cm_div_m3_dpll_abe; /* 4a0041f4 */ - u32 pad010[4]; /* 4a0041f8 */ - u32 cm_ssc_deltamstep_dpll_abe; /* 4a004208 */ - u32 cm_ssc_modfreqdiv_dpll_abe; /* 4a00420c */ - u32 pad011[4]; /* 4a004210 */ - u32 cm_clkmode_dpll_ddrphy; /* 4a004220 */ - u32 cm_idlest_dpll_ddrphy; /* 4a004224 */ - u32 cm_autoidle_dpll_ddrphy; /* 4a004228 */ - u32 cm_clksel_dpll_ddrphy; /* 4a00422c */ - u32 cm_div_m2_dpll_ddrphy; /* 4a004230 */ - u32 pad012[1]; /* 4a004234 */ - u32 cm_div_h11_dpll_ddrphy; /* 4a004238 */ - u32 cm_div_h12_dpll_ddrphy; /* 4a00423c */ - u32 cm_div_h13_dpll_ddrphy; /* 4a004240 */ - u32 pad013[1]; /* 4a004244 */ - u32 cm_ssc_deltamstep_dpll_ddrphy; /* 4a004248 */ - u32 pad014[5]; /* 4a00424c */ - u32 cm_shadow_freq_config1; /* 4a004260 */ - u32 pad0141[47]; /* 4a004264 */ - u32 cm_mpu_mpu_clkctrl; /* 4a004320 */ - - - /* cm1.dsp */ - u32 pad015[55]; /* 4a004324 */ - u32 cm_dsp_clkstctrl; /* 4a004400 */ - u32 pad016[7]; /* 4a004404 */ - u32 cm_dsp_dsp_clkctrl; /* 4a004420 */ - - /* cm1.abe */ - u32 pad017[55]; /* 4a004424 */ - u32 cm1_abe_clkstctrl; /* 4a004500 */ - u32 pad018[7]; /* 4a004504 */ - u32 cm1_abe_l4abe_clkctrl; /* 4a004520 */ - u32 pad019[1]; /* 4a004524 */ - u32 cm1_abe_aess_clkctrl; /* 4a004528 */ - u32 pad020[1]; /* 4a00452c */ - u32 cm1_abe_pdm_clkctrl; /* 4a004530 */ - u32 pad021[1]; /* 4a004534 */ - u32 cm1_abe_dmic_clkctrl; /* 4a004538 */ - u32 pad022[1]; /* 4a00453c */ - u32 cm1_abe_mcasp_clkctrl; /* 4a004540 */ - u32 pad023[1]; /* 4a004544 */ - u32 cm1_abe_mcbsp1_clkctrl; /* 4a004548 */ - u32 pad024[1]; /* 4a00454c */ - u32 cm1_abe_mcbsp2_clkctrl; /* 4a004550 */ - u32 pad025[1]; /* 4a004554 */ - u32 cm1_abe_mcbsp3_clkctrl; /* 4a004558 */ - u32 pad026[1]; /* 4a00455c */ - u32 cm1_abe_slimbus_clkctrl; /* 4a004560 */ - u32 pad027[1]; /* 4a004564 */ - u32 cm1_abe_timer5_clkctrl; /* 4a004568 */ - u32 pad028[1]; /* 4a00456c */ - u32 cm1_abe_timer6_clkctrl; /* 4a004570 */ - u32 pad029[1]; /* 4a004574 */ - u32 cm1_abe_timer7_clkctrl; /* 4a004578 */ - u32 pad030[1]; /* 4a00457c */ - u32 cm1_abe_timer8_clkctrl; /* 4a004580 */ - u32 pad031[1]; /* 4a004584 */ - u32 cm1_abe_wdt3_clkctrl; /* 4a004588 */ - - /* cm2.ckgen */ - u32 pad032[3805]; /* 4a00458c */ - u32 cm_clksel_mpu_m3_iss_root; /* 4a008100 */ - u32 cm_clksel_usb_60mhz; /* 4a008104 */ - u32 cm_scale_fclk; /* 4a008108 */ - u32 pad033[1]; /* 4a00810c */ - u32 cm_core_dvfs_perf1; /* 4a008110 */ - u32 cm_core_dvfs_perf2; /* 4a008114 */ - u32 cm_core_dvfs_perf3; /* 4a008118 */ - u32 cm_core_dvfs_perf4; /* 4a00811c */ - u32 pad034[1]; /* 4a008120 */ - u32 cm_core_dvfs_current; /* 4a008124 */ - u32 cm_iva_dvfs_perf_tesla; /* 4a008128 */ - u32 cm_iva_dvfs_perf_ivahd; /* 4a00812c */ - u32 cm_iva_dvfs_perf_abe; /* 4a008130 */ - u32 pad035[1]; /* 4a008134 */ - u32 cm_iva_dvfs_current; /* 4a008138 */ - u32 pad036[1]; /* 4a00813c */ - u32 cm_clkmode_dpll_per; /* 4a008140 */ - u32 cm_idlest_dpll_per; /* 4a008144 */ - u32 cm_autoidle_dpll_per; /* 4a008148 */ - u32 cm_clksel_dpll_per; /* 4a00814c */ - u32 cm_div_m2_dpll_per; /* 4a008150 */ - u32 cm_div_m3_dpll_per; /* 4a008154 */ - u32 cm_div_h11_dpll_per; /* 4a008158 */ - u32 cm_div_h12_dpll_per; /* 4a00815c */ - u32 pad0361[1]; /* 4a008160 */ - u32 cm_div_h14_dpll_per; /* 4a008164 */ - u32 cm_ssc_deltamstep_dpll_per; /* 4a008168 */ - u32 cm_ssc_modfreqdiv_dpll_per; /* 4a00816c */ - u32 cm_emu_override_dpll_per; /* 4a008170 */ - u32 pad037[3]; /* 4a008174 */ - u32 cm_clkmode_dpll_usb; /* 4a008180 */ - u32 cm_idlest_dpll_usb; /* 4a008184 */ - u32 cm_autoidle_dpll_usb; /* 4a008188 */ - u32 cm_clksel_dpll_usb; /* 4a00818c */ - u32 cm_div_m2_dpll_usb; /* 4a008190 */ - u32 pad038[5]; /* 4a008194 */ - u32 cm_ssc_deltamstep_dpll_usb; /* 4a0081a8 */ - u32 cm_ssc_modfreqdiv_dpll_usb; /* 4a0081ac */ - u32 pad039[1]; /* 4a0081b0 */ - u32 cm_clkdcoldo_dpll_usb; /* 4a0081b4 */ - u32 pad040[2]; /* 4a0081b8 */ - u32 cm_clkmode_dpll_unipro; /* 4a0081c0 */ - u32 cm_idlest_dpll_unipro; /* 4a0081c4 */ - u32 cm_autoidle_dpll_unipro; /* 4a0081c8 */ - u32 cm_clksel_dpll_unipro; /* 4a0081cc */ - u32 cm_div_m2_dpll_unipro; /* 4a0081d0 */ - u32 pad041[5]; /* 4a0081d4 */ - u32 cm_ssc_deltamstep_dpll_unipro; /* 4a0081e8 */ - u32 cm_ssc_modfreqdiv_dpll_unipro; /* 4a0081ec */ - - /* cm2.core */ - u32 pad0411[324]; /* 4a0081f0 */ - u32 cm_l3_1_clkstctrl; /* 4a008700 */ - u32 pad042[1]; /* 4a008704 */ - u32 cm_l3_1_dynamicdep; /* 4a008708 */ - u32 pad043[5]; /* 4a00870c */ - u32 cm_l3_1_l3_1_clkctrl; /* 4a008720 */ - u32 pad044[55]; /* 4a008724 */ - u32 cm_l3_2_clkstctrl; /* 4a008800 */ - u32 pad045[1]; /* 4a008804 */ - u32 cm_l3_2_dynamicdep; /* 4a008808 */ - u32 pad046[5]; /* 4a00880c */ - u32 cm_l3_2_l3_2_clkctrl; /* 4a008820 */ - u32 pad047[1]; /* 4a008824 */ - u32 cm_l3_2_gpmc_clkctrl; /* 4a008828 */ - u32 pad048[1]; /* 4a00882c */ - u32 cm_l3_2_ocmc_ram_clkctrl; /* 4a008830 */ - u32 pad049[51]; /* 4a008834 */ - u32 cm_mpu_m3_clkstctrl; /* 4a008900 */ - u32 cm_mpu_m3_staticdep; /* 4a008904 */ - u32 cm_mpu_m3_dynamicdep; /* 4a008908 */ - u32 pad050[5]; /* 4a00890c */ - u32 cm_mpu_m3_mpu_m3_clkctrl; /* 4a008920 */ - u32 pad051[55]; /* 4a008924 */ - u32 cm_sdma_clkstctrl; /* 4a008a00 */ - u32 cm_sdma_staticdep; /* 4a008a04 */ - u32 cm_sdma_dynamicdep; /* 4a008a08 */ - u32 pad052[5]; /* 4a008a0c */ - u32 cm_sdma_sdma_clkctrl; /* 4a008a20 */ - u32 pad053[55]; /* 4a008a24 */ - u32 cm_memif_clkstctrl; /* 4a008b00 */ - u32 pad054[7]; /* 4a008b04 */ - u32 cm_memif_dmm_clkctrl; /* 4a008b20 */ - u32 pad055[1]; /* 4a008b24 */ - u32 cm_memif_emif_fw_clkctrl; /* 4a008b28 */ - u32 pad056[1]; /* 4a008b2c */ - u32 cm_memif_emif_1_clkctrl; /* 4a008b30 */ - u32 pad057[1]; /* 4a008b34 */ - u32 cm_memif_emif_2_clkctrl; /* 4a008b38 */ - u32 pad058[1]; /* 4a008b3c */ - u32 cm_memif_dll_clkctrl; /* 4a008b40 */ - u32 pad059[3]; /* 4a008b44 */ - u32 cm_memif_emif_h1_clkctrl; /* 4a008b50 */ - u32 pad060[1]; /* 4a008b54 */ - u32 cm_memif_emif_h2_clkctrl; /* 4a008b58 */ - u32 pad061[1]; /* 4a008b5c */ - u32 cm_memif_dll_h_clkctrl; /* 4a008b60 */ - u32 pad062[39]; /* 4a008b64 */ - u32 cm_c2c_clkstctrl; /* 4a008c00 */ - u32 cm_c2c_staticdep; /* 4a008c04 */ - u32 cm_c2c_dynamicdep; /* 4a008c08 */ - u32 pad063[5]; /* 4a008c0c */ - u32 cm_c2c_sad2d_clkctrl; /* 4a008c20 */ - u32 pad064[1]; /* 4a008c24 */ - u32 cm_c2c_modem_icr_clkctrl; /* 4a008c28 */ - u32 pad065[1]; /* 4a008c2c */ - u32 cm_c2c_sad2d_fw_clkctrl; /* 4a008c30 */ - u32 pad066[51]; /* 4a008c34 */ - u32 cm_l4cfg_clkstctrl; /* 4a008d00 */ - u32 pad067[1]; /* 4a008d04 */ - u32 cm_l4cfg_dynamicdep; /* 4a008d08 */ - u32 pad068[5]; /* 4a008d0c */ - u32 cm_l4cfg_l4_cfg_clkctrl; /* 4a008d20 */ - u32 pad069[1]; /* 4a008d24 */ - u32 cm_l4cfg_hw_sem_clkctrl; /* 4a008d28 */ - u32 pad070[1]; /* 4a008d2c */ - u32 cm_l4cfg_mailbox_clkctrl; /* 4a008d30 */ - u32 pad071[1]; /* 4a008d34 */ - u32 cm_l4cfg_sar_rom_clkctrl; /* 4a008d38 */ - u32 pad072[49]; /* 4a008d3c */ - u32 cm_l3instr_clkstctrl; /* 4a008e00 */ - u32 pad073[7]; /* 4a008e04 */ - u32 cm_l3instr_l3_3_clkctrl; /* 4a008e20 */ - u32 pad074[1]; /* 4a008e24 */ - u32 cm_l3instr_l3_instr_clkctrl; /* 4a008e28 */ - u32 pad075[5]; /* 4a008e2c */ - u32 cm_l3instr_intrconn_wp1_clkctrl; /* 4a008e40 */ - - - /* cm2.ivahd */ - u32 pad076[47]; /* 4a008e44 */ - u32 cm_ivahd_clkstctrl; /* 4a008f00 */ - u32 pad077[7]; /* 4a008f04 */ - u32 cm_ivahd_ivahd_clkctrl; /* 4a008f20 */ - u32 pad078[1]; /* 4a008f24 */ - u32 cm_ivahd_sl2_clkctrl; /* 4a008f28 */ - - /* cm2.cam */ - u32 pad079[53]; /* 4a008f2c */ - u32 cm_cam_clkstctrl; /* 4a009000 */ - u32 pad080[7]; /* 4a009004 */ - u32 cm_cam_iss_clkctrl; /* 4a009020 */ - u32 pad081[1]; /* 4a009024 */ - u32 cm_cam_fdif_clkctrl; /* 4a009028 */ - - /* cm2.dss */ - u32 pad082[53]; /* 4a00902c */ - u32 cm_dss_clkstctrl; /* 4a009100 */ - u32 pad083[7]; /* 4a009104 */ - u32 cm_dss_dss_clkctrl; /* 4a009120 */ - - /* cm2.sgx */ - u32 pad084[55]; /* 4a009124 */ - u32 cm_sgx_clkstctrl; /* 4a009200 */ - u32 pad085[7]; /* 4a009204 */ - u32 cm_sgx_sgx_clkctrl; /* 4a009220 */ - - /* cm2.l3init */ - u32 pad086[55]; /* 4a009224 */ - u32 cm_l3init_clkstctrl; /* 4a009300 */ - - /* cm2.l3init */ - u32 pad087[9]; /* 4a009304 */ - u32 cm_l3init_hsmmc1_clkctrl; /* 4a009328 */ - u32 pad088[1]; /* 4a00932c */ - u32 cm_l3init_hsmmc2_clkctrl; /* 4a009330 */ - u32 pad089[1]; /* 4a009334 */ - u32 cm_l3init_hsi_clkctrl; /* 4a009338 */ - u32 pad090[7]; /* 4a00933c */ - u32 cm_l3init_hsusbhost_clkctrl; /* 4a009358 */ - u32 pad091[1]; /* 4a00935c */ - u32 cm_l3init_hsusbotg_clkctrl; /* 4a009360 */ - u32 pad092[1]; /* 4a009364 */ - u32 cm_l3init_hsusbtll_clkctrl; /* 4a009368 */ - u32 pad093[3]; /* 4a00936c */ - u32 cm_l3init_p1500_clkctrl; /* 4a009378 */ - u32 pad094[21]; /* 4a00937c */ - u32 cm_l3init_fsusb_clkctrl; /* 4a0093d0 */ - u32 pad095[3]; /* 4a0093d4 */ - u32 cm_l3init_ocp2scp1_clkctrl; - - /* cm2.l4per */ - u32 pad096[7]; /* 4a0093e4 */ - u32 cm_l4per_clkstctrl; /* 4a009400 */ - u32 pad097[1]; /* 4a009404 */ - u32 cm_l4per_dynamicdep; /* 4a009408 */ - u32 pad098[5]; /* 4a00940c */ - u32 cm_l4per_adc_clkctrl; /* 4a009420 */ - u32 pad100[1]; /* 4a009424 */ - u32 cm_l4per_gptimer10_clkctrl; /* 4a009428 */ - u32 pad101[1]; /* 4a00942c */ - u32 cm_l4per_gptimer11_clkctrl; /* 4a009430 */ - u32 pad102[1]; /* 4a009434 */ - u32 cm_l4per_gptimer2_clkctrl; /* 4a009438 */ - u32 pad103[1]; /* 4a00943c */ - u32 cm_l4per_gptimer3_clkctrl; /* 4a009440 */ - u32 pad104[1]; /* 4a009444 */ - u32 cm_l4per_gptimer4_clkctrl; /* 4a009448 */ - u32 pad105[1]; /* 4a00944c */ - u32 cm_l4per_gptimer9_clkctrl; /* 4a009450 */ - u32 pad106[1]; /* 4a009454 */ - u32 cm_l4per_elm_clkctrl; /* 4a009458 */ - u32 pad107[1]; /* 4a00945c */ - u32 cm_l4per_gpio2_clkctrl; /* 4a009460 */ - u32 pad108[1]; /* 4a009464 */ - u32 cm_l4per_gpio3_clkctrl; /* 4a009468 */ - u32 pad109[1]; /* 4a00946c */ - u32 cm_l4per_gpio4_clkctrl; /* 4a009470 */ - u32 pad110[1]; /* 4a009474 */ - u32 cm_l4per_gpio5_clkctrl; /* 4a009478 */ - u32 pad111[1]; /* 4a00947c */ - u32 cm_l4per_gpio6_clkctrl; /* 4a009480 */ - u32 pad112[1]; /* 4a009484 */ - u32 cm_l4per_hdq1w_clkctrl; /* 4a009488 */ - u32 pad113[1]; /* 4a00948c */ - u32 cm_l4per_hecc1_clkctrl; /* 4a009490 */ - u32 pad114[1]; /* 4a009494 */ - u32 cm_l4per_hecc2_clkctrl; /* 4a009498 */ - u32 pad115[1]; /* 4a00949c */ - u32 cm_l4per_i2c1_clkctrl; /* 4a0094a0 */ - u32 pad116[1]; /* 4a0094a4 */ - u32 cm_l4per_i2c2_clkctrl; /* 4a0094a8 */ - u32 pad117[1]; /* 4a0094ac */ - u32 cm_l4per_i2c3_clkctrl; /* 4a0094b0 */ - u32 pad118[1]; /* 4a0094b4 */ - u32 cm_l4per_i2c4_clkctrl; /* 4a0094b8 */ - u32 pad119[1]; /* 4a0094bc */ - u32 cm_l4per_l4per_clkctrl; /* 4a0094c0 */ - u32 pad1191[3]; /* 4a0094c4 */ - u32 cm_l4per_mcasp2_clkctrl; /* 4a0094d0 */ - u32 pad120[1]; /* 4a0094d4 */ - u32 cm_l4per_mcasp3_clkctrl; /* 4a0094d8 */ - u32 pad121[3]; /* 4a0094dc */ - u32 cm_l4per_mgate_clkctrl; /* 4a0094e8 */ - u32 pad123[1]; /* 4a0094ec */ - u32 cm_l4per_mcspi1_clkctrl; /* 4a0094f0 */ - u32 pad124[1]; /* 4a0094f4 */ - u32 cm_l4per_mcspi2_clkctrl; /* 4a0094f8 */ - u32 pad125[1]; /* 4a0094fc */ - u32 cm_l4per_mcspi3_clkctrl; /* 4a009500 */ - u32 pad126[1]; /* 4a009504 */ - u32 cm_l4per_mcspi4_clkctrl; /* 4a009508 */ - u32 pad127[1]; /* 4a00950c */ - u32 cm_l4per_gpio7_clkctrl; /* 4a009510 */ - u32 pad1271[1]; /* 4a009514 */ - u32 cm_l4per_gpio8_clkctrl; /* 4a009518 */ - u32 pad1272[1]; /* 4a00951c */ - u32 cm_l4per_mmcsd3_clkctrl; /* 4a009520 */ - u32 pad128[1]; /* 4a009524 */ - u32 cm_l4per_mmcsd4_clkctrl; /* 4a009528 */ - u32 pad129[1]; /* 4a00952c */ - u32 cm_l4per_msprohg_clkctrl; /* 4a009530 */ - u32 pad130[1]; /* 4a009534 */ - u32 cm_l4per_slimbus2_clkctrl; /* 4a009538 */ - u32 pad131[1]; /* 4a00953c */ - u32 cm_l4per_uart1_clkctrl; /* 4a009540 */ - u32 pad132[1]; /* 4a009544 */ - u32 cm_l4per_uart2_clkctrl; /* 4a009548 */ - u32 pad133[1]; /* 4a00954c */ - u32 cm_l4per_uart3_clkctrl; /* 4a009550 */ - u32 pad134[1]; /* 4a009554 */ - u32 cm_l4per_uart4_clkctrl; /* 4a009558 */ - u32 pad135[1]; /* 4a00955c */ - u32 cm_l4per_mmcsd5_clkctrl; /* 4a009560 */ - u32 pad136[1]; /* 4a009564 */ - u32 cm_l4per_i2c5_clkctrl; /* 4a009568 */ - u32 pad1371[1]; /* 4a00956c */ - u32 cm_l4per_uart5_clkctrl; /* 4a009570 */ - u32 pad1372[1]; /* 4a009574 */ - u32 cm_l4per_uart6_clkctrl; /* 4a009578 */ - u32 pad1374[1]; /* 4a00957c */ - u32 cm_l4sec_clkstctrl; /* 4a009580 */ - u32 cm_l4sec_staticdep; /* 4a009584 */ - u32 cm_l4sec_dynamicdep; /* 4a009588 */ - u32 pad138[5]; /* 4a00958c */ - u32 cm_l4sec_aes1_clkctrl; /* 4a0095a0 */ - u32 pad139[1]; /* 4a0095a4 */ - u32 cm_l4sec_aes2_clkctrl; /* 4a0095a8 */ - u32 pad140[1]; /* 4a0095ac */ - u32 cm_l4sec_des3des_clkctrl; /* 4a0095b0 */ - u32 pad141[1]; /* 4a0095b4 */ - u32 cm_l4sec_pkaeip29_clkctrl; /* 4a0095b8 */ - u32 pad142[1]; /* 4a0095bc */ - u32 cm_l4sec_rng_clkctrl; /* 4a0095c0 */ - u32 pad143[1]; /* 4a0095c4 */ - u32 cm_l4sec_sha2md51_clkctrl; /* 4a0095c8 */ - u32 pad144[3]; /* 4a0095cc */ - u32 cm_l4sec_cryptodma_clkctrl; /* 4a0095d8 */ - u32 pad145[3660425]; /* 4a0095dc */ - - /* l4 wkup regs */ - u32 pad201[6211]; /* 4ae00000 */ - u32 cm_abe_pll_ref_clksel; /* 4ae0610c */ - u32 cm_sys_clksel; /* 4ae06110 */ - u32 pad202[1467]; /* 4ae06114 */ - u32 cm_wkup_clkstctrl; /* 4ae07800 */ - u32 pad203[7]; /* 4ae07804 */ - u32 cm_wkup_l4wkup_clkctrl; /* 4ae07820 */ - u32 pad204; /* 4ae07824 */ - u32 cm_wkup_wdtimer1_clkctrl; /* 4ae07828 */ - u32 pad205; /* 4ae0782c */ - u32 cm_wkup_wdtimer2_clkctrl; /* 4ae07830 */ - u32 pad206; /* 4ae07834 */ - u32 cm_wkup_gpio1_clkctrl; /* 4ae07838 */ - u32 pad207; /* 4ae0783c */ - u32 cm_wkup_gptimer1_clkctrl; /* 4ae07840 */ - u32 pad208; /* 4ae07844 */ - u32 cm_wkup_gptimer12_clkctrl; /* 4ae07848 */ - u32 pad209; /* 4ae0784c */ - u32 cm_wkup_synctimer_clkctrl; /* 4ae07850 */ - u32 pad210; /* 4ae07854 */ - u32 cm_wkup_usim_clkctrl; /* 4ae07858 */ - u32 pad211; /* 4ae0785c */ - u32 cm_wkup_sarram_clkctrl; /* 4ae07860 */ - u32 pad212[5]; /* 4ae07864 */ - u32 cm_wkup_keyboard_clkctrl; /* 4ae07878 */ - u32 pad213; /* 4ae0787c */ - u32 cm_wkup_rtc_clkctrl; /* 4ae07880 */ - u32 pad214; /* 4ae07884 */ - u32 cm_wkup_bandgap_clkctrl; /* 4ae07888 */ - u32 pad215[1]; /* 4ae0788c */ - u32 cm_wkupaon_scrm_clkctrl; /* 4ae07890 */ - u32 pad216[195]; - u32 prm_vc_val_bypass; /* 4ae07ba0 */ - u32 pad217[4]; - u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */ - u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */ - u32 pad218[2]; - u32 prm_sldo_core_setup; /* 4ae07bc4 */ - u32 prm_sldo_core_ctrl; /* 4ae07bc8 */ - u32 prm_sldo_mpu_setup; /* 4ae07bcc */ - u32 prm_sldo_mpu_ctrl; /* 4ae07bd0 */ - u32 prm_sldo_mm_setup; /* 4ae07bd4 */ - u32 prm_sldo_mm_ctrl; /* 4ae07bd8 */ -}; - /* DPLL register offsets */ #define CM_CLKMODE_DPLL 0 #define CM_IDLEST_DPLL 0x4 @@ -625,9 +176,9 @@ struct omap5_prcm_regs { /* CM_MPU_MPU_CLKCTRL */ #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 -#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 -#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24) +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26 +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) /* CM_WKUPAON_SCRM_CLKCTRL */ #define OPTFCLKEN_SCRM_PER_SHIFT 9 @@ -635,6 +186,10 @@ struct omap5_prcm_regs { #define OPTFCLKEN_SCRM_CORE_SHIFT 8 #define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) +/* CM_COREAON_IO_SRCOMP_CLKCTRL */ +#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 +#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) + /* Clock frequencies */ #define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 @@ -650,12 +205,25 @@ struct omap5_prcm_regs { #define SMPS_REG_ADDR_8_CORE 0x37 /* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */ -#define VDD_MPU 1000 -#define VDD_MM 1000 +/* ES1.0 settings */ +#define VDD_MPU 1040 +#define VDD_MM 1040 #define VDD_CORE 1040 -#define VDD_MPU_5432 1150 -#define VDD_MM_5432 1150 -#define VDD_CORE_5432 1150 + +#define VDD_MPU_LOW 890 +#define VDD_MM_LOW 890 +#define VDD_CORE_LOW 890 + +/* ES2.0 settings */ +#define VDD_MPU_ES2 1060 +#define VDD_MM_ES2 1025 +#define VDD_CORE_ES2 1040 + +#define VDD_MPU_ES2_HIGH 1250 +#define VDD_MM_ES2_OD 1120 + +#define VDD_MPU_ES2_LOW 880 +#define VDD_MM_ES2_LOW 880 /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000 @@ -683,59 +251,4 @@ struct omap5_prcm_regs { #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 -#define NUM_SYS_CLKS 7 - -struct dpll_regs { - u32 cm_clkmode_dpll; - u32 cm_idlest_dpll; - u32 cm_autoidle_dpll; - u32 cm_clksel_dpll; - u32 cm_div_m2_dpll; - u32 cm_div_m3_dpll; - u32 cm_div_h11_dpll; - u32 cm_div_h12_dpll; - u32 cm_div_h13_dpll; - u32 cm_div_h14_dpll; - u32 reserved[3]; - u32 cm_div_h22_dpll; - u32 cm_div_h23_dpll; -}; - -/* DPLL parameter table */ -struct dpll_params { - u32 m; - u32 n; - s8 m2; - s8 m3; - s8 h11; - s8 h12; - s8 h13; - s8 h14; - s8 h22; - s8 h23; -}; - -extern struct omap5_prcm_regs *const prcm; -extern const u32 sys_clk_array[8]; - -void scale_vcores(void); -void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv); -u32 get_offset_code(u32 offset); -u32 omap_ddr_clk(void); -void do_scale_vcore(u32 vcore_reg, u32 volt_mv); -void setup_post_dividers(u32 *const base, const struct dpll_params *params); -u32 get_sys_clk_index(void); -void enable_basic_clocks(void); -void enable_non_essential_clocks(void); -void enable_basic_uboot_clocks(void); -void do_enable_clocks(u32 *const *clk_domains, - u32 *const *clk_modules_hw_auto, - u32 *const *clk_modules_explicit_en, - u8 wait_for_enable); -const struct dpll_params *get_mpu_dpll_params(void); -const struct dpll_params *get_core_dpll_params(void); -const struct dpll_params *get_per_dpll_params(void); -const struct dpll_params *get_iva_dpll_params(void); -const struct dpll_params *get_usb_dpll_params(void); -const struct dpll_params *get_abe_dpll_params(void); #endif /* _CLOCKS_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h index 2114046e7..9c8ccb6c8 100644 --- a/arch/arm/include/asm/arch-omap5/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h @@ -25,6 +25,8 @@ #ifndef MMC_HOST_DEF_H #define MMC_HOST_DEF_H +#include <asm/omap_mmc.h> + /* * OMAP HSMMC register definitions */ @@ -33,142 +35,4 @@ #define OMAP_HSMMC2_BASE 0x480B4100 #define OMAP_HSMMC3_BASE 0x480AD100 -struct hsmmc { - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned int sysstatus; /* 0x14 */ - unsigned char res2[0x14]; - unsigned int con; /* 0x2C */ - unsigned char res3[0xD4]; - unsigned int blk; /* 0x104 */ - unsigned int arg; /* 0x108 */ - unsigned int cmd; /* 0x10C */ - unsigned int rsp10; /* 0x110 */ - unsigned int rsp32; /* 0x114 */ - unsigned int rsp54; /* 0x118 */ - unsigned int rsp76; /* 0x11C */ - unsigned int data; /* 0x120 */ - unsigned int pstate; /* 0x124 */ - unsigned int hctl; /* 0x128 */ - unsigned int sysctl; /* 0x12C */ - unsigned int stat; /* 0x130 */ - unsigned int ie; /* 0x134 */ - unsigned char res4[0x8]; - unsigned int capa; /* 0x140 */ -}; - -/* - * OMAP HS MMC Bit definitions - */ -#define MMC_SOFTRESET (0x1 << 1) -#define RESETDONE (0x1 << 0) -#define NOOPENDRAIN (0x0 << 0) -#define OPENDRAIN (0x1 << 0) -#define OD (0x1 << 0) -#define INIT_NOINIT (0x0 << 1) -#define INIT_INITSTREAM (0x1 << 1) -#define HR_NOHOSTRESP (0x0 << 2) -#define STR_BLOCK (0x0 << 3) -#define MODE_FUNC (0x0 << 4) -#define DW8_1_4BITMODE (0x0 << 5) -#define MIT_CTO (0x0 << 6) -#define CDP_ACTIVEHIGH (0x0 << 7) -#define WPP_ACTIVEHIGH (0x0 << 8) -#define RESERVED_MASK (0x3 << 9) -#define CTPL_MMC_SD (0x0 << 11) -#define BLEN_512BYTESLEN (0x200 << 0) -#define NBLK_STPCNT (0x0 << 16) -#define DE_DISABLE (0x0 << 0) -#define BCE_DISABLE (0x0 << 1) -#define BCE_ENABLE (0x1 << 1) -#define ACEN_DISABLE (0x0 << 2) -#define DDIR_OFFSET (4) -#define DDIR_MASK (0x1 << 4) -#define DDIR_WRITE (0x0 << 4) -#define DDIR_READ (0x1 << 4) -#define MSBS_SGLEBLK (0x0 << 5) -#define MSBS_MULTIBLK (0x1 << 5) -#define RSP_TYPE_OFFSET (16) -#define RSP_TYPE_MASK (0x3 << 16) -#define RSP_TYPE_NORSP (0x0 << 16) -#define RSP_TYPE_LGHT136 (0x1 << 16) -#define RSP_TYPE_LGHT48 (0x2 << 16) -#define RSP_TYPE_LGHT48B (0x3 << 16) -#define CCCE_NOCHECK (0x0 << 19) -#define CCCE_CHECK (0x1 << 19) -#define CICE_NOCHECK (0x0 << 20) -#define CICE_CHECK (0x1 << 20) -#define DP_OFFSET (21) -#define DP_MASK (0x1 << 21) -#define DP_NO_DATA (0x0 << 21) -#define DP_DATA (0x1 << 21) -#define CMD_TYPE_NORMAL (0x0 << 22) -#define INDEX_OFFSET (24) -#define INDEX_MASK (0x3f << 24) -#define INDEX(i) (i << 24) -#define DATI_MASK (0x1 << 1) -#define CMDI_MASK (0x1 << 0) -#define DTW_1_BITMODE (0x0 << 1) -#define DTW_4_BITMODE (0x1 << 1) -#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ -#define SDBP_PWROFF (0x0 << 8) -#define SDBP_PWRON (0x1 << 8) -#define SDVS_1V8 (0x5 << 9) -#define SDVS_3V0 (0x6 << 9) -#define ICE_MASK (0x1 << 0) -#define ICE_STOP (0x0 << 0) -#define ICS_MASK (0x1 << 1) -#define ICS_NOTREADY (0x0 << 1) -#define ICE_OSCILLATE (0x1 << 0) -#define CEN_MASK (0x1 << 2) -#define CEN_DISABLE (0x0 << 2) -#define CEN_ENABLE (0x1 << 2) -#define CLKD_OFFSET (6) -#define CLKD_MASK (0x3FF << 6) -#define DTO_MASK (0xF << 16) -#define DTO_15THDTO (0xE << 16) -#define SOFTRESETALL (0x1 << 24) -#define CC_MASK (0x1 << 0) -#define TC_MASK (0x1 << 1) -#define BWR_MASK (0x1 << 4) -#define BRR_MASK (0x1 << 5) -#define ERRI_MASK (0x1 << 15) -#define IE_CC (0x01 << 0) -#define IE_TC (0x01 << 1) -#define IE_BWR (0x01 << 4) -#define IE_BRR (0x01 << 5) -#define IE_CTO (0x01 << 16) -#define IE_CCRC (0x01 << 17) -#define IE_CEB (0x01 << 18) -#define IE_CIE (0x01 << 19) -#define IE_DTO (0x01 << 20) -#define IE_DCRC (0x01 << 21) -#define IE_DEB (0x01 << 22) -#define IE_CERR (0x01 << 28) -#define IE_BADA (0x01 << 29) - -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) - -/* Driver definitions */ -#define MMCSD_SECTOR_SIZE 512 -#define MMC_CARD 0 -#define SD_CARD 1 -#define BYTE_MODE 0 -#define SECTOR_MODE 1 -#define CLK_INITSEQ 0 -#define CLK_400KHZ 1 -#define CLK_MISC 2 - -#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) -#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) - -/* Clock Configurations and Macros */ -#define MMC_CLOCK_REFERENCE 96 /* MHz */ - -#define mmc_reg_out(addr, mask, val)\ - writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) - -int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max); - #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h new file mode 100644 index 000000000..55e9de604 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h @@ -0,0 +1,344 @@ +/* + * (C) Copyright 2013 + * Texas Instruments Incorporated + * + * Nishant Kamat <nskamat@ti.com> + * Lokesh Vutla <lokeshvutla@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUX_DRA7XX_H_ +#define _MUX_DRA7XX_H_ + +#include <asm/types.h> + +#define IEN (1 << 18) +#define IDIS (0 << 18) + +#define PTU (3 << 16) +#define PTD (1 << 16) +#define PEN (1 << 16) +#define PDIS (0 << 16) + +#define WKEN (1 << 24) +#define WKDIS (0 << 24) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 +#define M8 8 +#define M9 9 +#define M10 10 +#define M11 11 +#define M12 12 +#define M13 13 +#define M14 14 +#define M15 15 + +#define SAFE_MODE M15 + +#define GPMC_AD0 0x000 +#define GPMC_AD1 0x004 +#define GPMC_AD2 0x008 +#define GPMC_AD3 0x00C +#define GPMC_AD4 0x010 +#define GPMC_AD5 0x014 +#define GPMC_AD6 0x018 +#define GPMC_AD7 0x01C +#define GPMC_AD8 0x020 +#define GPMC_AD9 0x024 +#define GPMC_AD10 0x028 +#define GPMC_AD11 0x02C +#define GPMC_AD12 0x030 +#define GPMC_AD13 0x034 +#define GPMC_AD14 0x038 +#define GPMC_AD15 0x03C +#define GPMC_A0 0x040 +#define GPMC_A1 0x044 +#define GPMC_A2 0x048 +#define GPMC_A3 0x04C +#define GPMC_A4 0x050 +#define GPMC_A5 0x054 +#define GPMC_A6 0x058 +#define GPMC_A7 0x05C +#define GPMC_A8 0x060 +#define GPMC_A9 0x064 +#define GPMC_A10 0x068 +#define GPMC_A11 0x06C +#define GPMC_A12 0x070 +#define GPMC_A13 0x074 +#define GPMC_A14 0x078 +#define GPMC_A15 0x07C +#define GPMC_A16 0x080 +#define GPMC_A17 0x084 +#define GPMC_A18 0x088 +#define GPMC_A19 0x08C +#define GPMC_A20 0x090 +#define GPMC_A21 0x094 +#define GPMC_A22 0x098 +#define GPMC_A23 0x09C +#define GPMC_A24 0x0A0 +#define GPMC_A25 0x0A4 +#define GPMC_A26 0x0A8 +#define GPMC_A27 0x0AC +#define GPMC_CS1 0x0B0 +#define GPMC_CS0 0x0B4 +#define GPMC_CS2 0x0B8 +#define GPMC_CS3 0x0BC +#define GPMC_CLK 0x0C0 +#define GPMC_ADVN_ALE 0x0C4 +#define GPMC_OEN_REN 0x0C8 +#define GPMC_WEN 0x0CC +#define GPMC_BEN0 0x0D0 +#define GPMC_BEN1 0x0D4 +#define GPMC_WAIT0 0x0D8 +#define VIN1A_CLK0 0x0DC +#define VIN1B_CLK1 0x0E0 +#define VIN1A_DE0 0x0E4 +#define VIN1A_FLD0 0x0E8 +#define VIN1A_HSYNC0 0x0EC +#define VIN1A_VSYNC0 0x0F0 +#define VIN1A_D0 0x0F4 +#define VIN1A_D1 0x0F8 +#define VIN1A_D2 0x0FC +#define VIN1A_D3 0x100 +#define VIN1A_D4 0x104 +#define VIN1A_D5 0x108 +#define VIN1A_D6 0x10C +#define VIN1A_D7 0x110 +#define VIN1A_D8 0x114 +#define VIN1A_D9 0x118 +#define VIN1A_D10 0x11C +#define VIN1A_D11 0x120 +#define VIN1A_D12 0x124 +#define VIN1A_D13 0x128 +#define VIN1A_D14 0x12C +#define VIN1A_D15 0x130 +#define VIN1A_D16 0x134 +#define VIN1A_D17 0x138 +#define VIN1A_D18 0x13C +#define VIN1A_D19 0x140 +#define VIN1A_D20 0x144 +#define VIN1A_D21 0x148 +#define VIN1A_D22 0x14C +#define VIN1A_D23 0x150 +#define VIN2A_CLK0 0x154 +#define VIN2A_DE0 0x158 +#define VIN2A_FLD0 0x15C +#define VIN2A_HSYNC0 0x160 +#define VIN2A_VSYNC0 0x164 +#define VIN2A_D0 0x168 +#define VIN2A_D1 0x16C +#define VIN2A_D2 0x170 +#define VIN2A_D3 0x174 +#define VIN2A_D4 0x178 +#define VIN2A_D5 0x17C +#define VIN2A_D6 0x180 +#define VIN2A_D7 0x184 +#define VIN2A_D8 0x188 +#define VIN2A_D9 0x18C +#define VIN2A_D10 0x190 +#define VIN2A_D11 0x194 +#define VIN2A_D12 0x198 +#define VIN2A_D13 0x19C +#define VIN2A_D14 0x1A0 +#define VIN2A_D15 0x1A4 +#define VIN2A_D16 0x1A8 +#define VIN2A_D17 0x1AC +#define VIN2A_D18 0x1B0 +#define VIN2A_D19 0x1B4 +#define VIN2A_D20 0x1B8 +#define VIN2A_D21 0x1BC +#define VIN2A_D22 0x1C0 +#define VIN2A_D23 0x1C4 +#define VOUT1_CLK 0x1C8 +#define VOUT1_DE 0x1CC +#define VOUT1_FLD 0x1D0 +#define VOUT1_HSYNC 0x1D4 +#define VOUT1_VSYNC 0x1D8 +#define VOUT1_D0 0x1DC +#define VOUT1_D1 0x1E0 +#define VOUT1_D2 0x1E4 +#define VOUT1_D3 0x1E8 +#define VOUT1_D4 0x1EC +#define VOUT1_D5 0x1F0 +#define VOUT1_D6 0x1F4 +#define VOUT1_D7 0x1F8 +#define VOUT1_D8 0x1FC +#define VOUT1_D9 0x200 +#define VOUT1_D10 0x204 +#define VOUT1_D11 0x208 +#define VOUT1_D12 0x20C +#define VOUT1_D13 0x210 +#define VOUT1_D14 0x214 +#define VOUT1_D15 0x218 +#define VOUT1_D16 0x21C +#define VOUT1_D17 0x220 +#define VOUT1_D18 0x224 +#define VOUT1_D19 0x228 +#define VOUT1_D20 0x22C +#define VOUT1_D21 0x230 +#define VOUT1_D22 0x234 +#define VOUT1_D23 0x238 +#define MDIO_MCLK 0x23C +#define MDIO_D 0x240 +#define RMII_MHZ_50_CLK 0x244 +#define UART3_RXD 0x248 +#define UART3_TXD 0x24C +#define RGMII0_TXC 0x250 +#define RGMII0_TXCTL 0x254 +#define RGMII0_TXD3 0x258 +#define RGMII0_TXD2 0x25C +#define RGMII0_TXD1 0x260 +#define RGMII0_TXD0 0x264 +#define RGMII0_RXC 0x268 +#define RGMII0_RXCTL 0x26C +#define RGMII0_RXD3 0x270 +#define RGMII0_RXD2 0x274 +#define RGMII0_RXD1 0x278 +#define RGMII0_RXD0 0x27C +#define USB1_DRVVBUS 0x280 +#define USB2_DRVVBUS 0x284 +#define GPIO6_14 0x288 +#define GPIO6_15 0x28C +#define GPIO6_16 0x290 +#define XREF_CLK0 0x294 +#define XREF_CLK1 0x298 +#define XREF_CLK2 0x29C +#define XREF_CLK3 0x2A0 +#define MCASP1_ACLKX 0x2A4 +#define MCASP1_FSX 0x2A8 +#define MCASP1_ACLKR 0x2AC +#define MCASP1_FSR 0x2B0 +#define MCASP1_AXR0 0x2B4 +#define MCASP1_AXR1 0x2B8 +#define MCASP1_AXR2 0x2BC +#define MCASP1_AXR3 0x2C0 +#define MCASP1_AXR4 0x2C4 +#define MCASP1_AXR5 0x2C8 +#define MCASP1_AXR6 0x2CC +#define MCASP1_AXR7 0x2D0 +#define MCASP1_AXR8 0x2D4 +#define MCASP1_AXR9 0x2D8 +#define MCASP1_AXR10 0x2DC +#define MCASP1_AXR11 0x2E0 +#define MCASP1_AXR12 0x2E4 +#define MCASP1_AXR13 0x2E8 +#define MCASP1_AXR14 0x2EC +#define MCASP1_AXR15 0x2F0 +#define MCASP2_ACLKX 0x2F4 +#define MCASP2_FSX 0x2F8 +#define MCASP2_ACLKR 0x2FC +#define MCASP2_FSR 0x300 +#define MCASP2_AXR0 0x304 +#define MCASP2_AXR1 0x308 +#define MCASP2_AXR2 0x30C +#define MCASP2_AXR3 0x310 +#define MCASP2_AXR4 0x314 +#define MCASP2_AXR5 0x318 +#define MCASP2_AXR6 0x31C +#define MCASP2_AXR7 0x320 +#define MCASP3_ACLKX 0x324 +#define MCASP3_FSX 0x328 +#define MCASP3_AXR0 0x32C +#define MCASP3_AXR1 0x330 +#define MCASP4_ACLKX 0x334 +#define MCASP4_FSX 0x338 +#define MCASP4_AXR0 0x33C +#define MCASP4_AXR1 0x340 +#define MCASP5_ACLKX 0x344 +#define MCASP5_FSX 0x348 +#define MCASP5_AXR0 0x34C +#define MCASP5_AXR1 0x350 +#define MMC1_CLK 0x354 +#define MMC1_CMD 0x358 +#define MMC1_DAT0 0x35C +#define MMC1_DAT1 0x360 +#define MMC1_DAT2 0x364 +#define MMC1_DAT3 0x368 +#define MMC1_SDCD 0x36C +#define MMC1_SDWP 0x370 +#define GPIO6_10 0x374 +#define GPIO6_11 0x378 +#define MMC3_CLK 0x37C +#define MMC3_CMD 0x380 +#define MMC3_DAT0 0x384 +#define MMC3_DAT1 0x388 +#define MMC3_DAT2 0x38C +#define MMC3_DAT3 0x390 +#define MMC3_DAT4 0x394 +#define MMC3_DAT5 0x398 +#define MMC3_DAT6 0x39C +#define MMC3_DAT7 0x3A0 +#define SPI1_SCLK 0x3A4 +#define SPI1_D1 0x3A8 +#define SPI1_D0 0x3AC +#define SPI1_CS0 0x3B0 +#define SPI1_CS1 0x3B4 +#define SPI1_CS2 0x3B8 +#define SPI1_CS3 0x3BC +#define SPI2_SCLK 0x3C0 +#define SPI2_D1 0x3C4 +#define SPI2_D0 0x3C8 +#define SPI2_CS0 0x3CC +#define DCAN1_TX 0x3D0 +#define DCAN1_RX 0x3D4 +#define DCAN2_TX 0x3D8 +#define DCAN2_RX 0x3DC +#define UART1_RXD 0x3E0 +#define UART1_TXD 0x3E4 +#define UART1_CTSN 0x3E8 +#define UART1_RTSN 0x3EC +#define UART2_RXD 0x3F0 +#define UART2_TXD 0x3F4 +#define UART2_CTSN 0x3F8 +#define UART2_RTSN 0x3FC +#define I2C1_SDA 0x400 +#define I2C1_SCL 0x404 +#define I2C2_SDA 0x408 +#define I2C2_SCL 0x40C +#define I2C3_SDA 0x410 +#define I2C3_SCL 0x414 +#define WAKEUP0 0x418 +#define WAKEUP1 0x41C +#define WAKEUP2 0x420 +#define WAKEUP3 0x424 +#define ON_OFF 0x428 +#define RTC_PORZ 0x42C +#define TMS 0x430 +#define TDI 0x434 +#define TDO 0x438 +#define TCLK 0x43C +#define TRSTN 0x440 +#define RTCK 0x444 +#define EMU0 0x448 +#define EMU1 0x44C +#define EMU2 0x450 +#define EMU3 0x454 +#define EMU4 0x458 +#define RESETN 0x45C +#define NMIN 0x460 +#define RSTOUTN 0x464 + +#endif /* _MUX_DRA7XX_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h index 4a6ed8b45..34b0dbd06 100644 --- a/arch/arm/include/asm/arch-omap5/mux_omap5.h +++ b/arch/arm/include/asm/arch-omap5/mux_omap5.h @@ -28,14 +28,6 @@ #include <asm/types.h> -struct pad_conf_entry { - - u16 offset; - - u16 val; - -}; - #ifdef CONFIG_OFF_PADCONF #define OFF_PD (1 << 12) #define OFF_PU (3 << 12) diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 9dce49ac4..b632635d3 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -57,7 +57,10 @@ /* To be verified */ #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F +#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F +#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F +#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F /* STD_FUSE_PROD_ID_1 */ #define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) @@ -131,87 +134,6 @@ struct s32ktimer { #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) #define DEVICE_GP 0x3 -struct omap_sys_ctrl_regs { - u32 pad0[77]; /* 0x4A002000 */ - u32 control_status; /* 0x4A002134 */ - u32 pad1[794]; /* 0x4A002138 */ - u32 control_paconf_global; /* 0x4A002DA0 */ - u32 control_paconf_mode; /* 0x4A002DA4 */ - u32 control_smart1io_padconf_0; /* 0x4A002DA8 */ - u32 control_smart1io_padconf_1; /* 0x4A002DAC */ - u32 control_smart1io_padconf_2; /* 0x4A002DB0 */ - u32 control_smart2io_padconf_0; /* 0x4A002DB4 */ - u32 control_smart2io_padconf_1; /* 0x4A002DB8 */ - u32 control_smart2io_padconf_2; /* 0x4A002DBC */ - u32 control_smart3io_padconf_0; /* 0x4A002DC0 */ - u32 control_smart3io_padconf_1; /* 0x4A002DC4 */ - u32 pad2[14]; - u32 control_pbias; /* 0x4A002E00 */ - u32 control_i2c_0; /* 0x4A002E04 */ - u32 control_camera_rx; /* 0x4A002E08 */ - u32 control_hdmi_tx_phy; /* 0x4A002E0C */ - u32 control_uniportm; /* 0x4A002E10 */ - u32 control_dsiphy; /* 0x4A002E14 */ - u32 control_mcbsplp; /* 0x4A002E18 */ - u32 control_usb2phycore; /* 0x4A002E1C */ - u32 control_hdmi_1; /*0x4A002E20*/ - u32 control_hsi; /*0x4A002E24*/ - u32 pad3[2]; - u32 control_ddr3ch1_0; /*0x4A002E30*/ - u32 control_ddr3ch2_0; /*0x4A002E34*/ - u32 control_ddrch1_0; /*0x4A002E38*/ - u32 control_ddrch1_1; /*0x4A002E3C*/ - u32 control_ddrch2_0; /*0x4A002E40*/ - u32 control_ddrch2_1; /*0x4A002E44*/ - u32 control_lpddr2ch1_0; /*0x4A002E48*/ - u32 control_lpddr2ch1_1; /*0x4A002E4C*/ - u32 control_ddrio_0; /*0x4A002E50*/ - u32 control_ddrio_1; /*0x4A002E54*/ - u32 control_ddrio_2; /*0x4A002E58*/ - u32 control_hyst_1; /*0x4A002E5C*/ - u32 control_usbb_hsic_control; /*0x4A002E60*/ - u32 control_c2c; /*0x4A002E64*/ - u32 control_core_control_spare_rw; /*0x4A002E68*/ - u32 control_core_control_spare_r; /*0x4A002E6C*/ - u32 control_core_control_spare_r_c0; /*0x4A002E70*/ - u32 control_srcomp_north_side; /*0x4A002E74*/ - u32 control_srcomp_south_side; /*0x4A002E78*/ - u32 control_srcomp_east_side; /*0x4A002E7C*/ - u32 control_srcomp_west_side; /*0x4A002E80*/ - u32 control_srcomp_code_latch; /*0x4A002E84*/ - u32 pad4[3679394]; - u32 control_port_emif1_sdram_config; /*0x4AE0C110*/ - u32 control_port_emif1_lpddr2_nvm_config; /*0x4AE0C114*/ - u32 control_port_emif2_sdram_config; /*0x4AE0C118*/ - u32 pad5[10]; - u32 control_emif1_sdram_config_ext; /* 0x4AE0C144 */ - u32 control_emif2_sdram_config_ext; /* 0x4AE0C148 */ - u32 pad6[789]; - u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */ - u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */ - u32 control_padconf_mode; /* 0x4AE0CDA8 */ - u32 control_xtal_oscillator; /* 0x4AE0CDAC */ - u32 control_i2c_2; /* 0x4AE0CDB0 */ - u32 control_ckobuffer; /* 0x4AE0CDB4 */ - u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */ - u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */ - u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */ - u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */ - u32 control_efuse_1; /* 0x4AE0CDC8 */ - u32 control_efuse_2; /* 0x4AE0CDCC */ - u32 control_efuse_3; /* 0x4AE0CDD0 */ - u32 control_efuse_4; /* 0x4AE0CDD4 */ - u32 control_efuse_5; /* 0x4AE0CDD8 */ - u32 control_efuse_6; /* 0x4AE0CDDC */ - u32 control_efuse_7; /* 0x4AE0CDE0 */ - u32 control_efuse_8; /* 0x4AE0CDE4 */ - u32 control_efuse_9; /* 0x4AE0CDE8 */ - u32 control_efuse_10; /* 0x4AE0CDEC */ - u32 control_efuse_11; /* 0x4AE0CDF0 */ - u32 control_efuse_12; /* 0x4AE0CDF4 */ - u32 control_efuse_13; /* 0x4AE0CDF8 */ -}; - /* Output impedance control */ #define ds_120_ohm 0x0 #define ds_60_ohm 0x1 @@ -247,6 +169,12 @@ struct omap_sys_ctrl_regs { #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 +#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465 +#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8 +#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 + #define EFUSE_1 0x45145100 #define EFUSE_2 0x45145100 #define EFUSE_3 0x45145100 @@ -271,7 +199,11 @@ struct omap_sys_ctrl_regs { #define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) #define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) #define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) -#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14) +#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) +#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) +#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) +#define OMAP5_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20) +#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24) /* Silicon revisions */ #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF @@ -298,7 +230,26 @@ struct omap_sys_ctrl_regs { #define CH_FLAGS_CHFLASH (0x1 << 2) #define CH_FLAGS_CHMMCSD (0x1 << 3) +/* CONTROL_SRCOMP_XXX_SIDE */ +#define OVERRIDE_XS_SHIFT 30 +#define OVERRIDE_XS_MASK (1 << 30) +#define SRCODE_READ_XS_SHIFT 12 +#define SRCODE_READ_XS_MASK (0xff << 12) +#define PWRDWN_XS_SHIFT 11 +#define PWRDWN_XS_MASK (1 << 11) +#define DIVIDE_FACTOR_XS_SHIFT 4 +#define DIVIDE_FACTOR_XS_MASK (0x7f << 4) +#define MULTIPLY_FACTOR_XS_SHIFT 1 +#define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) +#define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 +#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) + #ifndef __ASSEMBLY__ +struct srcomp_params { + s8 divide_factor; + s8 multiply_factor; +}; + struct omap_boot_parameters { char *boot_message; unsigned int mem_boot_descriptor; @@ -306,5 +257,15 @@ struct omap_boot_parameters { unsigned char reset_reason; unsigned char ch_flags; }; + +struct ctrl_ioregs { + u32 ctrl_ddrch; + u32 ctrl_lpddr2ch; + u32 ctrl_ddr3ch; + u32 ctrl_ddrio_0; + u32 ctrl_ddrio_1; + u32 ctrl_ddrio_2; + u32 ctrl_emif_sdram_config_ext; +}; #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h index d125c61f4..323cd6355 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ b/arch/arm/include/asm/arch-omap5/spl.h @@ -27,7 +27,7 @@ #define BOOT_DEVICE_XIP 1 #define BOOT_DEVICE_XIPWAIT 2 #define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONE_NAND 4 +#define BOOT_DEVICE_ONENAND 4 #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 7 diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 72e9df788..e66ab4434 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -25,9 +25,13 @@ #include <asm/io.h> #include <asm/arch/clocks.h> #include <asm/omap_common.h> -#include <asm/arch/mux_omap5.h> #include <asm/arch/clocks.h> +struct pad_conf_entry { + u32 offset; + u32 val; +}; + struct omap_sysinfo { char *board_string; }; @@ -44,7 +48,7 @@ u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); void setup_clocks_for_console(void); void prcm_init(void); -void bypass_dpll(u32 *const base); +void bypass_dpll(u32 const base); void freq_update_core(void); u32 get_sys_clk_freq(void); u32 omap5_ddr_clk(void); @@ -58,6 +62,8 @@ void omap_vc_init(u16 speed_khz); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); +void get_ioregs(const struct ctrl_ioregs **regs); +void srcomp_enable(void); /* * This is used to verify if the configuration header diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index ad9a875de..a73630bc4 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -33,6 +33,7 @@ /* Cortex-A15 revisions */ #define MIDR_CORTEX_A15_R0P0 0x410FC0F0 +#define MIDR_CORTEX_A15_R2P2 0x412FC0F2 /* CCSIDR */ #define CCSIDR_LINE_SIZE_OFFSET 0 diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index ed251ec8e..c5d1e6c83 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -519,6 +519,7 @@ #define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 +#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7 /* DMM */ #define DMM_BASE 0x4E000040 @@ -696,11 +697,9 @@ struct dmm_lisa_map_regs { u32 dmm_lisa_map_1; u32 dmm_lisa_map_2; u32 dmm_lisa_map_3; + u8 is_ma_present; }; -extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; -extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; - #define CS0 0 #define CS1 1 /* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ @@ -1027,6 +1026,11 @@ extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; #define MR8_IO_WIDTH_SHIFT 0x6 #define MR8_IO_WIDTH_MASK (0x3 << 0x6) +/* SDRAM TYPE */ +#define EMIF_SDRAM_TYPE_DDR2 0x2 +#define EMIF_SDRAM_TYPE_DDR3 0x3 +#define EMIF_SDRAM_TYPE_LPDDR2 0x4 + struct lpddr2_addressing { u8 num_banks; u8 t_REFI_us_x10; @@ -1129,6 +1133,14 @@ struct emif_regs { u32 emif_rd_wr_exec_thresh; }; +struct lpddr2_mr_regs { + s8 mr1; + s8 mr2; + s8 mr3; + s8 mr10; + s8 mr16; +}; + /* assert macros */ #if defined(DEBUG) #define emif_assert(c) ({ if (!(c)) for (;;); }) @@ -1148,6 +1160,7 @@ void emif_get_device_timings(u32 emif_nr, #endif void do_ext_phy_settings(u32 base, const struct emif_regs *regs); +void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs); #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS extern u32 *const T_num; @@ -1156,4 +1169,5 @@ extern u32 *const emif_sizes; #endif void config_data_eye_leveling_samples(u32 emif_base); +u32 emif_sdram_type(void); #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 2a40b898e..091ddb508 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -25,6 +25,524 @@ #ifndef _OMAP_COMMON_H_ #define _OMAP_COMMON_H_ +#include <common.h> + +#define NUM_SYS_CLKS 8 + +struct prcm_regs { + /* cm1.ckgen */ + u32 cm_clksel_core; + u32 cm_clksel_abe; + u32 cm_dll_ctrl; + u32 cm_clkmode_dpll_core; + u32 cm_idlest_dpll_core; + u32 cm_autoidle_dpll_core; + u32 cm_clksel_dpll_core; + u32 cm_div_m2_dpll_core; + u32 cm_div_m3_dpll_core; + u32 cm_div_h11_dpll_core; + u32 cm_div_h12_dpll_core; + u32 cm_div_h13_dpll_core; + u32 cm_div_h14_dpll_core; + u32 cm_div_h21_dpll_core; + u32 cm_div_h24_dpll_core; + u32 cm_ssc_deltamstep_dpll_core; + u32 cm_ssc_modfreqdiv_dpll_core; + u32 cm_emu_override_dpll_core; + u32 cm_div_h22_dpllcore; + u32 cm_div_h23_dpll_core; + u32 cm_clkmode_dpll_mpu; + u32 cm_idlest_dpll_mpu; + u32 cm_autoidle_dpll_mpu; + u32 cm_clksel_dpll_mpu; + u32 cm_div_m2_dpll_mpu; + u32 cm_ssc_deltamstep_dpll_mpu; + u32 cm_ssc_modfreqdiv_dpll_mpu; + u32 cm_bypclk_dpll_mpu; + u32 cm_clkmode_dpll_iva; + u32 cm_idlest_dpll_iva; + u32 cm_autoidle_dpll_iva; + u32 cm_clksel_dpll_iva; + u32 cm_div_h11_dpll_iva; + u32 cm_div_h12_dpll_iva; + u32 cm_ssc_deltamstep_dpll_iva; + u32 cm_ssc_modfreqdiv_dpll_iva; + u32 cm_bypclk_dpll_iva; + u32 cm_clkmode_dpll_abe; + u32 cm_idlest_dpll_abe; + u32 cm_autoidle_dpll_abe; + u32 cm_clksel_dpll_abe; + u32 cm_div_m2_dpll_abe; + u32 cm_div_m3_dpll_abe; + u32 cm_ssc_deltamstep_dpll_abe; + u32 cm_ssc_modfreqdiv_dpll_abe; + u32 cm_clkmode_dpll_ddrphy; + u32 cm_idlest_dpll_ddrphy; + u32 cm_autoidle_dpll_ddrphy; + u32 cm_clksel_dpll_ddrphy; + u32 cm_div_m2_dpll_ddrphy; + u32 cm_div_h11_dpll_ddrphy; + u32 cm_div_h12_dpll_ddrphy; + u32 cm_div_h13_dpll_ddrphy; + u32 cm_ssc_deltamstep_dpll_ddrphy; + u32 cm_clkmode_dpll_dsp; + u32 cm_shadow_freq_config1; + u32 cm_mpu_mpu_clkctrl; + + /* cm1.dsp */ + u32 cm_dsp_clkstctrl; + u32 cm_dsp_dsp_clkctrl; + + /* cm1.abe */ + u32 cm1_abe_clkstctrl; + u32 cm1_abe_l4abe_clkctrl; + u32 cm1_abe_aess_clkctrl; + u32 cm1_abe_pdm_clkctrl; + u32 cm1_abe_dmic_clkctrl; + u32 cm1_abe_mcasp_clkctrl; + u32 cm1_abe_mcbsp1_clkctrl; + u32 cm1_abe_mcbsp2_clkctrl; + u32 cm1_abe_mcbsp3_clkctrl; + u32 cm1_abe_slimbus_clkctrl; + u32 cm1_abe_timer5_clkctrl; + u32 cm1_abe_timer6_clkctrl; + u32 cm1_abe_timer7_clkctrl; + u32 cm1_abe_timer8_clkctrl; + u32 cm1_abe_wdt3_clkctrl; + + /* cm2.ckgen */ + u32 cm_clksel_mpu_m3_iss_root; + u32 cm_clksel_usb_60mhz; + u32 cm_scale_fclk; + u32 cm_core_dvfs_perf1; + u32 cm_core_dvfs_perf2; + u32 cm_core_dvfs_perf3; + u32 cm_core_dvfs_perf4; + u32 cm_core_dvfs_current; + u32 cm_iva_dvfs_perf_tesla; + u32 cm_iva_dvfs_perf_ivahd; + u32 cm_iva_dvfs_perf_abe; + u32 cm_iva_dvfs_current; + u32 cm_clkmode_dpll_per; + u32 cm_idlest_dpll_per; + u32 cm_autoidle_dpll_per; + u32 cm_clksel_dpll_per; + u32 cm_div_m2_dpll_per; + u32 cm_div_m3_dpll_per; + u32 cm_div_h11_dpll_per; + u32 cm_div_h12_dpll_per; + u32 cm_div_h13_dpll_per; + u32 cm_div_h14_dpll_per; + u32 cm_ssc_deltamstep_dpll_per; + u32 cm_ssc_modfreqdiv_dpll_per; + u32 cm_emu_override_dpll_per; + u32 cm_clkmode_dpll_usb; + u32 cm_idlest_dpll_usb; + u32 cm_autoidle_dpll_usb; + u32 cm_clksel_dpll_usb; + u32 cm_div_m2_dpll_usb; + u32 cm_ssc_deltamstep_dpll_usb; + u32 cm_ssc_modfreqdiv_dpll_usb; + u32 cm_clkdcoldo_dpll_usb; + u32 cm_clkmode_dpll_pcie_ref; + u32 cm_clkmode_apll_pcie; + u32 cm_idlest_apll_pcie; + u32 cm_div_m2_apll_pcie; + u32 cm_clkvcoldo_apll_pcie; + u32 cm_clkmode_dpll_unipro; + u32 cm_idlest_dpll_unipro; + u32 cm_autoidle_dpll_unipro; + u32 cm_clksel_dpll_unipro; + u32 cm_div_m2_dpll_unipro; + u32 cm_ssc_deltamstep_dpll_unipro; + u32 cm_ssc_modfreqdiv_dpll_unipro; + + /* cm2.core */ + u32 cm_coreaon_bandgap_clkctrl; + u32 cm_coreaon_io_srcomp_clkctrl; + u32 cm_l3_1_clkstctrl; + u32 cm_l3_1_dynamicdep; + u32 cm_l3_1_l3_1_clkctrl; + u32 cm_l3_2_clkstctrl; + u32 cm_l3_2_dynamicdep; + u32 cm_l3_2_l3_2_clkctrl; + u32 cm_l3_gpmc_clkctrl; + u32 cm_l3_2_ocmc_ram_clkctrl; + u32 cm_mpu_m3_clkstctrl; + u32 cm_mpu_m3_staticdep; + u32 cm_mpu_m3_dynamicdep; + u32 cm_mpu_m3_mpu_m3_clkctrl; + u32 cm_sdma_clkstctrl; + u32 cm_sdma_staticdep; + u32 cm_sdma_dynamicdep; + u32 cm_sdma_sdma_clkctrl; + u32 cm_memif_clkstctrl; + u32 cm_memif_dmm_clkctrl; + u32 cm_memif_emif_fw_clkctrl; + u32 cm_memif_emif_1_clkctrl; + u32 cm_memif_emif_2_clkctrl; + u32 cm_memif_dll_clkctrl; + u32 cm_memif_emif_h1_clkctrl; + u32 cm_memif_emif_h2_clkctrl; + u32 cm_memif_dll_h_clkctrl; + u32 cm_c2c_clkstctrl; + u32 cm_c2c_staticdep; + u32 cm_c2c_dynamicdep; + u32 cm_c2c_sad2d_clkctrl; + u32 cm_c2c_modem_icr_clkctrl; + u32 cm_c2c_sad2d_fw_clkctrl; + u32 cm_l4cfg_clkstctrl; + u32 cm_l4cfg_dynamicdep; + u32 cm_l4cfg_l4_cfg_clkctrl; + u32 cm_l4cfg_hw_sem_clkctrl; + u32 cm_l4cfg_mailbox_clkctrl; + u32 cm_l4cfg_sar_rom_clkctrl; + u32 cm_l3instr_clkstctrl; + u32 cm_l3instr_l3_3_clkctrl; + u32 cm_l3instr_l3_instr_clkctrl; + u32 cm_l3instr_intrconn_wp1_clkctrl; + + /* cm2.ivahd */ + u32 cm_ivahd_clkstctrl; + u32 cm_ivahd_ivahd_clkctrl; + u32 cm_ivahd_sl2_clkctrl; + + /* cm2.cam */ + u32 cm_cam_clkstctrl; + u32 cm_cam_iss_clkctrl; + u32 cm_cam_fdif_clkctrl; + u32 cm_cam_vip1_clkctrl; + u32 cm_cam_vip2_clkctrl; + u32 cm_cam_vip3_clkctrl; + u32 cm_cam_lvdsrx_clkctrl; + u32 cm_cam_csi1_clkctrl; + u32 cm_cam_csi2_clkctrl; + + /* cm2.dss */ + u32 cm_dss_clkstctrl; + u32 cm_dss_dss_clkctrl; + + /* cm2.sgx */ + u32 cm_sgx_clkstctrl; + u32 cm_sgx_sgx_clkctrl; + + /* cm2.l3init */ + u32 cm_l3init_clkstctrl; + + /* cm2.l3init */ + u32 cm_l3init_hsmmc1_clkctrl; + u32 cm_l3init_hsmmc2_clkctrl; + u32 cm_l3init_hsi_clkctrl; + u32 cm_l3init_hsusbhost_clkctrl; + u32 cm_l3init_hsusbotg_clkctrl; + u32 cm_l3init_hsusbtll_clkctrl; + u32 cm_l3init_p1500_clkctrl; + u32 cm_l3init_fsusb_clkctrl; + u32 cm_l3init_ocp2scp1_clkctrl; + + /* cm2.l4per */ + u32 cm_l4per_clkstctrl; + u32 cm_l4per_dynamicdep; + u32 cm_l4per_adc_clkctrl; + u32 cm_l4per_gptimer10_clkctrl; + u32 cm_l4per_gptimer11_clkctrl; + u32 cm_l4per_gptimer2_clkctrl; + u32 cm_l4per_gptimer3_clkctrl; + u32 cm_l4per_gptimer4_clkctrl; + u32 cm_l4per_gptimer9_clkctrl; + u32 cm_l4per_elm_clkctrl; + u32 cm_l4per_gpio2_clkctrl; + u32 cm_l4per_gpio3_clkctrl; + u32 cm_l4per_gpio4_clkctrl; + u32 cm_l4per_gpio5_clkctrl; + u32 cm_l4per_gpio6_clkctrl; + u32 cm_l4per_hdq1w_clkctrl; + u32 cm_l4per_hecc1_clkctrl; + u32 cm_l4per_hecc2_clkctrl; + u32 cm_l4per_i2c1_clkctrl; + u32 cm_l4per_i2c2_clkctrl; + u32 cm_l4per_i2c3_clkctrl; + u32 cm_l4per_i2c4_clkctrl; + u32 cm_l4per_l4per_clkctrl; + u32 cm_l4per_mcasp2_clkctrl; + u32 cm_l4per_mcasp3_clkctrl; + u32 cm_l4per_mgate_clkctrl; + u32 cm_l4per_mcspi1_clkctrl; + u32 cm_l4per_mcspi2_clkctrl; + u32 cm_l4per_mcspi3_clkctrl; + u32 cm_l4per_mcspi4_clkctrl; + u32 cm_l4per_gpio7_clkctrl; + u32 cm_l4per_gpio8_clkctrl; + u32 cm_l4per_mmcsd3_clkctrl; + u32 cm_l4per_mmcsd4_clkctrl; + u32 cm_l4per_msprohg_clkctrl; + u32 cm_l4per_slimbus2_clkctrl; + u32 cm_l4per_uart1_clkctrl; + u32 cm_l4per_uart2_clkctrl; + u32 cm_l4per_uart3_clkctrl; + u32 cm_l4per_uart4_clkctrl; + u32 cm_l4per_mmcsd5_clkctrl; + u32 cm_l4per_i2c5_clkctrl; + u32 cm_l4per_uart5_clkctrl; + u32 cm_l4per_uart6_clkctrl; + u32 cm_l4sec_clkstctrl; + u32 cm_l4sec_staticdep; + u32 cm_l4sec_dynamicdep; + u32 cm_l4sec_aes1_clkctrl; + u32 cm_l4sec_aes2_clkctrl; + u32 cm_l4sec_des3des_clkctrl; + u32 cm_l4sec_pkaeip29_clkctrl; + u32 cm_l4sec_rng_clkctrl; + u32 cm_l4sec_sha2md51_clkctrl; + u32 cm_l4sec_cryptodma_clkctrl; + + /* l4 wkup regs */ + u32 cm_abe_pll_ref_clksel; + u32 cm_sys_clksel; + u32 cm_wkup_clkstctrl; + u32 cm_wkup_l4wkup_clkctrl; + u32 cm_wkup_wdtimer1_clkctrl; + u32 cm_wkup_wdtimer2_clkctrl; + u32 cm_wkup_gpio1_clkctrl; + u32 cm_wkup_gptimer1_clkctrl; + u32 cm_wkup_gptimer12_clkctrl; + u32 cm_wkup_synctimer_clkctrl; + u32 cm_wkup_usim_clkctrl; + u32 cm_wkup_sarram_clkctrl; + u32 cm_wkup_keyboard_clkctrl; + u32 cm_wkup_rtc_clkctrl; + u32 cm_wkup_bandgap_clkctrl; + u32 cm_wkupaon_scrm_clkctrl; + u32 cm_wkupaon_io_srcomp_clkctrl; + u32 prm_rstctrl; + u32 prm_rstst; + u32 prm_vc_val_bypass; + u32 prm_vc_cfg_i2c_mode; + u32 prm_vc_cfg_i2c_clk; + u32 prm_sldo_core_setup; + u32 prm_sldo_core_ctrl; + u32 prm_sldo_mpu_setup; + u32 prm_sldo_mpu_ctrl; + u32 prm_sldo_mm_setup; + u32 prm_sldo_mm_ctrl; + + u32 cm_div_m4_dpll_core; + u32 cm_div_m5_dpll_core; + u32 cm_div_m6_dpll_core; + u32 cm_div_m7_dpll_core; + u32 cm_div_m4_dpll_iva; + u32 cm_div_m5_dpll_iva; + u32 cm_div_m4_dpll_ddrphy; + u32 cm_div_m5_dpll_ddrphy; + u32 cm_div_m6_dpll_ddrphy; + u32 cm_div_m4_dpll_per; + u32 cm_div_m5_dpll_per; + u32 cm_div_m6_dpll_per; + u32 cm_div_m7_dpll_per; + u32 cm_l3instr_intrconn_wp1_clkct; + u32 cm_l3init_usbphy_clkctrl; + u32 cm_l4per_mcbsp4_clkctrl; + u32 prm_vc_cfg_channel; +}; + +struct omap_sys_ctrl_regs { + u32 control_status; + u32 control_core_mmr_lock1; + u32 control_core_mmr_lock2; + u32 control_core_mmr_lock3; + u32 control_core_mmr_lock4; + u32 control_core_mmr_lock5; + u32 control_core_control_io1; + u32 control_core_control_io2; + u32 control_id_code; + u32 control_std_fuse_opp_bgap; + u32 control_ldosram_iva_voltage_ctrl; + u32 control_ldosram_mpu_voltage_ctrl; + u32 control_ldosram_core_voltage_ctrl; + u32 control_padconf_core_base; + u32 control_paconf_global; + u32 control_paconf_mode; + u32 control_smart1io_padconf_0; + u32 control_smart1io_padconf_1; + u32 control_smart1io_padconf_2; + u32 control_smart2io_padconf_0; + u32 control_smart2io_padconf_1; + u32 control_smart2io_padconf_2; + u32 control_smart3io_padconf_0; + u32 control_smart3io_padconf_1; + u32 control_pbias; + u32 control_i2c_0; + u32 control_camera_rx; + u32 control_hdmi_tx_phy; + u32 control_uniportm; + u32 control_dsiphy; + u32 control_mcbsplp; + u32 control_usb2phycore; + u32 control_hdmi_1; + u32 control_hsi; + u32 control_ddr3ch1_0; + u32 control_ddr3ch2_0; + u32 control_ddrch1_0; + u32 control_ddrch1_1; + u32 control_ddrch2_0; + u32 control_ddrch2_1; + u32 control_lpddr2ch1_0; + u32 control_lpddr2ch1_1; + u32 control_ddrio_0; + u32 control_ddrio_1; + u32 control_ddrio_2; + u32 control_lpddr2io1_0; + u32 control_lpddr2io1_1; + u32 control_lpddr2io1_2; + u32 control_lpddr2io1_3; + u32 control_lpddr2io2_0; + u32 control_lpddr2io2_1; + u32 control_lpddr2io2_2; + u32 control_lpddr2io2_3; + u32 control_hyst_1; + u32 control_usbb_hsic_control; + u32 control_c2c; + u32 control_core_control_spare_rw; + u32 control_core_control_spare_r; + u32 control_core_control_spare_r_c0; + u32 control_srcomp_north_side; + u32 control_srcomp_south_side; + u32 control_srcomp_east_side; + u32 control_srcomp_west_side; + u32 control_srcomp_code_latch; + u32 control_pbiaslite; + u32 control_port_emif1_sdram_config; + u32 control_port_emif1_lpddr2_nvm_config; + u32 control_port_emif2_sdram_config; + u32 control_emif1_sdram_config_ext; + u32 control_emif2_sdram_config_ext; + u32 control_smart1nopmio_padconf_0; + u32 control_smart1nopmio_padconf_1; + u32 control_padconf_mode; + u32 control_xtal_oscillator; + u32 control_i2c_2; + u32 control_ckobuffer; + u32 control_wkup_control_spare_rw; + u32 control_wkup_control_spare_r; + u32 control_wkup_control_spare_r_c0; + u32 control_srcomp_east_side_wkup; + u32 control_efuse_1; + u32 control_efuse_2; + u32 control_efuse_3; + u32 control_efuse_4; + u32 control_efuse_5; + u32 control_efuse_6; + u32 control_efuse_7; + u32 control_efuse_8; + u32 control_efuse_9; + u32 control_efuse_10; + u32 control_efuse_11; + u32 control_efuse_12; + u32 control_efuse_13; + u32 control_padconf_wkup_base; +}; + +struct dpll_params { + u32 m; + u32 n; + s8 m2; + s8 m3; + s8 m4_h11; + s8 m5_h12; + s8 m6_h13; + s8 m7_h14; + s8 h21; + s8 h22; + s8 h23; + s8 h24; +}; + +struct dpll_regs { + u32 cm_clkmode_dpll; + u32 cm_idlest_dpll; + u32 cm_autoidle_dpll; + u32 cm_clksel_dpll; + u32 cm_div_m2_dpll; + u32 cm_div_m3_dpll; + u32 cm_div_m4_h11_dpll; + u32 cm_div_m5_h12_dpll; + u32 cm_div_m6_h13_dpll; + u32 cm_div_m7_h14_dpll; + u32 reserved[2]; + u32 cm_div_h21_dpll; + u32 cm_div_h22_dpll; + u32 cm_div_h23_dpll; + u32 cm_div_h24_dpll; +}; + +struct dplls { + const struct dpll_params *mpu; + const struct dpll_params *core; + const struct dpll_params *per; + const struct dpll_params *abe; + const struct dpll_params *iva; + const struct dpll_params *usb; + const struct dpll_params *ddr; +}; + +struct pmic_data { + u32 base_offset; + u32 step; + u32 start_code; + unsigned gpio; + int gpio_en; +}; + +struct volts { + u32 value; + u32 addr; + struct pmic_data *pmic; +}; + +struct vcores_data { + struct volts mpu; + struct volts core; + struct volts mm; +}; + +extern struct prcm_regs const **prcm; +extern struct prcm_regs const omap5_es1_prcm; +extern struct prcm_regs const omap5_es2_prcm; +extern struct prcm_regs const omap4_prcm; +extern struct prcm_regs const dra7xx_prcm; +extern struct dplls const **dplls_data; +extern struct vcores_data const **omap_vcores; +extern const u32 sys_clk_array[8]; +extern struct omap_sys_ctrl_regs const **ctrl; +extern struct omap_sys_ctrl_regs const omap4_ctrl; +extern struct omap_sys_ctrl_regs const omap5_ctrl; +extern struct omap_sys_ctrl_regs const dra7xx_ctrl; + +void hw_data_init(void); + +const struct dpll_params *get_mpu_dpll_params(struct dplls const *); +const struct dpll_params *get_core_dpll_params(struct dplls const *); +const struct dpll_params *get_per_dpll_params(struct dplls const *); +const struct dpll_params *get_iva_dpll_params(struct dplls const *); +const struct dpll_params *get_usb_dpll_params(struct dplls const *); +const struct dpll_params *get_abe_dpll_params(struct dplls const *); + +void do_enable_clocks(u32 const *clk_domains, + u32 const *clk_modules_hw_auto, + u32 const *clk_modules_explicit_en, + u8 wait_for_enable); + +void setup_post_dividers(u32 const base, + const struct dpll_params *params); +u32 omap_ddr_clk(void); +u32 get_sys_clk_index(void); +void enable_basic_clocks(void); +void enable_basic_uboot_clocks(void); +void enable_non_essential_clocks(void); +void scale_vcores(struct vcores_data const *); +u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); +void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); + /* Max value for DPLL multiplier M */ #define OMAP_DPLL_MAX_N 127 @@ -60,4 +578,9 @@ static inline u32 omap_revision(void) #define OMAP5430_SILICON_ID_INVALID 0 #define OMAP5430_ES1_0 0x54300100 #define OMAP5432_ES1_0 0x54320100 +#define OMAP5430_ES2_0 0x54300200 +#define OMAP5432_ES2_0 0x54320200 + +/* DRA7XX */ +#define DRA752_ES1_0 0x07520100 #endif /* _OMAP_COMMON_H_ */ diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h new file mode 100644 index 000000000..617e22fa5 --- /dev/null +++ b/arch/arm/include/asm/omap_mmc.h @@ -0,0 +1,168 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef OMAP_MMC_H_ +#define OMAP_MMC_H_ + +struct hsmmc { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned int sysstatus; /* 0x14 */ + unsigned char res2[0x14]; + unsigned int con; /* 0x2C */ + unsigned char res3[0xD4]; + unsigned int blk; /* 0x104 */ + unsigned int arg; /* 0x108 */ + unsigned int cmd; /* 0x10C */ + unsigned int rsp10; /* 0x110 */ + unsigned int rsp32; /* 0x114 */ + unsigned int rsp54; /* 0x118 */ + unsigned int rsp76; /* 0x11C */ + unsigned int data; /* 0x120 */ + unsigned int pstate; /* 0x124 */ + unsigned int hctl; /* 0x128 */ + unsigned int sysctl; /* 0x12C */ + unsigned int stat; /* 0x130 */ + unsigned int ie; /* 0x134 */ + unsigned char res4[0x8]; + unsigned int capa; /* 0x140 */ +}; + +/* + * OMAP HS MMC Bit definitions + */ +#define MMC_SOFTRESET (0x1 << 1) +#define RESETDONE (0x1 << 0) +#define NOOPENDRAIN (0x0 << 0) +#define OPENDRAIN (0x1 << 0) +#define OD (0x1 << 0) +#define INIT_NOINIT (0x0 << 1) +#define INIT_INITSTREAM (0x1 << 1) +#define HR_NOHOSTRESP (0x0 << 2) +#define STR_BLOCK (0x0 << 3) +#define MODE_FUNC (0x0 << 4) +#define DW8_1_4BITMODE (0x0 << 5) +#define MIT_CTO (0x0 << 6) +#define CDP_ACTIVEHIGH (0x0 << 7) +#define WPP_ACTIVEHIGH (0x0 << 8) +#define RESERVED_MASK (0x3 << 9) +#define CTPL_MMC_SD (0x0 << 11) +#define BLEN_512BYTESLEN (0x200 << 0) +#define NBLK_STPCNT (0x0 << 16) +#define DE_DISABLE (0x0 << 0) +#define BCE_DISABLE (0x0 << 1) +#define BCE_ENABLE (0x1 << 1) +#define ACEN_DISABLE (0x0 << 2) +#define DDIR_OFFSET (4) +#define DDIR_MASK (0x1 << 4) +#define DDIR_WRITE (0x0 << 4) +#define DDIR_READ (0x1 << 4) +#define MSBS_SGLEBLK (0x0 << 5) +#define MSBS_MULTIBLK (0x1 << 5) +#define RSP_TYPE_OFFSET (16) +#define RSP_TYPE_MASK (0x3 << 16) +#define RSP_TYPE_NORSP (0x0 << 16) +#define RSP_TYPE_LGHT136 (0x1 << 16) +#define RSP_TYPE_LGHT48 (0x2 << 16) +#define RSP_TYPE_LGHT48B (0x3 << 16) +#define CCCE_NOCHECK (0x0 << 19) +#define CCCE_CHECK (0x1 << 19) +#define CICE_NOCHECK (0x0 << 20) +#define CICE_CHECK (0x1 << 20) +#define DP_OFFSET (21) +#define DP_MASK (0x1 << 21) +#define DP_NO_DATA (0x0 << 21) +#define DP_DATA (0x1 << 21) +#define CMD_TYPE_NORMAL (0x0 << 22) +#define INDEX_OFFSET (24) +#define INDEX_MASK (0x3f << 24) +#define INDEX(i) (i << 24) +#define DATI_MASK (0x1 << 1) +#define CMDI_MASK (0x1 << 0) +#define DTW_1_BITMODE (0x0 << 1) +#define DTW_4_BITMODE (0x1 << 1) +#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ +#define SDBP_PWROFF (0x0 << 8) +#define SDBP_PWRON (0x1 << 8) +#define SDVS_1V8 (0x5 << 9) +#define SDVS_3V0 (0x6 << 9) +#define ICE_MASK (0x1 << 0) +#define ICE_STOP (0x0 << 0) +#define ICS_MASK (0x1 << 1) +#define ICS_NOTREADY (0x0 << 1) +#define ICE_OSCILLATE (0x1 << 0) +#define CEN_MASK (0x1 << 2) +#define CEN_DISABLE (0x0 << 2) +#define CEN_ENABLE (0x1 << 2) +#define CLKD_OFFSET (6) +#define CLKD_MASK (0x3FF << 6) +#define DTO_MASK (0xF << 16) +#define DTO_15THDTO (0xE << 16) +#define SOFTRESETALL (0x1 << 24) +#define CC_MASK (0x1 << 0) +#define TC_MASK (0x1 << 1) +#define BWR_MASK (0x1 << 4) +#define BRR_MASK (0x1 << 5) +#define ERRI_MASK (0x1 << 15) +#define IE_CC (0x01 << 0) +#define IE_TC (0x01 << 1) +#define IE_BWR (0x01 << 4) +#define IE_BRR (0x01 << 5) +#define IE_CTO (0x01 << 16) +#define IE_CCRC (0x01 << 17) +#define IE_CEB (0x01 << 18) +#define IE_CIE (0x01 << 19) +#define IE_DTO (0x01 << 20) +#define IE_DCRC (0x01 << 21) +#define IE_DEB (0x01 << 22) +#define IE_CERR (0x01 << 28) +#define IE_BADA (0x01 << 29) + +#define VS30_3V0SUP (1 << 25) +#define VS18_1V8SUP (1 << 26) + +/* Driver definitions */ +#define MMCSD_SECTOR_SIZE 512 +#define MMC_CARD 0 +#define SD_CARD 1 +#define BYTE_MODE 0 +#define SECTOR_MODE 1 +#define CLK_INITSEQ 0 +#define CLK_400KHZ 1 +#define CLK_MISC 2 + +#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) +#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) + +/* Clock Configurations and Macros */ +#define MMC_CLOCK_REFERENCE 96 /* MHz */ + +#define mmc_reg_out(addr, mask, val)\ + writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) + +int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, + int wp_gpio); + + +#endif /* OMAP_MMC_H_ */ |