diff options
Diffstat (limited to 'arch/arm/include/asm')
49 files changed, 8707 insertions, 1201 deletions
diff --git a/arch/arm/include/asm/arch-davinci/aintc_defs.h b/arch/arm/include/asm/arch-davinci/aintc_defs.h index 8f3705320..38f814c01 100644 --- a/arch/arm/include/asm/arch-davinci/aintc_defs.h +++ b/arch/arm/include/asm/arch-davinci/aintc_defs.h @@ -47,4 +47,6 @@ struct dv_aintc_regs { #define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE) +#define DV_AINTC_INTCTL_IDMODE (1 << 2) + #endif /* _DV_AINTC_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-davinci/am1808_lowlevel.h b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h index 0bc7f76f1..e489c4747 100644 --- a/arch/arm/include/asm/arch-davinci/am1808_lowlevel.h +++ b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h @@ -1,5 +1,5 @@ /* - * SoC-specific lowlevel code for AM1808 and similar chips + * SoC-specific lowlevel code for DA850 * * Copyright (C) 2011 * Heiko Schocher, DENX Software Engineering, hs@denx.de. @@ -21,24 +21,24 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -#ifndef __AM1808_LOWLEVEL_H -#define __AM1808_LOWLEVEL_H +#ifndef __DA850_LOWLEVEL_H +#define __DA850_LOWLEVEL_H /* NOR Boot Configuration Word Field Descriptions */ -#define AM1808_NORBOOT_COPY_XK(X) ((X - 1) << 8) -#define AM1808_NORBOOT_METHOD_DIRECT (1 << 4) -#define AM1808_NORBOOT_16BIT (1 << 0) +#define DA850_NORBOOT_COPY_XK(X) ((X - 1) << 8) +#define DA850_NORBOOT_METHOD_DIRECT (1 << 4) +#define DA850_NORBOOT_16BIT (1 << 0) #define dv_maskbits(addr, val) \ writel((readl(addr) & val), addr) -void am1808_waitloop(unsigned long loopcnt); -int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult); -void am1808_lpc_transition(unsigned char pscnum, unsigned char module, +void da850_waitloop(unsigned long loopcnt); +int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult); +void da850_lpc_transition(unsigned char pscnum, unsigned char module, unsigned char domain, unsigned char state); -int am1808_ddr_setup(unsigned int freq); -void am1808_psc_init(void); -void am1808_pinmux_ctl(unsigned long offset, unsigned long mask, +int da850_ddr_setup(void); +void da850_psc_init(void); +void da850_pinmux_ctl(unsigned long offset, unsigned long mask, unsigned long value); -#endif /* #ifndef __AM1808_LOWLEVEL_H */ +#endif /* #ifndef __DA850_LOWLEVEL_H */ diff --git a/arch/arm/include/asm/arch-davinci/ddr2_defs.h b/arch/arm/include/asm/arch-davinci/ddr2_defs.h index 1b9430ce6..4f943b81b 100644 --- a/arch/arm/include/asm/arch-davinci/ddr2_defs.h +++ b/arch/arm/include/asm/arch-davinci/ddr2_defs.h @@ -63,6 +63,7 @@ struct dv_ddr2_regs_ctrl { #define DV_DDR_SDTMR2_RASMAX_SHIFT 27 #define DV_DDR_SDTMR2_XP_SHIFT 25 +#define DV_DDR_SDTMR2_ODT_SHIFT 23 #define DV_DDR_SDTMR2_XSNR_SHIFT 16 #define DV_DDR_SDTMR2_XSRD_SHIFT 8 #define DV_DDR_SDTMR2_RTP_SHIFT 5 @@ -84,6 +85,9 @@ struct dv_ddr2_regs_ctrl { #define DV_DDR_SDCR_IBANK_SHIFT 4 #define DV_DDR_SDCR_PAGESIZE_SHIFT 0 +#define DV_DDR_SDRCR_LPMODEN (1 << 31) +#define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30) + #define DV_DDR_SRCR_LPMODEN_SHIFT 31 #define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30 diff --git a/arch/arm/include/asm/arch-davinci/emif_defs.h b/arch/arm/include/asm/arch-davinci/emif_defs.h index b48ec17e9..b9e78a5db 100644 --- a/arch/arm/include/asm/arch-davinci/emif_defs.h +++ b/arch/arm/include/asm/arch-davinci/emif_defs.h @@ -70,6 +70,7 @@ struct davinci_emif_regs { #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) #define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) #define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) +#define DAVINCI_NANDFCR_CS2NAND (1 << 0) /* Chip Select setup */ #define DAVINCI_ABCR_STROBE_SELECT (1 << 31) diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index bea14993e..3e9a3b6de 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -230,6 +230,9 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_LPSC_CFG5 38 #define DAVINCI_LPSC_GEM 39 #define DAVINCI_LPSC_IMCOP 40 +#define DAVINCI_LPSC_VPSSMASTER 47 +#define DAVINCI_LPSC_MJCP 50 +#define DAVINCI_LPSC_HDVICP 51 #define DAVINCI_DM646X_LPSC_EMAC 14 #define DAVINCI_DM646X_LPSC_UART0 26 @@ -385,6 +388,20 @@ struct davinci_psc_regs { #define PINMUX3 0x01c4000c #define PINMUX4 0x01c40010 +struct davinci_uart_ctrl_regs { + dv_reg revid1; + dv_reg res; + dv_reg pwremu_mgmt; + dv_reg mdr; +}; + +#define DAVINCI_UART_CTRL_BASE 0x28 + +/* UART PWREMU_MGMT definitions */ +#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0) +#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13) +#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14) + #else /* CONFIG_SOC_DA8XX */ struct davinci_pllc_regs { @@ -431,6 +448,7 @@ struct davinci_pllc_regs { enum davinci_clk_ids { DAVINCI_SPI0_CLKID = 2, DAVINCI_UART2_CLKID = 2, + DAVINCI_MMC_CLKID = 2, DAVINCI_MDIO_CLKID = 4, DAVINCI_ARM_CLKID = 6, DAVINCI_PLLM_CLKID = 0xff, @@ -468,6 +486,7 @@ struct davinci_syscfg_regs { #define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21) #define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22) #define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18) +#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20) #define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27) struct davinci_syscfg1_regs { @@ -491,6 +510,9 @@ struct davinci_syscfg1_regs { #define VTP_READY (1 << 15) #define VTP_IOPWRDWN (1 << 14) +#define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13 +#define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0 + /* Interrupt controller */ struct davinci_aintc_regs { dv_reg revid; diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h index 5c309533a..f1396e319 100644 --- a/arch/arm/include/asm/arch-davinci/pll_defs.h +++ b/arch/arm/include/asm/arch-davinci/pll_defs.h @@ -57,11 +57,24 @@ struct dv_pll_regs { unsigned int plldiv9; /* 0x174 */ }; +#define PLL_MASTER_LOCK (1 << 4) + +#define PLLCTL_CLOCK_MODE_SHIFT 8 #define PLLCTL_PLLEN (1 << 0) #define PLLCTL_PLLPWRDN (1 << 1) #define PLLCTL_PLLRST (1 << 3) +#define PLLCTL_PLLDIS (1 << 4) #define PLLCTL_PLLENSRC (1 << 5) #define PLLCTL_RES_9 (1 << 8) +#define PLLCTL_EXTCLKSRC (1 << 9) + +#define PLL_POSTDEN (1 << 15) + +#define PLL_SCSCFG3_DIV45PENA (1 << 2) +#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1) + +#define PLL_RSTYPE_POR (1 << 0) +#define PLL_RSTYPE_XWRST (1 << 1) #define PLLSECCTL_TINITZ (1 << 16) #define PLLSECCTL_TENABLE (1 << 17) @@ -69,6 +82,7 @@ struct dv_pll_regs { #define PLLSECCTL_STOPMODE (1 << 22) #define PLLCMD_GOSET (1 << 0) +#define PLLCMD_GOSTAT (1 << 0) #define PLL0_LOCK 0x07000000 #define PLL1_LOCK 0x07000000 diff --git a/arch/arm/include/asm/arch-mx28/clock.h b/arch/arm/include/asm/arch-mx28/clock.h new file mode 100644 index 000000000..1700fe391 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/clock.h @@ -0,0 +1,61 @@ +/* + * Freescale i.MX28 Clock + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __CLOCK_H__ +#define __CLOCK_H__ + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_EMI_CLK, + MXC_GPMI_CLK, + MXC_IO0_CLK, + MXC_IO1_CLK, + MXC_SSP0_CLK, + MXC_SSP1_CLK, + MXC_SSP2_CLK, + MXC_SSP3_CLK, +}; + +enum mxs_ioclock { + MXC_IOCLK0 = 0, + MXC_IOCLK1, +}; + +enum mxs_sspclock { + MXC_SSPCLK0 = 0, + MXC_SSPCLK1, + MXC_SSPCLK2, + MXC_SSPCLK3, +}; + +uint32_t mxc_get_clock(enum mxc_clock clk); + +void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq); +void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal); +void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq); + +/* Compatibility with the FEC Ethernet driver */ +#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK) + +#endif /* __CLOCK_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/dma.h b/arch/arm/include/asm/arch-mx28/dma.h new file mode 100644 index 000000000..7061e7c2f --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/dma.h @@ -0,0 +1,170 @@ +/* + * Freescale i.MX28 APBH DMA + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __DMA_H__ +#define __DMA_H__ + +#include <linux/list.h> + +#ifndef CONFIG_ARCH_DMA_PIO_WORDS +#define DMA_PIO_WORDS 15 +#else +#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS +#endif + +#define MXS_DMA_ALIGNMENT 32 + +/* + * MXS DMA channels + */ +enum { + MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0, + MXS_DMA_CHANNEL_AHB_APBH_SSP1, + MXS_DMA_CHANNEL_AHB_APBH_SSP2, + MXS_DMA_CHANNEL_AHB_APBH_SSP3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + MXS_DMA_CHANNEL_AHB_APBH_GPMI1, + MXS_DMA_CHANNEL_AHB_APBH_GPMI2, + MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + MXS_DMA_CHANNEL_AHB_APBH_GPMI4, + MXS_DMA_CHANNEL_AHB_APBH_GPMI5, + MXS_DMA_CHANNEL_AHB_APBH_GPMI6, + MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + MXS_DMA_CHANNEL_AHB_APBH_SSP, + MXS_MAX_DMA_CHANNELS, +}; + +/* + * MXS DMA hardware command. + * + * This structure describes the in-memory layout of an entire DMA command, + * including space for the maximum number of PIO accesses. See the appropriate + * reference manual for a detailed description of what these fields mean to the + * DMA hardware. + */ +#define MXS_DMA_DESC_COMMAND_MASK 0x3 +#define MXS_DMA_DESC_COMMAND_OFFSET 0 +#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0 +#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1 +#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2 +#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3 +#define MXS_DMA_DESC_CHAIN (1 << 2) +#define MXS_DMA_DESC_IRQ (1 << 3) +#define MXS_DMA_DESC_NAND_LOCK (1 << 4) +#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5) +#define MXS_DMA_DESC_DEC_SEM (1 << 6) +#define MXS_DMA_DESC_WAIT4END (1 << 7) +#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8) +#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9) +#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12) +#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12 +#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16) +#define MXS_DMA_DESC_BYTES_OFFSET 16 + +struct mxs_dma_cmd { + unsigned long next; + unsigned long data; + union { + dma_addr_t address; + unsigned long alternate; + }; + unsigned long pio_words[DMA_PIO_WORDS]; +}; + +/* + * MXS DMA command descriptor. + * + * This structure incorporates an MXS DMA hardware command structure, along + * with metadata. + */ +#define MXS_DMA_DESC_FIRST (1 << 0) +#define MXS_DMA_DESC_LAST (1 << 1) +#define MXS_DMA_DESC_READY (1 << 31) + +struct mxs_dma_desc { + struct mxs_dma_cmd cmd; + unsigned int flags; + dma_addr_t address; + void *buffer; + struct list_head node; +}; + +/** + * MXS DMA channel + * + * This structure represents a single DMA channel. The MXS platform code + * maintains an array of these structures to represent every DMA channel in the + * system (see mxs_dma_channels). + */ +#define MXS_DMA_FLAGS_IDLE 0 +#define MXS_DMA_FLAGS_BUSY (1 << 0) +#define MXS_DMA_FLAGS_FREE 0 +#define MXS_DMA_FLAGS_ALLOCATED (1 << 16) +#define MXS_DMA_FLAGS_VALID (1 << 31) + +struct mxs_dma_chan { + const char *name; + unsigned long dev; + struct mxs_dma_device *dma; + unsigned int flags; + unsigned int active_num; + unsigned int pending_num; + struct list_head active; + struct list_head done; +}; + +/* Hardware management ops */ +int mxs_dma_enable(int channel); +int mxs_dma_disable(int channel); +int mxs_dma_reset(int channel); +int mxs_dma_freeze(int channel); +int mxs_dma_unfreeze(int channel); +int mxs_dma_read_semaphore(int channel); +int mxs_dma_enable_irq(int channel, int enable); +int mxs_dma_irq_is_pending(int channel); +int mxs_dma_ack_irq(int channel); + +/* Channel management ops */ +int mxs_dma_request(int channel); +int mxs_dma_release(int channel); + +/* Descriptor management ops */ +struct mxs_dma_desc *mxs_dma_desc_alloc(void); +void mxs_dma_desc_free(struct mxs_dma_desc *); + +unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc); +int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc); + +int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); + +int mxs_dma_get_finished(int channel, struct list_head *head); +int mxs_dma_finish(int channel, struct list_head *head); + +int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan); +int mxs_dma_go(int chan); + +int mxs_dma_init(void); + +#endif /* __DMA_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/gpio.h b/arch/arm/include/asm/arch-mx28/gpio.h new file mode 100644 index 000000000..be1c944eb --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/gpio.h @@ -0,0 +1,32 @@ +/* + * Freescale i.MX28 GPIO + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_GPIO_H__ +#define __MX28_GPIO_H__ + +#ifdef CONFIG_MXS_GPIO +void mxs_gpio_init(void); +#else +inline void mxs_gpio_init(void) {} +#endif + +#endif /* __MX28_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/imx-regs.h b/arch/arm/include/asm/arch-mx28/imx-regs.h new file mode 100644 index 000000000..9561b5e48 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/imx-regs.h @@ -0,0 +1,39 @@ +/* + * Freescale i.MX28 Registers + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __IMX_REGS_H__ +#define __IMX_REGS_H__ + +#include <asm/arch/regs-apbh.h> +#include <asm/arch/regs-base.h> +#include <asm/arch/regs-bch.h> +#include <asm/arch/regs-clkctrl.h> +#include <asm/arch/regs-gpmi.h> +#include <asm/arch/regs-i2c.h> +#include <asm/arch/regs-ocotp.h> +#include <asm/arch/regs-pinctrl.h> +#include <asm/arch/regs-power.h> +#include <asm/arch/regs-rtc.h> +#include <asm/arch/regs-ssp.h> +#include <asm/arch/regs-timrot.h> + +#endif /* __IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/iomux-mx28.h b/arch/arm/include/asm/arch-mx28/iomux-mx28.h new file mode 100644 index 000000000..b42820de7 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/iomux-mx28.h @@ -0,0 +1,537 @@ +/* + * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MACH_IOMUX_MX28_H__ +#define __MACH_IOMUX_MX28_H__ + +#include <asm/arch/iomux.h> + +/* + * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode> + * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> + * See also iomux.h + * + * BANK PIN MUX + */ +/* MUXSEL_0 */ +#define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) +#define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) + +#define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) +#define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) +#define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) +#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) +#define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) +#define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) +#define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) +#define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) +#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) +#define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0) + +#define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) +#define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) +#define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) +#define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) +#define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) + +#define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) +#define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) +#define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) +#define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) +#define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) +#define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) +#define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) +#define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) +#define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) +#define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0) +#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0) +#define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0) +#define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0) +#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0) +#define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0) +#define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0) +#define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0) +#define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0) + +#define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0) +#define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0) +#define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0) +#define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0) + +#define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0) +#define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0) +#define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0) +#define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0) +#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0) + +#define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0) +#define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0) +#define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0) +#define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0) +#define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0) +#define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0) +#define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0) +#define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0) + +/* MUXSEL_1 */ +#define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) +#define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) + +#define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) +#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) +#define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) +#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) +#define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) +#define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) +#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) +#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) +#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) + +#define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) +#define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1) +#define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1) +#define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1) +#define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1) +#define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1) +#define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1) + +#define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1) +#define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1) +#define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1) +#define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1) +#define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1) +#define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1) +#define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1) +#define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1) +#define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1) +#define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1) +#define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1) +#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1) +#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1) +#define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1) +#define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1) + +#define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1) +#define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1) + +/* MUXSEL_2 */ +#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) +#define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) + +#define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2) +#define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2) +#define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2) +#define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2) +#define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) +#define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) + +#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2) +#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2) +#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2) +#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2) +#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2) +#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2) + +#define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2) +#define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2) +#define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2) +#define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2) +#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2) +#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2) +#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2) +#define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2) +#define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2) +#define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2) +#define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2) +#define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2) +#define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2) +#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2) +#define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2) + +#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2) +#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2) + +/* MUXSEL_GPIO */ +#define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) +#define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) + +#define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO) + +#define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) + +#define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO) +#define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO) +#define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO) +#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO) +#define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO) +#define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO) +#define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO) + +#define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO) +#define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO) +#define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO) + +#endif /* __MACH_IOMUX_MX28_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/iomux.h b/arch/arm/include/asm/arch-mx28/iomux.h new file mode 100644 index 000000000..7abdf58b8 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/iomux.h @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * <armlinux@phytec.de> + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_MXS_IOMUX_H__ +#define __MACH_MXS_IOMUX_H__ + +/* + * IOMUX/PAD Bit field definitions + * + * PAD_BANK: 0..2 (3) + * PAD_PIN: 3..7 (5) + * PAD_MUXSEL: 8..9 (2) + * PAD_MA: 10..11 (2) + * PAD_MA_VALID: 12 (1) + * PAD_VOL: 13 (1) + * PAD_VOL_VALID: 14 (1) + * PAD_PULL: 15 (1) + * PAD_PULL_VALID: 16 (1) + * RESERVED: 17..31 (15) + */ +typedef u32 iomux_cfg_t; + +#define MXS_PAD_BANK_SHIFT 0 +#define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT) +#define MXS_PAD_PIN_SHIFT 3 +#define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT) +#define MXS_PAD_MUXSEL_SHIFT 8 +#define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT) +#define MXS_PAD_MA_SHIFT 10 +#define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT) +#define MXS_PAD_MA_VALID_SHIFT 12 +#define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT) +#define MXS_PAD_VOL_SHIFT 13 +#define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT) +#define MXS_PAD_VOL_VALID_SHIFT 14 +#define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT) +#define MXS_PAD_PULL_SHIFT 15 +#define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT) +#define MXS_PAD_PULL_VALID_SHIFT 16 +#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT) + +#define PAD_MUXSEL_0 0 +#define PAD_MUXSEL_1 1 +#define PAD_MUXSEL_2 2 +#define PAD_MUXSEL_GPIO 3 + +#define PAD_4MA 0 +#define PAD_8MA 1 +#define PAD_12MA 2 +#define PAD_16MA 3 + +#define PAD_1V8 0 +#define PAD_3V3 1 + +#define PAD_NOPULL 0 +#define PAD_PULLUP 1 + +#define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) +#define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) +#define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) +#define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \ + MXS_PAD_MA_VALID_MASK) + +#define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \ + MXS_PAD_VOL_VALID_MASK) +#define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \ + MXS_PAD_VOL_VALID_MASK) + +#define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \ + MXS_PAD_PULL_VALID_MASK) +#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ + MXS_PAD_PULL_VALID_MASK) + +/* generic pad control used in most cases */ +#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL) + +#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ + (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ + ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ + ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \ + ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \ + ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \ + ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT)) + +/* + * A pad becomes naked, when none of mA, vol or pull + * validity bits is set. + */ +#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \ + MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0) + +static inline unsigned int PAD_BANK(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT; +} + +static inline unsigned int PAD_PIN(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT; +} + +static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT; +} + +static inline unsigned int PAD_MA(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT; +} + +static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT; +} + +static inline unsigned int PAD_VOL(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT; +} + +static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT; +} + +static inline unsigned int PAD_PULL(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT; +} + +static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad) +{ + return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT; +} + +/* + * configures a single pad in the iomuxer + */ +int mxs_iomux_setup_pad(iomux_cfg_t pad); + +/* + * configures multiple pads + * convenient way to call the above function with tables + */ +int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); + +#endif /* __MACH_MXS_IOMUX_H__*/ diff --git a/arch/arm/include/asm/arch-mx28/regs-apbh.h b/arch/arm/include/asm/arch-mx28/regs-apbh.h new file mode 100644 index 000000000..a7fa1ec1c --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-apbh.h @@ -0,0 +1,466 @@ +/* + * Freescale i.MX28 APBH Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __REGS_APBH_H__ +#define __REGS_APBH_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_apbh_regs { + mx28_reg(hw_apbh_ctrl0) + mx28_reg(hw_apbh_ctrl1) + mx28_reg(hw_apbh_ctrl2) + mx28_reg(hw_apbh_channel_ctrl) + mx28_reg(hw_apbh_devsel) + mx28_reg(hw_apbh_dma_burst_size) + mx28_reg(hw_apbh_debug) + + uint32_t reserved[36]; + + union { + struct { + mx28_reg(hw_apbh_ch_curcmdar) + mx28_reg(hw_apbh_ch_nxtcmdar) + mx28_reg(hw_apbh_ch_cmd) + mx28_reg(hw_apbh_ch_bar) + mx28_reg(hw_apbh_ch_sema) + mx28_reg(hw_apbh_ch_debug1) + mx28_reg(hw_apbh_ch_debug2) + } ch[16]; + struct { + mx28_reg(hw_apbh_ch0_curcmdar) + mx28_reg(hw_apbh_ch0_nxtcmdar) + mx28_reg(hw_apbh_ch0_cmd) + mx28_reg(hw_apbh_ch0_bar) + mx28_reg(hw_apbh_ch0_sema) + mx28_reg(hw_apbh_ch0_debug1) + mx28_reg(hw_apbh_ch0_debug2) + mx28_reg(hw_apbh_ch1_curcmdar) + mx28_reg(hw_apbh_ch1_nxtcmdar) + mx28_reg(hw_apbh_ch1_cmd) + mx28_reg(hw_apbh_ch1_bar) + mx28_reg(hw_apbh_ch1_sema) + mx28_reg(hw_apbh_ch1_debug1) + mx28_reg(hw_apbh_ch1_debug2) + mx28_reg(hw_apbh_ch2_curcmdar) + mx28_reg(hw_apbh_ch2_nxtcmdar) + mx28_reg(hw_apbh_ch2_cmd) + mx28_reg(hw_apbh_ch2_bar) + mx28_reg(hw_apbh_ch2_sema) + mx28_reg(hw_apbh_ch2_debug1) + mx28_reg(hw_apbh_ch2_debug2) + mx28_reg(hw_apbh_ch3_curcmdar) + mx28_reg(hw_apbh_ch3_nxtcmdar) + mx28_reg(hw_apbh_ch3_cmd) + mx28_reg(hw_apbh_ch3_bar) + mx28_reg(hw_apbh_ch3_sema) + mx28_reg(hw_apbh_ch3_debug1) + mx28_reg(hw_apbh_ch3_debug2) + mx28_reg(hw_apbh_ch4_curcmdar) + mx28_reg(hw_apbh_ch4_nxtcmdar) + mx28_reg(hw_apbh_ch4_cmd) + mx28_reg(hw_apbh_ch4_bar) + mx28_reg(hw_apbh_ch4_sema) + mx28_reg(hw_apbh_ch4_debug1) + mx28_reg(hw_apbh_ch4_debug2) + mx28_reg(hw_apbh_ch5_curcmdar) + mx28_reg(hw_apbh_ch5_nxtcmdar) + mx28_reg(hw_apbh_ch5_cmd) + mx28_reg(hw_apbh_ch5_bar) + mx28_reg(hw_apbh_ch5_sema) + mx28_reg(hw_apbh_ch5_debug1) + mx28_reg(hw_apbh_ch5_debug2) + mx28_reg(hw_apbh_ch6_curcmdar) + mx28_reg(hw_apbh_ch6_nxtcmdar) + mx28_reg(hw_apbh_ch6_cmd) + mx28_reg(hw_apbh_ch6_bar) + mx28_reg(hw_apbh_ch6_sema) + mx28_reg(hw_apbh_ch6_debug1) + mx28_reg(hw_apbh_ch6_debug2) + mx28_reg(hw_apbh_ch7_curcmdar) + mx28_reg(hw_apbh_ch7_nxtcmdar) + mx28_reg(hw_apbh_ch7_cmd) + mx28_reg(hw_apbh_ch7_bar) + mx28_reg(hw_apbh_ch7_sema) + mx28_reg(hw_apbh_ch7_debug1) + mx28_reg(hw_apbh_ch7_debug2) + mx28_reg(hw_apbh_ch8_curcmdar) + mx28_reg(hw_apbh_ch8_nxtcmdar) + mx28_reg(hw_apbh_ch8_cmd) + mx28_reg(hw_apbh_ch8_bar) + mx28_reg(hw_apbh_ch8_sema) + mx28_reg(hw_apbh_ch8_debug1) + mx28_reg(hw_apbh_ch8_debug2) + mx28_reg(hw_apbh_ch9_curcmdar) + mx28_reg(hw_apbh_ch9_nxtcmdar) + mx28_reg(hw_apbh_ch9_cmd) + mx28_reg(hw_apbh_ch9_bar) + mx28_reg(hw_apbh_ch9_sema) + mx28_reg(hw_apbh_ch9_debug1) + mx28_reg(hw_apbh_ch9_debug2) + mx28_reg(hw_apbh_ch10_curcmdar) + mx28_reg(hw_apbh_ch10_nxtcmdar) + mx28_reg(hw_apbh_ch10_cmd) + mx28_reg(hw_apbh_ch10_bar) + mx28_reg(hw_apbh_ch10_sema) + mx28_reg(hw_apbh_ch10_debug1) + mx28_reg(hw_apbh_ch10_debug2) + mx28_reg(hw_apbh_ch11_curcmdar) + mx28_reg(hw_apbh_ch11_nxtcmdar) + mx28_reg(hw_apbh_ch11_cmd) + mx28_reg(hw_apbh_ch11_bar) + mx28_reg(hw_apbh_ch11_sema) + mx28_reg(hw_apbh_ch11_debug1) + mx28_reg(hw_apbh_ch11_debug2) + mx28_reg(hw_apbh_ch12_curcmdar) + mx28_reg(hw_apbh_ch12_nxtcmdar) + mx28_reg(hw_apbh_ch12_cmd) + mx28_reg(hw_apbh_ch12_bar) + mx28_reg(hw_apbh_ch12_sema) + mx28_reg(hw_apbh_ch12_debug1) + mx28_reg(hw_apbh_ch12_debug2) + mx28_reg(hw_apbh_ch13_curcmdar) + mx28_reg(hw_apbh_ch13_nxtcmdar) + mx28_reg(hw_apbh_ch13_cmd) + mx28_reg(hw_apbh_ch13_bar) + mx28_reg(hw_apbh_ch13_sema) + mx28_reg(hw_apbh_ch13_debug1) + mx28_reg(hw_apbh_ch13_debug2) + mx28_reg(hw_apbh_ch14_curcmdar) + mx28_reg(hw_apbh_ch14_nxtcmdar) + mx28_reg(hw_apbh_ch14_cmd) + mx28_reg(hw_apbh_ch14_bar) + mx28_reg(hw_apbh_ch14_sema) + mx28_reg(hw_apbh_ch14_debug1) + mx28_reg(hw_apbh_ch14_debug2) + mx28_reg(hw_apbh_ch15_curcmdar) + mx28_reg(hw_apbh_ch15_nxtcmdar) + mx28_reg(hw_apbh_ch15_cmd) + mx28_reg(hw_apbh_ch15_bar) + mx28_reg(hw_apbh_ch15_sema) + mx28_reg(hw_apbh_ch15_debug1) + mx28_reg(hw_apbh_ch15_debug2) + }; + }; + mx28_reg(hw_apbh_version) +}; +#endif + +#define APBH_CTRL0_SFTRST (1 << 31) +#define APBH_CTRL0_CLKGATE (1 << 30) +#define APBH_CTRL0_AHB_BURST8_EN (1 << 29) +#define APBH_CTRL0_APB_BURST_EN (1 << 28) +#define APBH_CTRL0_RSVD0_MASK (0xfff << 16) +#define APBH_CTRL0_RSVD0_OFFSET 16 +#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff +#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004 +#define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400 +#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 +#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 +#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 + +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16) +#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16 +#define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0) + +#define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31) +#define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30) +#define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29) +#define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28) +#define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27) +#define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26) +#define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25) +#define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24) +#define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23) +#define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22) +#define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21) +#define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20) +#define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19) +#define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18) +#define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17) +#define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16) +#define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15) +#define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14) +#define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13) +#define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12) +#define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11) +#define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10) +#define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9) +#define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8) +#define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7) +#define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6) +#define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5) +#define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4) +#define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3) +#define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2) +#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1) +#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0) + +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16) +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000 +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 + +#define APBH_DEVSEL_CH15_MASK (0x3 << 30) +#define APBH_DEVSEL_CH15_OFFSET 30 +#define APBH_DEVSEL_CH14_MASK (0x3 << 28) +#define APBH_DEVSEL_CH14_OFFSET 28 +#define APBH_DEVSEL_CH13_MASK (0x3 << 26) +#define APBH_DEVSEL_CH13_OFFSET 26 +#define APBH_DEVSEL_CH12_MASK (0x3 << 24) +#define APBH_DEVSEL_CH12_OFFSET 24 +#define APBH_DEVSEL_CH11_MASK (0x3 << 22) +#define APBH_DEVSEL_CH11_OFFSET 22 +#define APBH_DEVSEL_CH10_MASK (0x3 << 20) +#define APBH_DEVSEL_CH10_OFFSET 20 +#define APBH_DEVSEL_CH9_MASK (0x3 << 18) +#define APBH_DEVSEL_CH9_OFFSET 18 +#define APBH_DEVSEL_CH8_MASK (0x3 << 16) +#define APBH_DEVSEL_CH8_OFFSET 16 +#define APBH_DEVSEL_CH7_MASK (0x3 << 14) +#define APBH_DEVSEL_CH7_OFFSET 14 +#define APBH_DEVSEL_CH6_MASK (0x3 << 12) +#define APBH_DEVSEL_CH6_OFFSET 12 +#define APBH_DEVSEL_CH5_MASK (0x3 << 10) +#define APBH_DEVSEL_CH5_OFFSET 10 +#define APBH_DEVSEL_CH4_MASK (0x3 << 8) +#define APBH_DEVSEL_CH4_OFFSET 8 +#define APBH_DEVSEL_CH3_MASK (0x3 << 6) +#define APBH_DEVSEL_CH3_OFFSET 6 +#define APBH_DEVSEL_CH2_MASK (0x3 << 4) +#define APBH_DEVSEL_CH2_OFFSET 4 +#define APBH_DEVSEL_CH1_MASK (0x3 << 2) +#define APBH_DEVSEL_CH1_OFFSET 2 +#define APBH_DEVSEL_CH0_MASK (0x3 << 0) +#define APBH_DEVSEL_CH0_OFFSET 0 + +#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30) +#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30 +#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28) +#define APBH_DMA_BURST_SIZE_CH14_OFFSET 28 +#define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26) +#define APBH_DMA_BURST_SIZE_CH13_OFFSET 26 +#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24) +#define APBH_DMA_BURST_SIZE_CH12_OFFSET 24 +#define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22) +#define APBH_DMA_BURST_SIZE_CH11_OFFSET 22 +#define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20) +#define APBH_DMA_BURST_SIZE_CH10_OFFSET 20 +#define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18) +#define APBH_DMA_BURST_SIZE_CH9_OFFSET 18 +#define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16) +#define APBH_DMA_BURST_SIZE_CH8_OFFSET 16 +#define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16) +#define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16) +#define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16) +#define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14) +#define APBH_DMA_BURST_SIZE_CH7_OFFSET 14 +#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12) +#define APBH_DMA_BURST_SIZE_CH6_OFFSET 12 +#define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10) +#define APBH_DMA_BURST_SIZE_CH5_OFFSET 10 +#define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8) +#define APBH_DMA_BURST_SIZE_CH4_OFFSET 8 +#define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6) +#define APBH_DMA_BURST_SIZE_CH3_OFFSET 6 +#define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6) +#define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6) +#define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6) + +#define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4) +#define APBH_DMA_BURST_SIZE_CH2_OFFSET 4 +#define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4) +#define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4) +#define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4) +#define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2) +#define APBH_DMA_BURST_SIZE_CH1_OFFSET 2 +#define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2) +#define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2) +#define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2) + +#define APBH_DMA_BURST_SIZE_CH0_MASK 0x3 +#define APBH_DMA_BURST_SIZE_CH0_OFFSET 0 +#define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0 +#define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1 +#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2 + +#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0) + +#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff +#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0 + +#define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff +#define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0 + +#define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16) +#define APBH_CHn_CMD_XFER_COUNT_OFFSET 16 +#define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12) +#define APBH_CHn_CMD_CMDWORDS_OFFSET 12 +#define APBH_CHn_CMD_HALTONTERMINATE (1 << 8) +#define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7) +#define APBH_CHn_CMD_SEMAPHORE (1 << 6) +#define APBH_CHn_CMD_NANDWAIT4READY (1 << 5) +#define APBH_CHn_CMD_NANDLOCK (1 << 4) +#define APBH_CHn_CMD_IRQONCMPLT (1 << 3) +#define APBH_CHn_CMD_CHAIN (1 << 2) +#define APBH_CHn_CMD_COMMAND_MASK 0x3 +#define APBH_CHn_CMD_COMMAND_OFFSET 0 +#define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0 +#define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1 +#define APBH_CHn_CMD_COMMAND_DMA_READ 0x2 +#define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3 + +#define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff +#define APBH_CHn_BAR_ADDRESS_OFFSET 0 + +#define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24) +#define APBH_CHn_SEMA_RSVD2_OFFSET 24 +#define APBH_CHn_SEMA_PHORE_MASK (0xff << 16) +#define APBH_CHn_SEMA_PHORE_OFFSET 16 +#define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8) +#define APBH_CHn_SEMA_RSVD1_OFFSET 8 +#define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0) +#define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0 + +#define APBH_CHn_DEBUG1_REQ (1 << 31) +#define APBH_CHn_DEBUG1_BURST (1 << 30) +#define APBH_CHn_DEBUG1_KICK (1 << 29) +#define APBH_CHn_DEBUG1_END (1 << 28) +#define APBH_CHn_DEBUG1_SENSE (1 << 27) +#define APBH_CHn_DEBUG1_READY (1 << 26) +#define APBH_CHn_DEBUG1_LOCK (1 << 25) +#define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24) +#define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23) +#define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22) +#define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21) +#define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20) +#define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5) +#define APBH_CHn_DEBUG1_RSVD1_OFFSET 5 +#define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f +#define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0 +#define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03 +#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05 +#define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06 +#define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07 +#define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08 +#define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09 +#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c +#define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d +#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e +#define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f +#define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14 +#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15 +#define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c +#define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d +#define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e +#define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f + +#define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16) +#define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16 +#define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff +#define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0 + +#define APBH_VERSION_MAJOR_MASK (0xff << 24) +#define APBH_VERSION_MAJOR_OFFSET 24 +#define APBH_VERSION_MINOR_MASK (0xff << 16) +#define APBH_VERSION_MINOR_OFFSET 16 +#define APBH_VERSION_STEP_MASK 0xffff +#define APBH_VERSION_STEP_OFFSET 0 + +#endif /* __REGS_APBH_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-base.h b/arch/arm/include/asm/arch-mx28/regs-base.h new file mode 100644 index 000000000..dbdcc2b5b --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-base.h @@ -0,0 +1,88 @@ +/* + * Freescale i.MX28 Peripheral Base Addresses + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright (C) 2008 Embedded Alley Solutions Inc. + * + * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_BASE_H__ +#define __MX28_REGS_BASE_H__ + +/* + * Register base address + */ +#define MXS_ICOL_BASE 0x80000000 +#define MXS_HSADC_BASE 0x80002000 +#define MXS_APBH_BASE 0x80004000 +#define MXS_PERFMON_BASE 0x80006000 +#define MXS_BCH_BASE 0x8000A000 +#define MXS_GPMI_BASE 0x8000C000 +#define MXS_SSP0_BASE 0x80010000 +#define MXS_SSP1_BASE 0x80012000 +#define MXS_SSP2_BASE 0x80014000 +#define MXS_SSP3_BASE 0x80016000 +#define MXS_PINCTRL_BASE 0x80018000 +#define MXS_DIGCTL_BASE 0x8001C000 +#define MXS_ETM_BASE 0x80022000 +#define MXS_APBX_BASE 0x80024000 +#define MXS_DCP_BASE 0x80028000 +#define MXS_PXP_BASE 0x8002A000 +#define MXS_OCOTP_BASE 0x8002C000 +#define MXS_AXI_AHB0_BASE 0x8002E000 +#define MXS_LCDIF_BASE 0x80030000 +#define MXS_CAN0_BASE 0x80032000 +#define MXS_CAN1_BASE 0x80034000 +#define MXS_SIMDBG_BASE 0x8003C000 +#define MXS_SIMGPMISEL_BASE 0x8003C200 +#define MXS_SIMSSPSEL_BASE 0x8003C300 +#define MXS_SIMMEMSEL_BASE 0x8003C400 +#define MXS_GPIOMON_BASE 0x8003C500 +#define MXS_SIMENET_BASE 0x8003C700 +#define MXS_ARMJTAG_BASE 0x8003C800 +#define MXS_CLKCTRL_BASE 0x80040000 +#define MXS_SAIF0_BASE 0x80042000 +#define MXS_POWER_BASE 0x80044000 +#define MXS_SAIF1_BASE 0x80046000 +#define MXS_LRADC_BASE 0x80050000 +#define MXS_SPDIF_BASE 0x80054000 +#define MXS_RTC_BASE 0x80056000 +#define MXS_I2C0_BASE 0x80058000 +#define MXS_I2C1_BASE 0x8005A000 +#define MXS_PWM_BASE 0x80064000 +#define MXS_TIMROT_BASE 0x80068000 +#define MXS_UARTAPP0_BASE 0x8006A000 +#define MXS_UARTAPP1_BASE 0x8006C000 +#define MXS_UARTAPP2_BASE 0x8006E000 +#define MXS_UARTAPP3_BASE 0x80070000 +#define MXS_UARTAPP4_BASE 0x80072000 +#define MXS_UARTDBG_BASE 0x80074000 +#define MXS_USBPHY0_BASE 0x8007C000 +#define MXS_USBPHY1_BASE 0x8007E000 +#define MXS_USBCTRL0_BASE 0x80080000 +#define MXS_USBCTRL1_BASE 0x80090000 +#define MXS_DFLPT_BASE 0x800C0000 +#define MXS_DRAM_BASE 0x800E0000 +#define MXS_ENET0_BASE 0x800F0000 +#define MXS_ENET1_BASE 0x800F4000 + +#endif /* __MX28_REGS_BASE_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-bch.h b/arch/arm/include/asm/arch-mx28/regs-bch.h new file mode 100644 index 000000000..cac04709d --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-bch.h @@ -0,0 +1,230 @@ +/* + * Freescale i.MX28 BCH Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_BCH_H__ +#define __MX28_REGS_BCH_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_bch_regs { + mx28_reg(hw_bch_ctrl) + mx28_reg(hw_bch_status0) + mx28_reg(hw_bch_mode) + mx28_reg(hw_bch_encodeptr) + mx28_reg(hw_bch_dataptr) + mx28_reg(hw_bch_metaptr) + + uint32_t reserved[4]; + + mx28_reg(hw_bch_layoutselect) + mx28_reg(hw_bch_flash0layout0) + mx28_reg(hw_bch_flash0layout1) + mx28_reg(hw_bch_flash1layout0) + mx28_reg(hw_bch_flash1layout1) + mx28_reg(hw_bch_flash2layout0) + mx28_reg(hw_bch_flash2layout1) + mx28_reg(hw_bch_flash3layout0) + mx28_reg(hw_bch_flash3layout1) + mx28_reg(hw_bch_dbgkesread) + mx28_reg(hw_bch_dbgcsferead) + mx28_reg(hw_bch_dbgsyndegread) + mx28_reg(hw_bch_dbgahbmread) + mx28_reg(hw_bch_blockname) + mx28_reg(hw_bch_version) +}; +#endif + +#define BCH_CTRL_SFTRST (1 << 31) +#define BCH_CTRL_CLKGATE (1 << 30) +#define BCH_CTRL_DEBUGSYNDROME (1 << 22) +#define BCH_CTRL_M2M_LAYOUT_MASK (0x3 << 18) +#define BCH_CTRL_M2M_LAYOUT_OFFSET 18 +#define BCH_CTRL_M2M_ENCODE (1 << 17) +#define BCH_CTRL_M2M_ENABLE (1 << 16) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN (1 << 10) +#define BCH_CTRL_COMPLETE_IRQ_EN (1 << 8) +#define BCH_CTRL_BM_ERROR_IRQ (1 << 3) +#define BCH_CTRL_DEBUG_STALL_IRQ (1 << 2) +#define BCH_CTRL_COMPLETE_IRQ (1 << 0) + +#define BCH_STATUS0_HANDLE_MASK (0xfff << 20) +#define BCH_STATUS0_HANDLE_OFFSET 20 +#define BCH_STATUS0_COMPLETED_CE_MASK (0xf << 16) +#define BCH_STATUS0_COMPLETED_CE_OFFSET 16 +#define BCH_STATUS0_STATUS_BLK0_MASK (0xff << 8) +#define BCH_STATUS0_STATUS_BLK0_OFFSET 8 +#define BCH_STATUS0_STATUS_BLK0_ZERO (0x00 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR1 (0x01 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR2 (0x02 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR3 (0x03 << 8) +#define BCH_STATUS0_STATUS_BLK0_ERROR4 (0x04 << 8) +#define BCH_STATUS0_STATUS_BLK0_UNCORRECTABLE (0xfe << 8) +#define BCH_STATUS0_STATUS_BLK0_ERASED (0xff << 8) +#define BCH_STATUS0_ALLONES (1 << 4) +#define BCH_STATUS0_CORRECTED (1 << 3) +#define BCH_STATUS0_UNCORRECTABLE (1 << 2) + +#define BCH_MODE_ERASE_THRESHOLD_MASK 0xff +#define BCH_MODE_ERASE_THRESHOLD_OFFSET 0 + +#define BCH_ENCODEPTR_ADDR_MASK 0xffffffff +#define BCH_ENCODEPTR_ADDR_OFFSET 0 + +#define BCH_DATAPTR_ADDR_MASK 0xffffffff +#define BCH_DATAPTR_ADDR_OFFSET 0 + +#define BCH_METAPTR_ADDR_MASK 0xffffffff +#define BCH_METAPTR_ADDR_OFFSET 0 + +#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0x3 << 30) +#define BCH_LAYOUTSELECT_CS15_SELECT_OFFSET 30 +#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x3 << 28) +#define BCH_LAYOUTSELECT_CS14_SELECT_OFFSET 28 +#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0x3 << 26) +#define BCH_LAYOUTSELECT_CS13_SELECT_OFFSET 26 +#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3 << 24) +#define BCH_LAYOUTSELECT_CS12_SELECT_OFFSET 24 +#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0x3 << 22) +#define BCH_LAYOUTSELECT_CS11_SELECT_OFFSET 22 +#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x3 << 20) +#define BCH_LAYOUTSELECT_CS10_SELECT_OFFSET 20 +#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0x3 << 18) +#define BCH_LAYOUTSELECT_CS9_SELECT_OFFSET 18 +#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x3 << 16) +#define BCH_LAYOUTSELECT_CS8_SELECT_OFFSET 16 +#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0x3 << 14) +#define BCH_LAYOUTSELECT_CS7_SELECT_OFFSET 14 +#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3 << 12) +#define BCH_LAYOUTSELECT_CS6_SELECT_OFFSET 12 +#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0x3 << 10) +#define BCH_LAYOUTSELECT_CS5_SELECT_OFFSET 10 +#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x3 << 8) +#define BCH_LAYOUTSELECT_CS4_SELECT_OFFSET 8 +#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0x3 << 6) +#define BCH_LAYOUTSELECT_CS3_SELECT_OFFSET 6 +#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x3 << 4) +#define BCH_LAYOUTSELECT_CS2_SELECT_OFFSET 4 +#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0x3 << 2) +#define BCH_LAYOUTSELECT_CS1_SELECT_OFFSET 2 +#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3 << 0) +#define BCH_LAYOUTSELECT_CS0_SELECT_OFFSET 0 + +#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24) +#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 +#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) +#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 +#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12) +#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12 +#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC6 (0x3 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC8 (0x4 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC10 (0x5 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC12 (0x6 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC14 (0x7 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC16 (0x8 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC18 (0x9 << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC20 (0xa << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC22 (0xb << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC24 (0xc << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC26 (0xd << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC28 (0xe << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12) +#define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12) +#define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10) +#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff +#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0 + +#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) +#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 +#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12) +#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12 +#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC6 (0x3 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC8 (0x4 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC10 (0x5 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC12 (0x6 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC14 (0x7 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC16 (0x8 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC18 (0x9 << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC20 (0xa << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC22 (0xb << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC24 (0xc << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC26 (0xd << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC28 (0xe << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12) +#define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12) +#define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10) +#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff +#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0 + +#define BCH_DEBUG0_RSVD1_MASK (0x1f << 27) +#define BCH_DEBUG0_RSVD1_OFFSET 27 +#define BCH_DEBUG0_ROM_BIST_ENABLE (1 << 26) +#define BCH_DEBUG0_ROM_BIST_COMPLETE (1 << 25) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1ff << 16) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_OFFSET 16 +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_NORMAL (0x0 << 16) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_TEST_MODE (0x1 << 16) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND (1 << 15) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG (1 << 14) +#define BCH_DEBUG0_KES_DEBUG_MODE4K (1 << 13) +#define BCH_DEBUG0_KES_DEBUG_KICK (1 << 12) +#define BCH_DEBUG0_KES_STANDALONE (1 << 11) +#define BCH_DEBUG0_KES_DEBUG_STEP (1 << 10) +#define BCH_DEBUG0_KES_DEBUG_STALL (1 << 9) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS (1 << 8) +#define BCH_DEBUG0_RSVD0_MASK (0x3 << 6) +#define BCH_DEBUG0_RSVD0_OFFSET 6 +#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK 0x3f +#define BCH_DEBUG0_DEBUG_REG_SELECT_OFFSET 0 + +#define BCH_DBGKESREAD_VALUES_MASK 0xffffffff +#define BCH_DBGKESREAD_VALUES_OFFSET 0 + +#define BCH_DBGCSFEREAD_VALUES_MASK 0xffffffff +#define BCH_DBGCSFEREAD_VALUES_OFFSET 0 + +#define BCH_DBGSYNDGENREAD_VALUES_MASK 0xffffffff +#define BCH_DBGSYNDGENREAD_VALUES_OFFSET 0 + +#define BCH_DBGAHBMREAD_VALUES_MASK 0xffffffff +#define BCH_DBGAHBMREAD_VALUES_OFFSET 0 + +#define BCH_BLOCKNAME_NAME_MASK 0xffffffff +#define BCH_BLOCKNAME_NAME_OFFSET 0 + +#define BCH_VERSION_MAJOR_MASK (0xff << 24) +#define BCH_VERSION_MAJOR_OFFSET 24 +#define BCH_VERSION_MINOR_MASK (0xff << 16) +#define BCH_VERSION_MINOR_OFFSET 16 +#define BCH_VERSION_STEP_MASK 0xffff +#define BCH_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_BCH_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-clkctrl.h b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h new file mode 100644 index 000000000..93d0397ef --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-clkctrl.h @@ -0,0 +1,312 @@ +/* + * Freescale i.MX28 CLKCTRL Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_CLKCTRL_H__ +#define __MX28_REGS_CLKCTRL_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_clkctrl_regs { + mx28_reg(hw_clkctrl_pll0ctrl0) /* 0x00 */ + mx28_reg(hw_clkctrl_pll0ctrl1) /* 0x10 */ + mx28_reg(hw_clkctrl_pll1ctrl0) /* 0x20 */ + mx28_reg(hw_clkctrl_pll1ctrl1) /* 0x30 */ + mx28_reg(hw_clkctrl_pll2ctrl0) /* 0x40 */ + mx28_reg(hw_clkctrl_cpu) /* 0x50 */ + mx28_reg(hw_clkctrl_hbus) /* 0x60 */ + mx28_reg(hw_clkctrl_xbus) /* 0x70 */ + mx28_reg(hw_clkctrl_xtal) /* 0x80 */ + mx28_reg(hw_clkctrl_ssp0) /* 0x90 */ + mx28_reg(hw_clkctrl_ssp1) /* 0xa0 */ + mx28_reg(hw_clkctrl_ssp2) /* 0xb0 */ + mx28_reg(hw_clkctrl_ssp3) /* 0xc0 */ + mx28_reg(hw_clkctrl_gpmi) /* 0xd0 */ + mx28_reg(hw_clkctrl_spdif) /* 0xe0 */ + mx28_reg(hw_clkctrl_emi) /* 0xf0 */ + mx28_reg(hw_clkctrl_saif0) /* 0x100 */ + mx28_reg(hw_clkctrl_saif1) /* 0x110 */ + mx28_reg(hw_clkctrl_lcdif) /* 0x120 */ + mx28_reg(hw_clkctrl_etm) /* 0x130 */ + mx28_reg(hw_clkctrl_enet) /* 0x140 */ + mx28_reg(hw_clkctrl_hsadc) /* 0x150 */ + mx28_reg(hw_clkctrl_flexcan) /* 0x160 */ + + uint32_t reserved[16]; + + mx28_reg(hw_clkctrl_frac0) /* 0x1b0 */ + mx28_reg(hw_clkctrl_frac1) /* 0x1c0 */ + mx28_reg(hw_clkctrl_clkseq) /* 0x1d0 */ + mx28_reg(hw_clkctrl_reset) /* 0x1e0 */ + mx28_reg(hw_clkctrl_status) /* 0x1f0 */ + mx28_reg(hw_clkctrl_version) /* 0x200 */ +}; +#endif + +#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) +#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) +#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) +#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 +#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) +#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) +#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) +#define CLKCTRL_PLL0CTRL0_POWER (1 << 17) + +#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) +#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff +#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 + +#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) +#define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) +#define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24) +#define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20 +#define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20) +#define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) +#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18) +#define CLKCTRL_PLL1CTRL0_POWER (1 << 17) + +#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31) +#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30) +#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff +#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0 + +#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31) +#define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28) +#define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28 +#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26) +#define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24) +#define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24 +#define CLKCTRL_PLL2CTRL0_POWER (1 << 23) + +#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) +#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) +#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) +#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 +#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) +#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) +#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f +#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 + +#define CLKCTRL_HBUS_ASM_BUSY (1 << 31) +#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30) +#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29) +#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27) +#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) +#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) +#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) +#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) +#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) +#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) +#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20) +#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19) +#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 +#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) +#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) +#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) +#define CLKCTRL_HBUS_DIV_MASK 0x1f +#define CLKCTRL_HBUS_DIV_OFFSET 0 + +#define CLKCTRL_XBUS_BUSY (1 << 31) +#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11) +#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_XBUS_DIV_MASK 0x3ff +#define CLKCTRL_XBUS_DIV_OFFSET 0 + +#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) +#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) +#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) +#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 +#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 + +#define CLKCTRL_SSP_CLKGATE (1 << 31) +#define CLKCTRL_SSP_BUSY (1 << 29) +#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) +#define CLKCTRL_SSP_DIV_MASK 0x1ff +#define CLKCTRL_SSP_DIV_OFFSET 0 + +#define CLKCTRL_GPMI_CLKGATE (1 << 31) +#define CLKCTRL_GPMI_BUSY (1 << 29) +#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) +#define CLKCTRL_GPMI_DIV_MASK 0x3ff +#define CLKCTRL_GPMI_DIV_OFFSET 0 + +#define CLKCTRL_SPDIF_CLKGATE (1 << 31) + +#define CLKCTRL_EMI_CLKGATE (1 << 31) +#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) +#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) +#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) +#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) +#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) +#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) +#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) +#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) +#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 +#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f +#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 + +#define CLKCTRL_SAIF0_CLKGATE (1 << 31) +#define CLKCTRL_SAIF0_BUSY (1 << 29) +#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF0_DIV_MASK 0xffff +#define CLKCTRL_SAIF0_DIV_OFFSET 0 + +#define CLKCTRL_SAIF1_CLKGATE (1 << 31) +#define CLKCTRL_SAIF1_BUSY (1 << 29) +#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16) +#define CLKCTRL_SAIF1_DIV_MASK 0xffff +#define CLKCTRL_SAIF1_DIV_OFFSET 0 + +#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31) +#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) +#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13) +#define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff +#define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0 + +#define CLKCTRL_ETM_CLKGATE (1 << 31) +#define CLKCTRL_ETM_BUSY (1 << 29) +#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7) +#define CLKCTRL_ETM_DIV_MASK 0x7f +#define CLKCTRL_ETM_DIV_OFFSET 0 + +#define CLKCTRL_ENET_SLEEP (1 << 31) +#define CLKCTRL_ENET_DISABLE (1 << 30) +#define CLKCTRL_ENET_STATUS (1 << 29) +#define CLKCTRL_ENET_BUSY_TIME (1 << 27) +#define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21) +#define CLKCTRL_ENET_DIV_TIME_OFFSET 21 +#define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19) +#define CLKCTRL_ENET_TIME_SEL_OFFSET 19 +#define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19) +#define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19) +#define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19) +#define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19) +#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18) +#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17) +#define CLKCTRL_ENET_RESET_BY_SW (1 << 16) + +#define CLKCTRL_HSADC_RESETB (1 << 30) +#define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28) +#define CLKCTRL_HSADC_FREQDIV_OFFSET 28 + +#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30) +#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29) +#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28) +#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27) + +#define CLKCTRL_FRAC0_CLKGATEIO0 (1 << 31) +#define CLKCTRL_FRAC0_IO0_STABLE (1 << 30) +#define CLKCTRL_FRAC0_IO0FRAC_MASK (0x3f << 24) +#define CLKCTRL_FRAC0_IO0FRAC_OFFSET 24 +#define CLKCTRL_FRAC0_CLKGATEIO1 (1 << 23) +#define CLKCTRL_FRAC0_IO1_STABLE (1 << 22) +#define CLKCTRL_FRAC0_IO1FRAC_MASK (0x3f << 16) +#define CLKCTRL_FRAC0_IO1FRAC_OFFSET 16 +#define CLKCTRL_FRAC0_CLKGATEEMI (1 << 15) +#define CLKCTRL_FRAC0_EMI_STABLE (1 << 14) +#define CLKCTRL_FRAC0_EMIFRAC_MASK (0x3f << 8) +#define CLKCTRL_FRAC0_EMIFRAC_OFFSET 8 +#define CLKCTRL_FRAC0_CLKGATECPU (1 << 7) +#define CLKCTRL_FRAC0_CPU_STABLE (1 << 6) +#define CLKCTRL_FRAC0_CPUFRAC_MASK 0x3f +#define CLKCTRL_FRAC0_CPUFRAC_OFFSET 0 + +#define CLKCTRL_FRAC1_CLKGATEGPMI (1 << 23) +#define CLKCTRL_FRAC1_GPMI_STABLE (1 << 22) +#define CLKCTRL_FRAC1_GPMIFRAC_MASK (0x3f << 16) +#define CLKCTRL_FRAC1_GPMIFRAC_OFFSET 16 +#define CLKCTRL_FRAC1_CLKGATEHSADC (1 << 15) +#define CLKCTRL_FRAC1_HSADC_STABLE (1 << 14) +#define CLKCTRL_FRAC1_HSADCFRAC_MASK (0x3f << 8) +#define CLKCTRL_FRAC1_HSADCFRAC_OFFSET 8 +#define CLKCTRL_FRAC1_CLKGATEPIX (1 << 7) +#define CLKCTRL_FRAC1_PIX_STABLE (1 << 6) +#define CLKCTRL_FRAC1_PIXFRAC_MASK 0x3f +#define CLKCTRL_FRAC1_PIXFRAC_OFFSET 0 + +#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14) +#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) +#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7) +#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6) +#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5) +#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4) +#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3) +#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1) +#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0) + +#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5) +#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4) +#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3) +#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2) +#define CLKCTRL_RESET_CHIP (1 << 1) +#define CLKCTRL_RESET_DIG (1 << 0) + +#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) +#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 + +#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) +#define CLKCTRL_VERSION_MAJOR_OFFSET 24 +#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) +#define CLKCTRL_VERSION_MINOR_OFFSET 16 +#define CLKCTRL_VERSION_STEP_MASK 0xffff +#define CLKCTRL_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_CLKCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-common.h b/arch/arm/include/asm/arch-mx28/regs-common.h new file mode 100644 index 000000000..efe975b4b --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-common.h @@ -0,0 +1,66 @@ +/* + * Freescale i.MX28 Register Accessors + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_COMMON_H__ +#define __MX28_REGS_COMMON_H__ + +/* + * The i.MX28 has interesting feature when it comes to register access. There + * are four kinds of access to one particular register. Those are: + * + * 1) Common read/write access. To use this mode, just write to the address of + * the register. + * 2) Set bits only access. To set bits, write which bits you want to set to the + * address of the register + 0x4. + * 3) Clear bits only access. To clear bits, write which bits you want to clear + * to the address of the register + 0x8. + * 4) Toggle bits only access. To toggle bits, write which bits you want to + * toggle to the address of the register + 0xc. + * + * IMPORTANT NOTE: Not all registers support accesses 2-4! Also, not all bits + * can be set/cleared by pure write as in access type 1, some need to be + * explicitly set/cleared by using access type 2-3. + * + * The following macros and structures allow the user to either access the + * register in all aforementioned modes (by accessing reg_name, reg_name_set, + * reg_name_clr, reg_name_tog) or pass the register structure further into + * various functions with correct type information (by accessing reg_name_reg). + * + */ + +#define __mx28_reg(name) \ + uint32_t name; \ + uint32_t name##_set; \ + uint32_t name##_clr; \ + uint32_t name##_tog; + +struct mx28_register { + __mx28_reg(reg) +}; + +#define mx28_reg(name) \ + union { \ + struct { __mx28_reg(name) }; \ + struct mx28_register name##_reg; \ + }; + +#endif /* __MX28_REGS_COMMON_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-gpmi.h b/arch/arm/include/asm/arch-mx28/regs-gpmi.h new file mode 100644 index 000000000..00967938f --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-gpmi.h @@ -0,0 +1,222 @@ +/* + * Freescale i.MX28 GPMI Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_GPMI_H__ +#define __MX28_REGS_GPMI_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_gpmi_regs { + mx28_reg(hw_gpmi_ctrl0) + mx28_reg(hw_gpmi_compare) + mx28_reg(hw_gpmi_eccctrl) + mx28_reg(hw_gpmi_ecccount) + mx28_reg(hw_gpmi_payload) + mx28_reg(hw_gpmi_auxiliary) + mx28_reg(hw_gpmi_ctrl1) + mx28_reg(hw_gpmi_timing0) + mx28_reg(hw_gpmi_timing1) + + uint32_t reserved[4]; + + mx28_reg(hw_gpmi_data) + mx28_reg(hw_gpmi_stat) + mx28_reg(hw_gpmi_debug) + mx28_reg(hw_gpmi_version) +}; +#endif + +#define GPMI_CTRL0_SFTRST (1 << 31) +#define GPMI_CTRL0_CLKGATE (1 << 30) +#define GPMI_CTRL0_RUN (1 << 29) +#define GPMI_CTRL0_DEV_IRQ_EN (1 << 28) +#define GPMI_CTRL0_LOCK_CS (1 << 27) +#define GPMI_CTRL0_UDMA (1 << 26) +#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3 << 24) +#define GPMI_CTRL0_COMMAND_MODE_OFFSET 24 +#define GPMI_CTRL0_COMMAND_MODE_WRITE (0x0 << 24) +#define GPMI_CTRL0_COMMAND_MODE_READ (0x1 << 24) +#define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE (0x2 << 24) +#define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY (0x3 << 24) +#define GPMI_CTRL0_WORD_LENGTH (1 << 23) +#define GPMI_CTRL0_CS_MASK (0x7 << 20) +#define GPMI_CTRL0_CS_OFFSET 20 +#define GPMI_CTRL0_ADDRESS_MASK (0x7 << 17) +#define GPMI_CTRL0_ADDRESS_OFFSET 17 +#define GPMI_CTRL0_ADDRESS_NAND_DATA (0x0 << 17) +#define GPMI_CTRL0_ADDRESS_NAND_CLE (0x1 << 17) +#define GPMI_CTRL0_ADDRESS_NAND_ALE (0x2 << 17) +#define GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16) +#define GPMI_CTRL0_XFER_COUNT_MASK 0xffff +#define GPMI_CTRL0_XFER_COUNT_OFFSET 0 + +#define GPMI_COMPARE_MASK_MASK (0xffff << 16) +#define GPMI_COMPARE_MASK_OFFSET 16 +#define GPMI_COMPARE_REFERENCE_MASK 0xffff +#define GPMI_COMPARE_REFERENCE_OFFSET 0 + +#define GPMI_ECCCTRL_HANDLE_MASK (0xffff << 16) +#define GPMI_ECCCTRL_HANDLE_OFFSET 16 +#define GPMI_ECCCTRL_ECC_CMD_MASK (0x3 << 13) +#define GPMI_ECCCTRL_ECC_CMD_OFFSET 13 +#define GPMI_ECCCTRL_ECC_CMD_DECODE (0x0 << 13) +#define GPMI_ECCCTRL_ECC_CMD_ENCODE (0x1 << 13) +#define GPMI_ECCCTRL_ENABLE_ECC (1 << 12) +#define GPMI_ECCCTRL_BUFFER_MASK_MASK 0x1ff +#define GPMI_ECCCTRL_BUFFER_MASK_OFFSET 0 +#define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY 0x100 +#define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE 0x1ff + +#define GPMI_ECCCOUNT_COUNT_MASK 0xffff +#define GPMI_ECCCOUNT_COUNT_OFFSET 0 + +#define GPMI_PAYLOAD_ADDRESS_MASK (0x3fffffff << 2) +#define GPMI_PAYLOAD_ADDRESS_OFFSET 2 + +#define GPMI_AUXILIARY_ADDRESS_MASK (0x3fffffff << 2) +#define GPMI_AUXILIARY_ADDRESS_OFFSET 2 + +#define GPMI_CTRL1_DECOUPLE_CS (1 << 24) +#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22) +#define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22 +#define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20) +#define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19) +#define GPMI_CTRL1_BCH_MODE (1 << 18) +#define GPMI_CTRL1_DLL_ENABLE (1 << 17) +#define GPMI_CTRL1_HALF_PERIOD (1 << 16) +#define GPMI_CTRL1_RDN_DELAY_MASK (0xf << 12) +#define GPMI_CTRL1_RDN_DELAY_OFFSET 12 +#define GPMI_CTRL1_DMA2ECC_MODE (1 << 11) +#define GPMI_CTRL1_DEV_IRQ (1 << 10) +#define GPMI_CTRL1_TIMEOUT_IRQ (1 << 9) +#define GPMI_CTRL1_BURST_EN (1 << 8) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST (1 << 7) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x7 << 4) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET 4 +#define GPMI_CTRL1_DEV_RESET (1 << 3) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2) +#define GPMI_CTRL1_CAMERA_MODE (1 << 1) +#define GPMI_CTRL1_GPMI_MODE (1 << 0) + +#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16) +#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16 +#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8) +#define GPMI_TIMING0_DATA_HOLD_OFFSET 8 +#define GPMI_TIMING0_DATA_SETUP_MASK 0xff +#define GPMI_TIMING0_DATA_SETUP_OFFSET 0 + +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xffff << 16) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET 16 + +#define GPMI_TIMING2_UDMA_TRP_MASK (0xff << 24) +#define GPMI_TIMING2_UDMA_TRP_OFFSET 24 +#define GPMI_TIMING2_UDMA_ENV_MASK (0xff << 16) +#define GPMI_TIMING2_UDMA_ENV_OFFSET 16 +#define GPMI_TIMING2_UDMA_HOLD_MASK (0xff << 8) +#define GPMI_TIMING2_UDMA_HOLD_OFFSET 8 +#define GPMI_TIMING2_UDMA_SETUP_MASK 0xff +#define GPMI_TIMING2_UDMA_SETUP_OFFSET 0 + +#define GPMI_DATA_DATA_MASK 0xffffffff +#define GPMI_DATA_DATA_OFFSET 0 + +#define GPMI_STAT_READY_BUSY_MASK (0xff << 24) +#define GPMI_STAT_READY_BUSY_OFFSET 24 +#define GPMI_STAT_RDY_TIMEOUT_MASK (0xff << 16) +#define GPMI_STAT_RDY_TIMEOUT_OFFSET 16 +#define GPMI_STAT_DEV7_ERROR (1 << 15) +#define GPMI_STAT_DEV6_ERROR (1 << 14) +#define GPMI_STAT_DEV5_ERROR (1 << 13) +#define GPMI_STAT_DEV4_ERROR (1 << 12) +#define GPMI_STAT_DEV3_ERROR (1 << 11) +#define GPMI_STAT_DEV2_ERROR (1 << 10) +#define GPMI_STAT_DEV1_ERROR (1 << 9) +#define GPMI_STAT_DEV0_ERROR (1 << 8) +#define GPMI_STAT_ATA_IRQ (1 << 4) +#define GPMI_STAT_INVALID_BUFFER_MASK (1 << 3) +#define GPMI_STAT_FIFO_EMPTY (1 << 2) +#define GPMI_STAT_FIFO_FULL (1 << 1) +#define GPMI_STAT_PRESENT (1 << 0) + +#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xff << 24) +#define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET 24 +#define GPMI_DEBUG_DMA_SENSE_MASK (0xff << 16) +#define GPMI_DEBUG_DMA_SENSE_OFFSET 16 +#define GPMI_DEBUG_DMAREQ_MASK (0xff << 8) +#define GPMI_DEBUG_DMAREQ_OFFSET 8 +#define GPMI_DEBUG_CMD_END_MASK 0xff +#define GPMI_DEBUG_CMD_END_OFFSET 0 + +#define GPMI_VERSION_MAJOR_MASK (0xff << 24) +#define GPMI_VERSION_MAJOR_OFFSET 24 +#define GPMI_VERSION_MINOR_MASK (0xff << 16) +#define GPMI_VERSION_MINOR_OFFSET 16 +#define GPMI_VERSION_STEP_MASK 0xffff +#define GPMI_VERSION_STEP_OFFSET 0 + +#define GPMI_DEBUG2_UDMA_STATE_MASK (0xf << 24) +#define GPMI_DEBUG2_UDMA_STATE_OFFSET 24 +#define GPMI_DEBUG2_BUSY (1 << 23) +#define GPMI_DEBUG2_PIN_STATE_MASK (0x7 << 20) +#define GPMI_DEBUG2_PIN_STATE_OFFSET 20 +#define GPMI_DEBUG2_PIN_STATE_PSM_IDLE (0x0 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT (0x1 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_ADDR (0x2 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_STALL (0x3 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_STROBE (0x4 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY (0x5 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD (0x6 << 20) +#define GPMI_DEBUG2_PIN_STATE_PSM_DONE (0x7 << 20) +#define GPMI_DEBUG2_MAIN_STATE_MASK (0xf << 16) +#define GPMI_DEBUG2_MAIN_STATE_OFFSET 16 +#define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE (0x0 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT (0x1 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE (0x2 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR (0x3 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ (0x4 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK (0x5 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF (0x6 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO (0x7 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR (0x8 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP (0x9 << 16) +#define GPMI_DEBUG2_MAIN_STATE_MSM_DONE (0xa << 16) +#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xf << 12) +#define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET 12 +#define GPMI_DEBUG2_GPMI2SYND_VALID (1 << 11) +#define GPMI_DEBUG2_GPMI2SYND_READY (1 << 10) +#define GPMI_DEBUG2_SYND2GPMI_VALID (1 << 9) +#define GPMI_DEBUG2_SYND2GPMI_READY (1 << 8) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN (1 << 7) +#define GPMI_DEBUG2_UPDATE_WINDOW (1 << 6) +#define GPMI_DEBUG2_RDN_TAP_MASK 0x3f +#define GPMI_DEBUG2_RDN_TAP_OFFSET 0 + +#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xffff << 16) +#define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET 16 +#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK 0xffff +#define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET 0 + +#endif /* __MX28_REGS_GPMI_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-i2c.h b/arch/arm/include/asm/arch-mx28/regs-i2c.h new file mode 100644 index 000000000..30e0ed743 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-i2c.h @@ -0,0 +1,207 @@ +/* + * Freescale i.MX28 I2C Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_I2C_H__ +#define __MX28_REGS_I2C_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_i2c_regs { + mx28_reg(hw_i2c_ctrl0) + mx28_reg(hw_i2c_timing0) + mx28_reg(hw_i2c_timing1) + mx28_reg(hw_i2c_timing2) + mx28_reg(hw_i2c_ctrl1) + mx28_reg(hw_i2c_stat) + mx28_reg(hw_i2c_queuectrl) + mx28_reg(hw_i2c_queuestat) + mx28_reg(hw_i2c_queuecmd) + mx28_reg(hw_i2c_queuedata) + mx28_reg(hw_i2c_data) + mx28_reg(hw_i2c_debug0) + mx28_reg(hw_i2c_debug1) + mx28_reg(hw_i2c_version) +}; +#endif + +#define I2C_CTRL_SFTRST (1 << 31) +#define I2C_CTRL_CLKGATE (1 << 30) +#define I2C_CTRL_RUN (1 << 29) +#define I2C_CTRL_PREACK (1 << 27) +#define I2C_CTRL_ACKNOWLEDGE (1 << 26) +#define I2C_CTRL_SEND_NAK_ON_LAST (1 << 25) +#define I2C_CTRL_MULTI_MASTER (1 << 23) +#define I2C_CTRL_CLOCK_HELD (1 << 22) +#define I2C_CTRL_RETAIN_CLOCK (1 << 21) +#define I2C_CTRL_POST_SEND_STOP (1 << 20) +#define I2C_CTRL_PRE_SEND_START (1 << 19) +#define I2C_CTRL_SLAVE_ADDRESS_ENABLE (1 << 18) +#define I2C_CTRL_MASTER_MODE (1 << 17) +#define I2C_CTRL_DIRECTION (1 << 16) +#define I2C_CTRL_XFER_COUNT_MASK 0xffff +#define I2C_CTRL_XFER_COUNT_OFFSET 0 + +#define I2C_TIMING0_HIGH_COUNT_MASK (0x3ff << 16) +#define I2C_TIMING0_HIGH_COUNT_OFFSET 16 +#define I2C_TIMING0_RCV_COUNT_MASK 0x3ff +#define I2C_TIMING0_RCV_COUNT_OFFSET 0 + +#define I2C_TIMING1_LOW_COUNT_MASK (0x3ff << 16) +#define I2C_TIMING1_LOW_COUNT_OFFSET 16 +#define I2C_TIMING1_XMIT_COUNT_MASK 0x3ff +#define I2C_TIMING1_XMIT_COUNT_OFFSET 0 + +#define I2C_TIMING2_BUS_FREE_MASK (0x3ff << 16) +#define I2C_TIMING2_BUS_FREE_OFFSET 16 +#define I2C_TIMING2_LEADIN_COUNT_MASK 0x3ff +#define I2C_TIMING2_LEADIN_COUNT_OFFSET 0 + +#define I2C_CTRL1_RD_QUEUE_IRQ (1 << 30) +#define I2C_CTRL1_WR_QUEUE_IRQ (1 << 29) +#define I2C_CTRL1_CLR_GOT_A_NAK (1 << 28) +#define I2C_CTRL1_ACK_MODE (1 << 27) +#define I2C_CTRL1_FORCE_DATA_IDLE (1 << 26) +#define I2C_CTRL1_FORCE_CLK_IDLE (1 << 25) +#define I2C_CTRL1_BCAST_SLAVE_EN (1 << 24) +#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK (0xff << 16) +#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET 16 +#define I2C_CTRL1_BUS_FREE_IRQ_EN (1 << 15) +#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN (1 << 14) +#define I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN (1 << 13) +#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN (1 << 12) +#define I2C_CTRL1_EARLY_TERM_IRQ_EN (1 << 11) +#define I2C_CTRL1_MASTER_LOSS_IRQ_EN (1 << 10) +#define I2C_CTRL1_SLAVE_STOP_IRQ_EN (1 << 9) +#define I2C_CTRL1_SLAVE_IRQ_EN (1 << 8) +#define I2C_CTRL1_BUS_FREE_IRQ (1 << 7) +#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ (1 << 6) +#define I2C_CTRL1_NO_SLAVE_ACK_IRQ (1 << 5) +#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ (1 << 4) +#define I2C_CTRL1_EARLY_TERM_IRQ (1 << 3) +#define I2C_CTRL1_MASTER_LOSS_IRQ (1 << 2) +#define I2C_CTRL1_SLAVE_STOP_IRQ (1 << 1) +#define I2C_CTRL1_SLAVE_IRQ (1 << 0) + +#define I2C_STAT_MASTER_PRESENT (1 << 31) +#define I2C_STAT_SLAVE_PRESENT (1 << 30) +#define I2C_STAT_ANY_ENABLED_IRQ (1 << 29) +#define I2C_STAT_GOT_A_NAK (1 << 28) +#define I2C_STAT_RCVD_SLAVE_ADDR_MASK (0xff << 16) +#define I2C_STAT_RCVD_SLAVE_ADDR_OFFSET 16 +#define I2C_STAT_SLAVE_ADDR_EQ_ZERO (1 << 15) +#define I2C_STAT_SLAVE_FOUND (1 << 14) +#define I2C_STAT_SLAVE_SEARCHING (1 << 13) +#define I2C_STAT_DATA_ENGING_DMA_WAIT (1 << 12) +#define I2C_STAT_BUS_BUSY (1 << 11) +#define I2C_STAT_CLK_GEN_BUSY (1 << 10) +#define I2C_STAT_DATA_ENGINE_BUSY (1 << 9) +#define I2C_STAT_SLAVE_BUSY (1 << 8) +#define I2C_STAT_BUS_FREE_IRQ_SUMMARY (1 << 7) +#define I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY (1 << 6) +#define I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5) +#define I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4) +#define I2C_STAT_EARLY_TERM_IRQ_SUMMARY (1 << 3) +#define I2C_STAT_MASTER_LOSS_IRQ_SUMMARY (1 << 2) +#define I2C_STAT_SLAVE_STOP_IRQ_SUMMARY (1 << 1) +#define I2C_STAT_SLAVE_IRQ_SUMMARY (1 << 0) + +#define I2C_QUEUECTRL_RD_THRESH_MASK (0x1f << 16) +#define I2C_QUEUECTRL_RD_THRESH_OFFSET 16 +#define I2C_QUEUECTRL_WR_THRESH_MASK (0x1f << 8) +#define I2C_QUEUECTRL_WR_THRESH_OFFSET 8 +#define I2C_QUEUECTRL_QUEUE_RUN (1 << 5) +#define I2C_QUEUECTRL_RD_CLEAR (1 << 4) +#define I2C_QUEUECTRL_WR_CLEAR (1 << 3) +#define I2C_QUEUECTRL_PIO_QUEUE_MODE (1 << 2) +#define I2C_QUEUECTRL_RD_QUEUE_IRQ_EN (1 << 1) +#define I2C_QUEUECTRL_WR_QUEUE_IRQ_EN (1 << 0) + +#define I2C_QUEUESTAT_RD_QUEUE_FULL (1 << 14) +#define I2C_QUEUESTAT_RD_QUEUE_EMPTY (1 << 13) +#define I2C_QUEUESTAT_RD_QUEUE_CNT_MASK (0x1f << 8) +#define I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET 8 +#define I2C_QUEUESTAT_WR_QUEUE_FULL (1 << 6) +#define I2C_QUEUESTAT_WR_QUEUE_EMPTY (1 << 5) +#define I2C_QUEUESTAT_WR_QUEUE_CNT_MASK 0x1f +#define I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET 0 + +#define I2C_QUEUECMD_PREACK (1 << 27) +#define I2C_QUEUECMD_ACKNOWLEDGE (1 << 26) +#define I2C_QUEUECMD_SEND_NAK_ON_LAST (1 << 25) +#define I2C_QUEUECMD_MULTI_MASTER (1 << 23) +#define I2C_QUEUECMD_CLOCK_HELD (1 << 22) +#define I2C_QUEUECMD_RETAIN_CLOCK (1 << 21) +#define I2C_QUEUECMD_POST_SEND_STOP (1 << 20) +#define I2C_QUEUECMD_PRE_SEND_START (1 << 19) +#define I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE (1 << 18) +#define I2C_QUEUECMD_MASTER_MODE (1 << 17) +#define I2C_QUEUECMD_DIRECTION (1 << 16) +#define I2C_QUEUECMD_XFER_COUNT_MASK 0xffff +#define I2C_QUEUECMD_XFER_COUNT_OFFSET 0 + +#define I2C_QUEUEDATA_DATA_MASK 0xffffffff +#define I2C_QUEUEDATA_DATA_OFFSET 0 + +#define I2C_DATA_DATA_MASK 0xffffffff +#define I2C_DATA_DATA_OFFSET 0 + +#define I2C_DEBUG0_DMAREQ (1 << 31) +#define I2C_DEBUG0_DMAENDCMD (1 << 30) +#define I2C_DEBUG0_DMAKICK (1 << 29) +#define I2C_DEBUG0_DMATERMINATE (1 << 28) +#define I2C_DEBUG0_STATE_VALUE_MASK (0x3 << 26) +#define I2C_DEBUG0_STATE_VALUE_OFFSET 26 +#define I2C_DEBUG0_DMA_STATE_MASK (0x3ff << 16) +#define I2C_DEBUG0_DMA_STATE_OFFSET 16 +#define I2C_DEBUG0_START_TOGGLE (1 << 15) +#define I2C_DEBUG0_STOP_TOGGLE (1 << 14) +#define I2C_DEBUG0_GRAB_TOGGLE (1 << 13) +#define I2C_DEBUG0_CHANGE_TOGGLE (1 << 12) +#define I2C_DEBUG0_STATE_LATCH (1 << 11) +#define I2C_DEBUG0_SLAVE_HOLD_CLK (1 << 10) +#define I2C_DEBUG0_STATE_STATE_MASK 0x3ff +#define I2C_DEBUG0_STATE_STATE_OFFSET 0 + +#define I2C_DEBUG1_I2C_CLK_IN (1 << 31) +#define I2C_DEBUG1_I2C_DATA_IN (1 << 30) +#define I2C_DEBUG1_DMA_BYTE_ENABLES_MASK (0xf << 24) +#define I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET 24 +#define I2C_DEBUG1_CLK_GEN_STATE_MASK (0xff << 16) +#define I2C_DEBUG1_CLK_GEN_STATE_OFFSET 16 +#define I2C_DEBUG1_LST_MODE_MASK (0x3 << 9) +#define I2C_DEBUG1_LST_MODE_OFFSET 9 +#define I2C_DEBUG1_LOCAL_SLAVE_TEST (1 << 8) +#define I2C_DEBUG1_FORCE_CLK_ON (1 << 4) +#define I2C_DEBUG1_FORCE_ABR_LOSS (1 << 3) +#define I2C_DEBUG1_FORCE_RCV_ACK (1 << 2) +#define I2C_DEBUG1_FORCE_I2C_DATA_OE (1 << 1) +#define I2C_DEBUG1_FORCE_I2C_CLK_OE (1 << 0) + +#define I2C_VERSION_MAJOR_MASK (0xff << 24) +#define I2C_VERSION_MAJOR_OFFSET 24 +#define I2C_VERSION_MINOR_MASK (0xff << 16) +#define I2C_VERSION_MINOR_OFFSET 16 +#define I2C_VERSION_STEP_MASK 0xffff +#define I2C_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_I2C_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-ocotp.h b/arch/arm/include/asm/arch-mx28/regs-ocotp.h new file mode 100644 index 000000000..ea2fd7b16 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-ocotp.h @@ -0,0 +1,173 @@ +/* + * Freescale i.MX28 OCOTP Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_OCOTP_H__ +#define __MX28_REGS_OCOTP_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_ocotp_regs { + mx28_reg(hw_ocotp_ctrl) /* 0x0 */ + mx28_reg(hw_ocotp_data) /* 0x10 */ + mx28_reg(hw_ocotp_cust0) /* 0x20 */ + mx28_reg(hw_ocotp_cust1) /* 0x30 */ + mx28_reg(hw_ocotp_cust2) /* 0x40 */ + mx28_reg(hw_ocotp_cust3) /* 0x50 */ + mx28_reg(hw_ocotp_crypto0) /* 0x60 */ + mx28_reg(hw_ocotp_crypto1) /* 0x70 */ + mx28_reg(hw_ocotp_crypto2) /* 0x80 */ + mx28_reg(hw_ocotp_crypto3) /* 0x90 */ + mx28_reg(hw_ocotp_hwcap0) /* 0xa0 */ + mx28_reg(hw_ocotp_hwcap1) /* 0xb0 */ + mx28_reg(hw_ocotp_hwcap2) /* 0xc0 */ + mx28_reg(hw_ocotp_hwcap3) /* 0xd0 */ + mx28_reg(hw_ocotp_hwcap4) /* 0xe0 */ + mx28_reg(hw_ocotp_hwcap5) /* 0xf0 */ + mx28_reg(hw_ocotp_swcap) /* 0x100 */ + mx28_reg(hw_ocotp_custcap) /* 0x110 */ + mx28_reg(hw_ocotp_lock) /* 0x120 */ + mx28_reg(hw_ocotp_ops0) /* 0x130 */ + mx28_reg(hw_ocotp_ops1) /* 0x140 */ + mx28_reg(hw_ocotp_ops2) /* 0x150 */ + mx28_reg(hw_ocotp_ops3) /* 0x160 */ + mx28_reg(hw_ocotp_un0) /* 0x170 */ + mx28_reg(hw_ocotp_un1) /* 0x180 */ + mx28_reg(hw_ocotp_un2) /* 0x190 */ + mx28_reg(hw_ocotp_rom0) /* 0x1a0 */ + mx28_reg(hw_ocotp_rom1) /* 0x1b0 */ + mx28_reg(hw_ocotp_rom2) /* 0x1c0 */ + mx28_reg(hw_ocotp_rom3) /* 0x1d0 */ + mx28_reg(hw_ocotp_rom4) /* 0x1e0 */ + mx28_reg(hw_ocotp_rom5) /* 0x1f0 */ + mx28_reg(hw_ocotp_rom6) /* 0x200 */ + mx28_reg(hw_ocotp_rom7) /* 0x210 */ + mx28_reg(hw_ocotp_srk0) /* 0x220 */ + mx28_reg(hw_ocotp_srk1) /* 0x230 */ + mx28_reg(hw_ocotp_srk2) /* 0x240 */ + mx28_reg(hw_ocotp_srk3) /* 0x250 */ + mx28_reg(hw_ocotp_srk4) /* 0x260 */ + mx28_reg(hw_ocotp_srk5) /* 0x270 */ + mx28_reg(hw_ocotp_srk6) /* 0x280 */ + mx28_reg(hw_ocotp_srk7) /* 0x290 */ + mx28_reg(hw_ocotp_version) /* 0x2a0 */ +}; +#endif + +#define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16) +#define OCOTP_CTRL_WR_UNLOCK_OFFSET 16 +#define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16) +#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13) +#define OCOTP_CTRL_RD_BANK_OPEN (1 << 12) +#define OCOTP_CTRL_ERROR (1 << 9) +#define OCOTP_CTRL_BUSY (1 << 8) +#define OCOTP_CTRL_ADDR_MASK 0x3f +#define OCOTP_CTRL_ADDR_OFFSET 0 + +#define OCOTP_DATA_DATA_MASK 0xffffffff +#define OCOTP_DATA_DATA_OFFSET 0 + +#define OCOTP_CUST_BITS_MASK 0xffffffff +#define OCOTP_CUST_BITS_OFFSET 0 + +#define OCOTP_CRYPTO_BITS_MASK 0xffffffff +#define OCOTP_CRYPTO_BITS_OFFSET 0 + +#define OCOTP_HWCAP_BITS_MASK 0xffffffff +#define OCOTP_HWCAP_BITS_OFFSET 0 + +#define OCOTP_SWCAP_BITS_MASK 0xffffffff +#define OCOTP_SWCAP_BITS_OFFSET 0 + +#define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2) +#define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1) + +#define OCOTP_LOCK_ROM7 (1 << 31) +#define OCOTP_LOCK_ROM6 (1 << 30) +#define OCOTP_LOCK_ROM5 (1 << 29) +#define OCOTP_LOCK_ROM4 (1 << 28) +#define OCOTP_LOCK_ROM3 (1 << 27) +#define OCOTP_LOCK_ROM2 (1 << 26) +#define OCOTP_LOCK_ROM1 (1 << 25) +#define OCOTP_LOCK_ROM0 (1 << 24) +#define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23) +#define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22) +#define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21) +#define OCOTP_LOCK_PIN (1 << 20) +#define OCOTP_LOCK_OPS (1 << 19) +#define OCOTP_LOCK_UN2 (1 << 18) +#define OCOTP_LOCK_UN1 (1 << 17) +#define OCOTP_LOCK_UN0 (1 << 16) +#define OCOTP_LOCK_SRK (1 << 15) +#define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12) +#define OCOTP_LOCK_UNALLOCATED_OFFSET 12 +#define OCOTP_LOCK_SRK_SHADOW (1 << 11) +#define OCOTP_LOCK_ROM_SHADOW (1 << 10) +#define OCOTP_LOCK_CUSTCAP (1 << 9) +#define OCOTP_LOCK_HWSW (1 << 8) +#define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7) +#define OCOTP_LOCK_HWSW_SHADOW (1 << 6) +#define OCOTP_LOCK_CRYPTODCP (1 << 5) +#define OCOTP_LOCK_CRYPTOKEY (1 << 4) +#define OCOTP_LOCK_CUST3 (1 << 3) +#define OCOTP_LOCK_CUST2 (1 << 2) +#define OCOTP_LOCK_CUST1 (1 << 1) +#define OCOTP_LOCK_CUST0 (1 << 0) + +#define OCOTP_OPS_BITS_MASK 0xffffffff +#define OCOTP_OPS_BITS_OFFSET 0 + +#define OCOTP_UN_BITS_MASK 0xffffffff +#define OCOTP_UN_BITS_OFFSET 0 + +#define OCOTP_ROM_BOOT_MODE_MASK (0xff << 24) +#define OCOTP_ROM_BOOT_MODE_OFFSET 24 +#define OCOTP_ROM_SD_MMC_MODE_MASK (0x3 << 22) +#define OCOTP_ROM_SD_MMC_MODE_OFFSET 22 +#define OCOTP_ROM_SD_POWER_GATE_GPIO_MASK (0x3 << 20) +#define OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET 20 +#define OCOTP_ROM_SD_POWER_UP_DELAY_MASK (0x3f << 14) +#define OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET 14 +#define OCOTP_ROM_SD_BUS_WIDTH_MASK (0x3 << 12) +#define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12 +#define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8) +#define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8 +#define OCOTP_ROM_EMMC_USE_DDR (1 << 7) +#define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6) +#define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5) +#define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4) +#define OCOTP_ROM_SD_MBR_BOOT (1 << 3) + +#define OCOTP_SRK_BITS_MASK 0xffffffff +#define OCOTP_SRK_BITS_OFFSET 0 + +#define OCOTP_VERSION_MAJOR_MASK (0xff << 24) +#define OCOTP_VERSION_MAJOR_OFFSET 24 +#define OCOTP_VERSION_MINOR_MASK (0xff << 16) +#define OCOTP_VERSION_MINOR_OFFSET 16 +#define OCOTP_VERSION_STEP_MASK 0xffff +#define OCOTP_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_OCOTP_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-pinctrl.h b/arch/arm/include/asm/arch-mx28/regs-pinctrl.h new file mode 100644 index 000000000..73739cad5 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-pinctrl.h @@ -0,0 +1,1284 @@ +/* + * Freescale i.MX28 PINCTRL Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_PINCTRL_H__ +#define __MX28_REGS_PINCTRL_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_pinctrl_regs { + mx28_reg(hw_pinctrl_ctrl) /* 0x0 */ + + uint32_t reserved1[60]; + + mx28_reg(hw_pinctrl_muxsel0) /* 0x100 */ + mx28_reg(hw_pinctrl_muxsel1) /* 0x110 */ + mx28_reg(hw_pinctrl_muxsel2) /* 0x120 */ + mx28_reg(hw_pinctrl_muxsel3) /* 0x130 */ + mx28_reg(hw_pinctrl_muxsel4) /* 0x140 */ + mx28_reg(hw_pinctrl_muxsel5) /* 0x150 */ + mx28_reg(hw_pinctrl_muxsel6) /* 0x160 */ + mx28_reg(hw_pinctrl_muxsel7) /* 0x170 */ + mx28_reg(hw_pinctrl_muxsel8) /* 0x180 */ + mx28_reg(hw_pinctrl_muxsel9) /* 0x190 */ + mx28_reg(hw_pinctrl_muxsel10) /* 0x1a0 */ + mx28_reg(hw_pinctrl_muxsel11) /* 0x1b0 */ + mx28_reg(hw_pinctrl_muxsel12) /* 0x1c0 */ + mx28_reg(hw_pinctrl_muxsel13) /* 0x1d0 */ + + uint32_t reserved2[72]; + + mx28_reg(hw_pinctrl_drive0) /* 0x300 */ + mx28_reg(hw_pinctrl_drive1) /* 0x310 */ + mx28_reg(hw_pinctrl_drive2) /* 0x320 */ + mx28_reg(hw_pinctrl_drive3) /* 0x330 */ + mx28_reg(hw_pinctrl_drive4) /* 0x340 */ + mx28_reg(hw_pinctrl_drive5) /* 0x350 */ + mx28_reg(hw_pinctrl_drive6) /* 0x360 */ + mx28_reg(hw_pinctrl_drive7) /* 0x370 */ + mx28_reg(hw_pinctrl_drive8) /* 0x380 */ + mx28_reg(hw_pinctrl_drive9) /* 0x390 */ + mx28_reg(hw_pinctrl_drive10) /* 0x3a0 */ + mx28_reg(hw_pinctrl_drive11) /* 0x3b0 */ + mx28_reg(hw_pinctrl_drive12) /* 0x3c0 */ + mx28_reg(hw_pinctrl_drive13) /* 0x3d0 */ + mx28_reg(hw_pinctrl_drive14) /* 0x3e0 */ + mx28_reg(hw_pinctrl_drive15) /* 0x3f0 */ + mx28_reg(hw_pinctrl_drive16) /* 0x400 */ + mx28_reg(hw_pinctrl_drive17) /* 0x410 */ + mx28_reg(hw_pinctrl_drive18) /* 0x420 */ + mx28_reg(hw_pinctrl_drive19) /* 0x430 */ + + uint32_t reserved3[112]; + + mx28_reg(hw_pinctrl_pull0) /* 0x600 */ + mx28_reg(hw_pinctrl_pull1) /* 0x610 */ + mx28_reg(hw_pinctrl_pull2) /* 0x620 */ + mx28_reg(hw_pinctrl_pull3) /* 0x630 */ + mx28_reg(hw_pinctrl_pull4) /* 0x640 */ + mx28_reg(hw_pinctrl_pull5) /* 0x650 */ + mx28_reg(hw_pinctrl_pull6) /* 0x660 */ + + uint32_t reserved4[36]; + + mx28_reg(hw_pinctrl_dout0) /* 0x700 */ + mx28_reg(hw_pinctrl_dout1) /* 0x710 */ + mx28_reg(hw_pinctrl_dout2) /* 0x720 */ + mx28_reg(hw_pinctrl_dout3) /* 0x730 */ + mx28_reg(hw_pinctrl_dout4) /* 0x740 */ + + uint32_t reserved5[108]; + + mx28_reg(hw_pinctrl_din0) /* 0x900 */ + mx28_reg(hw_pinctrl_din1) /* 0x910 */ + mx28_reg(hw_pinctrl_din2) /* 0x920 */ + mx28_reg(hw_pinctrl_din3) /* 0x930 */ + mx28_reg(hw_pinctrl_din4) /* 0x940 */ + + uint32_t reserved6[108]; + + mx28_reg(hw_pinctrl_doe0) /* 0xb00 */ + mx28_reg(hw_pinctrl_doe1) /* 0xb10 */ + mx28_reg(hw_pinctrl_doe2) /* 0xb20 */ + mx28_reg(hw_pinctrl_doe3) /* 0xb30 */ + mx28_reg(hw_pinctrl_doe4) /* 0xb40 */ + + uint32_t reserved7[300]; + + mx28_reg(hw_pinctrl_pin2irq0) /* 0x1000 */ + mx28_reg(hw_pinctrl_pin2irq1) /* 0x1010 */ + mx28_reg(hw_pinctrl_pin2irq2) /* 0x1020 */ + mx28_reg(hw_pinctrl_pin2irq3) /* 0x1030 */ + mx28_reg(hw_pinctrl_pin2irq4) /* 0x1040 */ + + uint32_t reserved8[44]; + + mx28_reg(hw_pinctrl_irqen0) /* 0x1100 */ + mx28_reg(hw_pinctrl_irqen1) /* 0x1110 */ + mx28_reg(hw_pinctrl_irqen2) /* 0x1120 */ + mx28_reg(hw_pinctrl_irqen3) /* 0x1130 */ + mx28_reg(hw_pinctrl_irqen4) /* 0x1140 */ + + uint32_t reserved9[44]; + + mx28_reg(hw_pinctrl_irqlevel0) /* 0x1200 */ + mx28_reg(hw_pinctrl_irqlevel1) /* 0x1210 */ + mx28_reg(hw_pinctrl_irqlevel2) /* 0x1220 */ + mx28_reg(hw_pinctrl_irqlevel3) /* 0x1230 */ + mx28_reg(hw_pinctrl_irqlevel4) /* 0x1240 */ + + uint32_t reserved10[44]; + + mx28_reg(hw_pinctrl_irqpol0) /* 0x1300 */ + mx28_reg(hw_pinctrl_irqpol1) /* 0x1310 */ + mx28_reg(hw_pinctrl_irqpol2) /* 0x1320 */ + mx28_reg(hw_pinctrl_irqpol3) /* 0x1330 */ + mx28_reg(hw_pinctrl_irqpol4) /* 0x1340 */ + + uint32_t reserved11[44]; + + mx28_reg(hw_pinctrl_irqstat0) /* 0x1400 */ + mx28_reg(hw_pinctrl_irqstat1) /* 0x1410 */ + mx28_reg(hw_pinctrl_irqstat2) /* 0x1420 */ + mx28_reg(hw_pinctrl_irqstat3) /* 0x1430 */ + mx28_reg(hw_pinctrl_irqstat4) /* 0x1440 */ + + uint32_t reserved12[380]; + + mx28_reg(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ + + uint32_t reserved13[76]; + + mx28_reg(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ +}; +#endif + +#define PINCTRL_CTRL_SFTRST (1 << 31) +#define PINCTRL_CTRL_CLKGATE (1 << 30) +#define PINCTRL_CTRL_PRESENT4 (1 << 24) +#define PINCTRL_CTRL_PRESENT3 (1 << 23) +#define PINCTRL_CTRL_PRESENT2 (1 << 22) +#define PINCTRL_CTRL_PRESENT1 (1 << 21) +#define PINCTRL_CTRL_PRESENT0 (1 << 20) +#define PINCTRL_CTRL_IRQOUT4 (1 << 4) +#define PINCTRL_CTRL_IRQOUT3 (1 << 3) +#define PINCTRL_CTRL_IRQOUT2 (1 << 2) +#define PINCTRL_CTRL_IRQOUT1 (1 << 1) +#define PINCTRL_CTRL_IRQOUT0 (1 << 0) + +#define PINCTRL_MUXSEL0_BANK0_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL0_BANK0_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL0_BANK0_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL0_BANK0_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL0_BANK0_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL0_BANK0_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL0_BANK0_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL0_BANK0_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL0_BANK0_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL0_BANK0_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL0_BANK0_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL0_BANK0_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL0_BANK0_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL0_BANK0_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL0_BANK0_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL0_BANK0_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL1_BANK0_PIN28_MASK (0x3 << 24) +#define PINCTRL_MUXSEL1_BANK0_PIN28_OFFSET 24 +#define PINCTRL_MUXSEL1_BANK0_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL1_BANK0_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL1_BANK0_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL1_BANK0_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL1_BANK0_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL1_BANK0_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL1_BANK0_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL1_BANK0_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL1_BANK0_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL1_BANK0_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL1_BANK0_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL1_BANK0_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL1_BANK0_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL1_BANK0_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL1_BANK0_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL1_BANK0_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL1_BANK0_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL1_BANK0_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL1_BANK0_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL1_BANK0_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL1_BANK0_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL1_BANK0_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL1_BANK0_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL1_BANK0_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL2_BANK1_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL2_BANK1_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL2_BANK1_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL2_BANK1_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL2_BANK1_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL2_BANK1_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL2_BANK1_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL2_BANK1_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL2_BANK1_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL2_BANK1_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL2_BANK1_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL2_BANK1_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL2_BANK1_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL2_BANK1_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL2_BANK1_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL2_BANK1_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL2_BANK1_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL2_BANK1_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL2_BANK1_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL2_BANK1_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL2_BANK1_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL2_BANK1_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL2_BANK1_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL2_BANK1_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL2_BANK1_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL2_BANK1_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL2_BANK1_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL2_BANK1_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL2_BANK1_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL2_BANK1_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL2_BANK1_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL2_BANK1_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL3_BANK1_PIN31_MASK (0x3 << 30) +#define PINCTRL_MUXSEL3_BANK1_PIN31_OFFSET 30 +#define PINCTRL_MUXSEL3_BANK1_PIN30_MASK (0x3 << 28) +#define PINCTRL_MUXSEL3_BANK1_PIN30_OFFSET 28 +#define PINCTRL_MUXSEL3_BANK1_PIN29_MASK (0x3 << 26) +#define PINCTRL_MUXSEL3_BANK1_PIN29_OFFSET 26 +#define PINCTRL_MUXSEL3_BANK1_PIN28_MASK (0x3 << 24) +#define PINCTRL_MUXSEL3_BANK1_PIN28_OFFSET 24 +#define PINCTRL_MUXSEL3_BANK1_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL3_BANK1_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL3_BANK1_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL3_BANK1_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL3_BANK1_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL3_BANK1_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL3_BANK1_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL3_BANK1_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL3_BANK1_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL3_BANK1_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL3_BANK1_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL3_BANK1_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL3_BANK1_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL3_BANK1_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL3_BANK1_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL3_BANK1_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL3_BANK1_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL3_BANK1_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL3_BANK1_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL3_BANK1_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL3_BANK1_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL3_BANK1_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL3_BANK1_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL3_BANK1_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL4_BANK2_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL4_BANK2_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL4_BANK2_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL4_BANK2_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL4_BANK2_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL4_BANK2_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL4_BANK2_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL4_BANK2_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL4_BANK2_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL4_BANK2_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL4_BANK2_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL4_BANK2_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL4_BANK2_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL4_BANK2_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL4_BANK2_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL4_BANK2_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL4_BANK2_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL4_BANK2_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL4_BANK2_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL4_BANK2_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL4_BANK2_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL4_BANK2_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL4_BANK2_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL4_BANK2_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL4_BANK2_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL4_BANK2_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL4_BANK2_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL4_BANK2_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL4_BANK2_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL4_BANK2_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL5_BANK2_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL5_BANK2_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL5_BANK2_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL5_BANK2_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL5_BANK2_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL5_BANK2_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL5_BANK2_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL5_BANK2_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL5_BANK2_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL5_BANK2_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL5_BANK2_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL5_BANK2_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL5_BANK2_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL5_BANK2_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL5_BANK2_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL5_BANK2_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL5_BANK2_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL5_BANK2_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL5_BANK2_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL5_BANK2_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL6_BANK3_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL6_BANK3_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL6_BANK3_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL6_BANK3_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL6_BANK3_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL6_BANK3_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL6_BANK3_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL6_BANK3_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL6_BANK3_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL6_BANK3_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL6_BANK3_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL6_BANK3_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL6_BANK3_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL6_BANK3_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL6_BANK3_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL6_BANK3_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL6_BANK3_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL6_BANK3_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL6_BANK3_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL6_BANK3_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL6_BANK3_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL6_BANK3_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL6_BANK3_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL6_BANK3_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL6_BANK3_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL6_BANK3_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL6_BANK3_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL6_BANK3_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL6_BANK3_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL6_BANK3_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL6_BANK3_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL6_BANK3_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL7_BANK3_PIN30_MASK (0x3 << 28) +#define PINCTRL_MUXSEL7_BANK3_PIN30_OFFSET 28 +#define PINCTRL_MUXSEL7_BANK3_PIN29_MASK (0x3 << 26) +#define PINCTRL_MUXSEL7_BANK3_PIN29_OFFSET 26 +#define PINCTRL_MUXSEL7_BANK3_PIN28_MASK (0x3 << 24) +#define PINCTRL_MUXSEL7_BANK3_PIN28_OFFSET 24 +#define PINCTRL_MUXSEL7_BANK3_PIN27_MASK (0x3 << 22) +#define PINCTRL_MUXSEL7_BANK3_PIN27_OFFSET 22 +#define PINCTRL_MUXSEL7_BANK3_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL7_BANK3_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL7_BANK3_PIN25_MASK (0x3 << 18) +#define PINCTRL_MUXSEL7_BANK3_PIN25_OFFSET 18 +#define PINCTRL_MUXSEL7_BANK3_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL7_BANK3_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL7_BANK3_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL7_BANK3_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL7_BANK3_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL7_BANK3_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL7_BANK3_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL7_BANK3_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL7_BANK3_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL7_BANK3_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL7_BANK3_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL7_BANK3_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL7_BANK3_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL7_BANK3_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL7_BANK3_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL7_BANK3_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL8_BANK4_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL8_BANK4_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL8_BANK4_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL8_BANK4_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL8_BANK4_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL8_BANK4_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL8_BANK4_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL8_BANK4_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL8_BANK4_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL8_BANK4_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL8_BANK4_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL8_BANK4_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL8_BANK4_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL8_BANK4_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL8_BANK4_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL8_BANK4_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL8_BANK4_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL8_BANK4_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL8_BANK4_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL8_BANK4_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL8_BANK4_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL8_BANK4_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL8_BANK4_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL8_BANK4_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL8_BANK4_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL8_BANK4_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL8_BANK4_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL8_BANK4_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL8_BANK4_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL8_BANK4_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL8_BANK4_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL8_BANK4_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL9_BANK4_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL9_BANK4_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL9_BANK4_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL9_BANK4_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL10_BANK5_PIN15_MASK (0x3 << 30) +#define PINCTRL_MUXSEL10_BANK5_PIN15_OFFSET 30 +#define PINCTRL_MUXSEL10_BANK5_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL10_BANK5_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL10_BANK5_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL10_BANK5_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL10_BANK5_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL10_BANK5_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL10_BANK5_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL10_BANK5_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL10_BANK5_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL10_BANK5_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL10_BANK5_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL10_BANK5_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL10_BANK5_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL10_BANK5_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL10_BANK5_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL10_BANK5_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL10_BANK5_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL10_BANK5_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL10_BANK5_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL10_BANK5_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL10_BANK5_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL10_BANK5_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL10_BANK5_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL10_BANK5_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL10_BANK5_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL10_BANK5_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL10_BANK5_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL10_BANK5_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL10_BANK5_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL10_BANK5_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL11_BANK5_PIN26_MASK (0x3 << 20) +#define PINCTRL_MUXSEL11_BANK5_PIN26_OFFSET 20 +#define PINCTRL_MUXSEL11_BANK5_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL11_BANK5_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL11_BANK5_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL11_BANK5_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL11_BANK5_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL11_BANK5_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL11_BANK5_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL11_BANK5_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL11_BANK5_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL11_BANK5_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL11_BANK5_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL11_BANK5_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL11_BANK5_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL11_BANK5_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL11_BANK5_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL11_BANK5_PIN16_OFFSET 0 + +#define PINCTRL_MUXSEL12_BANK6_PIN14_MASK (0x3 << 28) +#define PINCTRL_MUXSEL12_BANK6_PIN14_OFFSET 28 +#define PINCTRL_MUXSEL12_BANK6_PIN13_MASK (0x3 << 26) +#define PINCTRL_MUXSEL12_BANK6_PIN13_OFFSET 26 +#define PINCTRL_MUXSEL12_BANK6_PIN12_MASK (0x3 << 24) +#define PINCTRL_MUXSEL12_BANK6_PIN12_OFFSET 24 +#define PINCTRL_MUXSEL12_BANK6_PIN11_MASK (0x3 << 22) +#define PINCTRL_MUXSEL12_BANK6_PIN11_OFFSET 22 +#define PINCTRL_MUXSEL12_BANK6_PIN10_MASK (0x3 << 20) +#define PINCTRL_MUXSEL12_BANK6_PIN10_OFFSET 20 +#define PINCTRL_MUXSEL12_BANK6_PIN09_MASK (0x3 << 18) +#define PINCTRL_MUXSEL12_BANK6_PIN09_OFFSET 18 +#define PINCTRL_MUXSEL12_BANK6_PIN08_MASK (0x3 << 16) +#define PINCTRL_MUXSEL12_BANK6_PIN08_OFFSET 16 +#define PINCTRL_MUXSEL12_BANK6_PIN07_MASK (0x3 << 14) +#define PINCTRL_MUXSEL12_BANK6_PIN07_OFFSET 14 +#define PINCTRL_MUXSEL12_BANK6_PIN06_MASK (0x3 << 12) +#define PINCTRL_MUXSEL12_BANK6_PIN06_OFFSET 12 +#define PINCTRL_MUXSEL12_BANK6_PIN05_MASK (0x3 << 10) +#define PINCTRL_MUXSEL12_BANK6_PIN05_OFFSET 10 +#define PINCTRL_MUXSEL12_BANK6_PIN04_MASK (0x3 << 8) +#define PINCTRL_MUXSEL12_BANK6_PIN04_OFFSET 8 +#define PINCTRL_MUXSEL12_BANK6_PIN03_MASK (0x3 << 6) +#define PINCTRL_MUXSEL12_BANK6_PIN03_OFFSET 6 +#define PINCTRL_MUXSEL12_BANK6_PIN02_MASK (0x3 << 4) +#define PINCTRL_MUXSEL12_BANK6_PIN02_OFFSET 4 +#define PINCTRL_MUXSEL12_BANK6_PIN01_MASK (0x3 << 2) +#define PINCTRL_MUXSEL12_BANK6_PIN01_OFFSET 2 +#define PINCTRL_MUXSEL12_BANK6_PIN00_MASK (0x3 << 0) +#define PINCTRL_MUXSEL12_BANK6_PIN00_OFFSET 0 + +#define PINCTRL_MUXSEL13_BANK6_PIN24_MASK (0x3 << 16) +#define PINCTRL_MUXSEL13_BANK6_PIN24_OFFSET 16 +#define PINCTRL_MUXSEL13_BANK6_PIN23_MASK (0x3 << 14) +#define PINCTRL_MUXSEL13_BANK6_PIN23_OFFSET 14 +#define PINCTRL_MUXSEL13_BANK6_PIN22_MASK (0x3 << 12) +#define PINCTRL_MUXSEL13_BANK6_PIN22_OFFSET 12 +#define PINCTRL_MUXSEL13_BANK6_PIN21_MASK (0x3 << 10) +#define PINCTRL_MUXSEL13_BANK6_PIN21_OFFSET 10 +#define PINCTRL_MUXSEL13_BANK6_PIN20_MASK (0x3 << 8) +#define PINCTRL_MUXSEL13_BANK6_PIN20_OFFSET 8 +#define PINCTRL_MUXSEL13_BANK6_PIN19_MASK (0x3 << 6) +#define PINCTRL_MUXSEL13_BANK6_PIN19_OFFSET 6 +#define PINCTRL_MUXSEL13_BANK6_PIN18_MASK (0x3 << 4) +#define PINCTRL_MUXSEL13_BANK6_PIN18_OFFSET 4 +#define PINCTRL_MUXSEL13_BANK6_PIN17_MASK (0x3 << 2) +#define PINCTRL_MUXSEL13_BANK6_PIN17_OFFSET 2 +#define PINCTRL_MUXSEL13_BANK6_PIN16_MASK (0x3 << 0) +#define PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET 0 + +#define PINCTRL_DRIVE0_BANK0_PIN07_V (1 << 30) +#define PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE0_BANK0_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE0_BANK0_PIN06_V (1 << 26) +#define PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE0_BANK0_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE0_BANK0_PIN05_V (1 << 22) +#define PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE0_BANK0_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE0_BANK0_PIN04_V (1 << 18) +#define PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE0_BANK0_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE0_BANK0_PIN03_V (1 << 14) +#define PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE0_BANK0_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE0_BANK0_PIN02_V (1 << 10) +#define PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE0_BANK0_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE0_BANK0_PIN01_V (1 << 6) +#define PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE0_BANK0_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE0_BANK0_PIN00_V (1 << 2) +#define PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE2_BANK0_PIN23_V (1 << 30) +#define PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE2_BANK0_PIN23_MA_OFFSET 28 +#define PINCTRL_DRIVE2_BANK0_PIN22_V (1 << 26) +#define PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE2_BANK0_PIN22_MA_OFFSET 24 +#define PINCTRL_DRIVE2_BANK0_PIN21_V (1 << 22) +#define PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE2_BANK0_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE2_BANK0_PIN20_V (1 << 18) +#define PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE2_BANK0_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE2_BANK0_PIN19_V (1 << 14) +#define PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE2_BANK0_PIN19_MA_OFFSET 12 +#define PINCTRL_DRIVE2_BANK0_PIN18_V (1 << 10) +#define PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE2_BANK0_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE2_BANK0_PIN17_V (1 << 6) +#define PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE2_BANK0_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE2_BANK0_PIN16_V (1 << 2) +#define PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE3_BANK0_PIN28_V (1 << 18) +#define PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE3_BANK0_PIN28_MA_OFFSET 16 +#define PINCTRL_DRIVE3_BANK0_PIN27_V (1 << 14) +#define PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE3_BANK0_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE3_BANK0_PIN26_V (1 << 10) +#define PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE3_BANK0_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE3_BANK0_PIN25_V (1 << 6) +#define PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE3_BANK0_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE3_BANK0_PIN24_V (1 << 2) +#define PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE4_BANK1_PIN07_V (1 << 30) +#define PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE4_BANK1_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE4_BANK1_PIN06_V (1 << 26) +#define PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE4_BANK1_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE4_BANK1_PIN05_V (1 << 22) +#define PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE4_BANK1_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE4_BANK1_PIN04_V (1 << 18) +#define PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE4_BANK1_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE4_BANK1_PIN03_V (1 << 14) +#define PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE4_BANK1_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE4_BANK1_PIN02_V (1 << 10) +#define PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE4_BANK1_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE4_BANK1_PIN01_V (1 << 6) +#define PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE4_BANK1_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE4_BANK1_PIN00_V (1 << 2) +#define PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE5_BANK1_PIN15_V (1 << 30) +#define PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE5_BANK1_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE5_BANK1_PIN14_V (1 << 26) +#define PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE5_BANK1_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE5_BANK1_PIN13_V (1 << 22) +#define PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE5_BANK1_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE5_BANK1_PIN12_V (1 << 18) +#define PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE5_BANK1_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE5_BANK1_PIN11_V (1 << 14) +#define PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE5_BANK1_PIN11_MA_OFFSET 12 +#define PINCTRL_DRIVE5_BANK1_PIN10_V (1 << 10) +#define PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE5_BANK1_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE5_BANK1_PIN09_V (1 << 6) +#define PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE5_BANK1_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE5_BANK1_PIN08_V (1 << 2) +#define PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE6_BANK1_PIN23_V (1 << 30) +#define PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE6_BANK1_PIN23_MA_OFFSET 28 +#define PINCTRL_DRIVE6_BANK1_PIN22_V (1 << 26) +#define PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE6_BANK1_PIN22_MA_OFFSET 24 +#define PINCTRL_DRIVE6_BANK1_PIN21_V (1 << 22) +#define PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE6_BANK1_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE6_BANK1_PIN20_V (1 << 18) +#define PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE6_BANK1_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE6_BANK1_PIN19_V (1 << 14) +#define PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE6_BANK1_PIN19_MA_OFFSET 12 +#define PINCTRL_DRIVE6_BANK1_PIN18_V (1 << 10) +#define PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE6_BANK1_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE6_BANK1_PIN17_V (1 << 6) +#define PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE6_BANK1_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE6_BANK1_PIN16_V (1 << 2) +#define PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE7_BANK1_PIN31_V (1 << 30) +#define PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE7_BANK1_PIN31_MA_OFFSET 28 +#define PINCTRL_DRIVE7_BANK1_PIN30_V (1 << 26) +#define PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE7_BANK1_PIN30_MA_OFFSET 24 +#define PINCTRL_DRIVE7_BANK1_PIN29_V (1 << 22) +#define PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE7_BANK1_PIN29_MA_OFFSET 20 +#define PINCTRL_DRIVE7_BANK1_PIN28_V (1 << 18) +#define PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE7_BANK1_PIN28_MA_OFFSET 16 +#define PINCTRL_DRIVE7_BANK1_PIN27_V (1 << 14) +#define PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE7_BANK1_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE7_BANK1_PIN26_V (1 << 10) +#define PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE7_BANK1_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE7_BANK1_PIN25_V (1 << 6) +#define PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE7_BANK1_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE7_BANK1_PIN24_V (1 << 2) +#define PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE8_BANK2_PIN07_V (1 << 30) +#define PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE8_BANK2_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE8_BANK2_PIN06_V (1 << 26) +#define PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE8_BANK2_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE8_BANK2_PIN05_V (1 << 22) +#define PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE8_BANK2_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE8_BANK2_PIN04_V (1 << 18) +#define PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE8_BANK2_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE8_BANK2_PIN03_V (1 << 14) +#define PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE8_BANK2_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE8_BANK2_PIN02_V (1 << 10) +#define PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE8_BANK2_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE8_BANK2_PIN01_V (1 << 6) +#define PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE8_BANK2_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE8_BANK2_PIN00_V (1 << 2) +#define PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE9_BANK2_PIN15_V (1 << 30) +#define PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE9_BANK2_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE9_BANK2_PIN14_V (1 << 26) +#define PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE9_BANK2_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE9_BANK2_PIN13_V (1 << 22) +#define PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE9_BANK2_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE9_BANK2_PIN12_V (1 << 18) +#define PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE9_BANK2_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE9_BANK2_PIN10_V (1 << 10) +#define PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE9_BANK2_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE9_BANK2_PIN09_V (1 << 6) +#define PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE9_BANK2_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE9_BANK2_PIN08_V (1 << 2) +#define PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE10_BANK2_PIN21_V (1 << 22) +#define PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE10_BANK2_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE10_BANK2_PIN20_V (1 << 18) +#define PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE10_BANK2_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE10_BANK2_PIN19_V (1 << 14) +#define PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE10_BANK2_PIN19_MA_OFFSET 12 +#define PINCTRL_DRIVE10_BANK2_PIN18_V (1 << 10) +#define PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE10_BANK2_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE10_BANK2_PIN17_V (1 << 6) +#define PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE10_BANK2_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE10_BANK2_PIN16_V (1 << 2) +#define PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE11_BANK2_PIN27_V (1 << 14) +#define PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE11_BANK2_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE11_BANK2_PIN26_V (1 << 10) +#define PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE11_BANK2_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE11_BANK2_PIN25_V (1 << 6) +#define PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE11_BANK2_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE11_BANK2_PIN24_V (1 << 2) +#define PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE12_BANK3_PIN07_V (1 << 30) +#define PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE12_BANK3_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE12_BANK3_PIN06_V (1 << 26) +#define PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE12_BANK3_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE12_BANK3_PIN05_V (1 << 22) +#define PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE12_BANK3_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE12_BANK3_PIN04_V (1 << 18) +#define PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE12_BANK3_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE12_BANK3_PIN03_V (1 << 14) +#define PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE12_BANK3_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE12_BANK3_PIN02_V (1 << 10) +#define PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE12_BANK3_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE12_BANK3_PIN01_V (1 << 6) +#define PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE12_BANK3_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE12_BANK3_PIN00_V (1 << 2) +#define PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE13_BANK3_PIN15_V (1 << 30) +#define PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE13_BANK3_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE13_BANK3_PIN14_V (1 << 26) +#define PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE13_BANK3_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE13_BANK3_PIN13_V (1 << 22) +#define PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE13_BANK3_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE13_BANK3_PIN12_V (1 << 18) +#define PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE13_BANK3_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE13_BANK3_PIN11_V (1 << 14) +#define PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE13_BANK3_PIN11_MA_OFFSET 12 +#define PINCTRL_DRIVE13_BANK3_PIN10_V (1 << 10) +#define PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE13_BANK3_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE13_BANK3_PIN09_V (1 << 6) +#define PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE13_BANK3_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE13_BANK3_PIN08_V (1 << 2) +#define PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE14_BANK3_PIN23_V (1 << 30) +#define PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE14_BANK3_PIN23_MA_OFFSET 28 +#define PINCTRL_DRIVE14_BANK3_PIN22_V (1 << 26) +#define PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE14_BANK3_PIN22_MA_OFFSET 24 +#define PINCTRL_DRIVE14_BANK3_PIN21_V (1 << 22) +#define PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE14_BANK3_PIN21_MA_OFFSET 20 +#define PINCTRL_DRIVE14_BANK3_PIN20_V (1 << 18) +#define PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE14_BANK3_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE14_BANK3_PIN18_V (1 << 10) +#define PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE14_BANK3_PIN18_MA_OFFSET 8 +#define PINCTRL_DRIVE14_BANK3_PIN17_V (1 << 6) +#define PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE14_BANK3_PIN17_MA_OFFSET 4 +#define PINCTRL_DRIVE14_BANK3_PIN16_V (1 << 2) +#define PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET 0 + +#define PINCTRL_DRIVE15_BANK3_PIN30_V (1 << 26) +#define PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE15_BANK3_PIN30_MA_OFFSET 24 +#define PINCTRL_DRIVE15_BANK3_PIN29_V (1 << 22) +#define PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE15_BANK3_PIN29_MA_OFFSET 20 +#define PINCTRL_DRIVE15_BANK3_PIN28_V (1 << 18) +#define PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE15_BANK3_PIN28_MA_OFFSET 16 +#define PINCTRL_DRIVE15_BANK3_PIN27_V (1 << 14) +#define PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE15_BANK3_PIN27_MA_OFFSET 12 +#define PINCTRL_DRIVE15_BANK3_PIN26_V (1 << 10) +#define PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE15_BANK3_PIN26_MA_OFFSET 8 +#define PINCTRL_DRIVE15_BANK3_PIN25_V (1 << 6) +#define PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE15_BANK3_PIN25_MA_OFFSET 4 +#define PINCTRL_DRIVE15_BANK3_PIN24_V (1 << 2) +#define PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET 0 + +#define PINCTRL_DRIVE16_BANK4_PIN07_V (1 << 30) +#define PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE16_BANK4_PIN07_MA_OFFSET 28 +#define PINCTRL_DRIVE16_BANK4_PIN06_V (1 << 26) +#define PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE16_BANK4_PIN06_MA_OFFSET 24 +#define PINCTRL_DRIVE16_BANK4_PIN05_V (1 << 22) +#define PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE16_BANK4_PIN05_MA_OFFSET 20 +#define PINCTRL_DRIVE16_BANK4_PIN04_V (1 << 18) +#define PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE16_BANK4_PIN04_MA_OFFSET 16 +#define PINCTRL_DRIVE16_BANK4_PIN03_V (1 << 14) +#define PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE16_BANK4_PIN03_MA_OFFSET 12 +#define PINCTRL_DRIVE16_BANK4_PIN02_V (1 << 10) +#define PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE16_BANK4_PIN02_MA_OFFSET 8 +#define PINCTRL_DRIVE16_BANK4_PIN01_V (1 << 6) +#define PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE16_BANK4_PIN01_MA_OFFSET 4 +#define PINCTRL_DRIVE16_BANK4_PIN00_V (1 << 2) +#define PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET 0 + +#define PINCTRL_DRIVE17_BANK4_PIN15_V (1 << 30) +#define PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK (0x3 << 28) +#define PINCTRL_DRIVE17_BANK4_PIN15_MA_OFFSET 28 +#define PINCTRL_DRIVE17_BANK4_PIN14_V (1 << 26) +#define PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK (0x3 << 24) +#define PINCTRL_DRIVE17_BANK4_PIN14_MA_OFFSET 24 +#define PINCTRL_DRIVE17_BANK4_PIN13_V (1 << 22) +#define PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK (0x3 << 20) +#define PINCTRL_DRIVE17_BANK4_PIN13_MA_OFFSET 20 +#define PINCTRL_DRIVE17_BANK4_PIN12_V (1 << 18) +#define PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE17_BANK4_PIN12_MA_OFFSET 16 +#define PINCTRL_DRIVE17_BANK4_PIN11_V (1 << 14) +#define PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK (0x3 << 12) +#define PINCTRL_DRIVE17_BANK4_PIN11_MA_OFFSET 12 +#define PINCTRL_DRIVE17_BANK4_PIN10_V (1 << 10) +#define PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK (0x3 << 8) +#define PINCTRL_DRIVE17_BANK4_PIN10_MA_OFFSET 8 +#define PINCTRL_DRIVE17_BANK4_PIN09_V (1 << 6) +#define PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK (0x3 << 4) +#define PINCTRL_DRIVE17_BANK4_PIN09_MA_OFFSET 4 +#define PINCTRL_DRIVE17_BANK4_PIN08_V (1 << 2) +#define PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET 0 + +#define PINCTRL_DRIVE18_BANK4_PIN20_V (1 << 18) +#define PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK (0x3 << 16) +#define PINCTRL_DRIVE18_BANK4_PIN20_MA_OFFSET 16 +#define PINCTRL_DRIVE18_BANK4_PIN16_V (1 << 2) +#define PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK (0x3 << 0) +#define PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET 0 + +#define PINCTRL_PULL0_BANK0_PIN28 (1 << 28) +#define PINCTRL_PULL0_BANK0_PIN27 (1 << 27) +#define PINCTRL_PULL0_BANK0_PIN26 (1 << 26) +#define PINCTRL_PULL0_BANK0_PIN25 (1 << 25) +#define PINCTRL_PULL0_BANK0_PIN24 (1 << 24) +#define PINCTRL_PULL0_BANK0_PIN23 (1 << 23) +#define PINCTRL_PULL0_BANK0_PIN22 (1 << 22) +#define PINCTRL_PULL0_BANK0_PIN21 (1 << 21) +#define PINCTRL_PULL0_BANK0_PIN20 (1 << 20) +#define PINCTRL_PULL0_BANK0_PIN19 (1 << 19) +#define PINCTRL_PULL0_BANK0_PIN18 (1 << 18) +#define PINCTRL_PULL0_BANK0_PIN17 (1 << 17) +#define PINCTRL_PULL0_BANK0_PIN16 (1 << 16) +#define PINCTRL_PULL0_BANK0_PIN07 (1 << 7) +#define PINCTRL_PULL0_BANK0_PIN06 (1 << 6) +#define PINCTRL_PULL0_BANK0_PIN05 (1 << 5) +#define PINCTRL_PULL0_BANK0_PIN04 (1 << 4) +#define PINCTRL_PULL0_BANK0_PIN03 (1 << 3) +#define PINCTRL_PULL0_BANK0_PIN02 (1 << 2) +#define PINCTRL_PULL0_BANK0_PIN01 (1 << 1) +#define PINCTRL_PULL0_BANK0_PIN00 (1 << 0) + +#define PINCTRL_PULL1_BANK1_PIN31 (1 << 31) +#define PINCTRL_PULL1_BANK1_PIN30 (1 << 30) +#define PINCTRL_PULL1_BANK1_PIN29 (1 << 29) +#define PINCTRL_PULL1_BANK1_PIN28 (1 << 28) +#define PINCTRL_PULL1_BANK1_PIN27 (1 << 27) +#define PINCTRL_PULL1_BANK1_PIN26 (1 << 26) +#define PINCTRL_PULL1_BANK1_PIN25 (1 << 25) +#define PINCTRL_PULL1_BANK1_PIN24 (1 << 24) +#define PINCTRL_PULL1_BANK1_PIN23 (1 << 23) +#define PINCTRL_PULL1_BANK1_PIN22 (1 << 22) +#define PINCTRL_PULL1_BANK1_PIN21 (1 << 21) +#define PINCTRL_PULL1_BANK1_PIN20 (1 << 20) +#define PINCTRL_PULL1_BANK1_PIN19 (1 << 19) +#define PINCTRL_PULL1_BANK1_PIN18 (1 << 18) +#define PINCTRL_PULL1_BANK1_PIN17 (1 << 17) +#define PINCTRL_PULL1_BANK1_PIN16 (1 << 16) +#define PINCTRL_PULL1_BANK1_PIN15 (1 << 15) +#define PINCTRL_PULL1_BANK1_PIN14 (1 << 14) +#define PINCTRL_PULL1_BANK1_PIN13 (1 << 13) +#define PINCTRL_PULL1_BANK1_PIN12 (1 << 12) +#define PINCTRL_PULL1_BANK1_PIN11 (1 << 11) +#define PINCTRL_PULL1_BANK1_PIN10 (1 << 10) +#define PINCTRL_PULL1_BANK1_PIN09 (1 << 9) +#define PINCTRL_PULL1_BANK1_PIN08 (1 << 8) +#define PINCTRL_PULL1_BANK1_PIN07 (1 << 7) +#define PINCTRL_PULL1_BANK1_PIN06 (1 << 6) +#define PINCTRL_PULL1_BANK1_PIN05 (1 << 5) +#define PINCTRL_PULL1_BANK1_PIN04 (1 << 4) +#define PINCTRL_PULL1_BANK1_PIN03 (1 << 3) +#define PINCTRL_PULL1_BANK1_PIN02 (1 << 2) +#define PINCTRL_PULL1_BANK1_PIN01 (1 << 1) +#define PINCTRL_PULL1_BANK1_PIN00 (1 << 0) + +#define PINCTRL_PULL2_BANK2_PIN27 (1 << 27) +#define PINCTRL_PULL2_BANK2_PIN26 (1 << 26) +#define PINCTRL_PULL2_BANK2_PIN25 (1 << 25) +#define PINCTRL_PULL2_BANK2_PIN24 (1 << 24) +#define PINCTRL_PULL2_BANK2_PIN21 (1 << 21) +#define PINCTRL_PULL2_BANK2_PIN20 (1 << 20) +#define PINCTRL_PULL2_BANK2_PIN19 (1 << 19) +#define PINCTRL_PULL2_BANK2_PIN18 (1 << 18) +#define PINCTRL_PULL2_BANK2_PIN17 (1 << 17) +#define PINCTRL_PULL2_BANK2_PIN16 (1 << 16) +#define PINCTRL_PULL2_BANK2_PIN15 (1 << 15) +#define PINCTRL_PULL2_BANK2_PIN14 (1 << 14) +#define PINCTRL_PULL2_BANK2_PIN13 (1 << 13) +#define PINCTRL_PULL2_BANK2_PIN12 (1 << 12) +#define PINCTRL_PULL2_BANK2_PIN10 (1 << 10) +#define PINCTRL_PULL2_BANK2_PIN09 (1 << 9) +#define PINCTRL_PULL2_BANK2_PIN08 (1 << 8) +#define PINCTRL_PULL2_BANK2_PIN07 (1 << 7) +#define PINCTRL_PULL2_BANK2_PIN06 (1 << 6) +#define PINCTRL_PULL2_BANK2_PIN05 (1 << 5) +#define PINCTRL_PULL2_BANK2_PIN04 (1 << 4) +#define PINCTRL_PULL2_BANK2_PIN03 (1 << 3) +#define PINCTRL_PULL2_BANK2_PIN02 (1 << 2) +#define PINCTRL_PULL2_BANK2_PIN01 (1 << 1) +#define PINCTRL_PULL2_BANK2_PIN00 (1 << 0) + +#define PINCTRL_PULL3_BANK3_PIN30 (1 << 30) +#define PINCTRL_PULL3_BANK3_PIN29 (1 << 29) +#define PINCTRL_PULL3_BANK3_PIN28 (1 << 28) +#define PINCTRL_PULL3_BANK3_PIN27 (1 << 27) +#define PINCTRL_PULL3_BANK3_PIN26 (1 << 26) +#define PINCTRL_PULL3_BANK3_PIN25 (1 << 25) +#define PINCTRL_PULL3_BANK3_PIN24 (1 << 24) +#define PINCTRL_PULL3_BANK3_PIN23 (1 << 23) +#define PINCTRL_PULL3_BANK3_PIN22 (1 << 22) +#define PINCTRL_PULL3_BANK3_PIN21 (1 << 21) +#define PINCTRL_PULL3_BANK3_PIN20 (1 << 20) +#define PINCTRL_PULL3_BANK3_PIN18 (1 << 18) +#define PINCTRL_PULL3_BANK3_PIN17 (1 << 17) +#define PINCTRL_PULL3_BANK3_PIN16 (1 << 16) +#define PINCTRL_PULL3_BANK3_PIN15 (1 << 15) +#define PINCTRL_PULL3_BANK3_PIN14 (1 << 14) +#define PINCTRL_PULL3_BANK3_PIN13 (1 << 13) +#define PINCTRL_PULL3_BANK3_PIN12 (1 << 12) +#define PINCTRL_PULL3_BANK3_PIN11 (1 << 11) +#define PINCTRL_PULL3_BANK3_PIN10 (1 << 10) +#define PINCTRL_PULL3_BANK3_PIN09 (1 << 9) +#define PINCTRL_PULL3_BANK3_PIN08 (1 << 8) +#define PINCTRL_PULL3_BANK3_PIN07 (1 << 7) +#define PINCTRL_PULL3_BANK3_PIN06 (1 << 6) +#define PINCTRL_PULL3_BANK3_PIN05 (1 << 5) +#define PINCTRL_PULL3_BANK3_PIN04 (1 << 4) +#define PINCTRL_PULL3_BANK3_PIN03 (1 << 3) +#define PINCTRL_PULL3_BANK3_PIN02 (1 << 2) +#define PINCTRL_PULL3_BANK3_PIN01 (1 << 1) +#define PINCTRL_PULL3_BANK3_PIN00 (1 << 0) + +#define PINCTRL_PULL4_BANK4_PIN20 (1 << 20) +#define PINCTRL_PULL4_BANK4_PIN16 (1 << 16) +#define PINCTRL_PULL4_BANK4_PIN15 (1 << 15) +#define PINCTRL_PULL4_BANK4_PIN14 (1 << 14) +#define PINCTRL_PULL4_BANK4_PIN13 (1 << 13) +#define PINCTRL_PULL4_BANK4_PIN12 (1 << 12) +#define PINCTRL_PULL4_BANK4_PIN11 (1 << 11) +#define PINCTRL_PULL4_BANK4_PIN10 (1 << 10) +#define PINCTRL_PULL4_BANK4_PIN09 (1 << 9) +#define PINCTRL_PULL4_BANK4_PIN08 (1 << 8) +#define PINCTRL_PULL4_BANK4_PIN07 (1 << 7) +#define PINCTRL_PULL4_BANK4_PIN06 (1 << 6) +#define PINCTRL_PULL4_BANK4_PIN05 (1 << 5) +#define PINCTRL_PULL4_BANK4_PIN04 (1 << 4) +#define PINCTRL_PULL4_BANK4_PIN03 (1 << 3) +#define PINCTRL_PULL4_BANK4_PIN02 (1 << 2) +#define PINCTRL_PULL4_BANK4_PIN01 (1 << 1) +#define PINCTRL_PULL4_BANK4_PIN00 (1 << 0) + +#define PINCTRL_PULL5_BANK5_PIN26 (1 << 26) +#define PINCTRL_PULL5_BANK5_PIN23 (1 << 23) +#define PINCTRL_PULL5_BANK5_PIN22 (1 << 22) +#define PINCTRL_PULL5_BANK5_PIN21 (1 << 21) +#define PINCTRL_PULL5_BANK5_PIN20 (1 << 20) +#define PINCTRL_PULL5_BANK5_PIN19 (1 << 19) +#define PINCTRL_PULL5_BANK5_PIN18 (1 << 18) +#define PINCTRL_PULL5_BANK5_PIN17 (1 << 17) +#define PINCTRL_PULL5_BANK5_PIN16 (1 << 16) +#define PINCTRL_PULL5_BANK5_PIN15 (1 << 15) +#define PINCTRL_PULL5_BANK5_PIN14 (1 << 14) +#define PINCTRL_PULL5_BANK5_PIN13 (1 << 13) +#define PINCTRL_PULL5_BANK5_PIN12 (1 << 12) +#define PINCTRL_PULL5_BANK5_PIN11 (1 << 11) +#define PINCTRL_PULL5_BANK5_PIN10 (1 << 10) +#define PINCTRL_PULL5_BANK5_PIN09 (1 << 9) +#define PINCTRL_PULL5_BANK5_PIN08 (1 << 8) +#define PINCTRL_PULL5_BANK5_PIN07 (1 << 7) +#define PINCTRL_PULL5_BANK5_PIN06 (1 << 6) +#define PINCTRL_PULL5_BANK5_PIN05 (1 << 5) +#define PINCTRL_PULL5_BANK5_PIN04 (1 << 4) +#define PINCTRL_PULL5_BANK5_PIN03 (1 << 3) +#define PINCTRL_PULL5_BANK5_PIN02 (1 << 2) +#define PINCTRL_PULL5_BANK5_PIN01 (1 << 1) +#define PINCTRL_PULL5_BANK5_PIN00 (1 << 0) + +#define PINCTRL_PULL6_BANK6_PIN24 (1 << 24) +#define PINCTRL_PULL6_BANK6_PIN23 (1 << 23) +#define PINCTRL_PULL6_BANK6_PIN22 (1 << 22) +#define PINCTRL_PULL6_BANK6_PIN21 (1 << 21) +#define PINCTRL_PULL6_BANK6_PIN20 (1 << 20) +#define PINCTRL_PULL6_BANK6_PIN19 (1 << 19) +#define PINCTRL_PULL6_BANK6_PIN18 (1 << 18) +#define PINCTRL_PULL6_BANK6_PIN17 (1 << 17) +#define PINCTRL_PULL6_BANK6_PIN16 (1 << 16) +#define PINCTRL_PULL6_BANK6_PIN14 (1 << 14) +#define PINCTRL_PULL6_BANK6_PIN13 (1 << 13) +#define PINCTRL_PULL6_BANK6_PIN12 (1 << 12) +#define PINCTRL_PULL6_BANK6_PIN11 (1 << 11) +#define PINCTRL_PULL6_BANK6_PIN10 (1 << 10) +#define PINCTRL_PULL6_BANK6_PIN09 (1 << 9) +#define PINCTRL_PULL6_BANK6_PIN08 (1 << 8) +#define PINCTRL_PULL6_BANK6_PIN07 (1 << 7) +#define PINCTRL_PULL6_BANK6_PIN06 (1 << 6) +#define PINCTRL_PULL6_BANK6_PIN05 (1 << 5) +#define PINCTRL_PULL6_BANK6_PIN04 (1 << 4) +#define PINCTRL_PULL6_BANK6_PIN03 (1 << 3) +#define PINCTRL_PULL6_BANK6_PIN02 (1 << 2) +#define PINCTRL_PULL6_BANK6_PIN01 (1 << 1) +#define PINCTRL_PULL6_BANK6_PIN00 (1 << 0) + +#define PINCTRL_DOUT0_DOUT_MASK 0x1fffffff +#define PINCTRL_DOUT0_DOUT_OFFSET 0 + +#define PINCTRL_DOUT1_DOUT_MASK 0xffffffff +#define PINCTRL_DOUT1_DOUT_OFFSET 0 + +#define PINCTRL_DOUT2_DOUT_MASK 0xfffffff +#define PINCTRL_DOUT2_DOUT_OFFSET 0 + +#define PINCTRL_DOUT3_DOUT_MASK 0x7fffffff +#define PINCTRL_DOUT3_DOUT_OFFSET 0 + +#define PINCTRL_DOUT4_DOUT_MASK 0x1fffff +#define PINCTRL_DOUT4_DOUT_OFFSET 0 + +#define PINCTRL_DIN0_DIN_MASK 0x1fffffff +#define PINCTRL_DIN0_DIN_OFFSET 0 + +#define PINCTRL_DIN1_DIN_MASK 0xffffffff +#define PINCTRL_DIN1_DIN_OFFSET 0 + +#define PINCTRL_DIN2_DIN_MASK 0xfffffff +#define PINCTRL_DIN2_DIN_OFFSET 0 + +#define PINCTRL_DIN3_DIN_MASK 0x7fffffff +#define PINCTRL_DIN3_DIN_OFFSET 0 + +#define PINCTRL_DIN4_DIN_MASK 0x1fffff +#define PINCTRL_DIN4_DIN_OFFSET 0 + +#define PINCTRL_DOE0_DOE_MASK 0x1fffffff +#define PINCTRL_DOE0_DOE_OFFSET 0 + +#define PINCTRL_DOE1_DOE_MASK 0xffffffff +#define PINCTRL_DOE1_DOE_OFFSET 0 + +#define PINCTRL_DOE2_DOE_MASK 0xfffffff +#define PINCTRL_DOE2_DOE_OFFSET 0 + +#define PINCTRL_DOE3_DOE_MASK 0x7fffffff +#define PINCTRL_DOE3_DOE_OFFSET 0 + +#define PINCTRL_DOE4_DOE_MASK 0x1fffff +#define PINCTRL_DOE4_DOE_OFFSET 0 + +#define PINCTRL_PIN2IRQ0_PIN2IRQ_MASK 0x1fffffff +#define PINCTRL_PIN2IRQ0_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ1_PIN2IRQ_MASK 0xffffffff +#define PINCTRL_PIN2IRQ1_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ2_PIN2IRQ_MASK 0xfffffff +#define PINCTRL_PIN2IRQ2_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ3_PIN2IRQ_MASK 0x7fffffff +#define PINCTRL_PIN2IRQ3_PIN2IRQ_OFFSET 0 + +#define PINCTRL_PIN2IRQ4_PIN2IRQ_MASK 0x1fffff +#define PINCTRL_PIN2IRQ4_PIN2IRQ_OFFSET 0 + +#define PINCTRL_IRQEN0_IRQEN_MASK 0x1fffffff +#define PINCTRL_IRQEN0_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN1_IRQEN_MASK 0xffffffff +#define PINCTRL_IRQEN1_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN2_IRQEN_MASK 0xfffffff +#define PINCTRL_IRQEN2_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN3_IRQEN_MASK 0x7fffffff +#define PINCTRL_IRQEN3_IRQEN_OFFSET 0 + +#define PINCTRL_IRQEN4_IRQEN_MASK 0x1fffff +#define PINCTRL_IRQEN4_IRQEN_OFFSET 0 + +#define PINCTRL_IRQLEVEL0_IRQLEVEL_MASK 0x1fffffff +#define PINCTRL_IRQLEVEL0_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL1_IRQLEVEL_MASK 0xffffffff +#define PINCTRL_IRQLEVEL1_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL2_IRQLEVEL_MASK 0xfffffff +#define PINCTRL_IRQLEVEL2_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL3_IRQLEVEL_MASK 0x7fffffff +#define PINCTRL_IRQLEVEL3_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQLEVEL4_IRQLEVEL_MASK 0x1fffff +#define PINCTRL_IRQLEVEL4_IRQLEVEL_OFFSET 0 + +#define PINCTRL_IRQPOL0_IRQPOL_MASK 0x1fffffff +#define PINCTRL_IRQPOL0_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL1_IRQPOL_MASK 0xffffffff +#define PINCTRL_IRQPOL1_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL2_IRQPOL_MASK 0xfffffff +#define PINCTRL_IRQPOL2_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL3_IRQPOL_MASK 0x7fffffff +#define PINCTRL_IRQPOL3_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQPOL4_IRQPOL_MASK 0x1fffff +#define PINCTRL_IRQPOL4_IRQPOL_OFFSET 0 + +#define PINCTRL_IRQSTAT0_IRQSTAT_MASK 0x1fffffff +#define PINCTRL_IRQSTAT0_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT1_IRQSTAT_MASK 0xffffffff +#define PINCTRL_IRQSTAT1_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT2_IRQSTAT_MASK 0xfffffff +#define PINCTRL_IRQSTAT2_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT3_IRQSTAT_MASK 0x7fffffff +#define PINCTRL_IRQSTAT3_IRQSTAT_OFFSET 0 + +#define PINCTRL_IRQSTAT4_IRQSTAT_MASK 0x1fffff +#define PINCTRL_IRQSTAT4_IRQSTAT_OFFSET 0 + +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_MASK (0x3 << 26) +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_OFFSET 26 +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_MASK (0x3 << 24) +#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_OFFSET 24 +#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_MASK (0x3 << 22) +#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_OFFSET 22 +#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_MASK (0x3 << 20) +#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_OFFSET 20 +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_MASK (0x3 << 18) +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_OFFSET 18 +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_MASK (0x3 << 16) +#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_OFFSET 16 +#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_MASK (0x3 << 14) +#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_OFFSET 14 +#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_MASK (0x3 << 12) +#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_OFFSET 12 +#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_MASK (0x3 << 10) +#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_OFFSET 10 +#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_MASK (0x3 << 8) +#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_OFFSET 8 +#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_MASK (0x3 << 6) +#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_OFFSET 6 +#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_MASK (0x3 << 4) +#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_OFFSET 4 +#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_MASK (0x3 << 2) +#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_OFFSET 2 +#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_MASK (0x3 << 0) +#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_OFFSET 0 + +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_MASK (0x3 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_OFFSET 16 +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_mDDR (0x0 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_GPIO (0x1 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2 (0x2 << 16) +#define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0x3 << 16) +#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK (0x3 << 12) +#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_OFFSET 12 +#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK (0x3 << 10) +#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_OFFSET 10 +#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK (0x3 << 8) +#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_OFFSET 8 +#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK (0x3 << 6) +#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_OFFSET 6 +#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK (0x3 << 4) +#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_OFFSET 4 +#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK (0x3 << 2) +#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_OFFSET 2 +#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK (0x3 << 0) +#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_OFFSET 0 + +#endif /* __MX28_REGS_PINCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-power.h b/arch/arm/include/asm/arch-mx28/regs-power.h new file mode 100644 index 000000000..9da63adc2 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-power.h @@ -0,0 +1,413 @@ +/* + * Freescale i.MX28 Power Controller Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_POWER_H__ +#define __MX28_REGS_POWER_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_power_regs { + mx28_reg(hw_power_ctrl) + mx28_reg(hw_power_5vctrl) + mx28_reg(hw_power_minpwr) + mx28_reg(hw_power_charge) + uint32_t hw_power_vdddctrl; + uint32_t reserved_vddd[3]; + uint32_t hw_power_vddactrl; + uint32_t reserved_vdda[3]; + uint32_t hw_power_vddioctrl; + uint32_t reserved_vddio[3]; + uint32_t hw_power_vddmemctrl; + uint32_t reserved_vddmem[3]; + uint32_t hw_power_dcdc4p2; + uint32_t reserved_dcdc4p2[3]; + uint32_t hw_power_misc; + uint32_t reserved_misc[3]; + uint32_t hw_power_dclimits; + uint32_t reserved_dclimits[3]; + mx28_reg(hw_power_loopctrl) + uint32_t hw_power_sts; + uint32_t reserved_sts[3]; + mx28_reg(hw_power_speed) + uint32_t hw_power_battmonitor; + uint32_t reserved_battmonitor[3]; + + uint32_t reserved[4]; + + mx28_reg(hw_power_reset) + mx28_reg(hw_power_debug) + mx28_reg(hw_power_thermal) + mx28_reg(hw_power_usb1ctrl) + mx28_reg(hw_power_special) + mx28_reg(hw_power_version) + mx28_reg(hw_power_anaclkctrl) + mx28_reg(hw_power_refctrl) +}; +#endif + +#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) +#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) +#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) +#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) +#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) +#define POWER_CTRL_PSWITCH_IRQ (1 << 20) +#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) +#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) +#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) +#define POWER_CTRL_POLARITY_DC_OK (1 << 16) +#define POWER_CTRL_DC_OK_IRQ (1 << 15) +#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) +#define POWER_CTRL_BATT_BO_IRQ (1 << 13) +#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) +#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) +#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) +#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) +#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) +#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) +#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) +#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) +#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) +#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) +#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) +#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) +#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) + +#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30 +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30) +#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30) +#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) +#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 +#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20) +#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 +#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) +#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 +#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 +#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) +#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) +#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) +#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) +#define POWER_5VCTRL_DCDC_XFER (1 << 5) +#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) +#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) +#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) +#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) +#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) + +#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) +#define POWER_MINPWR_PWD_BO (1 << 12) +#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) +#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) +#define POWER_MINPWR_ENABLE_OSC (1 << 9) +#define POWER_MINPWR_SELECT_OSC (1 << 8) +#define POWER_MINPWR_FBG_OFF (1 << 7) +#define POWER_MINPWR_DOUBLE_FETS (1 << 6) +#define POWER_MINPWR_HALFFETS (1 << 5) +#define POWER_MINPWR_LESSANA_I (1 << 4) +#define POWER_MINPWR_PWD_XTAL24 (1 << 3) +#define POWER_MINPWR_DC_STOPCLK (1 << 2) +#define POWER_MINPWR_EN_DC_PFM (1 << 1) +#define POWER_MINPWR_DC_HALFCLK (1 << 0) + +#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) +#define POWER_CHARGE_ADJ_VOLT_OFFSET 24 +#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) +#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) +#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) +#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) +#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) +#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) +#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) +#define POWER_CHARGE_ENABLE_LOAD (1 << 22) +#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) +#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) +#define POWER_CHARGE_LIION_4P1 (1 << 18) +#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) +#define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13) +#define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12) +#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) +#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 +#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) +#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) +#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) +#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) +#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f +#define POWER_CHARGE_BATTCHRG_I_OFFSET 0 +#define POWER_CHARGE_BATTCHRG_I_10MA 0x01 +#define POWER_CHARGE_BATTCHRG_I_20MA 0x02 +#define POWER_CHARGE_BATTCHRG_I_50MA 0x04 +#define POWER_CHARGE_BATTCHRG_I_100MA 0x08 +#define POWER_CHARGE_BATTCHRG_I_200MA 0x10 +#define POWER_CHARGE_BATTCHRG_I_400MA 0x20 + +#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) +#define POWER_VDDDCTRL_ADJTN_OFFSET 28 +#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) +#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) +#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) +#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) +#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 +#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) +#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) +#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDDCTRL_TRG_MASK 0x1f +#define POWER_VDDDCTRL_TRG_OFFSET 0 + +#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) +#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) +#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) +#define POWER_VDDACTRL_DISABLE_FET (1 << 16) +#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 +#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) +#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) +#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDACTRL_TRG_MASK 0x1f +#define POWER_VDDACTRL_TRG_OFFSET 0 + +#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) +#define POWER_VDDIOCTRL_ADJTN_OFFSET 20 +#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) +#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) +#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) +#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 +#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) +#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) +#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) +#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 +#define POWER_VDDIOCTRL_TRG_MASK 0x1f +#define POWER_VDDIOCTRL_TRG_OFFSET 0 + +#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) +#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) +#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) +#define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5) +#define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5 +#define POWER_VDDMEMCTRL_TRG_MASK 0x1f +#define POWER_VDDMEMCTRL_TRG_OFFSET 0 + +#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 +#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) +#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) +#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) +#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 +#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) +#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) +#define POWER_DCDC4P2_HYST_DIR (1 << 21) +#define POWER_DCDC4P2_HYST_THRESH (1 << 20) +#define POWER_DCDC4P2_TRG_MASK (0x7 << 16) +#define POWER_DCDC4P2_TRG_OFFSET 16 +#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) +#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) +#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) +#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) +#define POWER_DCDC4P2_TRG_BATT (0x4 << 16) +#define POWER_DCDC4P2_BO_MASK (0x1f << 8) +#define POWER_DCDC4P2_BO_OFFSET 8 +#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f +#define POWER_DCDC4P2_CMPTRIP_OFFSET 0 + +#define POWER_MISC_FREQSEL_MASK (0x7 << 4) +#define POWER_MISC_FREQSEL_OFFSET 4 +#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) +#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) +#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) +#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) +#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) +#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) +#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) +#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) +#define POWER_MISC_DELAY_TIMING (1 << 2) +#define POWER_MISC_TEST (1 << 1) +#define POWER_MISC_SEL_PLLCLK (1 << 0) + +#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) +#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 +#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f +#define POWER_DCLIMITS_NETLIMIT_OFFSET 0 + +#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) +#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) +#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) +#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) +#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) +#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) +#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) +#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 +#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) +#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) +#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) +#define POWER_LOOPCTRL_DC_FF_OFFSET 8 +#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) +#define POWER_LOOPCTRL_DC_R_OFFSET 4 +#define POWER_LOOPCTRL_DC_C_MASK 0x3 +#define POWER_LOOPCTRL_DC_C_OFFSET 0 +#define POWER_LOOPCTRL_DC_C_MAX 0x0 +#define POWER_LOOPCTRL_DC_C_2X 0x1 +#define POWER_LOOPCTRL_DC_C_4X 0x2 +#define POWER_LOOPCTRL_DC_C_MIN 0x3 + +#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) +#define POWER_STS_PWRUP_SOURCE_OFFSET 24 +#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) +#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) +#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) +#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) +#define POWER_STS_PSWITCH_MASK (0x3 << 20) +#define POWER_STS_PSWITCH_OFFSET 20 +#define POWER_STS_THERMAL_WARNING (1 << 19) +#define POWER_STS_VDDMEM_BO (1 << 18) +#define POWER_STS_AVALID0_STATUS (1 << 17) +#define POWER_STS_BVALID0_STATUS (1 << 16) +#define POWER_STS_VBUSVALID0_STATUS (1 << 15) +#define POWER_STS_SESSEND0_STATUS (1 << 14) +#define POWER_STS_BATT_BO (1 << 13) +#define POWER_STS_VDD5V_FAULT (1 << 12) +#define POWER_STS_CHRGSTS (1 << 11) +#define POWER_STS_DCDC_4P2_BO (1 << 10) +#define POWER_STS_DC_OK (1 << 9) +#define POWER_STS_VDDIO_BO (1 << 8) +#define POWER_STS_VDDA_BO (1 << 7) +#define POWER_STS_VDDD_BO (1 << 6) +#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) +#define POWER_STS_VDD5V_DROOP (1 << 4) +#define POWER_STS_AVALID0 (1 << 3) +#define POWER_STS_BVALID0 (1 << 2) +#define POWER_STS_VBUSVALID0 (1 << 1) +#define POWER_STS_SESSEND0 (1 << 0) + +#define POWER_SPEED_STATUS_MASK (0xffff << 8) +#define POWER_SPEED_STATUS_OFFSET 8 +#define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6) +#define POWER_SPEED_STATUS_SEL_OFFSET 6 +#define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6) +#define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6) +#define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6) +#define POWER_SPEED_CTRL_MASK 0x3 +#define POWER_SPEED_CTRL_OFFSET 0 +#define POWER_SPEED_CTRL_SS_OFF 0x0 +#define POWER_SPEED_CTRL_SS_ON 0x1 +#define POWER_SPEED_CTRL_SS_ENABLE 0x3 + +#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) +#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 +#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11) +#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) +#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) +#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) +#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f +#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 + +#define POWER_RESET_UNLOCK_MASK (0xffff << 16) +#define POWER_RESET_UNLOCK_OFFSET 16 +#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) +#define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2) +#define POWER_RESET_PWD_OFF (1 << 1) +#define POWER_RESET_PWD (1 << 0) + +#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) +#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) +#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) +#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) + +#define POWER_THERMAL_TEST (1 << 8) +#define POWER_THERMAL_PWD (1 << 7) +#define POWER_THERMAL_LOW_POWER (1 << 6) +#define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4) +#define POWER_THERMAL_OFFSET_ADJ_OFFSET 4 +#define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3) +#define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7 +#define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0 + +#define POWER_USB1CTRL_AVALID1 (1 << 3) +#define POWER_USB1CTRL_BVALID1 (1 << 2) +#define POWER_USB1CTRL_VBUSVALID1 (1 << 1) +#define POWER_USB1CTRL_SESSEND1 (1 << 0) + +#define POWER_SPECIAL_TEST_MASK 0xffffffff +#define POWER_SPECIAL_TEST_OFFSET 0 + +#define POWER_VERSION_MAJOR_MASK (0xff << 24) +#define POWER_VERSION_MAJOR_OFFSET 24 +#define POWER_VERSION_MINOR_MASK (0xff << 16) +#define POWER_VERSION_MINOR_OFFSET 16 +#define POWER_VERSION_STEP_MASK 0xffff +#define POWER_VERSION_STEP_OFFSET 0 + +#define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31) +#define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28) +#define POWER_ANACLKCTRL_OUTDIV_OFFSET 28 +#define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27) +#define POWER_ANACLKCTRL_CLKGATE_I (1 << 26) +#define POWER_ANACLKCTRL_DITHER_OFF (1 << 10) +#define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9) +#define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8) +#define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4) +#define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4 +#define POWER_ANACLKCTRL_INDIV_MASK 0x7 +#define POWER_ANACLKCTRL_INDIV_OFFSET 0 + +#define POWER_REFCTRL_FASTSETTLING (1 << 26) +#define POWER_REFCTRL_RAISE_REF (1 << 25) +#define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24) +#define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20) +#define POWER_REFCTRL_VBG_ADJ_OFFSET 20 +#define POWER_REFCTRL_LOW_PWR (1 << 19) +#define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16) +#define POWER_REFCTRL_BIAS_CTRL_OFFSET 16 +#define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14) +#define POWER_REFCTRL_ADJ_ANA (1 << 13) +#define POWER_REFCTRL_ADJ_VAG (1 << 12) +#define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8) +#define POWER_REFCTRL_ANA_REFVAL_OFFSET 8 +#define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4) +#define POWER_REFCTRL_VAG_VAL_OFFSET 4 + +#endif /* __MX28_REGS_POWER_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-rtc.h b/arch/arm/include/asm/arch-mx28/regs-rtc.h new file mode 100644 index 000000000..fe2fda965 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-rtc.h @@ -0,0 +1,147 @@ +/* + * Freescale i.MX28 RTC Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_RTC_H__ +#define __MX28_REGS_RTC_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_rtc_regs { + mx28_reg(hw_rtc_ctrl) + mx28_reg(hw_rtc_stat) + mx28_reg(hw_rtc_milliseconds) + mx28_reg(hw_rtc_seconds) + mx28_reg(hw_rtc_rtc_alarm) + mx28_reg(hw_rtc_watchdog) + mx28_reg(hw_rtc_persistent0) + mx28_reg(hw_rtc_persistent1) + mx28_reg(hw_rtc_persistent2) + mx28_reg(hw_rtc_persistent3) + mx28_reg(hw_rtc_persistent4) + mx28_reg(hw_rtc_persistent5) + mx28_reg(hw_rtc_debug) + mx28_reg(hw_rtc_version) +}; +#endif + +#define RTC_CTRL_SFTRST (1 << 31) +#define RTC_CTRL_CLKGATE (1 << 30) +#define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6) +#define RTC_CTRL_FORCE_UPDATE (1 << 5) +#define RTC_CTRL_WATCHDOGEN (1 << 4) +#define RTC_CTRL_ONEMSEC_IRQ (1 << 3) +#define RTC_CTRL_ALARM_IRQ (1 << 2) +#define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1) +#define RTC_CTRL_ALARM_IRQ_EN (1 << 0) + +#define RTC_STAT_RTC_PRESENT (1 << 31) +#define RTC_STAT_ALARM_PRESENT (1 << 30) +#define RTC_STAT_WATCHDOG_PRESENT (1 << 29) +#define RTC_STAT_XTAL32000_PRESENT (1 << 28) +#define RTC_STAT_XTAL32768_PRESENT (1 << 27) +#define RTC_STAT_STALE_REGS_MASK (0xff << 16) +#define RTC_STAT_STALE_REGS_OFFSET 16 +#define RTC_STAT_NEW_REGS_MASK (0xff << 8) +#define RTC_STAT_NEW_REGS_OFFSET 8 + +#define RTC_MILLISECONDS_COUNT_MASK 0xffffffff +#define RTC_MILLISECONDS_COUNT_OFFSET 0 + +#define RTC_SECONDS_COUNT_MASK 0xffffffff +#define RTC_SECONDS_COUNT_OFFSET 0 + +#define RTC_ALARM_VALUE_MASK 0xffffffff +#define RTC_ALARM_VALUE_OFFSET 0 + +#define RTC_WATCHDOG_COUNT_MASK 0xffffffff +#define RTC_WATCHDOG_COUNT_OFFSET 0 + +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28 +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28) +#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28) +#define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21) +#define RTC_PERSISTENT0_THERMAL_RESET (1 << 20) +#define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18) +#define RTC_PERSISTENT0_AUTO_RESTART (1 << 17) +#define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16) +#define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14) +#define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14 +#define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14) +#define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14) +#define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14) +#define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13) +#define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8) +#define RTC_PERSISTENT0_MSEC_RES_OFFSET 8 +#define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8) +#define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8) +#define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8) +#define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8) +#define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8) +#define RTC_PERSISTENT0_ALARM_WAKE (1 << 7) +#define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6) +#define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5) +#define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4) +#define RTC_PERSISTENT0_LCK_SECS (1 << 3) +#define RTC_PERSISTENT0_ALARM_EN (1 << 2) +#define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1) +#define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0) + +#define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT1_GENERAL_OFFSET 0 +#define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080 +#define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100 +#define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200 +#define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400 +#define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800 +#define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000 + +#define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT2_GENERAL_OFFSET 0 + +#define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT3_GENERAL_OFFSET 0 + +#define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT4_GENERAL_OFFSET 0 + +#define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff +#define RTC_PERSISTENT5_GENERAL_OFFSET 0 + +#define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1) +#define RTC_DEBUG_WATCHDOG_RESET (1 << 0) + +#define RTC_VERSION_MAJOR_MASK (0xff << 24) +#define RTC_VERSION_MAJOR_OFFSET 24 +#define RTC_VERSION_MINOR_MASK (0xff << 16) +#define RTC_VERSION_MINOR_OFFSET 16 +#define RTC_VERSION_STEP_MASK 0xffff +#define RTC_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_RTC_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-ssp.h b/arch/arm/include/asm/arch-mx28/regs-ssp.h new file mode 100644 index 000000000..ab3870c14 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-ssp.h @@ -0,0 +1,349 @@ +/* + * Freescale i.MX28 SSP Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_SSP_H__ +#define __MX28_REGS_SSP_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_ssp_regs { + mx28_reg(hw_ssp_ctrl0) + mx28_reg(hw_ssp_cmd0) + mx28_reg(hw_ssp_cmd1) + mx28_reg(hw_ssp_xfer_size) + mx28_reg(hw_ssp_block_size) + mx28_reg(hw_ssp_compref) + mx28_reg(hw_ssp_compmask) + mx28_reg(hw_ssp_timing) + mx28_reg(hw_ssp_ctrl1) + mx28_reg(hw_ssp_data) + mx28_reg(hw_ssp_sdresp0) + mx28_reg(hw_ssp_sdresp1) + mx28_reg(hw_ssp_sdresp2) + mx28_reg(hw_ssp_sdresp3) + mx28_reg(hw_ssp_ddr_ctrl) + mx28_reg(hw_ssp_dll_ctrl) + mx28_reg(hw_ssp_status) + mx28_reg(hw_ssp_dll_sts) + mx28_reg(hw_ssp_debug) + mx28_reg(hw_ssp_version) +}; +#endif + +#define SSP_CTRL0_SFTRST (1 << 31) +#define SSP_CTRL0_CLKGATE (1 << 30) +#define SSP_CTRL0_RUN (1 << 29) +#define SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) +#define SSP_CTRL0_LOCK_CS (1 << 27) +#define SSP_CTRL0_IGNORE_CRC (1 << 26) +#define SSP_CTRL0_READ (1 << 25) +#define SSP_CTRL0_DATA_XFER (1 << 24) +#define SSP_CTRL0_BUS_WIDTH_MASK (0x3 << 22) +#define SSP_CTRL0_BUS_WIDTH_OFFSET 22 +#define SSP_CTRL0_BUS_WIDTH_ONE_BIT (0x0 << 22) +#define SSP_CTRL0_BUS_WIDTH_FOUR_BIT (0x1 << 22) +#define SSP_CTRL0_BUS_WIDTH_EIGHT_BIT (0x2 << 22) +#define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) +#define SSP_CTRL0_WAIT_FOR_CMD (1 << 20) +#define SSP_CTRL0_LONG_RESP (1 << 19) +#define SSP_CTRL0_CHECK_RESP (1 << 18) +#define SSP_CTRL0_GET_RESP (1 << 17) +#define SSP_CTRL0_ENABLE (1 << 16) + +#define SSP_CMD0_SOFT_TERMINATE (1 << 26) +#define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) +#define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24) +#define SSP_CMD0_BOOT_ACK_EN (1 << 23) +#define SSP_CMD0_SLOW_CLKING_EN (1 << 22) +#define SSP_CMD0_CONT_CLKING_EN (1 << 21) +#define SSP_CMD0_APPEND_8CYC (1 << 20) +#define SSP_CMD0_CMD_MASK 0xff +#define SSP_CMD0_CMD_OFFSET 0 +#define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00 +#define SSP_CMD0_CMD_MMC_SEND_OP_COND 0x01 +#define SSP_CMD0_CMD_MMC_ALL_SEND_CID 0x02 +#define SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR 0x03 +#define SSP_CMD0_CMD_MMC_SET_DSR 0x04 +#define SSP_CMD0_CMD_MMC_RESERVED_5 0x05 +#define SSP_CMD0_CMD_MMC_SWITCH 0x06 +#define SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD 0x07 +#define SSP_CMD0_CMD_MMC_SEND_EXT_CSD 0x08 +#define SSP_CMD0_CMD_MMC_SEND_CSD 0x09 +#define SSP_CMD0_CMD_MMC_SEND_CID 0x0a +#define SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP 0x0b +#define SSP_CMD0_CMD_MMC_STOP_TRANSMISSION 0x0c +#define SSP_CMD0_CMD_MMC_SEND_STATUS 0x0d +#define SSP_CMD0_CMD_MMC_BUSTEST_R 0x0e +#define SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE 0x0f +#define SSP_CMD0_CMD_MMC_SET_BLOCKLEN 0x10 +#define SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK 0x11 +#define SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK 0x12 +#define SSP_CMD0_CMD_MMC_BUSTEST_W 0x13 +#define SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP 0x14 +#define SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT 0x17 +#define SSP_CMD0_CMD_MMC_WRITE_BLOCK 0x18 +#define SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK 0x19 +#define SSP_CMD0_CMD_MMC_PROGRAM_CID 0x1a +#define SSP_CMD0_CMD_MMC_PROGRAM_CSD 0x1b +#define SSP_CMD0_CMD_MMC_SET_WRITE_PROT 0x1c +#define SSP_CMD0_CMD_MMC_CLR_WRITE_PROT 0x1d +#define SSP_CMD0_CMD_MMC_SEND_WRITE_PROT 0x1e +#define SSP_CMD0_CMD_MMC_ERASE_GROUP_START 0x23 +#define SSP_CMD0_CMD_MMC_ERASE_GROUP_END 0x24 +#define SSP_CMD0_CMD_MMC_ERASE 0x26 +#define SSP_CMD0_CMD_MMC_FAST_IO 0x27 +#define SSP_CMD0_CMD_MMC_GO_IRQ_STATE 0x28 +#define SSP_CMD0_CMD_MMC_LOCK_UNLOCK 0x2a +#define SSP_CMD0_CMD_MMC_APP_CMD 0x37 +#define SSP_CMD0_CMD_MMC_GEN_CMD 0x38 +#define SSP_CMD0_CMD_SD_GO_IDLE_STATE 0x00 +#define SSP_CMD0_CMD_SD_ALL_SEND_CID 0x02 +#define SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR 0x03 +#define SSP_CMD0_CMD_SD_SET_DSR 0x04 +#define SSP_CMD0_CMD_SD_IO_SEND_OP_COND 0x05 +#define SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD 0x07 +#define SSP_CMD0_CMD_SD_SEND_CSD 0x09 +#define SSP_CMD0_CMD_SD_SEND_CID 0x0a +#define SSP_CMD0_CMD_SD_STOP_TRANSMISSION 0x0c +#define SSP_CMD0_CMD_SD_SEND_STATUS 0x0d +#define SSP_CMD0_CMD_SD_GO_INACTIVE_STATE 0x0f +#define SSP_CMD0_CMD_SD_SET_BLOCKLEN 0x10 +#define SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK 0x11 +#define SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK 0x12 +#define SSP_CMD0_CMD_SD_WRITE_BLOCK 0x18 +#define SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK 0x19 +#define SSP_CMD0_CMD_SD_PROGRAM_CSD 0x1b +#define SSP_CMD0_CMD_SD_SET_WRITE_PROT 0x1c +#define SSP_CMD0_CMD_SD_CLR_WRITE_PROT 0x1d +#define SSP_CMD0_CMD_SD_SEND_WRITE_PROT 0x1e +#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_START 0x20 +#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_END 0x21 +#define SSP_CMD0_CMD_SD_ERASE_GROUP_START 0x23 +#define SSP_CMD0_CMD_SD_ERASE_GROUP_END 0x24 +#define SSP_CMD0_CMD_SD_ERASE 0x26 +#define SSP_CMD0_CMD_SD_LOCK_UNLOCK 0x2a +#define SSP_CMD0_CMD_SD_IO_RW_DIRECT 0x34 +#define SSP_CMD0_CMD_SD_IO_RW_EXTENDED 0x35 +#define SSP_CMD0_CMD_SD_APP_CMD 0x37 +#define SSP_CMD0_CMD_SD_GEN_CMD 0x38 + +#define SSP_CMD1_CMD_ARG_MASK 0xffffffff +#define SSP_CMD1_CMD_ARG_OFFSET 0 + +#define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff +#define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0 + +#define SSP_BLOCK_SIZE_BLOCK_COUNT_MASK (0xffffff << 4) +#define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4 +#define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf +#define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0 + +#define SSP_COMPREF_REFERENCE_MASK 0xffffffff +#define SSP_COMPREF_REFERENCE_OFFSET 0 + +#define SSP_COMPMASK_MASK_MASK 0xffffffff +#define SSP_COMPMASK_MASK_OFFSET 0 + +#define SSP_TIMING_TIMEOUT_MASK (0xffff << 16) +#define SSP_TIMING_TIMEOUT_OFFSET 16 +#define SSP_TIMING_CLOCK_DIVIDE_MASK (0xff << 8) +#define SSP_TIMING_CLOCK_DIVIDE_OFFSET 8 +#define SSP_TIMING_CLOCK_RATE_MASK 0xff +#define SSP_TIMING_CLOCK_RATE_OFFSET 0 + +#define SSP_CTRL1_SDIO_IRQ (1 << 31) +#define SSP_CTRL1_SDIO_IRQ_EN (1 << 30) +#define SSP_CTRL1_RESP_ERR_IRQ (1 << 29) +#define SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) +#define SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) +#define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) +#define SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) +#define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) +#define SSP_CTRL1_DATA_CRC_IRQ (1 << 23) +#define SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) +#define SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) +#define SSP_CTRL1_FIFO_UNDERRUN_EN (1 << 20) +#define SSP_CTRL1_CEATA_CCS_ERR_IRQ (1 << 19) +#define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN (1 << 18) +#define SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) +#define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) +#define SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) +#define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) +#define SSP_CTRL1_DMA_ENABLE (1 << 13) +#define SSP_CTRL1_CEATA_CCS_ERR_EN (1 << 12) +#define SSP_CTRL1_SLAVE_OUT_DISABLE (1 << 11) +#define SSP_CTRL1_PHASE (1 << 10) +#define SSP_CTRL1_POLARITY (1 << 9) +#define SSP_CTRL1_SLAVE_MODE (1 << 8) +#define SSP_CTRL1_WORD_LENGTH_MASK (0xf << 4) +#define SSP_CTRL1_WORD_LENGTH_OFFSET 4 +#define SSP_CTRL1_WORD_LENGTH_RESERVED0 (0x0 << 4) +#define SSP_CTRL1_WORD_LENGTH_RESERVED1 (0x1 << 4) +#define SSP_CTRL1_WORD_LENGTH_RESERVED2 (0x2 << 4) +#define SSP_CTRL1_WORD_LENGTH_FOUR_BITS (0x3 << 4) +#define SSP_CTRL1_WORD_LENGTH_EIGHT_BITS (0x7 << 4) +#define SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS (0xf << 4) +#define SSP_CTRL1_SSP_MODE_MASK 0xf +#define SSP_CTRL1_SSP_MODE_OFFSET 0 +#define SSP_CTRL1_SSP_MODE_SPI 0x0 +#define SSP_CTRL1_SSP_MODE_SSI 0x1 +#define SSP_CTRL1_SSP_MODE_SD_MMC 0x3 +#define SSP_CTRL1_SSP_MODE_MS 0x4 + +#define SSP_DATA_DATA_MASK 0xffffffff +#define SSP_DATA_DATA_OFFSET 0 + +#define SSP_SDRESP0_RESP0_MASK 0xffffffff +#define SSP_SDRESP0_RESP0_OFFSET 0 + +#define SSP_SDRESP1_RESP1_MASK 0xffffffff +#define SSP_SDRESP1_RESP1_OFFSET 0 + +#define SSP_SDRESP2_RESP2_MASK 0xffffffff +#define SSP_SDRESP2_RESP2_OFFSET 0 + +#define SSP_SDRESP3_RESP3_MASK 0xffffffff +#define SSP_SDRESP3_RESP3_OFFSET 0 + +#define SSP_DDR_CTRL_DMA_BURST_TYPE_MASK (0x3 << 30) +#define SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET 30 +#define SSP_DDR_CTRL_NIBBLE_POS (1 << 1) +#define SSP_DDR_CTRL_TXCLK_DELAY_TYPE (1 << 0) + +#define SSP_DLL_CTRL_REF_UPDATE_INT_MASK (0xf << 28) +#define SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET 28 +#define SSP_DLL_CTRL_SLV_UPDATE_INT_MASK (0xff << 20) +#define SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET 20 +#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3f << 10) +#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET 10 +#define SSP_DLL_CTRL_SLV_OVERRIDE (1 << 9) +#define SSP_DLL_CTRL_GATE_UPDATE (1 << 7) +#define SSP_DLL_CTRL_SLV_DLY_TARGET_MASK (0xf << 3) +#define SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET 3 +#define SSP_DLL_CTRL_SLV_FORCE_UPD (1 << 2) +#define SSP_DLL_CTRL_RESET (1 << 1) +#define SSP_DLL_CTRL_ENABLE (1 << 0) + +#define SSP_STATUS_PRESENT (1 << 31) +#define SSP_STATUS_MS_PRESENT (1 << 30) +#define SSP_STATUS_SD_PRESENT (1 << 29) +#define SSP_STATUS_CARD_DETECT (1 << 28) +#define SSP_STATUS_DMABURST (1 << 22) +#define SSP_STATUS_DMASENSE (1 << 21) +#define SSP_STATUS_DMATERM (1 << 20) +#define SSP_STATUS_DMAREQ (1 << 19) +#define SSP_STATUS_DMAEND (1 << 18) +#define SSP_STATUS_SDIO_IRQ (1 << 17) +#define SSP_STATUS_RESP_CRC_ERR (1 << 16) +#define SSP_STATUS_RESP_ERR (1 << 15) +#define SSP_STATUS_RESP_TIMEOUT (1 << 14) +#define SSP_STATUS_DATA_CRC_ERR (1 << 13) +#define SSP_STATUS_TIMEOUT (1 << 12) +#define SSP_STATUS_RECV_TIMEOUT_STAT (1 << 11) +#define SSP_STATUS_CEATA_CCS_ERR (1 << 10) +#define SSP_STATUS_FIFO_OVRFLW (1 << 9) +#define SSP_STATUS_FIFO_FULL (1 << 8) +#define SSP_STATUS_FIFO_EMPTY (1 << 5) +#define SSP_STATUS_FIFO_UNDRFLW (1 << 4) +#define SSP_STATUS_CMD_BUSY (1 << 3) +#define SSP_STATUS_DATA_BUSY (1 << 2) +#define SSP_STATUS_BUSY (1 << 0) + +#define SSP_DLL_STS_REF_SEL_MASK (0x3f << 8) +#define SSP_DLL_STS_REF_SEL_OFFSET 8 +#define SSP_DLL_STS_SLV_SEL_MASK (0x3f << 2) +#define SSP_DLL_STS_SLV_SEL_OFFSET 2 +#define SSP_DLL_STS_REF_LOCK (1 << 1) +#define SSP_DLL_STS_SLV_LOCK (1 << 0) + +#define SSP_DEBUG_DATACRC_ERR_MASK (0xf << 28) +#define SSP_DEBUG_DATACRC_ERR_OFFSET 28 +#define SSP_DEBUG_DATA_STALL (1 << 27) +#define SSP_DEBUG_DAT_SM_MASK (0x7 << 24) +#define SSP_DEBUG_DAT_SM_OFFSET 24 +#define SSP_DEBUG_DAT_SM_DSM_IDLE (0x0 << 24) +#define SSP_DEBUG_DAT_SM_DSM_WORD (0x2 << 24) +#define SSP_DEBUG_DAT_SM_DSM_CRC1 (0x3 << 24) +#define SSP_DEBUG_DAT_SM_DSM_CRC2 (0x4 << 24) +#define SSP_DEBUG_DAT_SM_DSM_END (0x5 << 24) +#define SSP_DEBUG_MSTK_SM_MASK (0xf << 20) +#define SSP_DEBUG_MSTK_SM_OFFSET 20 +#define SSP_DEBUG_MSTK_SM_MSTK_IDLE (0x0 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_CKON (0x1 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS1 (0x2 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_TPC (0x3 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS2 (0x4 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_HDSHK (0x5 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS3 (0x6 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_RW (0x7 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_CRC1 (0x8 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_CRC2 (0x9 << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_BS0 (0xa << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_END1 (0xb << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_END2W (0xc << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_END2R (0xd << 20) +#define SSP_DEBUG_MSTK_SM_MSTK_DONE (0xe << 20) +#define SSP_DEBUG_CMD_OE (1 << 19) +#define SSP_DEBUG_DMA_SM_MASK (0x7 << 16) +#define SSP_DEBUG_DMA_SM_OFFSET 16 +#define SSP_DEBUG_DMA_SM_DMA_IDLE (0x0 << 16) +#define SSP_DEBUG_DMA_SM_DMA_DMAREQ (0x1 << 16) +#define SSP_DEBUG_DMA_SM_DMA_DMAACK (0x2 << 16) +#define SSP_DEBUG_DMA_SM_DMA_STALL (0x3 << 16) +#define SSP_DEBUG_DMA_SM_DMA_BUSY (0x4 << 16) +#define SSP_DEBUG_DMA_SM_DMA_DONE (0x5 << 16) +#define SSP_DEBUG_DMA_SM_DMA_COUNT (0x6 << 16) +#define SSP_DEBUG_MMC_SM_MASK (0xf << 12) +#define SSP_DEBUG_MMC_SM_OFFSET 12 +#define SSP_DEBUG_MMC_SM_MMC_IDLE (0x0 << 12) +#define SSP_DEBUG_MMC_SM_MMC_CMD (0x1 << 12) +#define SSP_DEBUG_MMC_SM_MMC_TRC (0x2 << 12) +#define SSP_DEBUG_MMC_SM_MMC_RESP (0x3 << 12) +#define SSP_DEBUG_MMC_SM_MMC_RPRX (0x4 << 12) +#define SSP_DEBUG_MMC_SM_MMC_TX (0x5 << 12) +#define SSP_DEBUG_MMC_SM_MMC_CTOK (0x6 << 12) +#define SSP_DEBUG_MMC_SM_MMC_RX (0x7 << 12) +#define SSP_DEBUG_MMC_SM_MMC_CCS (0x8 << 12) +#define SSP_DEBUG_MMC_SM_MMC_PUP (0x9 << 12) +#define SSP_DEBUG_MMC_SM_MMC_WAIT (0xa << 12) +#define SSP_DEBUG_CMD_SM_MASK (0x3 << 10) +#define SSP_DEBUG_CMD_SM_OFFSET 10 +#define SSP_DEBUG_CMD_SM_CSM_IDLE (0x0 << 10) +#define SSP_DEBUG_CMD_SM_CSM_INDEX (0x1 << 10) +#define SSP_DEBUG_CMD_SM_CSM_ARG (0x2 << 10) +#define SSP_DEBUG_CMD_SM_CSM_CRC (0x3 << 10) +#define SSP_DEBUG_SSP_CMD (1 << 9) +#define SSP_DEBUG_SSP_RESP (1 << 8) +#define SSP_DEBUG_SSP_RXD_MASK 0xff +#define SSP_DEBUG_SSP_RXD_OFFSET 0 + +#define SSP_VERSION_MAJOR_MASK (0xff << 24) +#define SSP_VERSION_MAJOR_OFFSET 24 +#define SSP_VERSION_MINOR_MASK (0xff << 16) +#define SSP_VERSION_MINOR_OFFSET 16 +#define SSP_VERSION_STEP_MASK 0xffff +#define SSP_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_SSP_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-timrot.h b/arch/arm/include/asm/arch-mx28/regs-timrot.h new file mode 100644 index 000000000..1b941cf28 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-timrot.h @@ -0,0 +1,171 @@ +/* + * Freescale i.MX28 TIMROT Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_REGS_TIMROT_H__ +#define __MX28_REGS_TIMROT_H__ + +#include <asm/arch/regs-common.h> + +#ifndef __ASSEMBLY__ +struct mx28_timrot_regs { + mx28_reg(hw_timrot_rotctrl) + mx28_reg(hw_timrot_rotcount) + mx28_reg(hw_timrot_timctrl0) + mx28_reg(hw_timrot_running_count0) + mx28_reg(hw_timrot_fixed_count0) + mx28_reg(hw_timrot_match_count0) + mx28_reg(hw_timrot_timctrl1) + mx28_reg(hw_timrot_running_count1) + mx28_reg(hw_timrot_fixed_count1) + mx28_reg(hw_timrot_match_count1) + mx28_reg(hw_timrot_timctrl2) + mx28_reg(hw_timrot_running_count2) + mx28_reg(hw_timrot_fixed_count2) + mx28_reg(hw_timrot_match_count2) + mx28_reg(hw_timrot_timctrl3) + mx28_reg(hw_timrot_running_count3) + mx28_reg(hw_timrot_fixed_count3) + mx28_reg(hw_timrot_match_count3) + mx28_reg(hw_timrot_version) +}; +#endif + +#define TIMROT_ROTCTRL_SFTRST (1 << 31) +#define TIMROT_ROTCTRL_CLKGATE (1 << 30) +#define TIMROT_ROTCTRL_ROTARY_PRESENT (1 << 29) +#define TIMROT_ROTCTRL_TIM3_PRESENT (1 << 28) +#define TIMROT_ROTCTRL_TIM2_PRESENT (1 << 27) +#define TIMROT_ROTCTRL_TIM1_PRESENT (1 << 26) +#define TIMROT_ROTCTRL_TIM0_PRESENT (1 << 25) +#define TIMROT_ROTCTRL_STATE_MASK (0x7 << 22) +#define TIMROT_ROTCTRL_STATE_OFFSET 22 +#define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16) +#define TIMROT_ROTCTRL_DIVIDER_OFFSET 16 +#define TIMROT_ROTCTRL_RELATIVE (1 << 12) +#define TIMROT_ROTCTRL_OVERSAMPLE_MASK (0x3 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_OFFSET 10 +#define TIMROT_ROTCTRL_OVERSAMPLE_8X (0x0 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_4X (0x1 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_2X (0x2 << 10) +#define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) +#define TIMROT_ROTCTRL_POLARITY_B (1 << 9) +#define TIMROT_ROTCTRL_POLARITY_A (1 << 8) +#define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) +#define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 +#define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM1 (0x2 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) +#define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) +#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) +#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) +#define TIMROT_ROTCTRL_SELECT_A_MASK 0xf +#define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 +#define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0 +#define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1 +#define TIMROT_ROTCTRL_SELECT_A_PWM1 0x2 +#define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 +#define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 +#define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 +#define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 +#define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 +#define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 +#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9 +#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa + +#define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff +#define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0 + +#define TIMROT_TIMCTRLn_IRQ (1 << 15) +#define TIMROT_TIMCTRLn_IRQ_EN (1 << 14) +#define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11) +#define TIMROT_TIMCTRLn_POLARITY (1 << 8) +#define TIMROT_TIMCTRLn_UPDATE (1 << 7) +#define TIMROT_TIMCTRLn_RELOAD (1 << 6) +#define TIMROT_TIMCTRLn_PRESCALE_MASK (0x3 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_OFFSET 4 +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1 (0x0 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2 (0x1 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4 (0x2 << 4) +#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8 (0x3 << 4) +#define TIMROT_TIMCTRLn_SELECT_MASK 0xf +#define TIMROT_TIMCTRLn_SELECT_OFFSET 0 +#define TIMROT_TIMCTRLn_SELECT_NEVER_TICK 0x0 +#define TIMROT_TIMCTRLn_SELECT_PWM0 0x1 +#define TIMROT_TIMCTRLn_SELECT_PWM1 0x2 +#define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 +#define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 +#define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 +#define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 +#define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 +#define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 +#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x9 +#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0xa +#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0xb +#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0xc +#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd +#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe +#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf + +#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff +#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 + +#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff +#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 + +#define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff +#define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0 + +#define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16 +#define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x9 << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0xa << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0xb << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0xc << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) +#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) +#define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) + +#define TIMROT_VERSION_MAJOR_MASK (0xff << 24) +#define TIMROT_VERSION_MAJOR_OFFSET 24 +#define TIMROT_VERSION_MINOR_MASK (0xff << 16) +#define TIMROT_VERSION_MINOR_OFFSET 16 +#define TIMROT_VERSION_STEP_MASK 0xffff +#define TIMROT_VERSION_STEP_OFFSET 0 + +#endif /* __MX28_REGS_TIMROT_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-usb.h b/arch/arm/include/asm/arch-mx28/regs-usb.h new file mode 100644 index 000000000..ea61de80d --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-usb.h @@ -0,0 +1,178 @@ +/* + * Freescale i.MX28 USB OTG Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __REGS_USB_H__ +#define __REGS_USB_H__ + +struct mx28_usb_regs { + uint32_t hw_usbctrl_id; /* 0x000 */ + uint32_t hw_usbctrl_hwgeneral; /* 0x004 */ + uint32_t hw_usbctrl_hwhost; /* 0x008 */ + uint32_t hw_usbctrl_hwdevice; /* 0x00c */ + uint32_t hw_usbctrl_hwtxbuf; /* 0x010 */ + uint32_t hw_usbctrl_hwrxbuf; /* 0x014 */ + + uint32_t reserved1[26]; + + uint32_t hw_usbctrl_gptimer0ld; /* 0x080 */ + uint32_t hw_usbctrl_gptimer0ctrl; /* 0x084 */ + uint32_t hw_usbctrl_gptimer1ld; /* 0x088 */ + uint32_t hw_usbctrl_gptimer1ctrl; /* 0x08c */ + uint32_t hw_usbctrl_sbuscfg; /* 0x090 */ + + uint32_t reserved2[27]; + + uint32_t hw_usbctrl_caplength; /* 0x100 */ + uint32_t hw_usbctrl_hcsparams; /* 0x104 */ + uint32_t hw_usbctrl_hccparams; /* 0x108 */ + + uint32_t reserved3[5]; + + uint32_t hw_usbctrl_dciversion; /* 0x120 */ + uint32_t hw_usbctrl_dccparams; /* 0x124 */ + + uint32_t reserved4[6]; + + uint32_t hw_usbctrl_usbcmd; /* 0x140 */ + uint32_t hw_usbctrl_usbsts; /* 0x144 */ + uint32_t hw_usbctrl_usbintr; /* 0x148 */ + uint32_t hw_usbctrl_frindex; /* 0x14c */ + + uint32_t reserved5; + + union { + uint32_t hw_usbctrl_periodiclistbase; /* 0x154 */ + uint32_t hw_usbctrl_deviceaddr; /* 0x154 */ + }; + union { + uint32_t hw_usbctrl_asynclistaddr; /* 0x158 */ + uint32_t hw_usbctrl_endpointlistaddr; /* 0x158 */ + }; + + uint32_t hw_usbctrl_ttctrl; /* 0x15c */ + uint32_t hw_usbctrl_burstsize; /* 0x160 */ + uint32_t hw_usbctrl_txfilltuning; /* 0x164 */ + + uint32_t reserved6; + + uint32_t hw_usbctrl_ic_usb; /* 0x16c */ + uint32_t hw_usbctrl_ulpi; /* 0x170 */ + + uint32_t reserved7; + + uint32_t hw_usbctrl_endptnak; /* 0x178 */ + uint32_t hw_usbctrl_endptnaken; /* 0x17c */ + + uint32_t reserved8; + + uint32_t hw_usbctrl_portsc1; /* 0x184 */ + + uint32_t reserved9[7]; + + uint32_t hw_usbctrl_otgsc; /* 0x1a4 */ + uint32_t hw_usbctrl_usbmode; /* 0x1a8 */ + uint32_t hw_usbctrl_endptsetupstat; /* 0x1ac */ + uint32_t hw_usbctrl_endptprime; /* 0x1b0 */ + uint32_t hw_usbctrl_endptflush; /* 0x1b4 */ + uint32_t hw_usbctrl_endptstat; /* 0x1b8 */ + uint32_t hw_usbctrl_endptcomplete; /* 0x1bc */ + uint32_t hw_usbctrl_endptctrl0; /* 0x1c0 */ + uint32_t hw_usbctrl_endptctrl1; /* 0x1c4 */ + uint32_t hw_usbctrl_endptctrl2; /* 0x1c8 */ + uint32_t hw_usbctrl_endptctrl3; /* 0x1cc */ + uint32_t hw_usbctrl_endptctrl4; /* 0x1d0 */ + uint32_t hw_usbctrl_endptctrl5; /* 0x1d4 */ + uint32_t hw_usbctrl_endptctrl6; /* 0x1d8 */ + uint32_t hw_usbctrl_endptctrl7; /* 0x1dc */ +}; + +#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) + +#define HW_USBCTRL_ID_CIVERSION_OFFSET 29 +#define HW_USBCTRL_ID_CIVERSION_MASK (0x7 << 29) +#define HW_USBCTRL_ID_VERSION_OFFSET 25 +#define HW_USBCTRL_ID_VERSION_MASK (0xf << 25) +#define HW_USBCTRL_ID_REVISION_OFFSET 21 +#define HW_USBCTRL_ID_REVISION_MASK (0xf << 21) +#define HW_USBCTRL_ID_TAG_OFFSET 16 +#define HW_USBCTRL_ID_TAG_MASK (0x1f << 16) +#define HW_USBCTRL_ID_NID_OFFSET 8 +#define HW_USBCTRL_ID_NID_MASK (0x3f << 8) +#define HW_USBCTRL_ID_ID_OFFSET 0 +#define HW_USBCTRL_ID_ID_MASK (0x3f << 0) + +#define HW_USBCTRL_HWGENERAL_SM_OFFSET 9 +#define HW_USBCTRL_HWGENERAL_SM_MASK (0x3 << 9) +#define HW_USBCTRL_HWGENERAL_PHYM_OFFSET 6 +#define HW_USBCTRL_HWGENERAL_PHYM_MASK (0x7 << 6) +#define HW_USBCTRL_HWGENERAL_PHYW_OFFSET 4 +#define HW_USBCTRL_HWGENERAL_PHYW_MASK (0x3 << 4) +#define HW_USBCTRL_HWGENERAL_BWT (1 << 3) +#define HW_USBCTRL_HWGENERAL_CLKC_OFFSET 1 +#define HW_USBCTRL_HWGENERAL_CLKC_MASK (0x3 << 1) +#define HW_USBCTRL_HWGENERAL_RT (1 << 0) + +#define HW_USBCTRL_HWHOST_TTPER_OFFSET 24 +#define HW_USBCTRL_HWHOST_TTPER_MASK (0xff << 24) +#define HW_USBCTRL_HWHOST_TTASY_OFFSET 16 +#define HW_USBCTRL_HWHOST_TTASY_MASK (0xff << 19) +#define HW_USBCTRL_HWHOST_NPORT_OFFSET 1 +#define HW_USBCTRL_HWHOST_NPORT_MASK (0x7 << 1) +#define HW_USBCTRL_HWHOST_HC (1 << 0) + +#define HW_USBCTRL_HWDEVICE_DEVEP_OFFSET 1 +#define HW_USBCTRL_HWDEVICE_DEVEP_MASK (0x1f << 1) +#define HW_USBCTRL_HWDEVICE_DC (1 << 0) + +#define HW_USBCTRL_HWTXBUF_TXLCR (1 << 31) +#define HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET 16 +#define HW_USBCTRL_HWTXBUF_TXCHANADD_MASK (0xff << 16) +#define HW_USBCTRL_HWTXBUF_TXADD_OFFSET 8 +#define HW_USBCTRL_HWTXBUF_TXADD_MASK (0xff << 8) +#define HW_USBCTRL_HWTXBUF_TXBURST_OFFSET 0 +#define HW_USBCTRL_HWTXBUF_TXBURST_MASK 0xff + +#define HW_USBCTRL_HWRXBUF_RXADD_OFFSET 8 +#define HW_USBCTRL_HWRXBUF_RXADD_MASK (0xff << 8) +#define HW_USBCTRL_HWRXBUF_RXBURST_OFFSET 0 +#define HW_USBCTRL_HWRXBUF_RXBURST_MASK 0xff + +#define HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET 0 +#define HW_USBCTRL_GPTIMERLD_GPTLD_MASK 0xffffff + +#define HW_USBCTRL_GPTIMERCTRL_GPTRUN (1 << 31) +#define HW_USBCTRL_GPTIMERCTRL_GPTRST (1 << 30) +#define HW_USBCTRL_GPTIMERCTRL_GPTMODE (1 << 24) +#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET 0 +#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK 0xffffff + +#define HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET 0 +#define HW_USBCTRL_SBUSCFG_AHBBURST_MASK 0x7 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR 0x0 +#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4 0x1 +#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8 0x2 +#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16 0x3 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4 0x5 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8 0x6 +#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16 0x7 + +#endif /* __REGS_USB_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/regs-usbphy.h b/arch/arm/include/asm/arch-mx28/regs-usbphy.h new file mode 100644 index 000000000..e823e1997 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/regs-usbphy.h @@ -0,0 +1,151 @@ +/* + * Freescale i.MX28 USB PHY Register Definitions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __REGS_USBPHY_H__ +#define __REGS_USBPHY_H__ + +struct mx28_usbphy_regs { + mx28_reg(hw_usbphy_pwd) + mx28_reg(hw_usbphy_tx) + mx28_reg(hw_usbphy_rx) + mx28_reg(hw_usbphy_ctrl) + mx28_reg(hw_usbphy_status) + mx28_reg(hw_usbphy_debug) + mx28_reg(hw_usbphy_debug0_status) + mx28_reg(hw_usbphy_debug1) + mx28_reg(hw_usbphy_version) + mx28_reg(hw_usbphy_ip) +}; + +#define USBPHY_PWD_RXPWDRX (1 << 20) +#define USBPHY_PWD_RXPWDDIFF (1 << 19) +#define USBPHY_PWD_RXPWD1PT1 (1 << 18) +#define USBPHY_PWD_RXPWDENV (1 << 17) +#define USBPHY_PWD_TXPWDV2I (1 << 12) +#define USBPHY_PWD_TXPWDIBIAS (1 << 11) +#define USBPHY_PWD_TXPWDFS (1 << 10) + +#define USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET 26 +#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x7 << 26) +#define USBPHY_TX_USBPHY_TX_SYNC_INVERT (1 << 25) +#define USBPHY_TX_USBPHY_TX_SYNC_MUX (1 << 24) +#define USBPHY_TX_TXENCAL45DP (1 << 21) +#define USBPHY_TX_TXCAL45DP_OFFSET 16 +#define USBPHY_TX_TXCAL45DP_MASK (0xf << 16) +#define USBPHY_TX_TXENCAL45DM (1 << 13) +#define USBPHY_TX_TXCAL45DM_OFFSET 8 +#define USBPHY_TX_TXCAL45DM_MASK (0xf << 8) +#define USBPHY_TX_D_CAL_OFFSET 0 +#define USBPHY_TX_D_CAL_MASK 0xf + +#define USBPHY_RX_RXDBYPASS (1 << 22) +#define USBPHY_RX_DISCONADJ_OFFSET 4 +#define USBPHY_RX_DISCONADJ_MASK (0x7 << 4) +#define USBPHY_RX_ENVADJ_OFFSET 0 +#define USBPHY_RX_ENVADJ_MASK 0x7 + +#define USBPHY_CTRL_SFTRST (1 << 31) +#define USBPHY_CTRL_CLKGATE (1 << 30) +#define USBPHY_CTRL_UTMI_SUSPENDM (1 << 29) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0 (1 << 28) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS (1 << 26) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE (1 << 25) +#define USBPHY_CTRL_FSDLL_RST_EN (1 << 24) +#define USBPHY_CTRL_ENVBUSCHG_WKUP (1 << 23) +#define USBPHY_CTRL_ENIDCHG_WKUP (1 << 22) +#define USBPHY_CTRL_ENDPDMCHG_WKUP (1 << 21) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD (1 << 20) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE (1 << 19) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL (1 << 18) +#define USBPHY_CTRL_WAKEUP_IRQ (1 << 17) +#define USBPHY_CTRL_ENIRQWAKEUP (1 << 16) +#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) +#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) +#define USBPHY_CTRL_DATA_ON_LRADC (1 << 13) +#define USBPHY_CTRL_DEVPLUGIN_IRQ (1 << 12) +#define USBPHY_CTRL_ENIRQDEVPLUGIN (1 << 11) +#define USBPHY_CTRL_RESUME_IRQ (1 << 10) +#define USBPHY_CTRL_ENIRQRESUMEDETECT (1 << 9) +#define USBPHY_CTRL_RESUMEIRQSTICKY (1 << 8) +#define USBPHY_CTRL_ENOTGIDDETECT (1 << 7) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY (1 << 5) +#define USBPHY_CTRL_ENDEVPLUGINDETECT (1 << 4) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ (1 << 3) +#define USBPHY_CTRL_ENIRQHOSTDISCON (1 << 2) +#define USBPHY_CTRL_ENHOSTDISCONDETECT (1 << 1) + +#define USBPHY_STATUS_RESUME_STATUS (1 << 10) +#define USBPHY_STATUS_OTGID_STATUS (1 << 8) +#define USBPHY_STATUS_DEVPLUGIN_STATUS (1 << 6) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS (1 << 3) + +#define USBPHY_DEBUG_CLKGATE (1 << 30) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG (1 << 29) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET 25 +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0xf << 25) +#define USBPHY_DEBUG_ENSQUELCHRESET (1 << 24) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET 16 +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1f << 16) +#define USBPHY_DEBUG_ENTX2RXCOUNT (1 << 12) +#define USBPHY_DEBUG_TX2RXCOUNT_OFFSET 8 +#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xf << 8) +#define USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET 4 +#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x3 << 4) +#define USBPHY_DEBUG_HSTPULLDOWN_OFFSET 2 +#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0x3 << 2) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD (1 << 1) +#define USBPHY_DEBUG_OTGIDPIDLOCK (1 << 0) + +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET 26 +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0x3f << 26) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_OFFSET 16 +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_MASK (0x3ff << 16) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_OFFSET 0 +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_MASK 0xffff + +#define USBPHY_DEBUG1_ENTAILADJVD_OFFSET 13 +#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x3 << 13) +#define USBPHY_DEBUG1_ENTX2TX (1 << 12) +#define USBPHY_DEBUG1_DBG_ADDRESS_OFFSET 0 +#define USBPHY_DEBUG1_DBG_ADDRESS_MASK 0xf + +#define USBPHY_VERSION_MAJOR_MASK (0xff << 24) +#define USBPHY_VERSION_MAJOR_OFFSET 24 +#define USBPHY_VERSION_MINOR_MASK (0xff << 16) +#define USBPHY_VERSION_MINOR_OFFSET 16 +#define USBPHY_VERSION_STEP_MASK 0xffff +#define USBPHY_VERSION_STEP_OFFSET 0 + +#define USBPHY_IP_DIV_SEL_OFFSET 23 +#define USBPHY_IP_DIV_SEL_MASK (0x3 << 23) +#define USBPHY_IP_LFR_SEL_OFFSET 21 +#define USBPHY_IP_LFR_SEL_MASK (0x3 << 21) +#define USBPHY_IP_CP_SEL_OFFSET 19 +#define USBPHY_IP_CP_SEL_MASK (0x3 << 19) +#define USBPHY_IP_TSTI_TX_DP (1 << 18) +#define USBPHY_IP_TSTI_TX_DM (1 << 17) +#define USBPHY_IP_ANALOG_TESTMODE (1 << 16) +#define USBPHY_IP_EN_USB_CLKS (1 << 2) +#define USBPHY_IP_PLL_LOCKED (1 << 1) +#define USBPHY_IP_PLL_POWER (1 << 0) + +#endif /* __REGS_USBPHY_H__ */ diff --git a/arch/arm/include/asm/arch-mx28/sys_proto.h b/arch/arm/include/asm/arch-mx28/sys_proto.h new file mode 100644 index 000000000..a226ea484 --- /dev/null +++ b/arch/arm/include/asm/arch-mx28/sys_proto.h @@ -0,0 +1,32 @@ +/* + * Freescale i.MX28 MX28 specific functions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX28_H__ +#define __MX28_H__ + +int mx28_reset_block(struct mx28_register *reg); +int mx28_wait_mask_set(struct mx28_register *reg, uint32_t mask, int timeout); +int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout); + +int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int)); + +#endif /* __MX28_H__ */ diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index afdaa1ce6..0147920e4 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -98,6 +98,12 @@ struct iim_regs { u32 iim_scs3; }; +struct iomuxc_regs { + u32 unused1; + u32 unused2; + u32 gpr; +}; + struct mx3_cpu_type { u8 srev; u32 v; @@ -636,7 +642,6 @@ struct esdc_regs { #define WEIM_BASE 0xb8002000 #define IOMUXC_BASE 0x43FAC000 -#define IOMUXC_GPR (IOMUXC_BASE + 0x8) #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h index ba1c2ffc0..296367948 100644 --- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h @@ -55,7 +55,7 @@ typedef struct t2 { #define OMAP_HSMMC2_BASE 0x480B4000 #define OMAP_HSMMC3_BASE 0x480AD000 -typedef struct hsmmc { +struct hsmmc { unsigned char res1[0x10]; unsigned int sysconfig; /* 0x10 */ unsigned int sysstatus; /* 0x14 */ @@ -77,7 +77,7 @@ typedef struct hsmmc { unsigned int ie; /* 0x134 */ unsigned char res4[0x8]; unsigned int capa; /* 0x140 */ -} hsmmc_t; +}; /* * OMAP HS MMC Bit definitions @@ -182,13 +182,6 @@ typedef struct hsmmc { #define CLK_400KHZ 1 #define CLK_MISC 2 -typedef struct { - unsigned int card_type; - unsigned int version; - unsigned int mode; - unsigned int size; - unsigned int RCA; -} mmc_card_data; #define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) #define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index 45c947d64..c2a9b46cf 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -687,4 +687,27 @@ struct dpll_params { s8 m7; }; +extern struct omap4_prcm_regs *const prcm; +extern const u32 sys_clk_array[8]; + +void scale_vcores(void); +void do_scale_tps62361(u32 reg, u32 volt_mv); +u32 omap_ddr_clk(void); +void do_scale_vcore(u32 vcore_reg, u32 volt_mv); +void setup_sri2c(void); +void setup_post_dividers(u32 *const base, const struct dpll_params *params); +u32 get_sys_clk_index(void); +void enable_basic_clocks(void); +void enable_basic_uboot_clocks(void); +void enable_non_essential_clocks(void); +void do_enable_clocks(u32 *const *clk_domains, + u32 *const *clk_modules_hw_auto, + u32 *const *clk_modules_explicit_en, + u8 wait_for_enable); +const struct dpll_params *get_mpu_dpll_params(void); +const struct dpll_params *get_core_dpll_params(void); +const struct dpll_params *get_per_dpll_params(void); +const struct dpll_params *get_iva_dpll_params(void); +const struct dpll_params *get_usb_dpll_params(void); +const struct dpll_params *get_abe_dpll_params(void); #endif /* _CLOCKS_OMAP4_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h deleted file mode 100644 index 3a549bad5..000000000 --- a/arch/arm/include/asm/arch-omap4/emif.h +++ /dev/null @@ -1,1021 +0,0 @@ -/* - * OMAP44xx EMIF header - * - * Copyright (C) 2009-2010 Texas Instruments, Inc. - * - * Aneesh V <aneesh@ti.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _EMIF_H_ -#define _EMIF_H_ -#include <asm/types.h> -#include <common.h> - -/* Base address */ -#define OMAP44XX_EMIF1 0x4c000000 -#define OMAP44XX_EMIF2 0x4d000000 - -/* Registers shifts and masks */ - -/* EMIF_MOD_ID_REV */ -#define OMAP44XX_REG_SCHEME_SHIFT 30 -#define OMAP44XX_REG_SCHEME_MASK (0x3 << 30) -#define OMAP44XX_REG_MODULE_ID_SHIFT 16 -#define OMAP44XX_REG_MODULE_ID_MASK (0xfff << 16) -#define OMAP44XX_REG_RTL_VERSION_SHIFT 11 -#define OMAP44XX_REG_RTL_VERSION_MASK (0x1f << 11) -#define OMAP44XX_REG_MAJOR_REVISION_SHIFT 8 -#define OMAP44XX_REG_MAJOR_REVISION_MASK (0x7 << 8) -#define OMAP44XX_REG_MINOR_REVISION_SHIFT 0 -#define OMAP44XX_REG_MINOR_REVISION_MASK (0x3f << 0) - -/* STATUS */ -#define OMAP44XX_REG_BE_SHIFT 31 -#define OMAP44XX_REG_BE_MASK (1 << 31) -#define OMAP44XX_REG_DUAL_CLK_MODE_SHIFT 30 -#define OMAP44XX_REG_DUAL_CLK_MODE_MASK (1 << 30) -#define OMAP44XX_REG_FAST_INIT_SHIFT 29 -#define OMAP44XX_REG_FAST_INIT_MASK (1 << 29) -#define OMAP44XX_REG_PHY_DLL_READY_SHIFT 2 -#define OMAP44XX_REG_PHY_DLL_READY_MASK (1 << 2) - -/* SDRAM_CONFIG */ -#define OMAP44XX_REG_SDRAM_TYPE_SHIFT 29 -#define OMAP44XX_REG_SDRAM_TYPE_MASK (0x7 << 29) -#define OMAP44XX_REG_IBANK_POS_SHIFT 27 -#define OMAP44XX_REG_IBANK_POS_MASK (0x3 << 27) -#define OMAP44XX_REG_DDR_TERM_SHIFT 24 -#define OMAP44XX_REG_DDR_TERM_MASK (0x7 << 24) -#define OMAP44XX_REG_DDR2_DDQS_SHIFT 23 -#define OMAP44XX_REG_DDR2_DDQS_MASK (1 << 23) -#define OMAP44XX_REG_DYN_ODT_SHIFT 21 -#define OMAP44XX_REG_DYN_ODT_MASK (0x3 << 21) -#define OMAP44XX_REG_DDR_DISABLE_DLL_SHIFT 20 -#define OMAP44XX_REG_DDR_DISABLE_DLL_MASK (1 << 20) -#define OMAP44XX_REG_SDRAM_DRIVE_SHIFT 18 -#define OMAP44XX_REG_SDRAM_DRIVE_MASK (0x3 << 18) -#define OMAP44XX_REG_CWL_SHIFT 16 -#define OMAP44XX_REG_CWL_MASK (0x3 << 16) -#define OMAP44XX_REG_NARROW_MODE_SHIFT 14 -#define OMAP44XX_REG_NARROW_MODE_MASK (0x3 << 14) -#define OMAP44XX_REG_CL_SHIFT 10 -#define OMAP44XX_REG_CL_MASK (0xf << 10) -#define OMAP44XX_REG_ROWSIZE_SHIFT 7 -#define OMAP44XX_REG_ROWSIZE_MASK (0x7 << 7) -#define OMAP44XX_REG_IBANK_SHIFT 4 -#define OMAP44XX_REG_IBANK_MASK (0x7 << 4) -#define OMAP44XX_REG_EBANK_SHIFT 3 -#define OMAP44XX_REG_EBANK_MASK (1 << 3) -#define OMAP44XX_REG_PAGESIZE_SHIFT 0 -#define OMAP44XX_REG_PAGESIZE_MASK (0x7 << 0) - -/* SDRAM_CONFIG_2 */ -#define OMAP44XX_REG_CS1NVMEN_SHIFT 30 -#define OMAP44XX_REG_CS1NVMEN_MASK (1 << 30) -#define OMAP44XX_REG_EBANK_POS_SHIFT 27 -#define OMAP44XX_REG_EBANK_POS_MASK (1 << 27) -#define OMAP44XX_REG_RDBNUM_SHIFT 4 -#define OMAP44XX_REG_RDBNUM_MASK (0x3 << 4) -#define OMAP44XX_REG_RDBSIZE_SHIFT 0 -#define OMAP44XX_REG_RDBSIZE_MASK (0x7 << 0) - -/* SDRAM_REF_CTRL */ -#define OMAP44XX_REG_INITREF_DIS_SHIFT 31 -#define OMAP44XX_REG_INITREF_DIS_MASK (1 << 31) -#define OMAP44XX_REG_SRT_SHIFT 29 -#define OMAP44XX_REG_SRT_MASK (1 << 29) -#define OMAP44XX_REG_ASR_SHIFT 28 -#define OMAP44XX_REG_ASR_MASK (1 << 28) -#define OMAP44XX_REG_PASR_SHIFT 24 -#define OMAP44XX_REG_PASR_MASK (0x7 << 24) -#define OMAP44XX_REG_REFRESH_RATE_SHIFT 0 -#define OMAP44XX_REG_REFRESH_RATE_MASK (0xffff << 0) - -/* SDRAM_REF_CTRL_SHDW */ -#define OMAP44XX_REG_REFRESH_RATE_SHDW_SHIFT 0 -#define OMAP44XX_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0) - -/* SDRAM_TIM_1 */ -#define OMAP44XX_REG_T_RP_SHIFT 25 -#define OMAP44XX_REG_T_RP_MASK (0xf << 25) -#define OMAP44XX_REG_T_RCD_SHIFT 21 -#define OMAP44XX_REG_T_RCD_MASK (0xf << 21) -#define OMAP44XX_REG_T_WR_SHIFT 17 -#define OMAP44XX_REG_T_WR_MASK (0xf << 17) -#define OMAP44XX_REG_T_RAS_SHIFT 12 -#define OMAP44XX_REG_T_RAS_MASK (0x1f << 12) -#define OMAP44XX_REG_T_RC_SHIFT 6 -#define OMAP44XX_REG_T_RC_MASK (0x3f << 6) -#define OMAP44XX_REG_T_RRD_SHIFT 3 -#define OMAP44XX_REG_T_RRD_MASK (0x7 << 3) -#define OMAP44XX_REG_T_WTR_SHIFT 0 -#define OMAP44XX_REG_T_WTR_MASK (0x7 << 0) - -/* SDRAM_TIM_1_SHDW */ -#define OMAP44XX_REG_T_RP_SHDW_SHIFT 25 -#define OMAP44XX_REG_T_RP_SHDW_MASK (0xf << 25) -#define OMAP44XX_REG_T_RCD_SHDW_SHIFT 21 -#define OMAP44XX_REG_T_RCD_SHDW_MASK (0xf << 21) -#define OMAP44XX_REG_T_WR_SHDW_SHIFT 17 -#define OMAP44XX_REG_T_WR_SHDW_MASK (0xf << 17) -#define OMAP44XX_REG_T_RAS_SHDW_SHIFT 12 -#define OMAP44XX_REG_T_RAS_SHDW_MASK (0x1f << 12) -#define OMAP44XX_REG_T_RC_SHDW_SHIFT 6 -#define OMAP44XX_REG_T_RC_SHDW_MASK (0x3f << 6) -#define OMAP44XX_REG_T_RRD_SHDW_SHIFT 3 -#define OMAP44XX_REG_T_RRD_SHDW_MASK (0x7 << 3) -#define OMAP44XX_REG_T_WTR_SHDW_SHIFT 0 -#define OMAP44XX_REG_T_WTR_SHDW_MASK (0x7 << 0) - -/* SDRAM_TIM_2 */ -#define OMAP44XX_REG_T_XP_SHIFT 28 -#define OMAP44XX_REG_T_XP_MASK (0x7 << 28) -#define OMAP44XX_REG_T_ODT_SHIFT 25 -#define OMAP44XX_REG_T_ODT_MASK (0x7 << 25) -#define OMAP44XX_REG_T_XSNR_SHIFT 16 -#define OMAP44XX_REG_T_XSNR_MASK (0x1ff << 16) -#define OMAP44XX_REG_T_XSRD_SHIFT 6 -#define OMAP44XX_REG_T_XSRD_MASK (0x3ff << 6) -#define OMAP44XX_REG_T_RTP_SHIFT 3 -#define OMAP44XX_REG_T_RTP_MASK (0x7 << 3) -#define OMAP44XX_REG_T_CKE_SHIFT 0 -#define OMAP44XX_REG_T_CKE_MASK (0x7 << 0) - -/* SDRAM_TIM_2_SHDW */ -#define OMAP44XX_REG_T_XP_SHDW_SHIFT 28 -#define OMAP44XX_REG_T_XP_SHDW_MASK (0x7 << 28) -#define OMAP44XX_REG_T_ODT_SHDW_SHIFT 25 -#define OMAP44XX_REG_T_ODT_SHDW_MASK (0x7 << 25) -#define OMAP44XX_REG_T_XSNR_SHDW_SHIFT 16 -#define OMAP44XX_REG_T_XSNR_SHDW_MASK (0x1ff << 16) -#define OMAP44XX_REG_T_XSRD_SHDW_SHIFT 6 -#define OMAP44XX_REG_T_XSRD_SHDW_MASK (0x3ff << 6) -#define OMAP44XX_REG_T_RTP_SHDW_SHIFT 3 -#define OMAP44XX_REG_T_RTP_SHDW_MASK (0x7 << 3) -#define OMAP44XX_REG_T_CKE_SHDW_SHIFT 0 -#define OMAP44XX_REG_T_CKE_SHDW_MASK (0x7 << 0) - -/* SDRAM_TIM_3 */ -#define OMAP44XX_REG_T_CKESR_SHIFT 21 -#define OMAP44XX_REG_T_CKESR_MASK (0x7 << 21) -#define OMAP44XX_REG_ZQ_ZQCS_SHIFT 15 -#define OMAP44XX_REG_ZQ_ZQCS_MASK (0x3f << 15) -#define OMAP44XX_REG_T_TDQSCKMAX_SHIFT 13 -#define OMAP44XX_REG_T_TDQSCKMAX_MASK (0x3 << 13) -#define OMAP44XX_REG_T_RFC_SHIFT 4 -#define OMAP44XX_REG_T_RFC_MASK (0x1ff << 4) -#define OMAP44XX_REG_T_RAS_MAX_SHIFT 0 -#define OMAP44XX_REG_T_RAS_MAX_MASK (0xf << 0) - -/* SDRAM_TIM_3_SHDW */ -#define OMAP44XX_REG_T_CKESR_SHDW_SHIFT 21 -#define OMAP44XX_REG_T_CKESR_SHDW_MASK (0x7 << 21) -#define OMAP44XX_REG_ZQ_ZQCS_SHDW_SHIFT 15 -#define OMAP44XX_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15) -#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_SHIFT 13 -#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13) -#define OMAP44XX_REG_T_RFC_SHDW_SHIFT 4 -#define OMAP44XX_REG_T_RFC_SHDW_MASK (0x1ff << 4) -#define OMAP44XX_REG_T_RAS_MAX_SHDW_SHIFT 0 -#define OMAP44XX_REG_T_RAS_MAX_SHDW_MASK (0xf << 0) - -/* LPDDR2_NVM_TIM */ -#define OMAP44XX_REG_NVM_T_XP_SHIFT 28 -#define OMAP44XX_REG_NVM_T_XP_MASK (0x7 << 28) -#define OMAP44XX_REG_NVM_T_WTR_SHIFT 24 -#define OMAP44XX_REG_NVM_T_WTR_MASK (0x7 << 24) -#define OMAP44XX_REG_NVM_T_RP_SHIFT 20 -#define OMAP44XX_REG_NVM_T_RP_MASK (0xf << 20) -#define OMAP44XX_REG_NVM_T_WRA_SHIFT 16 -#define OMAP44XX_REG_NVM_T_WRA_MASK (0xf << 16) -#define OMAP44XX_REG_NVM_T_RRD_SHIFT 8 -#define OMAP44XX_REG_NVM_T_RRD_MASK (0xff << 8) -#define OMAP44XX_REG_NVM_T_RCDMIN_SHIFT 0 -#define OMAP44XX_REG_NVM_T_RCDMIN_MASK (0xff << 0) - -/* LPDDR2_NVM_TIM_SHDW */ -#define OMAP44XX_REG_NVM_T_XP_SHDW_SHIFT 28 -#define OMAP44XX_REG_NVM_T_XP_SHDW_MASK (0x7 << 28) -#define OMAP44XX_REG_NVM_T_WTR_SHDW_SHIFT 24 -#define OMAP44XX_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24) -#define OMAP44XX_REG_NVM_T_RP_SHDW_SHIFT 20 -#define OMAP44XX_REG_NVM_T_RP_SHDW_MASK (0xf << 20) -#define OMAP44XX_REG_NVM_T_WRA_SHDW_SHIFT 16 -#define OMAP44XX_REG_NVM_T_WRA_SHDW_MASK (0xf << 16) -#define OMAP44XX_REG_NVM_T_RRD_SHDW_SHIFT 8 -#define OMAP44XX_REG_NVM_T_RRD_SHDW_MASK (0xff << 8) -#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_SHIFT 0 -#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0) - -/* PWR_MGMT_CTRL */ -#define OMAP44XX_REG_IDLEMODE_SHIFT 30 -#define OMAP44XX_REG_IDLEMODE_MASK (0x3 << 30) -#define OMAP44XX_REG_PD_TIM_SHIFT 12 -#define OMAP44XX_REG_PD_TIM_MASK (0xf << 12) -#define OMAP44XX_REG_DPD_EN_SHIFT 11 -#define OMAP44XX_REG_DPD_EN_MASK (1 << 11) -#define OMAP44XX_REG_LP_MODE_SHIFT 8 -#define OMAP44XX_REG_LP_MODE_MASK (0x7 << 8) -#define OMAP44XX_REG_SR_TIM_SHIFT 4 -#define OMAP44XX_REG_SR_TIM_MASK (0xf << 4) -#define OMAP44XX_REG_CS_TIM_SHIFT 0 -#define OMAP44XX_REG_CS_TIM_MASK (0xf << 0) - -/* PWR_MGMT_CTRL_SHDW */ -#define OMAP44XX_REG_PD_TIM_SHDW_SHIFT 8 -#define OMAP44XX_REG_PD_TIM_SHDW_MASK (0xf << 8) -#define OMAP44XX_REG_SR_TIM_SHDW_SHIFT 4 -#define OMAP44XX_REG_SR_TIM_SHDW_MASK (0xf << 4) -#define OMAP44XX_REG_CS_TIM_SHDW_SHIFT 0 -#define OMAP44XX_REG_CS_TIM_SHDW_MASK (0xf << 0) - -/* LPDDR2_MODE_REG_DATA */ -#define OMAP44XX_REG_VALUE_0_SHIFT 0 -#define OMAP44XX_REG_VALUE_0_MASK (0x7f << 0) - -/* LPDDR2_MODE_REG_CFG */ -#define OMAP44XX_REG_CS_SHIFT 31 -#define OMAP44XX_REG_CS_MASK (1 << 31) -#define OMAP44XX_REG_REFRESH_EN_SHIFT 30 -#define OMAP44XX_REG_REFRESH_EN_MASK (1 << 30) -#define OMAP44XX_REG_ADDRESS_SHIFT 0 -#define OMAP44XX_REG_ADDRESS_MASK (0xff << 0) - -/* OCP_CONFIG */ -#define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT 24 -#define OMAP44XX_REG_SYS_THRESH_MAX_MASK (0xf << 24) -#define OMAP44XX_REG_MPU_THRESH_MAX_SHIFT 20 -#define OMAP44XX_REG_MPU_THRESH_MAX_MASK (0xf << 20) -#define OMAP44XX_REG_LL_THRESH_MAX_SHIFT 16 -#define OMAP44XX_REG_LL_THRESH_MAX_MASK (0xf << 16) -#define OMAP44XX_REG_PR_OLD_COUNT_SHIFT 0 -#define OMAP44XX_REG_PR_OLD_COUNT_MASK (0xff << 0) - -/* OCP_CFG_VAL_1 */ -#define OMAP44XX_REG_SYS_BUS_WIDTH_SHIFT 30 -#define OMAP44XX_REG_SYS_BUS_WIDTH_MASK (0x3 << 30) -#define OMAP44XX_REG_LL_BUS_WIDTH_SHIFT 28 -#define OMAP44XX_REG_LL_BUS_WIDTH_MASK (0x3 << 28) -#define OMAP44XX_REG_WR_FIFO_DEPTH_SHIFT 8 -#define OMAP44XX_REG_WR_FIFO_DEPTH_MASK (0xff << 8) -#define OMAP44XX_REG_CMD_FIFO_DEPTH_SHIFT 0 -#define OMAP44XX_REG_CMD_FIFO_DEPTH_MASK (0xff << 0) - -/* OCP_CFG_VAL_2 */ -#define OMAP44XX_REG_RREG_FIFO_DEPTH_SHIFT 16 -#define OMAP44XX_REG_RREG_FIFO_DEPTH_MASK (0xff << 16) -#define OMAP44XX_REG_RSD_FIFO_DEPTH_SHIFT 8 -#define OMAP44XX_REG_RSD_FIFO_DEPTH_MASK (0xff << 8) -#define OMAP44XX_REG_RCMD_FIFO_DEPTH_SHIFT 0 -#define OMAP44XX_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0) - -/* IODFT_TLGC */ -#define OMAP44XX_REG_TLEC_SHIFT 16 -#define OMAP44XX_REG_TLEC_MASK (0xffff << 16) -#define OMAP44XX_REG_MT_SHIFT 14 -#define OMAP44XX_REG_MT_MASK (1 << 14) -#define OMAP44XX_REG_ACT_CAP_EN_SHIFT 13 -#define OMAP44XX_REG_ACT_CAP_EN_MASK (1 << 13) -#define OMAP44XX_REG_OPG_LD_SHIFT 12 -#define OMAP44XX_REG_OPG_LD_MASK (1 << 12) -#define OMAP44XX_REG_RESET_PHY_SHIFT 10 -#define OMAP44XX_REG_RESET_PHY_MASK (1 << 10) -#define OMAP44XX_REG_MMS_SHIFT 8 -#define OMAP44XX_REG_MMS_MASK (1 << 8) -#define OMAP44XX_REG_MC_SHIFT 4 -#define OMAP44XX_REG_MC_MASK (0x3 << 4) -#define OMAP44XX_REG_PC_SHIFT 1 -#define OMAP44XX_REG_PC_MASK (0x7 << 1) -#define OMAP44XX_REG_TM_SHIFT 0 -#define OMAP44XX_REG_TM_MASK (1 << 0) - -/* IODFT_CTRL_MISR_RSLT */ -#define OMAP44XX_REG_DQM_TLMR_SHIFT 16 -#define OMAP44XX_REG_DQM_TLMR_MASK (0x3ff << 16) -#define OMAP44XX_REG_CTL_TLMR_SHIFT 0 -#define OMAP44XX_REG_CTL_TLMR_MASK (0x7ff << 0) - -/* IODFT_ADDR_MISR_RSLT */ -#define OMAP44XX_REG_ADDR_TLMR_SHIFT 0 -#define OMAP44XX_REG_ADDR_TLMR_MASK (0x1fffff << 0) - -/* IODFT_DATA_MISR_RSLT_1 */ -#define OMAP44XX_REG_DATA_TLMR_31_0_SHIFT 0 -#define OMAP44XX_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0) - -/* IODFT_DATA_MISR_RSLT_2 */ -#define OMAP44XX_REG_DATA_TLMR_63_32_SHIFT 0 -#define OMAP44XX_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0) - -/* IODFT_DATA_MISR_RSLT_3 */ -#define OMAP44XX_REG_DATA_TLMR_66_64_SHIFT 0 -#define OMAP44XX_REG_DATA_TLMR_66_64_MASK (0x7 << 0) - -/* PERF_CNT_1 */ -#define OMAP44XX_REG_COUNTER1_SHIFT 0 -#define OMAP44XX_REG_COUNTER1_MASK (0xffffffff << 0) - -/* PERF_CNT_2 */ -#define OMAP44XX_REG_COUNTER2_SHIFT 0 -#define OMAP44XX_REG_COUNTER2_MASK (0xffffffff << 0) - -/* PERF_CNT_CFG */ -#define OMAP44XX_REG_CNTR2_MCONNID_EN_SHIFT 31 -#define OMAP44XX_REG_CNTR2_MCONNID_EN_MASK (1 << 31) -#define OMAP44XX_REG_CNTR2_REGION_EN_SHIFT 30 -#define OMAP44XX_REG_CNTR2_REGION_EN_MASK (1 << 30) -#define OMAP44XX_REG_CNTR2_CFG_SHIFT 16 -#define OMAP44XX_REG_CNTR2_CFG_MASK (0xf << 16) -#define OMAP44XX_REG_CNTR1_MCONNID_EN_SHIFT 15 -#define OMAP44XX_REG_CNTR1_MCONNID_EN_MASK (1 << 15) -#define OMAP44XX_REG_CNTR1_REGION_EN_SHIFT 14 -#define OMAP44XX_REG_CNTR1_REGION_EN_MASK (1 << 14) -#define OMAP44XX_REG_CNTR1_CFG_SHIFT 0 -#define OMAP44XX_REG_CNTR1_CFG_MASK (0xf << 0) - -/* PERF_CNT_SEL */ -#define OMAP44XX_REG_MCONNID2_SHIFT 24 -#define OMAP44XX_REG_MCONNID2_MASK (0xff << 24) -#define OMAP44XX_REG_REGION_SEL2_SHIFT 16 -#define OMAP44XX_REG_REGION_SEL2_MASK (0x3 << 16) -#define OMAP44XX_REG_MCONNID1_SHIFT 8 -#define OMAP44XX_REG_MCONNID1_MASK (0xff << 8) -#define OMAP44XX_REG_REGION_SEL1_SHIFT 0 -#define OMAP44XX_REG_REGION_SEL1_MASK (0x3 << 0) - -/* PERF_CNT_TIM */ -#define OMAP44XX_REG_TOTAL_TIME_SHIFT 0 -#define OMAP44XX_REG_TOTAL_TIME_MASK (0xffffffff << 0) - -/* READ_IDLE_CTRL */ -#define OMAP44XX_REG_READ_IDLE_LEN_SHIFT 16 -#define OMAP44XX_REG_READ_IDLE_LEN_MASK (0xf << 16) -#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT 0 -#define OMAP44XX_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0) - -/* READ_IDLE_CTRL_SHDW */ -#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_SHIFT 16 -#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16) -#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0 -#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0) - -/* IRQ_EOI */ -#define OMAP44XX_REG_EOI_SHIFT 0 -#define OMAP44XX_REG_EOI_MASK (1 << 0) - -/* IRQSTATUS_RAW_SYS */ -#define OMAP44XX_REG_DNV_SYS_SHIFT 2 -#define OMAP44XX_REG_DNV_SYS_MASK (1 << 2) -#define OMAP44XX_REG_TA_SYS_SHIFT 1 -#define OMAP44XX_REG_TA_SYS_MASK (1 << 1) -#define OMAP44XX_REG_ERR_SYS_SHIFT 0 -#define OMAP44XX_REG_ERR_SYS_MASK (1 << 0) - -/* IRQSTATUS_RAW_LL */ -#define OMAP44XX_REG_DNV_LL_SHIFT 2 -#define OMAP44XX_REG_DNV_LL_MASK (1 << 2) -#define OMAP44XX_REG_TA_LL_SHIFT 1 -#define OMAP44XX_REG_TA_LL_MASK (1 << 1) -#define OMAP44XX_REG_ERR_LL_SHIFT 0 -#define OMAP44XX_REG_ERR_LL_MASK (1 << 0) - -/* IRQSTATUS_SYS */ - -/* IRQSTATUS_LL */ - -/* IRQENABLE_SET_SYS */ -#define OMAP44XX_REG_EN_DNV_SYS_SHIFT 2 -#define OMAP44XX_REG_EN_DNV_SYS_MASK (1 << 2) -#define OMAP44XX_REG_EN_TA_SYS_SHIFT 1 -#define OMAP44XX_REG_EN_TA_SYS_MASK (1 << 1) -#define OMAP44XX_REG_EN_ERR_SYS_SHIFT 0 -#define OMAP44XX_REG_EN_ERR_SYS_MASK (1 << 0) - -/* IRQENABLE_SET_LL */ -#define OMAP44XX_REG_EN_DNV_LL_SHIFT 2 -#define OMAP44XX_REG_EN_DNV_LL_MASK (1 << 2) -#define OMAP44XX_REG_EN_TA_LL_SHIFT 1 -#define OMAP44XX_REG_EN_TA_LL_MASK (1 << 1) -#define OMAP44XX_REG_EN_ERR_LL_SHIFT 0 -#define OMAP44XX_REG_EN_ERR_LL_MASK (1 << 0) - -/* IRQENABLE_CLR_SYS */ - -/* IRQENABLE_CLR_LL */ - -/* ZQ_CONFIG */ -#define OMAP44XX_REG_ZQ_CS1EN_SHIFT 31 -#define OMAP44XX_REG_ZQ_CS1EN_MASK (1 << 31) -#define OMAP44XX_REG_ZQ_CS0EN_SHIFT 30 -#define OMAP44XX_REG_ZQ_CS0EN_MASK (1 << 30) -#define OMAP44XX_REG_ZQ_DUALCALEN_SHIFT 29 -#define OMAP44XX_REG_ZQ_DUALCALEN_MASK (1 << 29) -#define OMAP44XX_REG_ZQ_SFEXITEN_SHIFT 28 -#define OMAP44XX_REG_ZQ_SFEXITEN_MASK (1 << 28) -#define OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT 18 -#define OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18) -#define OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT 16 -#define OMAP44XX_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16) -#define OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT 0 -#define OMAP44XX_REG_ZQ_REFINTERVAL_MASK (0xffff << 0) - -/* TEMP_ALERT_CONFIG */ -#define OMAP44XX_REG_TA_CS1EN_SHIFT 31 -#define OMAP44XX_REG_TA_CS1EN_MASK (1 << 31) -#define OMAP44XX_REG_TA_CS0EN_SHIFT 30 -#define OMAP44XX_REG_TA_CS0EN_MASK (1 << 30) -#define OMAP44XX_REG_TA_SFEXITEN_SHIFT 28 -#define OMAP44XX_REG_TA_SFEXITEN_MASK (1 << 28) -#define OMAP44XX_REG_TA_DEVWDT_SHIFT 26 -#define OMAP44XX_REG_TA_DEVWDT_MASK (0x3 << 26) -#define OMAP44XX_REG_TA_DEVCNT_SHIFT 24 -#define OMAP44XX_REG_TA_DEVCNT_MASK (0x3 << 24) -#define OMAP44XX_REG_TA_REFINTERVAL_SHIFT 0 -#define OMAP44XX_REG_TA_REFINTERVAL_MASK (0x3fffff << 0) - -/* OCP_ERR_LOG */ -#define OMAP44XX_REG_MADDRSPACE_SHIFT 14 -#define OMAP44XX_REG_MADDRSPACE_MASK (0x3 << 14) -#define OMAP44XX_REG_MBURSTSEQ_SHIFT 11 -#define OMAP44XX_REG_MBURSTSEQ_MASK (0x7 << 11) -#define OMAP44XX_REG_MCMD_SHIFT 8 -#define OMAP44XX_REG_MCMD_MASK (0x7 << 8) -#define OMAP44XX_REG_MCONNID_SHIFT 0 -#define OMAP44XX_REG_MCONNID_MASK (0xff << 0) - -/* DDR_PHY_CTRL_1 */ -#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHIFT 4 -#define OMAP44XX_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4) -#define OMAP44XX_REG_READ_LATENCY_SHIFT 0 -#define OMAP44XX_REG_READ_LATENCY_MASK (0xf << 0) -#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4 -#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4) -#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12 -#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12) - -/* DDR_PHY_CTRL_1_SHDW */ -#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4 -#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4) -#define OMAP44XX_REG_READ_LATENCY_SHDW_SHIFT 0 -#define OMAP44XX_REG_READ_LATENCY_SHDW_MASK (0xf << 0) -#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4 -#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) -#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 -#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) - -/* DDR_PHY_CTRL_2 */ -#define OMAP44XX_REG_DDR_PHY_CTRL_2_SHIFT 0 -#define OMAP44XX_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) - -/* DMM */ -#define OMAP44XX_DMM_LISA_MAP_BASE 0x4E000040 - -/* Memory Adapter (4460 onwards) */ -#define OMAP44XX_MA_LISA_MAP_BASE 0x482AF040 - -/* DMM_LISA_MAP */ -#define OMAP44XX_SYS_ADDR_SHIFT 24 -#define OMAP44XX_SYS_ADDR_MASK (0xff << 24) -#define OMAP44XX_SYS_SIZE_SHIFT 20 -#define OMAP44XX_SYS_SIZE_MASK (0x7 << 20) -#define OMAP44XX_SDRC_INTL_SHIFT 18 -#define OMAP44XX_SDRC_INTL_MASK (0x3 << 18) -#define OMAP44XX_SDRC_ADDRSPC_SHIFT 16 -#define OMAP44XX_SDRC_ADDRSPC_MASK (0x3 << 16) -#define OMAP44XX_SDRC_MAP_SHIFT 8 -#define OMAP44XX_SDRC_MAP_MASK (0x3 << 8) -#define OMAP44XX_SDRC_ADDR_SHIFT 0 -#define OMAP44XX_SDRC_ADDR_MASK (0xff << 0) - -/* DMM_LISA_MAP fields */ -#define DMM_SDRC_MAP_UNMAPPED 0 -#define DMM_SDRC_MAP_EMIF1_ONLY 1 -#define DMM_SDRC_MAP_EMIF2_ONLY 2 -#define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3 - -#define DMM_SDRC_INTL_NONE 0 -#define DMM_SDRC_INTL_128B 1 -#define DMM_SDRC_INTL_256B 2 -#define DMM_SDRC_INTL_512 3 - -#define DMM_SDRC_ADDR_SPC_SDRAM 0 -#define DMM_SDRC_ADDR_SPC_NVM 1 -#define DMM_SDRC_ADDR_SPC_INVALID 2 - -#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\ - (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << OMAP44XX_SDRC_MAP_SHIFT) |\ - (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT) |\ - (DMM_SDRC_INTL_128B << OMAP44XX_SDRC_INTL_SHIFT) |\ - (CONFIG_SYS_SDRAM_BASE << OMAP44XX_SYS_ADDR_SHIFT)) - -#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ - (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ - (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ - (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)) - -#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\ - (DMM_SDRC_MAP_EMIF2_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ - (DMM_SDRC_ADDR_SPC_SDRAM << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ - (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)) - -/* Trap for invalid TILER PAT entries */ -#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\ - (0 << OMAP44XX_SDRC_ADDR_SHIFT) |\ - (DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\ - (DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\ - (DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\ - (0xFF << OMAP44XX_SYS_ADDR_SHIFT)) - - -/* Reg mapping structure */ -struct emif_reg_struct { - u32 emif_mod_id_rev; - u32 emif_status; - u32 emif_sdram_config; - u32 emif_lpddr2_nvm_config; - u32 emif_sdram_ref_ctrl; - u32 emif_sdram_ref_ctrl_shdw; - u32 emif_sdram_tim_1; - u32 emif_sdram_tim_1_shdw; - u32 emif_sdram_tim_2; - u32 emif_sdram_tim_2_shdw; - u32 emif_sdram_tim_3; - u32 emif_sdram_tim_3_shdw; - u32 emif_lpddr2_nvm_tim; - u32 emif_lpddr2_nvm_tim_shdw; - u32 emif_pwr_mgmt_ctrl; - u32 emif_pwr_mgmt_ctrl_shdw; - u32 emif_lpddr2_mode_reg_data; - u32 padding1[1]; - u32 emif_lpddr2_mode_reg_data_es2; - u32 padding11[1]; - u32 emif_lpddr2_mode_reg_cfg; - u32 emif_l3_config; - u32 emif_l3_cfg_val_1; - u32 emif_l3_cfg_val_2; - u32 emif_iodft_tlgc; - u32 padding2[7]; - u32 emif_perf_cnt_1; - u32 emif_perf_cnt_2; - u32 emif_perf_cnt_cfg; - u32 emif_perf_cnt_sel; - u32 emif_perf_cnt_tim; - u32 padding3; - u32 emif_read_idlectrl; - u32 emif_read_idlectrl_shdw; - u32 padding4; - u32 emif_irqstatus_raw_sys; - u32 emif_irqstatus_raw_ll; - u32 emif_irqstatus_sys; - u32 emif_irqstatus_ll; - u32 emif_irqenable_set_sys; - u32 emif_irqenable_set_ll; - u32 emif_irqenable_clr_sys; - u32 emif_irqenable_clr_ll; - u32 padding5; - u32 emif_zq_config; - u32 emif_temp_alert_config; - u32 emif_l3_err_log; - u32 padding6[4]; - u32 emif_ddr_phy_ctrl_1; - u32 emif_ddr_phy_ctrl_1_shdw; - u32 emif_ddr_phy_ctrl_2; -}; - -struct dmm_lisa_map_regs { - u32 dmm_lisa_map_0; - u32 dmm_lisa_map_1; - u32 dmm_lisa_map_2; - u32 dmm_lisa_map_3; -}; - -#define CS0 0 -#define CS1 1 -/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ -#define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */ - -/* - * The period of DDR clk is represented as numerator and denominator for - * better accuracy in integer based calculations. However, if the numerator - * and denominator are very huge there may be chances of overflow in - * calculations. So, as a trade-off keep denominator(and consequently - * numerator) within a limit sacrificing some accuracy - but not much - * If denominator and numerator are already small (such as at 400 MHz) - * no adjustment is needed - */ -#define EMIF_PERIOD_DEN_LIMIT 1000 -/* - * Maximum number of different frequencies supported by EMIF driver - * Determines the number of entries in the pointer array for register - * cache - */ -#define EMIF_MAX_NUM_FREQUENCIES 6 -/* - * Indices into the Addressing Table array. - * One entry each for all the different types of devices with different - * addressing schemes - */ -#define ADDR_TABLE_INDEX64M 0 -#define ADDR_TABLE_INDEX128M 1 -#define ADDR_TABLE_INDEX256M 2 -#define ADDR_TABLE_INDEX512M 3 -#define ADDR_TABLE_INDEX1GS4 4 -#define ADDR_TABLE_INDEX2GS4 5 -#define ADDR_TABLE_INDEX4G 6 -#define ADDR_TABLE_INDEX8G 7 -#define ADDR_TABLE_INDEX1GS2 8 -#define ADDR_TABLE_INDEX2GS2 9 -#define ADDR_TABLE_INDEXMAX 10 - -/* Number of Row bits */ -#define ROW_9 0 -#define ROW_10 1 -#define ROW_11 2 -#define ROW_12 3 -#define ROW_13 4 -#define ROW_14 5 -#define ROW_15 6 -#define ROW_16 7 - -/* Number of Column bits */ -#define COL_8 0 -#define COL_9 1 -#define COL_10 2 -#define COL_11 3 -#define COL_7 4 /*Not supported by OMAP included for completeness */ - -/* Number of Banks*/ -#define BANKS1 0 -#define BANKS2 1 -#define BANKS4 2 -#define BANKS8 3 - -/* Refresh rate in micro seconds x 10 */ -#define T_REFI_15_6 156 -#define T_REFI_7_8 78 -#define T_REFI_3_9 39 - -#define EBANK_CS1_DIS 0 -#define EBANK_CS1_EN 1 - -/* Read Latency used by the device at reset */ -#define RL_BOOT 3 -/* Read Latency for the highest frequency you want to use */ -#define RL_FINAL 6 - -/* Interleaving policies at EMIF level- between banks and Chip Selects */ -#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0 -#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3 - -/* - * Interleaving policy to be used - * Currently set to MAX interleaving for better performance - */ -#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING - -/* State of the core voltage: - * This is important for some parameters such as read idle control and - * ZQ calibration timings. Timings are much stricter when voltage ramp - * is happening compared to when the voltage is stable. - * We need to calculate two sets of values for these parameters and use - * them accordingly - */ -#define LPDDR2_VOLTAGE_STABLE 0 -#define LPDDR2_VOLTAGE_RAMPING 1 - -/* Length of the forced read idle period in terms of cycles */ -#define EMIF_REG_READ_IDLE_LEN_VAL 5 - -/* Interval between forced 'read idles' */ -/* To be used when voltage is changed for DPS/DVFS - 1us */ -#define READ_IDLE_INTERVAL_DVFS (1*1000) -/* - * To be used when voltage is not scaled except by Smart Reflex - * 50us - or maximum value will do - */ -#define READ_IDLE_INTERVAL_NORMAL (50*1000) - - -/* - * Unless voltage is changing due to DVFS one ZQCS command every 50ms should - * be enough. This shoule be enough also in the case when voltage is changing - * due to smart-reflex. - */ -#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000) -/* - * If voltage is changing due to DVFS ZQCS should be performed more - * often(every 50us) - */ -#define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50 - -/* The interval between ZQCL commands as a multiple of ZQCS interval */ -#define REG_ZQ_ZQCL_MULT 4 -/* The interval between ZQINIT commands as a multiple of ZQCL interval */ -#define REG_ZQ_ZQINIT_MULT 3 -/* Enable ZQ Calibration on exiting Self-refresh */ -#define REG_ZQ_SFEXITEN_ENABLE 1 -/* - * ZQ Calibration simultaneously on both chip-selects: - * Needs one calibration resistor per CS - * None of the boards that we know of have this capability - * So disabled by default - */ -#define REG_ZQ_DUALCALEN_DISABLE 0 -/* - * Enable ZQ Calibration by default on CS0. If we are asked to program - * the EMIF there will be something connected to CS0 for sure - */ -#define REG_ZQ_CS0EN_ENABLE 1 - -/* EMIF_PWR_MGMT_CTRL register */ -/* Low power modes */ -#define LP_MODE_DISABLE 0 -#define LP_MODE_CLOCK_STOP 1 -#define LP_MODE_SELF_REFRESH 2 -#define LP_MODE_PWR_DN 3 - -/* REG_DPD_EN */ -#define DPD_DISABLE 0 -#define DPD_ENABLE 1 - -/* Maximum delay before Low Power Modes */ -#define REG_CS_TIM 0xF -#define REG_SR_TIM 0xF -#define REG_PD_TIM 0xF - -/* EMIF_PWR_MGMT_CTRL register */ -#define EMIF_PWR_MGMT_CTRL (\ - ((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHIFT) & OMAP44XX_REG_CS_TIM_MASK)|\ - ((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHIFT) & OMAP44XX_REG_SR_TIM_MASK)|\ - ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\ - ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHIFT) & OMAP44XX_REG_PD_TIM_MASK)|\ - ((LP_MODE_DISABLE << OMAP44XX_REG_LP_MODE_SHIFT)\ - & OMAP44XX_REG_LP_MODE_MASK) |\ - ((DPD_DISABLE << OMAP44XX_REG_DPD_EN_SHIFT)\ - & OMAP44XX_REG_DPD_EN_MASK))\ - -#define EMIF_PWR_MGMT_CTRL_SHDW (\ - ((REG_CS_TIM << OMAP44XX_REG_CS_TIM_SHDW_SHIFT)\ - & OMAP44XX_REG_CS_TIM_SHDW_MASK) |\ - ((REG_SR_TIM << OMAP44XX_REG_SR_TIM_SHDW_SHIFT)\ - & OMAP44XX_REG_SR_TIM_SHDW_MASK) |\ - ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\ - & OMAP44XX_REG_PD_TIM_SHDW_MASK) |\ - ((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\ - & OMAP44XX_REG_PD_TIM_SHDW_MASK)) - -/* EMIF_L3_CONFIG register value */ -#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF -#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000 -/* - * Value of bits 12:31 of DDR_PHY_CTRL_1 register: - * All these fields have magic values dependent on frequency and - * determined by PHY and DLL integration with EMIF. Setting the magic - * values suggested by hw team. - */ -#define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF -#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41 -#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80 -#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF - -/* -* MR1 value: -* Burst length : 8 -* Burst type : sequential -* Wrap : enabled -* nWR : 3(default). EMIF does not do pre-charge. -* : So nWR is don't care -*/ -#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23 - -/* MR2 */ -#define MR2_RL3_WL1 1 -#define MR2_RL4_WL2 2 -#define MR2_RL5_WL2 3 -#define MR2_RL6_WL3 4 - -/* MR10: ZQ calibration codes */ -#define MR10_ZQ_ZQCS 0x56 -#define MR10_ZQ_ZQCL 0xAB -#define MR10_ZQ_ZQINIT 0xFF -#define MR10_ZQ_ZQRESET 0xC3 - -/* TEMP_ALERT_CONFIG */ -#define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */ -#define TEMP_ALERT_CONFIG_DEVCT_1 0 -#define TEMP_ALERT_CONFIG_DEVWDT_32 2 - -/* MR16 value: refresh full array(no partial array self refresh) */ -#define MR16_REF_FULL_ARRAY 0 - -/* - * Maximum number of entries we keep in our array of timing tables - * We need not keep all the speed bins supported by the device - * We need to keep timing tables for only the speed bins that we - * are interested in - */ -#define MAX_NUM_SPEEDBINS 4 - -/* LPDDR2 Densities */ -#define LPDDR2_DENSITY_64Mb 0 -#define LPDDR2_DENSITY_128Mb 1 -#define LPDDR2_DENSITY_256Mb 2 -#define LPDDR2_DENSITY_512Mb 3 -#define LPDDR2_DENSITY_1Gb 4 -#define LPDDR2_DENSITY_2Gb 5 -#define LPDDR2_DENSITY_4Gb 6 -#define LPDDR2_DENSITY_8Gb 7 -#define LPDDR2_DENSITY_16Gb 8 -#define LPDDR2_DENSITY_32Gb 9 - -/* LPDDR2 type */ -#define LPDDR2_TYPE_S4 0 -#define LPDDR2_TYPE_S2 1 -#define LPDDR2_TYPE_NVM 2 - -/* LPDDR2 IO width */ -#define LPDDR2_IO_WIDTH_32 0 -#define LPDDR2_IO_WIDTH_16 1 -#define LPDDR2_IO_WIDTH_8 2 - -/* Mode register numbers */ -#define LPDDR2_MR0 0 -#define LPDDR2_MR1 1 -#define LPDDR2_MR2 2 -#define LPDDR2_MR3 3 -#define LPDDR2_MR4 4 -#define LPDDR2_MR5 5 -#define LPDDR2_MR6 6 -#define LPDDR2_MR7 7 -#define LPDDR2_MR8 8 -#define LPDDR2_MR9 9 -#define LPDDR2_MR10 10 -#define LPDDR2_MR11 11 -#define LPDDR2_MR16 16 -#define LPDDR2_MR17 17 -#define LPDDR2_MR18 18 - -/* MR0 */ -#define LPDDR2_MR0_DAI_SHIFT 0 -#define LPDDR2_MR0_DAI_MASK 1 -#define LPDDR2_MR0_DI_SHIFT 1 -#define LPDDR2_MR0_DI_MASK (1 << 1) -#define LPDDR2_MR0_DNVI_SHIFT 2 -#define LPDDR2_MR0_DNVI_MASK (1 << 2) - -/* MR4 */ -#define MR4_SDRAM_REF_RATE_SHIFT 0 -#define MR4_SDRAM_REF_RATE_MASK 7 -#define MR4_TUF_SHIFT 7 -#define MR4_TUF_MASK (1 << 7) - -/* MR4 SDRAM Refresh Rate field values */ -#define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0 -#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1 -#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2 -#define SDRAM_TEMP_NOMINAL 0x3 -#define SDRAM_TEMP_RESERVED_4 0x4 -#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5 -#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6 -#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7 - -#define LPDDR2_MANUFACTURER_SAMSUNG 1 -#define LPDDR2_MANUFACTURER_QIMONDA 2 -#define LPDDR2_MANUFACTURER_ELPIDA 3 -#define LPDDR2_MANUFACTURER_ETRON 4 -#define LPDDR2_MANUFACTURER_NANYA 5 -#define LPDDR2_MANUFACTURER_HYNIX 6 -#define LPDDR2_MANUFACTURER_MOSEL 7 -#define LPDDR2_MANUFACTURER_WINBOND 8 -#define LPDDR2_MANUFACTURER_ESMT 9 -#define LPDDR2_MANUFACTURER_SPANSION 11 -#define LPDDR2_MANUFACTURER_SST 12 -#define LPDDR2_MANUFACTURER_ZMOS 13 -#define LPDDR2_MANUFACTURER_INTEL 14 -#define LPDDR2_MANUFACTURER_NUMONYX 254 -#define LPDDR2_MANUFACTURER_MICRON 255 - -/* MR8 register fields */ -#define MR8_TYPE_SHIFT 0x0 -#define MR8_TYPE_MASK 0x3 -#define MR8_DENSITY_SHIFT 0x2 -#define MR8_DENSITY_MASK (0xF << 0x2) -#define MR8_IO_WIDTH_SHIFT 0x6 -#define MR8_IO_WIDTH_MASK (0x3 << 0x6) - -struct lpddr2_addressing { - u8 num_banks; - u8 t_REFI_us_x10; - u8 row_sz[2]; /* One entry each for x32 and x16 */ - u8 col_sz[2]; /* One entry each for x32 and x16 */ -}; - -/* Structure for timings from the DDR datasheet */ -struct lpddr2_ac_timings { - u32 max_freq; - u8 RL; - u8 tRPab; - u8 tRCD; - u8 tWR; - u8 tRASmin; - u8 tRRD; - u8 tWTRx2; - u8 tXSR; - u8 tXPx2; - u8 tRFCab; - u8 tRTPx2; - u8 tCKE; - u8 tCKESR; - u8 tZQCS; - u32 tZQCL; - u32 tZQINIT; - u8 tDQSCKMAXx2; - u8 tRASmax; - u8 tFAW; - -}; - -/* - * Min tCK values for some of the parameters: - * If the calculated clock cycles for the respective parameter is - * less than the corresponding min tCK value, we need to set the min - * tCK value. This may happen at lower frequencies. - */ -struct lpddr2_min_tck { - u32 tRL; - u32 tRP_AB; - u32 tRCD; - u32 tWR; - u32 tRAS_MIN; - u32 tRRD; - u32 tWTR; - u32 tXP; - u32 tRTP; - u8 tCKE; - u32 tCKESR; - u32 tFAW; -}; - -struct lpddr2_device_details { - u8 type; - u8 density; - u8 io_width; - u8 manufacturer; -}; - -struct lpddr2_device_timings { - const struct lpddr2_ac_timings **ac_timings; - const struct lpddr2_min_tck *min_tck; -}; - -/* Details of the devices connected to each chip-select of an EMIF instance */ -struct emif_device_details { - const struct lpddr2_device_details *cs0_device_details; - const struct lpddr2_device_details *cs1_device_details; - const struct lpddr2_device_timings *cs0_device_timings; - const struct lpddr2_device_timings *cs1_device_timings; -}; - -/* - * Structure containing shadow of important registers in EMIF - * The calculation function fills in this structure to be later used for - * initialization and DVFS - */ -struct emif_regs { - u32 freq; - u32 sdram_config_init; - u32 sdram_config; - u32 ref_ctrl; - u32 sdram_tim1; - u32 sdram_tim2; - u32 sdram_tim3; - u32 read_idle_ctrl; - u32 zq_config; - u32 temp_alert_config; - u32 emif_ddr_phy_ctlr_1_init; - u32 emif_ddr_phy_ctlr_1; -}; - -/* assert macros */ -#if defined(DEBUG) -#define emif_assert(c) ({ if (!(c)) for (;;); }) -#else -#define emif_assert(c) ({ if (0) hang(); }) -#endif - -#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs); -void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs); -#else -struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, - struct lpddr2_device_details *lpddr2_dev_details); -void emif_get_device_timings(u32 emif_nr, - const struct lpddr2_device_timings **cs0_device_timings, - const struct lpddr2_device_timings **cs1_device_timings); -#endif - -#endif diff --git a/arch/arm/include/asm/arch-omap4/mmc_host_def.h b/arch/arm/include/asm/arch-omap4/mmc_host_def.h index 733d8ed34..74439c9d9 100644 --- a/arch/arm/include/asm/arch-omap4/mmc_host_def.h +++ b/arch/arm/include/asm/arch-omap4/mmc_host_def.h @@ -33,7 +33,7 @@ #define OMAP_HSMMC2_BASE 0x480B4100 #define OMAP_HSMMC3_BASE 0x480AD100 -typedef struct hsmmc { +struct hsmmc { unsigned char res1[0x10]; unsigned int sysconfig; /* 0x10 */ unsigned int sysstatus; /* 0x14 */ @@ -55,7 +55,7 @@ typedef struct hsmmc { unsigned int ie; /* 0x134 */ unsigned char res4[0x8]; unsigned int capa; /* 0x140 */ -} hsmmc_t; +}; /* * OMAP HS MMC Bit definitions @@ -160,13 +160,6 @@ typedef struct hsmmc { #define CLK_400KHZ 1 #define CLK_MISC 2 -typedef struct { - unsigned int card_type; - unsigned int version; - unsigned int mode; - unsigned int size; - unsigned int RCA; -} mmc_card_data; #define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) #define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap.h index 61ebb3d46..e9942574f 100644 --- a/arch/arm/include/asm/arch-omap4/omap4.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -44,7 +44,8 @@ #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000 #define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000 - +#define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START +#define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END /* CONTROL */ #define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000) @@ -57,16 +58,11 @@ /* CONTROL_ID_CODE */ #define CONTROL_ID_CODE 0x4A002204 -/* 4430 */ -#define OMAP4430_CONTROL_ID_CODE_ES1_0 0x0B85202F -#define OMAP4430_CONTROL_ID_CODE_ES2_0 0x1B85202F -#define OMAP4430_CONTROL_ID_CODE_ES2_1 0x3B95C02F -#define OMAP4430_CONTROL_ID_CODE_ES2_2 0x4B95C02F -#define OMAP4430_CONTROL_ID_CODE_ES2_3 0x6B95C02F - -/* 4460 */ -#define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F -#define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F +#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F +#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F +#define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F +#define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F +#define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F /* UART */ #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000) @@ -151,7 +147,7 @@ struct omap4_sys_ctrl_regs { unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */ unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */ unsigned int pad3[260277]; - unsigned int control_pbiaslite; /* 0x4A100600 */ + unsigned int control_pbiaslite; /* 0x4A100600 */ unsigned int pad4[63]; unsigned int control_efuse_1; /* 0x4A100700 */ unsigned int control_efuse_2; /* 0x4A100704 */ @@ -188,16 +184,6 @@ struct control_lpddr2io_regs { #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) #define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14) -/* Silicon revisions */ -#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF -#define OMAP4430_ES1_0 0x44300100 -#define OMAP4430_ES2_0 0x44300200 -#define OMAP4430_ES2_1 0x44300210 -#define OMAP4430_ES2_2 0x44300220 -#define OMAP4430_ES2_3 0x44300230 -#define OMAP4460_ES1_0 0x44600100 -#define OMAP4460_ES1_1 0x44600110 - /* ROM code defines */ /* Boot device */ #define BOOT_DEVICE_MASK 0xFF @@ -205,5 +191,21 @@ struct control_lpddr2io_regs { #define DEV_DESC_PTR_OFFSET 0x4 #define DEV_DATA_PTR_OFFSET 0x18 #define BOOT_MODE_OFFSET 0x8 +#define RESET_REASON_OFFSET 0x9 +#define CH_FLAGS_OFFSET 0xA + +#define CH_FLAGS_CHSETTINGS (0x1 << 0) +#define CH_FLAGS_CHRAM (0x1 << 1) +#define CH_FLAGS_CHFLASH (0x1 << 2) +#define CH_FLAGS_CHMMCSD (0x1 << 3) +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + char *boot_message; + unsigned int mem_boot_descriptor; + unsigned char omap_bootdevice; + unsigned char reset_reason; + unsigned char ch_flags; +}; +#endif #endif diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 1aacbb12e..4146e2181 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -21,7 +21,7 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -#include <asm/arch/omap4.h> +#include <asm/arch/omap.h> #include <asm/arch/clocks.h> #include <asm/io.h> #include <asm/omap_common.h> @@ -32,17 +32,17 @@ struct omap_sysinfo { }; extern const struct omap_sysinfo sysinfo; -extern struct omap4_prcm_regs *const prcm; - void gpmc_init(void); void watchdog_init(void); u32 get_device_type(void); void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); +void set_muxconf_regs_essential(void); void set_muxconf_regs_non_essential(void); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); void set_pl310_ctrl_reg(u32 val); +void omap_rev_string(char *omap_rev_string); void setup_clocks_for_console(void); void prcm_init(void); void bypass_dpll(u32 *const base); @@ -51,7 +51,17 @@ u32 get_sys_clk_freq(void); u32 omap4_ddr_clk(void); void cancel_out(u32 *num, u32 *den, u32 den_limit); void sdram_init(void); -u32 omap4_sdram_size(void); +u32 omap_sdram_size(void); +u32 cortex_rev(void); +void init_omap_revision(void); +void do_io_settings(void); +/* + * This is used to verify if the configuration header + * was executed by Romcode prior to control of transfer + * to the bootloader. SPL is responsible for saving and + * passing this to the u-boot. + */ +extern struct omap_boot_parameters boot_params; static inline u32 running_from_sdram(void) { @@ -64,15 +74,17 @@ static inline u32 running_from_sdram(void) static inline u8 uboot_loaded_by_spl(void) { /* - * Configuration Header is not supported yet, so u-boot init running - * from SDRAM implies that it was loaded by SPL. When this situation - * changes one of these approaches could be taken: - * i. Pass a magic from SPL to U-Boot and U-Boot save it at a known - * location. - * ii. Check the OPP. CH can support only 50% OPP while SPL initializes - * the DPLLs at 100% OPP. + * u-boot can be running from sdram either because of configuration + * Header or by SPL. If because of CH, then the romcode sets the + * CHSETTINGS executed bit to true in the boot parameter structure that + * it passes to the bootloader.This parameter is stored in the ch_flags + * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a + * mandatory section if CH is present. */ - return running_from_sdram(); + if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) + return 0; + else + return running_from_sdram(); } /* * The basic hardware init of OMAP(s_init()) can happen in 4 @@ -86,7 +98,7 @@ static inline u8 uboot_loaded_by_spl(void) * This function finds this context. * Defining as inline may help in compiling out unused functions in SPL */ -static inline u32 omap4_hw_init_context(void) +static inline u32 omap_hw_init_context(void) { #ifdef CONFIG_SPL_BUILD return OMAP_INIT_CONTEXT_SPL; diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h new file mode 100644 index 000000000..fa99f654b --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -0,0 +1,722 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> + * Sricharan R <r.sricharan@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CLOCKS_OMAP5_H_ +#define _CLOCKS_OMAP5_H_ +#include <common.h> + +/* + * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per + * loop, allow for a minimum of 2 ms wait (in reality the wait will be + * much more than that) + */ +#define LDELAY 1000000 + +#define CM_CLKMODE_DPLL_CORE (OMAP54XX_L4_CORE_BASE + 0x4120) +#define CM_CLKMODE_DPLL_PER (OMAP54XX_L4_CORE_BASE + 0x8140) +#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160) +#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100) + +struct omap5_prcm_regs { + /* cm1.ckgen */ + u32 cm_clksel_core; /* 4a004100 */ + u32 pad001[1]; /* 4a004104 */ + u32 cm_clksel_abe; /* 4a004108 */ + u32 pad002[1]; /* 4a00410c */ + u32 cm_dll_ctrl; /* 4a004110 */ + u32 pad003[3]; /* 4a004114 */ + u32 cm_clkmode_dpll_core; /* 4a004120 */ + u32 cm_idlest_dpll_core; /* 4a004124 */ + u32 cm_autoidle_dpll_core; /* 4a004128 */ + u32 cm_clksel_dpll_core; /* 4a00412c */ + u32 cm_div_m2_dpll_core; /* 4a004130 */ + u32 cm_div_m3_dpll_core; /* 4a004134 */ + u32 cm_div_h11_dpll_core; /* 4a004138 */ + u32 cm_div_h12_dpll_core; /* 4a00413c */ + u32 cm_div_h13_dpll_core; /* 4a004140 */ + u32 cm_div_h14_dpll_core; /* 4a004144 */ + u32 cm_ssc_deltamstep_dpll_core; /* 4a004148 */ + u32 cm_ssc_modfreqdiv_dpll_core; /* 4a00414c */ + u32 cm_emu_override_dpll_core; /* 4a004150 */ + + u32 cm_div_h22_dpllcore; /* 4a004154 */ + u32 cm_div_h23_dpll_core; /* 4a004158 */ + u32 pad0041[1]; /* 4a00415c */ + u32 cm_clkmode_dpll_mpu; /* 4a004160 */ + u32 cm_idlest_dpll_mpu; /* 4a004164 */ + u32 cm_autoidle_dpll_mpu; /* 4a004168 */ + u32 cm_clksel_dpll_mpu; /* 4a00416c */ + u32 cm_div_m2_dpll_mpu; /* 4a004170 */ + u32 pad005[5]; /* 4a004174 */ + u32 cm_ssc_deltamstep_dpll_mpu; /* 4a004188 */ + u32 cm_ssc_modfreqdiv_dpll_mpu; /* 4a00418c */ + u32 pad006[3]; /* 4a004190 */ + u32 cm_bypclk_dpll_mpu; /* 4a00419c */ + u32 cm_clkmode_dpll_iva; /* 4a0041a0 */ + u32 cm_idlest_dpll_iva; /* 4a0041a4 */ + u32 cm_autoidle_dpll_iva; /* 4a0041a8 */ + u32 cm_clksel_dpll_iva; /* 4a0041ac */ + u32 pad007[2]; /* 4a0041b0 */ + u32 cm_div_h11_dpll_iva; /* 4a0041b8 */ + u32 cm_div_h12_dpll_iva; /* 4a0041bc */ + u32 pad008[2]; /* 4a0041c0 */ + u32 cm_ssc_deltamstep_dpll_iva; /* 4a0041c8 */ + u32 cm_ssc_modfreqdiv_dpll_iva; /* 4a0041cc */ + u32 pad009[3]; /* 4a0041d0 */ + u32 cm_bypclk_dpll_iva; /* 4a0041dc */ + u32 cm_clkmode_dpll_abe; /* 4a0041e0 */ + u32 cm_idlest_dpll_abe; /* 4a0041e4 */ + u32 cm_autoidle_dpll_abe; /* 4a0041e8 */ + u32 cm_clksel_dpll_abe; /* 4a0041ec */ + u32 cm_div_m2_dpll_abe; /* 4a0041f0 */ + u32 cm_div_m3_dpll_abe; /* 4a0041f4 */ + u32 pad010[4]; /* 4a0041f8 */ + u32 cm_ssc_deltamstep_dpll_abe; /* 4a004208 */ + u32 cm_ssc_modfreqdiv_dpll_abe; /* 4a00420c */ + u32 pad011[4]; /* 4a004210 */ + u32 cm_clkmode_dpll_ddrphy; /* 4a004220 */ + u32 cm_idlest_dpll_ddrphy; /* 4a004224 */ + u32 cm_autoidle_dpll_ddrphy; /* 4a004228 */ + u32 cm_clksel_dpll_ddrphy; /* 4a00422c */ + u32 cm_div_m2_dpll_ddrphy; /* 4a004230 */ + u32 pad012[1]; /* 4a004234 */ + u32 cm_div_h11_dpll_ddrphy; /* 4a004238 */ + u32 cm_div_h12_dpll_ddrphy; /* 4a00423c */ + u32 cm_div_h13_dpll_ddrphy; /* 4a004240 */ + u32 pad013[1]; /* 4a004244 */ + u32 cm_ssc_deltamstep_dpll_ddrphy; /* 4a004248 */ + u32 pad014[5]; /* 4a00424c */ + u32 cm_shadow_freq_config1; /* 4a004260 */ + u32 pad0141[47]; /* 4a004264 */ + u32 cm_mpu_mpu_clkctrl; /* 4a004320 */ + + + /* cm1.dsp */ + u32 pad015[55]; /* 4a004324 */ + u32 cm_dsp_clkstctrl; /* 4a004400 */ + u32 pad016[7]; /* 4a004404 */ + u32 cm_dsp_dsp_clkctrl; /* 4a004420 */ + + /* cm1.abe */ + u32 pad017[55]; /* 4a004424 */ + u32 cm1_abe_clkstctrl; /* 4a004500 */ + u32 pad018[7]; /* 4a004504 */ + u32 cm1_abe_l4abe_clkctrl; /* 4a004520 */ + u32 pad019[1]; /* 4a004524 */ + u32 cm1_abe_aess_clkctrl; /* 4a004528 */ + u32 pad020[1]; /* 4a00452c */ + u32 cm1_abe_pdm_clkctrl; /* 4a004530 */ + u32 pad021[1]; /* 4a004534 */ + u32 cm1_abe_dmic_clkctrl; /* 4a004538 */ + u32 pad022[1]; /* 4a00453c */ + u32 cm1_abe_mcasp_clkctrl; /* 4a004540 */ + u32 pad023[1]; /* 4a004544 */ + u32 cm1_abe_mcbsp1_clkctrl; /* 4a004548 */ + u32 pad024[1]; /* 4a00454c */ + u32 cm1_abe_mcbsp2_clkctrl; /* 4a004550 */ + u32 pad025[1]; /* 4a004554 */ + u32 cm1_abe_mcbsp3_clkctrl; /* 4a004558 */ + u32 pad026[1]; /* 4a00455c */ + u32 cm1_abe_slimbus_clkctrl; /* 4a004560 */ + u32 pad027[1]; /* 4a004564 */ + u32 cm1_abe_timer5_clkctrl; /* 4a004568 */ + u32 pad028[1]; /* 4a00456c */ + u32 cm1_abe_timer6_clkctrl; /* 4a004570 */ + u32 pad029[1]; /* 4a004574 */ + u32 cm1_abe_timer7_clkctrl; /* 4a004578 */ + u32 pad030[1]; /* 4a00457c */ + u32 cm1_abe_timer8_clkctrl; /* 4a004580 */ + u32 pad031[1]; /* 4a004584 */ + u32 cm1_abe_wdt3_clkctrl; /* 4a004588 */ + + /* cm2.ckgen */ + u32 pad032[3805]; /* 4a00458c */ + u32 cm_clksel_mpu_m3_iss_root; /* 4a008100 */ + u32 cm_clksel_usb_60mhz; /* 4a008104 */ + u32 cm_scale_fclk; /* 4a008108 */ + u32 pad033[1]; /* 4a00810c */ + u32 cm_core_dvfs_perf1; /* 4a008110 */ + u32 cm_core_dvfs_perf2; /* 4a008114 */ + u32 cm_core_dvfs_perf3; /* 4a008118 */ + u32 cm_core_dvfs_perf4; /* 4a00811c */ + u32 pad034[1]; /* 4a008120 */ + u32 cm_core_dvfs_current; /* 4a008124 */ + u32 cm_iva_dvfs_perf_tesla; /* 4a008128 */ + u32 cm_iva_dvfs_perf_ivahd; /* 4a00812c */ + u32 cm_iva_dvfs_perf_abe; /* 4a008130 */ + u32 pad035[1]; /* 4a008134 */ + u32 cm_iva_dvfs_current; /* 4a008138 */ + u32 pad036[1]; /* 4a00813c */ + u32 cm_clkmode_dpll_per; /* 4a008140 */ + u32 cm_idlest_dpll_per; /* 4a008144 */ + u32 cm_autoidle_dpll_per; /* 4a008148 */ + u32 cm_clksel_dpll_per; /* 4a00814c */ + u32 cm_div_m2_dpll_per; /* 4a008150 */ + u32 cm_div_m3_dpll_per; /* 4a008154 */ + u32 cm_div_h11_dpll_per; /* 4a008158 */ + u32 cm_div_h12_dpll_per; /* 4a00815c */ + u32 pad0361[1]; /* 4a008160 */ + u32 cm_div_h14_dpll_per; /* 4a008164 */ + u32 cm_ssc_deltamstep_dpll_per; /* 4a008168 */ + u32 cm_ssc_modfreqdiv_dpll_per; /* 4a00816c */ + u32 cm_emu_override_dpll_per; /* 4a008170 */ + u32 pad037[3]; /* 4a008174 */ + u32 cm_clkmode_dpll_usb; /* 4a008180 */ + u32 cm_idlest_dpll_usb; /* 4a008184 */ + u32 cm_autoidle_dpll_usb; /* 4a008188 */ + u32 cm_clksel_dpll_usb; /* 4a00818c */ + u32 cm_div_m2_dpll_usb; /* 4a008190 */ + u32 pad038[5]; /* 4a008194 */ + u32 cm_ssc_deltamstep_dpll_usb; /* 4a0081a8 */ + u32 cm_ssc_modfreqdiv_dpll_usb; /* 4a0081ac */ + u32 pad039[1]; /* 4a0081b0 */ + u32 cm_clkdcoldo_dpll_usb; /* 4a0081b4 */ + u32 pad040[2]; /* 4a0081b8 */ + u32 cm_clkmode_dpll_unipro; /* 4a0081c0 */ + u32 cm_idlest_dpll_unipro; /* 4a0081c4 */ + u32 cm_autoidle_dpll_unipro; /* 4a0081c8 */ + u32 cm_clksel_dpll_unipro; /* 4a0081cc */ + u32 cm_div_m2_dpll_unipro; /* 4a0081d0 */ + u32 pad041[5]; /* 4a0081d4 */ + u32 cm_ssc_deltamstep_dpll_unipro; /* 4a0081e8 */ + u32 cm_ssc_modfreqdiv_dpll_unipro; /* 4a0081ec */ + + /* cm2.core */ + u32 pad0411[324]; /* 4a0081f0 */ + u32 cm_l3_1_clkstctrl; /* 4a008700 */ + u32 pad042[1]; /* 4a008704 */ + u32 cm_l3_1_dynamicdep; /* 4a008708 */ + u32 pad043[5]; /* 4a00870c */ + u32 cm_l3_1_l3_1_clkctrl; /* 4a008720 */ + u32 pad044[55]; /* 4a008724 */ + u32 cm_l3_2_clkstctrl; /* 4a008800 */ + u32 pad045[1]; /* 4a008804 */ + u32 cm_l3_2_dynamicdep; /* 4a008808 */ + u32 pad046[5]; /* 4a00880c */ + u32 cm_l3_2_l3_2_clkctrl; /* 4a008820 */ + u32 pad047[1]; /* 4a008824 */ + u32 cm_l3_2_gpmc_clkctrl; /* 4a008828 */ + u32 pad048[1]; /* 4a00882c */ + u32 cm_l3_2_ocmc_ram_clkctrl; /* 4a008830 */ + u32 pad049[51]; /* 4a008834 */ + u32 cm_mpu_m3_clkstctrl; /* 4a008900 */ + u32 cm_mpu_m3_staticdep; /* 4a008904 */ + u32 cm_mpu_m3_dynamicdep; /* 4a008908 */ + u32 pad050[5]; /* 4a00890c */ + u32 cm_mpu_m3_mpu_m3_clkctrl; /* 4a008920 */ + u32 pad051[55]; /* 4a008924 */ + u32 cm_sdma_clkstctrl; /* 4a008a00 */ + u32 cm_sdma_staticdep; /* 4a008a04 */ + u32 cm_sdma_dynamicdep; /* 4a008a08 */ + u32 pad052[5]; /* 4a008a0c */ + u32 cm_sdma_sdma_clkctrl; /* 4a008a20 */ + u32 pad053[55]; /* 4a008a24 */ + u32 cm_memif_clkstctrl; /* 4a008b00 */ + u32 pad054[7]; /* 4a008b04 */ + u32 cm_memif_dmm_clkctrl; /* 4a008b20 */ + u32 pad055[1]; /* 4a008b24 */ + u32 cm_memif_emif_fw_clkctrl; /* 4a008b28 */ + u32 pad056[1]; /* 4a008b2c */ + u32 cm_memif_emif_1_clkctrl; /* 4a008b30 */ + u32 pad057[1]; /* 4a008b34 */ + u32 cm_memif_emif_2_clkctrl; /* 4a008b38 */ + u32 pad058[1]; /* 4a008b3c */ + u32 cm_memif_dll_clkctrl; /* 4a008b40 */ + u32 pad059[3]; /* 4a008b44 */ + u32 cm_memif_emif_h1_clkctrl; /* 4a008b50 */ + u32 pad060[1]; /* 4a008b54 */ + u32 cm_memif_emif_h2_clkctrl; /* 4a008b58 */ + u32 pad061[1]; /* 4a008b5c */ + u32 cm_memif_dll_h_clkctrl; /* 4a008b60 */ + u32 pad062[39]; /* 4a008b64 */ + u32 cm_c2c_clkstctrl; /* 4a008c00 */ + u32 cm_c2c_staticdep; /* 4a008c04 */ + u32 cm_c2c_dynamicdep; /* 4a008c08 */ + u32 pad063[5]; /* 4a008c0c */ + u32 cm_c2c_sad2d_clkctrl; /* 4a008c20 */ + u32 pad064[1]; /* 4a008c24 */ + u32 cm_c2c_modem_icr_clkctrl; /* 4a008c28 */ + u32 pad065[1]; /* 4a008c2c */ + u32 cm_c2c_sad2d_fw_clkctrl; /* 4a008c30 */ + u32 pad066[51]; /* 4a008c34 */ + u32 cm_l4cfg_clkstctrl; /* 4a008d00 */ + u32 pad067[1]; /* 4a008d04 */ + u32 cm_l4cfg_dynamicdep; /* 4a008d08 */ + u32 pad068[5]; /* 4a008d0c */ + u32 cm_l4cfg_l4_cfg_clkctrl; /* 4a008d20 */ + u32 pad069[1]; /* 4a008d24 */ + u32 cm_l4cfg_hw_sem_clkctrl; /* 4a008d28 */ + u32 pad070[1]; /* 4a008d2c */ + u32 cm_l4cfg_mailbox_clkctrl; /* 4a008d30 */ + u32 pad071[1]; /* 4a008d34 */ + u32 cm_l4cfg_sar_rom_clkctrl; /* 4a008d38 */ + u32 pad072[49]; /* 4a008d3c */ + u32 cm_l3instr_clkstctrl; /* 4a008e00 */ + u32 pad073[7]; /* 4a008e04 */ + u32 cm_l3instr_l3_3_clkctrl; /* 4a008e20 */ + u32 pad074[1]; /* 4a008e24 */ + u32 cm_l3instr_l3_instr_clkctrl; /* 4a008e28 */ + u32 pad075[5]; /* 4a008e2c */ + u32 cm_l3instr_intrconn_wp1_clkctrl; /* 4a008e40 */ + + + /* cm2.ivahd */ + u32 pad076[47]; /* 4a008e44 */ + u32 cm_ivahd_clkstctrl; /* 4a008f00 */ + u32 pad077[7]; /* 4a008f04 */ + u32 cm_ivahd_ivahd_clkctrl; /* 4a008f20 */ + u32 pad078[1]; /* 4a008f24 */ + u32 cm_ivahd_sl2_clkctrl; /* 4a008f28 */ + + /* cm2.cam */ + u32 pad079[53]; /* 4a008f2c */ + u32 cm_cam_clkstctrl; /* 4a009000 */ + u32 pad080[7]; /* 4a009004 */ + u32 cm_cam_iss_clkctrl; /* 4a009020 */ + u32 pad081[1]; /* 4a009024 */ + u32 cm_cam_fdif_clkctrl; /* 4a009028 */ + + /* cm2.dss */ + u32 pad082[53]; /* 4a00902c */ + u32 cm_dss_clkstctrl; /* 4a009100 */ + u32 pad083[7]; /* 4a009104 */ + u32 cm_dss_dss_clkctrl; /* 4a009120 */ + + /* cm2.sgx */ + u32 pad084[55]; /* 4a009124 */ + u32 cm_sgx_clkstctrl; /* 4a009200 */ + u32 pad085[7]; /* 4a009204 */ + u32 cm_sgx_sgx_clkctrl; /* 4a009220 */ + + /* cm2.l3init */ + u32 pad086[55]; /* 4a009224 */ + u32 cm_l3init_clkstctrl; /* 4a009300 */ + + /* cm2.l3init */ + u32 pad087[9]; /* 4a009304 */ + u32 cm_l3init_hsmmc1_clkctrl; /* 4a009328 */ + u32 pad088[1]; /* 4a00932c */ + u32 cm_l3init_hsmmc2_clkctrl; /* 4a009330 */ + u32 pad089[1]; /* 4a009334 */ + u32 cm_l3init_hsi_clkctrl; /* 4a009338 */ + u32 pad090[7]; /* 4a00933c */ + u32 cm_l3init_hsusbhost_clkctrl; /* 4a009358 */ + u32 pad091[1]; /* 4a00935c */ + u32 cm_l3init_hsusbotg_clkctrl; /* 4a009360 */ + u32 pad092[1]; /* 4a009364 */ + u32 cm_l3init_hsusbtll_clkctrl; /* 4a009368 */ + u32 pad093[3]; /* 4a00936c */ + u32 cm_l3init_p1500_clkctrl; /* 4a009378 */ + u32 pad094[21]; /* 4a00937c */ + u32 cm_l3init_fsusb_clkctrl; /* 4a0093d0 */ + u32 pad095[3]; /* 4a0093d4 */ + u32 cm_l3init_ocp2scp1_clkctrl; + + /* cm2.l4per */ + u32 pad096[7]; /* 4a0093e4 */ + u32 cm_l4per_clkstctrl; /* 4a009400 */ + u32 pad097[1]; /* 4a009404 */ + u32 cm_l4per_dynamicdep; /* 4a009408 */ + u32 pad098[5]; /* 4a00940c */ + u32 cm_l4per_adc_clkctrl; /* 4a009420 */ + u32 pad100[1]; /* 4a009424 */ + u32 cm_l4per_gptimer10_clkctrl; /* 4a009428 */ + u32 pad101[1]; /* 4a00942c */ + u32 cm_l4per_gptimer11_clkctrl; /* 4a009430 */ + u32 pad102[1]; /* 4a009434 */ + u32 cm_l4per_gptimer2_clkctrl; /* 4a009438 */ + u32 pad103[1]; /* 4a00943c */ + u32 cm_l4per_gptimer3_clkctrl; /* 4a009440 */ + u32 pad104[1]; /* 4a009444 */ + u32 cm_l4per_gptimer4_clkctrl; /* 4a009448 */ + u32 pad105[1]; /* 4a00944c */ + u32 cm_l4per_gptimer9_clkctrl; /* 4a009450 */ + u32 pad106[1]; /* 4a009454 */ + u32 cm_l4per_elm_clkctrl; /* 4a009458 */ + u32 pad107[1]; /* 4a00945c */ + u32 cm_l4per_gpio2_clkctrl; /* 4a009460 */ + u32 pad108[1]; /* 4a009464 */ + u32 cm_l4per_gpio3_clkctrl; /* 4a009468 */ + u32 pad109[1]; /* 4a00946c */ + u32 cm_l4per_gpio4_clkctrl; /* 4a009470 */ + u32 pad110[1]; /* 4a009474 */ + u32 cm_l4per_gpio5_clkctrl; /* 4a009478 */ + u32 pad111[1]; /* 4a00947c */ + u32 cm_l4per_gpio6_clkctrl; /* 4a009480 */ + u32 pad112[1]; /* 4a009484 */ + u32 cm_l4per_hdq1w_clkctrl; /* 4a009488 */ + u32 pad113[1]; /* 4a00948c */ + u32 cm_l4per_hecc1_clkctrl; /* 4a009490 */ + u32 pad114[1]; /* 4a009494 */ + u32 cm_l4per_hecc2_clkctrl; /* 4a009498 */ + u32 pad115[1]; /* 4a00949c */ + u32 cm_l4per_i2c1_clkctrl; /* 4a0094a0 */ + u32 pad116[1]; /* 4a0094a4 */ + u32 cm_l4per_i2c2_clkctrl; /* 4a0094a8 */ + u32 pad117[1]; /* 4a0094ac */ + u32 cm_l4per_i2c3_clkctrl; /* 4a0094b0 */ + u32 pad118[1]; /* 4a0094b4 */ + u32 cm_l4per_i2c4_clkctrl; /* 4a0094b8 */ + u32 pad119[1]; /* 4a0094bc */ + u32 cm_l4per_l4per_clkctrl; /* 4a0094c0 */ + u32 pad1191[3]; /* 4a0094c4 */ + u32 cm_l4per_mcasp2_clkctrl; /* 4a0094d0 */ + u32 pad120[1]; /* 4a0094d4 */ + u32 cm_l4per_mcasp3_clkctrl; /* 4a0094d8 */ + u32 pad121[3]; /* 4a0094dc */ + u32 cm_l4per_mgate_clkctrl; /* 4a0094e8 */ + u32 pad123[1]; /* 4a0094ec */ + u32 cm_l4per_mcspi1_clkctrl; /* 4a0094f0 */ + u32 pad124[1]; /* 4a0094f4 */ + u32 cm_l4per_mcspi2_clkctrl; /* 4a0094f8 */ + u32 pad125[1]; /* 4a0094fc */ + u32 cm_l4per_mcspi3_clkctrl; /* 4a009500 */ + u32 pad126[1]; /* 4a009504 */ + u32 cm_l4per_mcspi4_clkctrl; /* 4a009508 */ + u32 pad127[1]; /* 4a00950c */ + u32 cm_l4per_gpio7_clkctrl; /* 4a009510 */ + u32 pad1271[1]; /* 4a009514 */ + u32 cm_l4per_gpio8_clkctrl; /* 4a009518 */ + u32 pad1272[1]; /* 4a00951c */ + u32 cm_l4per_mmcsd3_clkctrl; /* 4a009520 */ + u32 pad128[1]; /* 4a009524 */ + u32 cm_l4per_mmcsd4_clkctrl; /* 4a009528 */ + u32 pad129[1]; /* 4a00952c */ + u32 cm_l4per_msprohg_clkctrl; /* 4a009530 */ + u32 pad130[1]; /* 4a009534 */ + u32 cm_l4per_slimbus2_clkctrl; /* 4a009538 */ + u32 pad131[1]; /* 4a00953c */ + u32 cm_l4per_uart1_clkctrl; /* 4a009540 */ + u32 pad132[1]; /* 4a009544 */ + u32 cm_l4per_uart2_clkctrl; /* 4a009548 */ + u32 pad133[1]; /* 4a00954c */ + u32 cm_l4per_uart3_clkctrl; /* 4a009550 */ + u32 pad134[1]; /* 4a009554 */ + u32 cm_l4per_uart4_clkctrl; /* 4a009558 */ + u32 pad135[1]; /* 4a00955c */ + u32 cm_l4per_mmcsd5_clkctrl; /* 4a009560 */ + u32 pad136[1]; /* 4a009564 */ + u32 cm_l4per_i2c5_clkctrl; /* 4a009568 */ + u32 pad1371[1]; /* 4a00956c */ + u32 cm_l4per_uart5_clkctrl; /* 4a009570 */ + u32 pad1372[1]; /* 4a009574 */ + u32 cm_l4per_uart6_clkctrl; /* 4a009578 */ + u32 pad1374[1]; /* 4a00957c */ + u32 cm_l4sec_clkstctrl; /* 4a009580 */ + u32 cm_l4sec_staticdep; /* 4a009584 */ + u32 cm_l4sec_dynamicdep; /* 4a009588 */ + u32 pad138[5]; /* 4a00958c */ + u32 cm_l4sec_aes1_clkctrl; /* 4a0095a0 */ + u32 pad139[1]; /* 4a0095a4 */ + u32 cm_l4sec_aes2_clkctrl; /* 4a0095a8 */ + u32 pad140[1]; /* 4a0095ac */ + u32 cm_l4sec_des3des_clkctrl; /* 4a0095b0 */ + u32 pad141[1]; /* 4a0095b4 */ + u32 cm_l4sec_pkaeip29_clkctrl; /* 4a0095b8 */ + u32 pad142[1]; /* 4a0095bc */ + u32 cm_l4sec_rng_clkctrl; /* 4a0095c0 */ + u32 pad143[1]; /* 4a0095c4 */ + u32 cm_l4sec_sha2md51_clkctrl; /* 4a0095c8 */ + u32 pad144[3]; /* 4a0095cc */ + u32 cm_l4sec_cryptodma_clkctrl; /* 4a0095d8 */ + u32 pad145[3660425]; /* 4a0095dc */ + + /* l4 wkup regs */ + u32 pad201[6211]; /* 4ae00000 */ + u32 cm_abe_pll_ref_clksel; /* 4ae0610c */ + u32 cm_sys_clksel; /* 4ae06110 */ + u32 pad202[1467]; /* 4ae06114 */ + u32 cm_wkup_clkstctrl; /* 4ae07800 */ + u32 pad203[7]; /* 4ae07804 */ + u32 cm_wkup_l4wkup_clkctrl; /* 4ae07820 */ + u32 pad204; /* 4ae07824 */ + u32 cm_wkup_wdtimer1_clkctrl; /* 4ae07828 */ + u32 pad205; /* 4ae0782c */ + u32 cm_wkup_wdtimer2_clkctrl; /* 4ae07830 */ + u32 pad206; /* 4ae07834 */ + u32 cm_wkup_gpio1_clkctrl; /* 4ae07838 */ + u32 pad207; /* 4ae0783c */ + u32 cm_wkup_gptimer1_clkctrl; /* 4ae07840 */ + u32 pad208; /* 4ae07844 */ + u32 cm_wkup_gptimer12_clkctrl; /* 4ae07848 */ + u32 pad209; /* 4ae0784c */ + u32 cm_wkup_synctimer_clkctrl; /* 4ae07850 */ + u32 pad210; /* 4ae07854 */ + u32 cm_wkup_usim_clkctrl; /* 4ae07858 */ + u32 pad211; /* 4ae0785c */ + u32 cm_wkup_sarram_clkctrl; /* 4ae07860 */ + u32 pad212[5]; /* 4ae07864 */ + u32 cm_wkup_keyboard_clkctrl; /* 4ae07878 */ + u32 pad213; /* 4ae0787c */ + u32 cm_wkup_rtc_clkctrl; /* 4ae07880 */ + u32 pad214; /* 4ae07884 */ + u32 cm_wkup_bandgap_clkctrl; /* 4ae07888 */ + u32 pad215[197]; /* 4ae0788c */ + u32 prm_vc_val_bypass; /* 4ae07ba0 */ + u32 pad216[4]; + u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */ + u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */ +}; + +/* DPLL register offsets */ +#define CM_CLKMODE_DPLL 0 +#define CM_IDLEST_DPLL 0x4 +#define CM_AUTOIDLE_DPLL 0x8 +#define CM_CLKSEL_DPLL 0xC + +#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */ + +/* CM_CLKMODE_DPLL */ +#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 +#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) +#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 +#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 +#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 +#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) +#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 +#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) +#define CM_CLKMODE_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) + +#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 +#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 + +#define DPLL_EN_STOP 1 +#define DPLL_EN_MN_BYPASS 4 +#define DPLL_EN_LOW_POWER_BYPASS 5 +#define DPLL_EN_FAST_RELOCK_BYPASS 6 +#define DPLL_EN_LOCK 7 + +/* CM_IDLEST_DPLL fields */ +#define ST_DPLL_CLK_MASK 1 + +/* CM_CLKSEL_DPLL */ +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 +#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) +#define CM_CLKSEL_DPLL_M_SHIFT 8 +#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) +#define CM_CLKSEL_DPLL_N_SHIFT 0 +#define CM_CLKSEL_DPLL_N_MASK 0x7F +#define CM_CLKSEL_DCC_EN_SHIFT 22 +#define CM_CLKSEL_DCC_EN_MASK (1 << 22) + +#define OMAP4_DPLL_MAX_N 127 + +/* CM_SYS_CLKSEL */ +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 + +/* CM_CLKSEL_CORE */ +#define CLKSEL_CORE_SHIFT 0 +#define CLKSEL_L3_SHIFT 4 +#define CLKSEL_L4_SHIFT 8 + +#define CLKSEL_CORE_X2_DIV_1 0 +#define CLKSEL_L3_CORE_DIV_2 1 +#define CLKSEL_L4_L3_DIV_2 1 + +/* CM_ABE_PLL_REF_CLKSEL */ +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 +#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 + +/* CM_BYPCLK_DPLL_IVA */ +#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 +#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 + +#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 + +/* CM_SHADOW_FREQ_CONFIG1 */ +#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 +#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 +#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 + +#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 +#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) + +#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 +#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) + +/*CM_<clock_domain>__CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 +#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 + + +/* CM_<clock_domain>_<module>_CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + +/* CM_L4PER_GPIO4_CLKCTRL */ +#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_L3INIT_HSMMCn_CLKCTRL */ +#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_WKUP_GPTIMER1_CLKCTRL */ +#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) + +/* CM_CAM_ISS_CLKCTRL */ +#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + +/* CM_DSS_DSS_CLKCTRL */ +#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 + +/* CM_L3INIT_USBPHY_CLKCTRL */ +#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8 + +/* CM_MPU_MPU_CLKCTRL */ +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 +#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 +#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) + +/* Clock frequencies */ +#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 +#define OMAP_SYS_CLK_IND_38_4_MHZ 6 +#define OMAP_32K_CLK_FREQ 32768 + +/* PRM_VC_CFG_I2C_CLK */ +#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0 +#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF +#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8 +#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8) + +/* PRM_VC_VAL_BYPASS */ +#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 + +#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000 +#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 +#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F +#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 +#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF +#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 +#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF + +/* SMPS */ +#define SMPS_I2C_SLAVE_ADDR 0x12 +#define SMPS_REG_ADDR_VCORE1 0x55 +#define SMPS_REG_ADDR_VCORE2 0x5B +#define SMPS_REG_ADDR_VCORE3 0x61 + +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 +#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 + +/* TPS */ +#define TPS62361_I2C_SLAVE_ADDR 0x60 +#define TPS62361_REG_ADDR_SET0 0x0 +#define TPS62361_REG_ADDR_SET1 0x1 +#define TPS62361_REG_ADDR_SET2 0x2 +#define TPS62361_REG_ADDR_SET3 0x3 +#define TPS62361_REG_ADDR_CTRL 0x4 +#define TPS62361_REG_ADDR_TEMP 0x5 +#define TPS62361_REG_ADDR_RMP_CTRL 0x6 +#define TPS62361_REG_ADDR_CHIP_ID 0x8 +#define TPS62361_REG_ADDR_CHIP_ID_2 0x9 + +#define TPS62361_BASE_VOLT_MV 500 +#define TPS62361_VSEL0_GPIO 7 + +/* Defines for DPLL setup */ +#define DPLL_LOCKED_FREQ_TOLERANCE_0 0 +#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500 +#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000 + +#define DPLL_NO_LOCK 0 +#define DPLL_LOCK 1 + +#define NUM_SYS_CLKS 7 + +struct dpll_regs { + u32 cm_clkmode_dpll; + u32 cm_idlest_dpll; + u32 cm_autoidle_dpll; + u32 cm_clksel_dpll; + u32 cm_div_m2_dpll; + u32 cm_div_m3_dpll; + u32 cm_div_h11_dpll; + u32 cm_div_h12_dpll; + u32 cm_div_h13_dpll; + u32 cm_div_h14_dpll; + u32 reserved[2]; + u32 cm_div_h22_dpll; + u32 cm_div_h23_dpll; +}; + +/* DPLL parameter table */ +struct dpll_params { + u32 m; + u32 n; + u8 m2; + u8 m3; + u8 h11; + u8 h12; + u8 h13; + u8 h14; + u8 h22; + u8 h23; +}; + +extern struct omap5_prcm_regs *const prcm; +extern const u32 sys_clk_array[8]; + +void scale_vcores(void); +void do_scale_tps62361(u32 reg, u32 volt_mv); +u32 omap_ddr_clk(void); +void do_scale_vcore(u32 vcore_reg, u32 volt_mv); +void setup_sri2c(void); +void setup_post_dividers(u32 *const base, const struct dpll_params *params); +u32 get_sys_clk_index(void); +void enable_basic_clocks(void); +void enable_non_essential_clocks(void); +void enable_basic_uboot_clocks(void); +void do_enable_clocks(u32 *const *clk_domains, + u32 *const *clk_modules_hw_auto, + u32 *const *clk_modules_explicit_en, + u8 wait_for_enable); +const struct dpll_params *get_mpu_dpll_params(void); +const struct dpll_params *get_core_dpll_params(void); +const struct dpll_params *get_per_dpll_params(void); +const struct dpll_params *get_iva_dpll_params(void); +const struct dpll_params *get_usb_dpll_params(void); +const struct dpll_params *get_abe_dpll_params(void); +#endif /* _CLOCKS_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h new file mode 100644 index 000000000..0697a732d --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -0,0 +1,175 @@ +/* + * (C) Copyright 2006-2010 + * Texas Instruments, <www.ti.com> + * + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _CPU_H +#define _CPU_H + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct gpmc_cs { + u32 config1; /* 0x00 */ + u32 config2; /* 0x04 */ + u32 config3; /* 0x08 */ + u32 config4; /* 0x0C */ + u32 config5; /* 0x10 */ + u32 config6; /* 0x14 */ + u32 config7; /* 0x18 */ + u32 nand_cmd; /* 0x1C */ + u32 nand_adr; /* 0x20 */ + u32 nand_dat; /* 0x24 */ + u8 res[8]; /* blow up to 0x30 byte */ +}; + +struct gpmc { + u8 res1[0x10]; + u32 sysconfig; /* 0x10 */ + u8 res2[0x4]; + u32 irqstatus; /* 0x18 */ + u32 irqenable; /* 0x1C */ + u8 res3[0x20]; + u32 timeout_control; /* 0x40 */ + u8 res4[0xC]; + u32 config; /* 0x50 */ + u32 status; /* 0x54 */ + u8 res5[0x8]; /* 0x58 */ + struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ + u8 res6[0x14]; /* 0x1E0 */ + u32 ecc_config; /* 0x1F4 */ + u32 ecc_control; /* 0x1F8 */ + u32 ecc_size_config; /* 0x1FC */ + u32 ecc1_result; /* 0x200 */ + u32 ecc2_result; /* 0x204 */ + u32 ecc3_result; /* 0x208 */ + u32 ecc4_result; /* 0x20C */ + u32 ecc5_result; /* 0x210 */ + u32 ecc6_result; /* 0x214 */ + u32 ecc7_result; /* 0x218 */ + u32 ecc8_result; /* 0x21C */ + u32 ecc9_result; /* 0x220 */ +}; + +/* Used for board specific gpmc initialization */ +extern struct gpmc *gpmc_cfg; + +struct gptimer { + u32 tidr; /* 0x00 r */ + u8 res1[0xc]; + u32 tiocp_cfg; /* 0x10 rw */ + u8 res2[0x10]; + u32 tisr_raw; /* 0x24 r */ + u32 tisr; /* 0x28 rw */ + u32 tier; /* 0x2c rw */ + u32 ticr; /* 0x30 rw */ + u32 twer; /* 0x34 rw */ + u32 tclr; /* 0x38 rw */ + u32 tcrr; /* 0x3c rw */ + u32 tldr; /* 0x40 rw */ + u32 ttgr; /* 0x44 rw */ + u32 twpc; /* 0x48 r */ + u32 tmar; /* 0x4c rw */ + u32 tcar1; /* 0x50 r */ + u32 tcicr; /* 0x54 rw */ + u32 tcar2; /* 0x58 r */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +/* enable sys_clk NO-prescale /1 */ +#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) + +/* Watchdog */ +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ +struct watchdog { + u8 res1[0x34]; + u32 wwps; /* 0x34 r */ + u8 res2[0x10]; + u32 wspr; /* 0x48 rw */ +}; +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +#define SYSCLKDIV_1 (0x1 << 6) +#define SYSCLKDIV_2 (0x1 << 7) + +#define CLKSEL_GPT1 (0x1 << 0) + +#define EN_GPT1 (0x1 << 0) +#define EN_32KSYNC (0x1 << 2) + +#define ST_WDT2 (0x1 << 5) + +#define RESETDONE (0x1 << 0) + +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) + +/* GPMC BASE */ +#define GPMC_BASE (OMAP54XX_GPMC_BASE) + +/* I2C base */ +#define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000) +#define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000) +#define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000) + +/* MUSB base */ +#define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000) + +/* OMAP4 GPIO registers */ +#define OMAP_GPIO_REVISION 0x0000 +#define OMAP_GPIO_SYSCONFIG 0x0010 +#define OMAP_GPIO_SYSSTATUS 0x0114 +#define OMAP_GPIO_IRQSTATUS1 0x0118 +#define OMAP_GPIO_IRQSTATUS2 0x0128 +#define OMAP_GPIO_IRQENABLE2 0x012c +#define OMAP_GPIO_IRQENABLE1 0x011c +#define OMAP_GPIO_WAKE_EN 0x0120 +#define OMAP_GPIO_CTRL 0x0130 +#define OMAP_GPIO_OE 0x0134 +#define OMAP_GPIO_DATAIN 0x0138 +#define OMAP_GPIO_DATAOUT 0x013c +#define OMAP_GPIO_LEVELDETECT0 0x0140 +#define OMAP_GPIO_LEVELDETECT1 0x0144 +#define OMAP_GPIO_RISINGDETECT 0x0148 +#define OMAP_GPIO_FALLINGDETECT 0x014c +#define OMAP_GPIO_DEBOUNCE_EN 0x0150 +#define OMAP_GPIO_DEBOUNCE_VAL 0x0154 +#define OMAP_GPIO_CLEARIRQENABLE1 0x0160 +#define OMAP_GPIO_SETIRQENABLE1 0x0164 +#define OMAP_GPIO_CLEARWKUENA 0x0180 +#define OMAP_GPIO_SETWKUENA 0x0184 +#define OMAP_GPIO_CLEARDATAOUT 0x0190 +#define OMAP_GPIO_SETDATAOUT 0x0194 + +#endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-omap5/gpio.h b/arch/arm/include/asm/arch-omap5/gpio.h new file mode 100644 index 000000000..c14dff0f3 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/gpio.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix@windriver.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This work is derived from the linux 2.6.27 kernel source + * To fetch, use the kernel repository + * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git + * Use the v2.6.27 tag. + * + * Below is the original's header including its copyright + * + * linux/arch/arm/plat-omap/gpio.c + * + * Support functions for OMAP GPIO + * + * Copyright (C) 2003-2005 Nokia Corporation + * Written by Juha Yrjölä <juha.yrjola@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _GPIO_OMAP5_H +#define _GPIO_OMAP5_H + +#include <asm/omap_gpio.h> + +#define OMAP54XX_GPIO1_BASE 0x4Ae10000 +#define OMAP54XX_GPIO2_BASE 0x48055000 +#define OMAP54XX_GPIO3_BASE 0x48057000 +#define OMAP54XX_GPIO4_BASE 0x48059000 +#define OMAP54XX_GPIO5_BASE 0x4805B000 +#define OMAP54XX_GPIO6_BASE 0x4805D000 + +#endif /* _GPIO_OMAP5_H */ diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h new file mode 100644 index 000000000..68be03be5 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/i2c.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2004-2010 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP5_I2C_H_ +#define _OMAP5_I2C_H_ + +#define I2C_BUS_MAX 3 +#define I2C_DEFAULT_BASE I2C_BASE1 + +struct i2c { + unsigned short revnb_lo; /* 0x00 */ + unsigned short res1; + unsigned short revnb_hi; /* 0x04 */ + unsigned short res2[13]; + unsigned short sysc; /* 0x20 */ + unsigned short res3; + unsigned short irqstatus_raw; /* 0x24 */ + unsigned short res4; + unsigned short stat; /* 0x28 */ + unsigned short res5; + unsigned short ie; /* 0x2C */ + unsigned short res6; + unsigned short irqenable_clr; /* 0x30 */ + unsigned short res7; + unsigned short iv; /* 0x34 */ + unsigned short res8[45]; + unsigned short syss; /* 0x90 */ + unsigned short res9; + unsigned short buf; /* 0x94 */ + unsigned short res10; + unsigned short cnt; /* 0x98 */ + unsigned short res11; + unsigned short data; /* 0x9C */ + unsigned short res13; + unsigned short res14; /* 0xA0 */ + unsigned short res15; + unsigned short con; /* 0xA4 */ + unsigned short res16; + unsigned short oa; /* 0xA8 */ + unsigned short res17; + unsigned short sa; /* 0xAC */ + unsigned short res18; + unsigned short psc; /* 0xB0 */ + unsigned short res19; + unsigned short scll; /* 0xB4 */ + unsigned short res20; + unsigned short sclh; /* 0xB8 */ + unsigned short res21; + unsigned short systest; /* 0xBC */ + unsigned short res22; + unsigned short bufstat; /* 0xC0 */ + unsigned short res23; +}; + +#endif /* _OMAP5_I2C_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h new file mode 100644 index 000000000..74439c9d9 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h @@ -0,0 +1,174 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MMC_HOST_DEF_H +#define MMC_HOST_DEF_H + +/* + * OMAP HSMMC register definitions + */ + +#define OMAP_HSMMC1_BASE 0x4809C100 +#define OMAP_HSMMC2_BASE 0x480B4100 +#define OMAP_HSMMC3_BASE 0x480AD100 + +struct hsmmc { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned int sysstatus; /* 0x14 */ + unsigned char res2[0x14]; + unsigned int con; /* 0x2C */ + unsigned char res3[0xD4]; + unsigned int blk; /* 0x104 */ + unsigned int arg; /* 0x108 */ + unsigned int cmd; /* 0x10C */ + unsigned int rsp10; /* 0x110 */ + unsigned int rsp32; /* 0x114 */ + unsigned int rsp54; /* 0x118 */ + unsigned int rsp76; /* 0x11C */ + unsigned int data; /* 0x120 */ + unsigned int pstate; /* 0x124 */ + unsigned int hctl; /* 0x128 */ + unsigned int sysctl; /* 0x12C */ + unsigned int stat; /* 0x130 */ + unsigned int ie; /* 0x134 */ + unsigned char res4[0x8]; + unsigned int capa; /* 0x140 */ +}; + +/* + * OMAP HS MMC Bit definitions + */ +#define MMC_SOFTRESET (0x1 << 1) +#define RESETDONE (0x1 << 0) +#define NOOPENDRAIN (0x0 << 0) +#define OPENDRAIN (0x1 << 0) +#define OD (0x1 << 0) +#define INIT_NOINIT (0x0 << 1) +#define INIT_INITSTREAM (0x1 << 1) +#define HR_NOHOSTRESP (0x0 << 2) +#define STR_BLOCK (0x0 << 3) +#define MODE_FUNC (0x0 << 4) +#define DW8_1_4BITMODE (0x0 << 5) +#define MIT_CTO (0x0 << 6) +#define CDP_ACTIVEHIGH (0x0 << 7) +#define WPP_ACTIVEHIGH (0x0 << 8) +#define RESERVED_MASK (0x3 << 9) +#define CTPL_MMC_SD (0x0 << 11) +#define BLEN_512BYTESLEN (0x200 << 0) +#define NBLK_STPCNT (0x0 << 16) +#define DE_DISABLE (0x0 << 0) +#define BCE_DISABLE (0x0 << 1) +#define BCE_ENABLE (0x1 << 1) +#define ACEN_DISABLE (0x0 << 2) +#define DDIR_OFFSET (4) +#define DDIR_MASK (0x1 << 4) +#define DDIR_WRITE (0x0 << 4) +#define DDIR_READ (0x1 << 4) +#define MSBS_SGLEBLK (0x0 << 5) +#define MSBS_MULTIBLK (0x1 << 5) +#define RSP_TYPE_OFFSET (16) +#define RSP_TYPE_MASK (0x3 << 16) +#define RSP_TYPE_NORSP (0x0 << 16) +#define RSP_TYPE_LGHT136 (0x1 << 16) +#define RSP_TYPE_LGHT48 (0x2 << 16) +#define RSP_TYPE_LGHT48B (0x3 << 16) +#define CCCE_NOCHECK (0x0 << 19) +#define CCCE_CHECK (0x1 << 19) +#define CICE_NOCHECK (0x0 << 20) +#define CICE_CHECK (0x1 << 20) +#define DP_OFFSET (21) +#define DP_MASK (0x1 << 21) +#define DP_NO_DATA (0x0 << 21) +#define DP_DATA (0x1 << 21) +#define CMD_TYPE_NORMAL (0x0 << 22) +#define INDEX_OFFSET (24) +#define INDEX_MASK (0x3f << 24) +#define INDEX(i) (i << 24) +#define DATI_MASK (0x1 << 1) +#define DATI_CMDDIS (0x1 << 1) +#define DTW_1_BITMODE (0x0 << 1) +#define DTW_4_BITMODE (0x1 << 1) +#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ +#define SDBP_PWROFF (0x0 << 8) +#define SDBP_PWRON (0x1 << 8) +#define SDVS_1V8 (0x5 << 9) +#define SDVS_3V0 (0x6 << 9) +#define ICE_MASK (0x1 << 0) +#define ICE_STOP (0x0 << 0) +#define ICS_MASK (0x1 << 1) +#define ICS_NOTREADY (0x0 << 1) +#define ICE_OSCILLATE (0x1 << 0) +#define CEN_MASK (0x1 << 2) +#define CEN_DISABLE (0x0 << 2) +#define CEN_ENABLE (0x1 << 2) +#define CLKD_OFFSET (6) +#define CLKD_MASK (0x3FF << 6) +#define DTO_MASK (0xF << 16) +#define DTO_15THDTO (0xE << 16) +#define SOFTRESETALL (0x1 << 24) +#define CC_MASK (0x1 << 0) +#define TC_MASK (0x1 << 1) +#define BWR_MASK (0x1 << 4) +#define BRR_MASK (0x1 << 5) +#define ERRI_MASK (0x1 << 15) +#define IE_CC (0x01 << 0) +#define IE_TC (0x01 << 1) +#define IE_BWR (0x01 << 4) +#define IE_BRR (0x01 << 5) +#define IE_CTO (0x01 << 16) +#define IE_CCRC (0x01 << 17) +#define IE_CEB (0x01 << 18) +#define IE_CIE (0x01 << 19) +#define IE_DTO (0x01 << 20) +#define IE_DCRC (0x01 << 21) +#define IE_DEB (0x01 << 22) +#define IE_CERR (0x01 << 28) +#define IE_BADA (0x01 << 29) + +#define VS30_3V0SUP (1 << 25) +#define VS18_1V8SUP (1 << 26) + +/* Driver definitions */ +#define MMCSD_SECTOR_SIZE 512 +#define MMC_CARD 0 +#define SD_CARD 1 +#define BYTE_MODE 0 +#define SECTOR_MODE 1 +#define CLK_INITSEQ 0 +#define CLK_400KHZ 1 +#define CLK_MISC 2 + +#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) +#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) + +/* Clock Configurations and Macros */ +#define MMC_CLOCK_REFERENCE 96 /* MHz */ + +#define mmc_reg_out(addr, mask, val)\ + writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) + +int omap_mmc_init(int dev_index); + +#endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h new file mode 100644 index 000000000..b8c21853f --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/mux_omap5.h @@ -0,0 +1,344 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments Incorporated + * Richard Woodruff <r-woodruff2@ti.com> + * Aneesh V <aneesh@ti.com> + * Balaji Krishnamoorthy <balajitk@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUX_OMAP5_H_ +#define _MUX_OMAP5_H_ + +#include <asm/types.h> + +struct pad_conf_entry { + + u16 offset; + + u16 val; + +} __attribute__ ((__packed__)); + +#ifdef CONFIG_OFF_PADCONF +#define OFF_PD (1 << 12) +#define OFF_PU (3 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (2 << 10) +#define OFF_IN (1 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (1 << 9) +#else +#define OFF_PD (0 << 12) +#define OFF_PU (0 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (0 << 10) +#define OFF_IN (0 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (0 << 9) +#endif + +#define IEN (1 << 8) +#define IDIS (0 << 8) +#define PTU (3 << 3) +#define PTD (1 << 3) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +#define SAFE_MODE M7 + +#ifdef CONFIG_OFF_PADCONF +#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) +#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) +#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) +#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) +#else +#define OFF_IN_PD 0 +#define OFF_IN_PU 0 +#define OFF_OUT_PD 0 +#define OFF_OUT_PU 0 +#endif + +#define CORE_REVISION 0x0000 +#define CORE_HWINFO 0x0004 +#define CORE_SYSCONFIG 0x0010 +#define GPMC_AD0 0x0040 +#define GPMC_AD1 0x0042 +#define GPMC_AD2 0x0044 +#define GPMC_AD3 0x0046 +#define GPMC_AD4 0x0048 +#define GPMC_AD5 0x004A +#define GPMC_AD6 0x004C +#define GPMC_AD7 0x004E +#define GPMC_AD8 0x0050 +#define GPMC_AD9 0x0052 +#define GPMC_AD10 0x0054 +#define GPMC_AD11 0x0056 +#define GPMC_AD12 0x0058 +#define GPMC_AD13 0x005A +#define GPMC_AD14 0x005C +#define GPMC_AD15 0x005E +#define GPMC_A16 0x0060 +#define GPMC_A17 0x0062 +#define GPMC_A18 0x0064 +#define GPMC_A19 0x0066 +#define GPMC_A20 0x0068 +#define GPMC_A21 0x006A +#define GPMC_A22 0x006C +#define GPMC_A23 0x006E +#define GPMC_A24 0x0070 +#define GPMC_A25 0x0072 +#define GPMC_NCS0 0x0074 +#define GPMC_NCS1 0x0076 +#define GPMC_NCS2 0x0078 +#define GPMC_NCS3 0x007A +#define GPMC_NWP 0x007C +#define GPMC_CLK 0x007E +#define GPMC_NADV_ALE 0x0080 +#define GPMC_NOE 0x0082 +#define GPMC_NWE 0x0084 +#define GPMC_NBE0_CLE 0x0086 +#define GPMC_NBE1 0x0088 +#define GPMC_WAIT0 0x008A +#define GPMC_WAIT1 0x008C +#define C2C_DATA11 0x008E +#define C2C_DATA12 0x0090 +#define C2C_DATA13 0x0092 +#define C2C_DATA14 0x0094 +#define C2C_DATA15 0x0096 +#define HDMI_HPD 0x0098 +#define HDMI_CEC 0x009A +#define HDMI_DDC_SCL 0x009C +#define HDMI_DDC_SDA 0x009E +#define CSI21_DX0 0x00A0 +#define CSI21_DY0 0x00A2 +#define CSI21_DX1 0x00A4 +#define CSI21_DY1 0x00A6 +#define CSI21_DX2 0x00A8 +#define CSI21_DY2 0x00AA +#define CSI21_DX3 0x00AC +#define CSI21_DY3 0x00AE +#define CSI21_DX4 0x00B0 +#define CSI21_DY4 0x00B2 +#define CSI22_DX0 0x00B4 +#define CSI22_DY0 0x00B6 +#define CSI22_DX1 0x00B8 +#define CSI22_DY1 0x00BA +#define CAM_SHUTTER 0x00BC +#define CAM_STROBE 0x00BE +#define CAM_GLOBALRESET 0x00C0 +#define USBB1_ULPITLL_CLK 0x00C2 +#define USBB1_ULPITLL_STP 0x00C4 +#define USBB1_ULPITLL_DIR 0x00C6 +#define USBB1_ULPITLL_NXT 0x00C8 +#define USBB1_ULPITLL_DAT0 0x00CA +#define USBB1_ULPITLL_DAT1 0x00CC +#define USBB1_ULPITLL_DAT2 0x00CE +#define USBB1_ULPITLL_DAT3 0x00D0 +#define USBB1_ULPITLL_DAT4 0x00D2 +#define USBB1_ULPITLL_DAT5 0x00D4 +#define USBB1_ULPITLL_DAT6 0x00D6 +#define USBB1_ULPITLL_DAT7 0x00D8 +#define USBB1_HSIC_DATA 0x00DA +#define USBB1_HSIC_STROBE 0x00DC +#define USBC1_ICUSB_DP 0x00DE +#define USBC1_ICUSB_DM 0x00E0 +#define SDMMC1_CLK 0x00E2 +#define SDMMC1_CMD 0x00E4 +#define SDMMC1_DAT0 0x00E6 +#define SDMMC1_DAT1 0x00E8 +#define SDMMC1_DAT2 0x00EA +#define SDMMC1_DAT3 0x00EC +#define SDMMC1_DAT4 0x00EE +#define SDMMC1_DAT5 0x00F0 +#define SDMMC1_DAT6 0x00F2 +#define SDMMC1_DAT7 0x00F4 +#define ABE_MCBSP2_CLKX 0x00F6 +#define ABE_MCBSP2_DR 0x00F8 +#define ABE_MCBSP2_DX 0x00FA +#define ABE_MCBSP2_FSX 0x00FC +#define ABE_MCBSP1_CLKX 0x00FE +#define ABE_MCBSP1_DR 0x0100 +#define ABE_MCBSP1_DX 0x0102 +#define ABE_MCBSP1_FSX 0x0104 +#define ABE_PDM_UL_DATA 0x0106 +#define ABE_PDM_DL_DATA 0x0108 +#define ABE_PDM_FRAME 0x010A +#define ABE_PDM_LB_CLK 0x010C +#define ABE_CLKS 0x010E +#define ABE_DMIC_CLK1 0x0110 +#define ABE_DMIC_DIN1 0x0112 +#define ABE_DMIC_DIN2 0x0114 +#define ABE_DMIC_DIN3 0x0116 +#define UART2_CTS 0x0118 +#define UART2_RTS 0x011A +#define UART2_RX 0x011C +#define UART2_TX 0x011E +#define HDQ_SIO 0x0120 +#define I2C1_SCL 0x0122 +#define I2C1_SDA 0x0124 +#define I2C2_SCL 0x0126 +#define I2C2_SDA 0x0128 +#define I2C3_SCL 0x012A +#define I2C3_SDA 0x012C +#define I2C4_SCL 0x012E +#define I2C4_SDA 0x0130 +#define MCSPI1_CLK 0x0132 +#define MCSPI1_SOMI 0x0134 +#define MCSPI1_SIMO 0x0136 +#define MCSPI1_CS0 0x0138 +#define MCSPI1_CS1 0x013A +#define MCSPI1_CS2 0x013C +#define MCSPI1_CS3 0x013E +#define UART3_CTS_RCTX 0x0140 +#define UART3_RTS_SD 0x0142 +#define UART3_RX_IRRX 0x0144 +#define UART3_TX_IRTX 0x0146 +#define SDMMC5_CLK 0x0148 +#define SDMMC5_CMD 0x014A +#define SDMMC5_DAT0 0x014C +#define SDMMC5_DAT1 0x014E +#define SDMMC5_DAT2 0x0150 +#define SDMMC5_DAT3 0x0152 +#define MCSPI4_CLK 0x0154 +#define MCSPI4_SIMO 0x0156 +#define MCSPI4_SOMI 0x0158 +#define MCSPI4_CS0 0x015A +#define UART4_RX 0x015C +#define UART4_TX 0x015E +#define USBB2_ULPITLL_CLK 0x0160 +#define USBB2_ULPITLL_STP 0x0162 +#define USBB2_ULPITLL_DIR 0x0164 +#define USBB2_ULPITLL_NXT 0x0166 +#define USBB2_ULPITLL_DAT0 0x0168 +#define USBB2_ULPITLL_DAT1 0x016A +#define USBB2_ULPITLL_DAT2 0x016C +#define USBB2_ULPITLL_DAT3 0x016E +#define USBB2_ULPITLL_DAT4 0x0170 +#define USBB2_ULPITLL_DAT5 0x0172 +#define USBB2_ULPITLL_DAT6 0x0174 +#define USBB2_ULPITLL_DAT7 0x0176 +#define USBB2_HSIC_DATA 0x0178 +#define USBB2_HSIC_STROBE 0x017A +#define UNIPRO_TX0 0x017C +#define UNIPRO_TY0 0x017E +#define UNIPRO_TX1 0x0180 +#define UNIPRO_TY1 0x0182 +#define UNIPRO_TX2 0x0184 +#define UNIPRO_TY2 0x0186 +#define UNIPRO_RX0 0x0188 +#define UNIPRO_RY0 0x018A +#define UNIPRO_RX1 0x018C +#define UNIPRO_RY1 0x018E +#define UNIPRO_RX2 0x0190 +#define UNIPRO_RY2 0x0192 +#define USBA0_OTG_CE 0x0194 +#define USBA0_OTG_DP 0x0196 +#define USBA0_OTG_DM 0x0198 +#define FREF_CLK1_OUT 0x019A +#define FREF_CLK2_OUT 0x019C +#define SYS_NIRQ1 0x019E +#define SYS_NIRQ2 0x01A0 +#define SYS_BOOT0 0x01A2 +#define SYS_BOOT1 0x01A4 +#define SYS_BOOT2 0x01A6 +#define SYS_BOOT3 0x01A8 +#define SYS_BOOT4 0x01AA +#define SYS_BOOT5 0x01AC +#define DPM_EMU0 0x01AE +#define DPM_EMU1 0x01B0 +#define DPM_EMU2 0x01B2 +#define DPM_EMU3 0x01B4 +#define DPM_EMU4 0x01B6 +#define DPM_EMU5 0x01B8 +#define DPM_EMU6 0x01BA +#define DPM_EMU7 0x01BC +#define DPM_EMU8 0x01BE +#define DPM_EMU9 0x01C0 +#define DPM_EMU10 0x01C2 +#define DPM_EMU11 0x01C4 +#define DPM_EMU12 0x01C6 +#define DPM_EMU13 0x01C8 +#define DPM_EMU14 0x01CA +#define DPM_EMU15 0x01CC +#define DPM_EMU16 0x01CE +#define DPM_EMU17 0x01D0 +#define DPM_EMU18 0x01D2 +#define DPM_EMU19 0x01D4 +#define WAKEUPEVENT_0 0x01D8 +#define WAKEUPEVENT_1 0x01DC +#define WAKEUPEVENT_2 0x01E0 +#define WAKEUPEVENT_3 0x01E4 +#define WAKEUPEVENT_4 0x01E8 +#define WAKEUPEVENT_5 0x01EC +#define WAKEUPEVENT_6 0x01F0 + +#define WKUP_REVISION 0x0000 +#define WKUP_HWINFO 0x0004 +#define WKUP_SYSCONFIG 0x0010 +#define PAD0_SIM_IO 0x0040 +#define PAD1_SIM_CLK 0x0042 +#define PAD0_SIM_RESET 0x0044 +#define PAD1_SIM_CD 0x0046 +#define PAD0_SIM_PWRCTRL 0x0048 +#define PAD1_SR_SCL 0x004A +#define PAD0_SR_SDA 0x004C +#define PAD1_FREF_XTAL_IN 0x004E +#define PAD0_FREF_SLICER_IN 0x0050 +#define PAD1_FREF_CLK_IOREQ 0x0052 +#define PAD0_FREF_CLK0_OUT 0x0054 +#define PAD1_FREF_CLK3_REQ 0x0056 +#define PAD0_FREF_CLK3_OUT 0x0058 +#define PAD1_FREF_CLK4_REQ 0x005A +#define PAD0_FREF_CLK4_OUT 0x005C +#define PAD1_SYS_32K 0x005E +#define PAD0_SYS_NRESPWRON 0x0060 +#define PAD1_SYS_NRESWARM 0x0062 +#define PAD0_SYS_PWR_REQ 0x0064 +#define PAD1_SYS_PWRON_RESET 0x0066 +#define PAD0_SYS_BOOT6 0x0068 +#define PAD1_SYS_BOOT7 0x006A +#define PAD0_JTAG_NTRST 0x006C +#define PAD1_JTAG_TCK 0x006D +#define PAD0_JTAG_RTCK 0x0070 +#define PAD1_JTAG_TMS_TMSC 0x0072 +#define PAD0_JTAG_TDI 0x0074 +#define PAD1_JTAG_TDO 0x0076 +#define PADCONF_WAKEUPEVENT_0 0x007C +#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 +#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 +#define PADCONF_MODE 0x05A8 +#define CONTROL_XTAL_OSCILLATOR 0x05AC +#define CONTROL_CONTROL_I2C_2 0x0604 +#define CONTROL_CONTROL_JTAG 0x0608 +#define CONTROL_CONTROL_SYS 0x060C +#define CONTROL_SPARE_RW 0x0614 +#define CONTROL_SPARE_R 0x0618 +#define CONTROL_SPARE_R_C0 0x061C + +#endif /* _MUX_OMAP5_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h new file mode 100644 index 000000000..d811d6ec2 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -0,0 +1,223 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * Authors: + * Aneesh V <aneesh@ti.com> + * Sricharan R <r.sricharan@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP5_H_ +#define _OMAP5_H_ + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> +#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ + +/* + * L4 Peripherals - L4 Wakeup and L4 Core now + */ +#define OMAP54XX_L4_CORE_BASE 0x4A000000 +#define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 +#define OMAP54XX_L4_PER_BASE 0x48000000 + +#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000 +#define OMAP54XX_DRAM_ADDR_SPACE_END 0xD0000000 +#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START +#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END + +/* CONTROL */ +#define CTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) +#define CONTROL_PADCONF_CORE (CTRL_BASE + 0x0800) +#define CONTROL_PADCONF_WKUP (OMAP54XX_L4_WKUP_BASE + 0xc800) + +/* LPDDR2 IO regs. To be verified */ +#define LPDDR2_IO_REGS_BASE 0x4A100638 + +/* CONTROL_ID_CODE */ +#define CONTROL_ID_CODE (CTRL_BASE + 0x204) + +/* To be verified */ +#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B85202F + +/* STD_FUSE_PROD_ID_1 */ +#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) +#define PROD_ID_1_SILICON_TYPE_SHIFT 16 +#define PROD_ID_1_SILICON_TYPE_MASK (3 << 16) + +/* UART */ +#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) +#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000) +#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000) + +/* General Purpose Timers */ +#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000) +#define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000) +#define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000) + +/* Watchdog Timer2 - MPU watchdog */ +#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) + +/* 32KTIMER */ +#define SYNC_32KTIMER_BASE (OMAP54XX_L4_WKUP_BASE + 0x4000) + +/* GPMC */ +#define OMAP54XX_GPMC_BASE 0x50000000 + +/* SYSTEM CONTROL MODULE */ +#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000 + +/* + * Hardware Register Details + */ + +/* Watchdog Timer */ +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* GP Timer */ +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) + +/* + * PRCM + */ + +/* PRM */ +#define PRM_BASE 0x4AE06000 +#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00) + +#define PRM_RSTCTRL PRM_DEVICE_BASE +#define PRM_RSTCTRL_RESET 0x01 + +/* Control Module */ +#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5) +#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f +#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110 +#define CONTROL_EFUSE_2_OVERRIDE 0x00084000 + +/* LPDDR2 IO regs */ +#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C +#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E +#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C +#define LPDDR2IO_GR10_WD_MASK (3 << 17) +#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00 + +/* CONTROL_EFUSE_2 */ +#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000 + +#define MMC1_PWRDNZ (1 << 26) +#define MMC1_PBIASLITE_PWRDNZ (1 << 22) +#define MMC1_PBIASLITE_VMODE (1 << 21) + +#ifndef __ASSEMBLY__ + +struct s32ktimer { + unsigned char res[0x10]; + unsigned int s32k_cr; /* 0x10 */ +}; + +struct omap4_sys_ctrl_regs { + unsigned int pad1[129]; + unsigned int control_id_code; /* 0x4A002204 */ + unsigned int pad11[22]; + unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */ + unsigned int pad2[47]; + unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */ + unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */ + unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */ + unsigned int pad3[260277]; + unsigned int control_pbiaslite; /* 0x4A100600 */ + unsigned int pad4[63]; + unsigned int control_efuse_1; /* 0x4A100700 */ + unsigned int control_efuse_2; /* 0x4A100704 */ +}; + +struct control_lpddr2io_regs { + unsigned int control_lpddr2io1_0; + unsigned int control_lpddr2io1_1; + unsigned int control_lpddr2io1_2; + unsigned int control_lpddr2io1_3; + unsigned int control_lpddr2io2_0; + unsigned int control_lpddr2io2_1; + unsigned int control_lpddr2io2_2; + unsigned int control_lpddr2io2_3; +}; +#endif /* __ASSEMBLY__ */ + +/* + * Non-secure SRAM Addresses + * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE + * at 0x40304000(EMU base) so that our code works for both EMU and GP + */ +#define NON_SECURE_SRAM_START 0x40304000 +#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_ROM_VECT_BASE 0x4031F000 +/* Temporary SRAM stack used while low level init is done */ +#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END + +#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START +/* + * SRAM scratch space entries + */ +#define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR +#define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) +#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) +#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) +#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14) + +/* Silicon revisions */ +#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF +#define OMAP4430_ES1_0 0x44300100 +#define OMAP4430_ES2_0 0x44300200 +#define OMAP4430_ES2_1 0x44300210 +#define OMAP4430_ES2_2 0x44300220 +#define OMAP4430_ES2_3 0x44300230 +#define OMAP4460_ES1_0 0x44600100 +#define OMAP4460_ES1_1 0x44600110 + +/* ROM code defines */ +/* Boot device */ +#define BOOT_DEVICE_MASK 0xFF +#define BOOT_DEVICE_OFFSET 0x8 +#define DEV_DESC_PTR_OFFSET 0x4 +#define DEV_DATA_PTR_OFFSET 0x18 +#define BOOT_MODE_OFFSET 0x8 +#define RESET_REASON_OFFSET 0x9 +#define CH_FLAGS_OFFSET 0xA + +#define CH_FLAGS_CHSETTINGS (0x1 << 0) +#define CH_FLAGS_CHRAM (0x1 << 1) +#define CH_FLAGS_CHFLASH (0x1 << 2) +#define CH_FLAGS_CHMMCSD (0x1 << 3) + +#ifndef __ASSEMBLY__ +struct omap_boot_parameters { + char *boot_message; + unsigned int mem_boot_descriptor; + unsigned char omap_bootdevice; + unsigned char reset_reason; + unsigned char ch_flags; +}; +#endif /* __ASSEMBLY__ */ +#endif diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h new file mode 100644 index 000000000..c31e18ca2 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +#include <asm/arch/omap.h> +#include <asm/io.h> +#include <asm/arch/clocks.h> +#include <asm/omap_common.h> +#include <asm/arch/mux_omap5.h> +#include <asm/arch/clocks.h> + +struct omap_sysinfo { + char *board_string; +}; +extern const struct omap_sysinfo sysinfo; + +void gpmc_init(void); +void watchdog_init(void); +u32 get_device_type(void); +void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); +void set_muxconf_regs_essential(void); +void set_muxconf_regs_non_essential(void); +void sr32(void *, u32, u32, u32); +u32 wait_on_value(u32, u32, void *, u32); +void sdelay(unsigned long); +void omap_rev_string(char *omap_rev_string); +void setup_clocks_for_console(void); +void prcm_init(void); +void bypass_dpll(u32 *const base); +void freq_update_core(void); +u32 get_sys_clk_freq(void); +u32 omap5_ddr_clk(void); +void cancel_out(u32 *num, u32 *den, u32 den_limit); +void sdram_init(void); +u32 omap_sdram_size(void); +u32 cortex_rev(void); +void init_omap_revision(void); +void do_io_settings(void); + +/* + * This is used to verify if the configuration header + * was executed by Romcode prior to control of transfer + * to the bootloader. SPL is responsible for saving and + * passing this to the u-boot. + */ +extern struct omap_boot_parameters boot_params; + +static inline u32 running_from_sdram(void) +{ + u32 pc; + asm volatile ("mov %0, pc" : "=r" (pc)); + return ((pc >= OMAP54XX_DRAM_ADDR_SPACE_START) && + (pc < OMAP54XX_DRAM_ADDR_SPACE_END)); +} + +static inline u8 uboot_loaded_by_spl(void) +{ + /* + * u-boot can be running from sdram either because of configuration + * Header or by SPL. If because of CH, then the romcode sets the + * CHSETTINGS executed bit to true in the boot parameter structure that + * it passes to the bootloader.This parameter is stored in the ch_flags + * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a + * mandatory section if CH is present. + */ + if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) + return 0; + else + return running_from_sdram(); +} +/* + * The basic hardware init of OMAP(s_init()) can happen in 4 + * different contexts: + * 1. SPL running from SRAM + * 2. U-Boot running from FLASH + * 3. Non-XIP U-Boot loaded to SDRAM by SPL + * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the + * Configuration Header feature + * + * This function finds this context. + * Defining as inline may help in compiling out unused functions in SPL + */ +static inline u32 omap_hw_init_context(void) +{ +#ifdef CONFIG_SPL_BUILD + return OMAP_INIT_CONTEXT_SPL; +#else + if (uboot_loaded_by_spl()) + return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; + else if (running_from_sdram()) + return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; + else + return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; +#endif +} + +static inline u32 omap_revision(void) +{ + extern u32 *const omap5_revision; + return *omap5_revision; +} + +#endif diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index 109fdc06a..52c79a9e6 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -315,117 +315,6 @@ typedef void (*ExcpHndlr) (void) ; /******************************************************************************/ /* - * UARTs - */ -/* Full Function UART (FFUART) */ -#define FFUART FFRBR -#define FFRBR 0x40100000 /* Receive Buffer Register (read only) */ -#define FFTHR 0x40100000 /* Transmit Holding Register (write only) */ -#define FFIER 0x40100004 /* Interrupt Enable Register (read/write) */ -#define FFIIR 0x40100008 /* Interrupt ID Register (read only) */ -#define FFFCR 0x40100008 /* FIFO Control Register (write only) */ -#define FFLCR 0x4010000C /* Line Control Register (read/write) */ -#define FFMCR 0x40100010 /* Modem Control Register (read/write) */ -#define FFLSR 0x40100014 /* Line Status Register (read only) */ -#define FFMSR 0x40100018 /* Modem Status Register (read only) */ -#define FFSPR 0x4010001C /* Scratch Pad Register (read/write) */ -#define FFISR 0x40100020 /* Infrared Selection Register (read/write) */ -#define FFDLL 0x40100000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define FFDLH 0x40100004 /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Bluetooth UART (BTUART) */ -#define BTUART BTRBR -#define BTRBR 0x40200000 /* Receive Buffer Register (read only) */ -#define BTTHR 0x40200000 /* Transmit Holding Register (write only) */ -#define BTIER 0x40200004 /* Interrupt Enable Register (read/write) */ -#define BTIIR 0x40200008 /* Interrupt ID Register (read only) */ -#define BTFCR 0x40200008 /* FIFO Control Register (write only) */ -#define BTLCR 0x4020000C /* Line Control Register (read/write) */ -#define BTMCR 0x40200010 /* Modem Control Register (read/write) */ -#define BTLSR 0x40200014 /* Line Status Register (read only) */ -#define BTMSR 0x40200018 /* Modem Status Register (read only) */ -#define BTSPR 0x4020001C /* Scratch Pad Register (read/write) */ -#define BTISR 0x40200020 /* Infrared Selection Register (read/write) */ -#define BTDLL 0x40200000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define BTDLH 0x40200004 /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -/* Standard UART (STUART) */ -#define STUART STRBR -#define STRBR 0x40700000 /* Receive Buffer Register (read only) */ -#define STTHR 0x40700000 /* Transmit Holding Register (write only) */ -#define STIER 0x40700004 /* Interrupt Enable Register (read/write) */ -#define STIIR 0x40700008 /* Interrupt ID Register (read only) */ -#define STFCR 0x40700008 /* FIFO Control Register (write only) */ -#define STLCR 0x4070000C /* Line Control Register (read/write) */ -#define STMCR 0x40700010 /* Modem Control Register (read/write) */ -#define STLSR 0x40700014 /* Line Status Register (read only) */ -#define STMSR 0x40700018 /* Reserved */ -#define STSPR 0x4070001C /* Scratch Pad Register (read/write) */ -#define STISR 0x40700020 /* Infrared Selection Register (read/write) */ -#define STDLL 0x40700000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define STDLH 0x40700004 /* Divisor Latch High Register (DLAB = 1) (read/write) */ - -#define IER_DMAE (1 << 7) /* DMA Requests Enable */ -#define IER_UUE (1 << 6) /* UART Unit Enable */ -#define IER_NRZE (1 << 5) /* NRZ coding Enable */ -#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ -#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ -#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ -#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ -#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ - -#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ -#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ -#define IIR_TOD (1 << 3) /* Time Out Detected */ -#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ -#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ -#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ - -#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ -#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ -#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ -#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ -#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ -#define FCR_ITL_1 (0) -#define FCR_ITL_8 (FCR_ITL1) -#define FCR_ITL_16 (FCR_ITL2) -#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) - -#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ -#define LCR_SB (1 << 6) /* Set Break */ -#define LCR_STKYP (1 << 5) /* Sticky Parity */ -#define LCR_EPS (1 << 4) /* Even Parity Select */ -#define LCR_PEN (1 << 3) /* Parity Enable */ -#define LCR_STB (1 << 2) /* Stop Bit */ -#define LCR_WLS1 (1 << 1) /* Word Length Select */ -#define LCR_WLS0 (1 << 0) /* Word Length Select */ - -#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ -#define LSR_TEMT (1 << 6) /* Transmitter Empty */ -#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ -#define LSR_BI (1 << 4) /* Break Interrupt */ -#define LSR_FE (1 << 3) /* Framing Error */ -#define LSR_PE (1 << 2) /* Parity Error */ -#define LSR_OE (1 << 1) /* Overrun Error */ -#define LSR_DR (1 << 0) /* Data Ready */ - -#define MCR_LOOP (1 << 4) /* */ -#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ -#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ -#define MCR_RTS (1 << 1) /* Request to Send */ -#define MCR_DTR (1 << 0) /* Data Terminal Ready */ - -#define MSR_DCD (1 << 7) /* Data Carrier Detect */ -#define MSR_RI (1 << 6) /* Ring Indicator */ -#define MSR_DSR (1 << 5) /* Data Set Ready */ -#define MSR_CTS (1 << 4) /* Clear To Send */ -#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ -#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ -#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ -#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ - -/******************************************************************************/ -/* * IrSR (Infrared Selection Register) */ #define IrSR_OFFSET 0x20 diff --git a/arch/arm/include/asm/arch-pxa/regs-uart.h b/arch/arm/include/asm/arch-pxa/regs-uart.h new file mode 100644 index 000000000..355e89245 --- /dev/null +++ b/arch/arm/include/asm/arch-pxa/regs-uart.h @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __REGS_UART_H__ +#define __REGS_UART_H__ + +#define FFUART_BASE 0x40100000 +#define BTUART_BASE 0x40200000 +#define STUART_BASE 0x40700000 +#define HWUART_BASE 0x41600000 + +struct pxa_uart_regs { + union { + uint32_t thr; + uint32_t rbr; + uint32_t dll; + }; + union { + uint32_t ier; + uint32_t dlh; + }; + union { + uint32_t fcr; + uint32_t iir; + }; + uint32_t lcr; + uint32_t mcr; + uint32_t lsr; + uint32_t msr; + uint32_t spr; + uint32_t isr; +}; + +#define IER_DMAE (1 << 7) +#define IER_UUE (1 << 6) +#define IER_NRZE (1 << 5) +#define IER_RTIOE (1 << 4) +#define IER_MIE (1 << 3) +#define IER_RLSE (1 << 2) +#define IER_TIE (1 << 1) +#define IER_RAVIE (1 << 0) + +#define IIR_FIFOES1 (1 << 7) +#define IIR_FIFOES0 (1 << 6) +#define IIR_TOD (1 << 3) +#define IIR_IID2 (1 << 2) +#define IIR_IID1 (1 << 1) +#define IIR_IP (1 << 0) + +#define FCR_ITL2 (1 << 7) +#define FCR_ITL1 (1 << 6) +#define FCR_RESETTF (1 << 2) +#define FCR_RESETRF (1 << 1) +#define FCR_TRFIFOE (1 << 0) +#define FCR_ITL_1 0 +#define FCR_ITL_8 (FCR_ITL1) +#define FCR_ITL_16 (FCR_ITL2) +#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) + +#define LCR_DLAB (1 << 7) +#define LCR_SB (1 << 6) +#define LCR_STKYP (1 << 5) +#define LCR_EPS (1 << 4) +#define LCR_PEN (1 << 3) +#define LCR_STB (1 << 2) +#define LCR_WLS1 (1 << 1) +#define LCR_WLS0 (1 << 0) + +#define LSR_FIFOE (1 << 7) +#define LSR_TEMT (1 << 6) +#define LSR_TDRQ (1 << 5) +#define LSR_BI (1 << 4) +#define LSR_FE (1 << 3) +#define LSR_PE (1 << 2) +#define LSR_OE (1 << 1) +#define LSR_DR (1 << 0) + +#define MCR_LOOP (1 << 4) +#define MCR_OUT2 (1 << 3) +#define MCR_OUT1 (1 << 2) +#define MCR_RTS (1 << 1) +#define MCR_DTR (1 << 0) + +#define MSR_DCD (1 << 7) +#define MSR_RI (1 << 6) +#define MSR_DSR (1 << 5) +#define MSR_CTS (1 << 4) +#define MSR_DDCD (1 << 3) +#define MSR_TERI (1 << 2) +#define MSR_DDSR (1 << 1) +#define MSR_DCTS (1 << 0) + +#endif /* __REGS_UART_H__ */ diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index 9adc56378..ad9a875de 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -31,6 +31,9 @@ #define MIDR_CORTEX_A9_R1P3 0x411FC093 #define MIDR_CORTEX_A9_R2P10 0x412FC09A +/* Cortex-A15 revisions */ +#define MIDR_CORTEX_A15_R0P0 0x410FC0F0 + /* CCSIDR */ #define CCSIDR_LINE_SIZE_OFFSET 0 #define CCSIDR_LINE_SIZE_MASK 0x7 diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h new file mode 100644 index 000000000..e5c7d2cab --- /dev/null +++ b/arch/arm/include/asm/emif.h @@ -0,0 +1,1035 @@ +/* + * OMAP44xx EMIF header + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Aneesh V <aneesh@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _EMIF_H_ +#define _EMIF_H_ +#include <asm/types.h> +#include <common.h> + +/* Base address */ +#define EMIF1_BASE 0x4c000000 +#define EMIF2_BASE 0x4d000000 + +/* Registers shifts and masks */ + +/* EMIF_MOD_ID_REV */ +#define EMIF_REG_SCHEME_SHIFT 30 +#define EMIF_REG_SCHEME_MASK (0x3 << 30) +#define EMIF_REG_MODULE_ID_SHIFT 16 +#define EMIF_REG_MODULE_ID_MASK (0xfff << 16) +#define EMIF_REG_RTL_VERSION_SHIFT 11 +#define EMIF_REG_RTL_VERSION_MASK (0x1f << 11) +#define EMIF_REG_MAJOR_REVISION_SHIFT 8 +#define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8) +#define EMIF_REG_MINOR_REVISION_SHIFT 0 +#define EMIF_REG_MINOR_REVISION_MASK (0x3f << 0) + +/* STATUS */ +#define EMIF_REG_BE_SHIFT 31 +#define EMIF_REG_BE_MASK (1 << 31) +#define EMIF_REG_DUAL_CLK_MODE_SHIFT 30 +#define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30) +#define EMIF_REG_FAST_INIT_SHIFT 29 +#define EMIF_REG_FAST_INIT_MASK (1 << 29) +#define EMIF_REG_PHY_DLL_READY_SHIFT 2 +#define EMIF_REG_PHY_DLL_READY_MASK (1 << 2) + +/* SDRAM_CONFIG */ +#define EMIF_REG_SDRAM_TYPE_SHIFT 29 +#define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29) +#define EMIF_REG_IBANK_POS_SHIFT 27 +#define EMIF_REG_IBANK_POS_MASK (0x3 << 27) +#define EMIF_REG_DDR_TERM_SHIFT 24 +#define EMIF_REG_DDR_TERM_MASK (0x7 << 24) +#define EMIF_REG_DDR2_DDQS_SHIFT 23 +#define EMIF_REG_DDR2_DDQS_MASK (1 << 23) +#define EMIF_REG_DYN_ODT_SHIFT 21 +#define EMIF_REG_DYN_ODT_MASK (0x3 << 21) +#define EMIF_REG_DDR_DISABLE_DLL_SHIFT 20 +#define EMIF_REG_DDR_DISABLE_DLL_MASK (1 << 20) +#define EMIF_REG_SDRAM_DRIVE_SHIFT 18 +#define EMIF_REG_SDRAM_DRIVE_MASK (0x3 << 18) +#define EMIF_REG_CWL_SHIFT 16 +#define EMIF_REG_CWL_MASK (0x3 << 16) +#define EMIF_REG_NARROW_MODE_SHIFT 14 +#define EMIF_REG_NARROW_MODE_MASK (0x3 << 14) +#define EMIF_REG_CL_SHIFT 10 +#define EMIF_REG_CL_MASK (0xf << 10) +#define EMIF_REG_ROWSIZE_SHIFT 7 +#define EMIF_REG_ROWSIZE_MASK (0x7 << 7) +#define EMIF_REG_IBANK_SHIFT 4 +#define EMIF_REG_IBANK_MASK (0x7 << 4) +#define EMIF_REG_EBANK_SHIFT 3 +#define EMIF_REG_EBANK_MASK (1 << 3) +#define EMIF_REG_PAGESIZE_SHIFT 0 +#define EMIF_REG_PAGESIZE_MASK (0x7 << 0) + +/* SDRAM_CONFIG_2 */ +#define EMIF_REG_CS1NVMEN_SHIFT 30 +#define EMIF_REG_CS1NVMEN_MASK (1 << 30) +#define EMIF_REG_EBANK_POS_SHIFT 27 +#define EMIF_REG_EBANK_POS_MASK (1 << 27) +#define EMIF_REG_RDBNUM_SHIFT 4 +#define EMIF_REG_RDBNUM_MASK (0x3 << 4) +#define EMIF_REG_RDBSIZE_SHIFT 0 +#define EMIF_REG_RDBSIZE_MASK (0x7 << 0) + +/* SDRAM_REF_CTRL */ +#define EMIF_REG_INITREF_DIS_SHIFT 31 +#define EMIF_REG_INITREF_DIS_MASK (1 << 31) +#define EMIF_REG_SRT_SHIFT 29 +#define EMIF_REG_SRT_MASK (1 << 29) +#define EMIF_REG_ASR_SHIFT 28 +#define EMIF_REG_ASR_MASK (1 << 28) +#define EMIF_REG_PASR_SHIFT 24 +#define EMIF_REG_PASR_MASK (0x7 << 24) +#define EMIF_REG_REFRESH_RATE_SHIFT 0 +#define EMIF_REG_REFRESH_RATE_MASK (0xffff << 0) + +/* SDRAM_REF_CTRL_SHDW */ +#define EMIF_REG_REFRESH_RATE_SHDW_SHIFT 0 +#define EMIF_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0) + +/* SDRAM_TIM_1 */ +#define EMIF_REG_T_RP_SHIFT 25 +#define EMIF_REG_T_RP_MASK (0xf << 25) +#define EMIF_REG_T_RCD_SHIFT 21 +#define EMIF_REG_T_RCD_MASK (0xf << 21) +#define EMIF_REG_T_WR_SHIFT 17 +#define EMIF_REG_T_WR_MASK (0xf << 17) +#define EMIF_REG_T_RAS_SHIFT 12 +#define EMIF_REG_T_RAS_MASK (0x1f << 12) +#define EMIF_REG_T_RC_SHIFT 6 +#define EMIF_REG_T_RC_MASK (0x3f << 6) +#define EMIF_REG_T_RRD_SHIFT 3 +#define EMIF_REG_T_RRD_MASK (0x7 << 3) +#define EMIF_REG_T_WTR_SHIFT 0 +#define EMIF_REG_T_WTR_MASK (0x7 << 0) + +/* SDRAM_TIM_1_SHDW */ +#define EMIF_REG_T_RP_SHDW_SHIFT 25 +#define EMIF_REG_T_RP_SHDW_MASK (0xf << 25) +#define EMIF_REG_T_RCD_SHDW_SHIFT 21 +#define EMIF_REG_T_RCD_SHDW_MASK (0xf << 21) +#define EMIF_REG_T_WR_SHDW_SHIFT 17 +#define EMIF_REG_T_WR_SHDW_MASK (0xf << 17) +#define EMIF_REG_T_RAS_SHDW_SHIFT 12 +#define EMIF_REG_T_RAS_SHDW_MASK (0x1f << 12) +#define EMIF_REG_T_RC_SHDW_SHIFT 6 +#define EMIF_REG_T_RC_SHDW_MASK (0x3f << 6) +#define EMIF_REG_T_RRD_SHDW_SHIFT 3 +#define EMIF_REG_T_RRD_SHDW_MASK (0x7 << 3) +#define EMIF_REG_T_WTR_SHDW_SHIFT 0 +#define EMIF_REG_T_WTR_SHDW_MASK (0x7 << 0) + +/* SDRAM_TIM_2 */ +#define EMIF_REG_T_XP_SHIFT 28 +#define EMIF_REG_T_XP_MASK (0x7 << 28) +#define EMIF_REG_T_ODT_SHIFT 25 +#define EMIF_REG_T_ODT_MASK (0x7 << 25) +#define EMIF_REG_T_XSNR_SHIFT 16 +#define EMIF_REG_T_XSNR_MASK (0x1ff << 16) +#define EMIF_REG_T_XSRD_SHIFT 6 +#define EMIF_REG_T_XSRD_MASK (0x3ff << 6) +#define EMIF_REG_T_RTP_SHIFT 3 +#define EMIF_REG_T_RTP_MASK (0x7 << 3) +#define EMIF_REG_T_CKE_SHIFT 0 +#define EMIF_REG_T_CKE_MASK (0x7 << 0) + +/* SDRAM_TIM_2_SHDW */ +#define EMIF_REG_T_XP_SHDW_SHIFT 28 +#define EMIF_REG_T_XP_SHDW_MASK (0x7 << 28) +#define EMIF_REG_T_ODT_SHDW_SHIFT 25 +#define EMIF_REG_T_ODT_SHDW_MASK (0x7 << 25) +#define EMIF_REG_T_XSNR_SHDW_SHIFT 16 +#define EMIF_REG_T_XSNR_SHDW_MASK (0x1ff << 16) +#define EMIF_REG_T_XSRD_SHDW_SHIFT 6 +#define EMIF_REG_T_XSRD_SHDW_MASK (0x3ff << 6) +#define EMIF_REG_T_RTP_SHDW_SHIFT 3 +#define EMIF_REG_T_RTP_SHDW_MASK (0x7 << 3) +#define EMIF_REG_T_CKE_SHDW_SHIFT 0 +#define EMIF_REG_T_CKE_SHDW_MASK (0x7 << 0) + +/* SDRAM_TIM_3 */ +#define EMIF_REG_T_CKESR_SHIFT 21 +#define EMIF_REG_T_CKESR_MASK (0x7 << 21) +#define EMIF_REG_ZQ_ZQCS_SHIFT 15 +#define EMIF_REG_ZQ_ZQCS_MASK (0x3f << 15) +#define EMIF_REG_T_TDQSCKMAX_SHIFT 13 +#define EMIF_REG_T_TDQSCKMAX_MASK (0x3 << 13) +#define EMIF_REG_T_RFC_SHIFT 4 +#define EMIF_REG_T_RFC_MASK (0x1ff << 4) +#define EMIF_REG_T_RAS_MAX_SHIFT 0 +#define EMIF_REG_T_RAS_MAX_MASK (0xf << 0) + +/* SDRAM_TIM_3_SHDW */ +#define EMIF_REG_T_CKESR_SHDW_SHIFT 21 +#define EMIF_REG_T_CKESR_SHDW_MASK (0x7 << 21) +#define EMIF_REG_ZQ_ZQCS_SHDW_SHIFT 15 +#define EMIF_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15) +#define EMIF_REG_T_TDQSCKMAX_SHDW_SHIFT 13 +#define EMIF_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13) +#define EMIF_REG_T_RFC_SHDW_SHIFT 4 +#define EMIF_REG_T_RFC_SHDW_MASK (0x1ff << 4) +#define EMIF_REG_T_RAS_MAX_SHDW_SHIFT 0 +#define EMIF_REG_T_RAS_MAX_SHDW_MASK (0xf << 0) + +/* LPDDR2_NVM_TIM */ +#define EMIF_REG_NVM_T_XP_SHIFT 28 +#define EMIF_REG_NVM_T_XP_MASK (0x7 << 28) +#define EMIF_REG_NVM_T_WTR_SHIFT 24 +#define EMIF_REG_NVM_T_WTR_MASK (0x7 << 24) +#define EMIF_REG_NVM_T_RP_SHIFT 20 +#define EMIF_REG_NVM_T_RP_MASK (0xf << 20) +#define EMIF_REG_NVM_T_WRA_SHIFT 16 +#define EMIF_REG_NVM_T_WRA_MASK (0xf << 16) +#define EMIF_REG_NVM_T_RRD_SHIFT 8 +#define EMIF_REG_NVM_T_RRD_MASK (0xff << 8) +#define EMIF_REG_NVM_T_RCDMIN_SHIFT 0 +#define EMIF_REG_NVM_T_RCDMIN_MASK (0xff << 0) + +/* LPDDR2_NVM_TIM_SHDW */ +#define EMIF_REG_NVM_T_XP_SHDW_SHIFT 28 +#define EMIF_REG_NVM_T_XP_SHDW_MASK (0x7 << 28) +#define EMIF_REG_NVM_T_WTR_SHDW_SHIFT 24 +#define EMIF_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24) +#define EMIF_REG_NVM_T_RP_SHDW_SHIFT 20 +#define EMIF_REG_NVM_T_RP_SHDW_MASK (0xf << 20) +#define EMIF_REG_NVM_T_WRA_SHDW_SHIFT 16 +#define EMIF_REG_NVM_T_WRA_SHDW_MASK (0xf << 16) +#define EMIF_REG_NVM_T_RRD_SHDW_SHIFT 8 +#define EMIF_REG_NVM_T_RRD_SHDW_MASK (0xff << 8) +#define EMIF_REG_NVM_T_RCDMIN_SHDW_SHIFT 0 +#define EMIF_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0) + +/* PWR_MGMT_CTRL */ +#define EMIF_REG_IDLEMODE_SHIFT 30 +#define EMIF_REG_IDLEMODE_MASK (0x3 << 30) +#define EMIF_REG_PD_TIM_SHIFT 12 +#define EMIF_REG_PD_TIM_MASK (0xf << 12) +#define EMIF_REG_DPD_EN_SHIFT 11 +#define EMIF_REG_DPD_EN_MASK (1 << 11) +#define EMIF_REG_LP_MODE_SHIFT 8 +#define EMIF_REG_LP_MODE_MASK (0x7 << 8) +#define EMIF_REG_SR_TIM_SHIFT 4 +#define EMIF_REG_SR_TIM_MASK (0xf << 4) +#define EMIF_REG_CS_TIM_SHIFT 0 +#define EMIF_REG_CS_TIM_MASK (0xf << 0) + +/* PWR_MGMT_CTRL_SHDW */ +#define EMIF_REG_PD_TIM_SHDW_SHIFT 8 +#define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 8) +#define EMIF_REG_SR_TIM_SHDW_SHIFT 4 +#define EMIF_REG_SR_TIM_SHDW_MASK (0xf << 4) +#define EMIF_REG_CS_TIM_SHDW_SHIFT 0 +#define EMIF_REG_CS_TIM_SHDW_MASK (0xf << 0) + +/* LPDDR2_MODE_REG_DATA */ +#define EMIF_REG_VALUE_0_SHIFT 0 +#define EMIF_REG_VALUE_0_MASK (0x7f << 0) + +/* LPDDR2_MODE_REG_CFG */ +#define EMIF_REG_CS_SHIFT 31 +#define EMIF_REG_CS_MASK (1 << 31) +#define EMIF_REG_REFRESH_EN_SHIFT 30 +#define EMIF_REG_REFRESH_EN_MASK (1 << 30) +#define EMIF_REG_ADDRESS_SHIFT 0 +#define EMIF_REG_ADDRESS_MASK (0xff << 0) + +/* OCP_CONFIG */ +#define EMIF_REG_SYS_THRESH_MAX_SHIFT 24 +#define EMIF_REG_SYS_THRESH_MAX_MASK (0xf << 24) +#define EMIF_REG_MPU_THRESH_MAX_SHIFT 20 +#define EMIF_REG_MPU_THRESH_MAX_MASK (0xf << 20) +#define EMIF_REG_LL_THRESH_MAX_SHIFT 16 +#define EMIF_REG_LL_THRESH_MAX_MASK (0xf << 16) +#define EMIF_REG_PR_OLD_COUNT_SHIFT 0 +#define EMIF_REG_PR_OLD_COUNT_MASK (0xff << 0) + +/* OCP_CFG_VAL_1 */ +#define EMIF_REG_SYS_BUS_WIDTH_SHIFT 30 +#define EMIF_REG_SYS_BUS_WIDTH_MASK (0x3 << 30) +#define EMIF_REG_LL_BUS_WIDTH_SHIFT 28 +#define EMIF_REG_LL_BUS_WIDTH_MASK (0x3 << 28) +#define EMIF_REG_WR_FIFO_DEPTH_SHIFT 8 +#define EMIF_REG_WR_FIFO_DEPTH_MASK (0xff << 8) +#define EMIF_REG_CMD_FIFO_DEPTH_SHIFT 0 +#define EMIF_REG_CMD_FIFO_DEPTH_MASK (0xff << 0) + +/* OCP_CFG_VAL_2 */ +#define EMIF_REG_RREG_FIFO_DEPTH_SHIFT 16 +#define EMIF_REG_RREG_FIFO_DEPTH_MASK (0xff << 16) +#define EMIF_REG_RSD_FIFO_DEPTH_SHIFT 8 +#define EMIF_REG_RSD_FIFO_DEPTH_MASK (0xff << 8) +#define EMIF_REG_RCMD_FIFO_DEPTH_SHIFT 0 +#define EMIF_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0) + +/* IODFT_TLGC */ +#define EMIF_REG_TLEC_SHIFT 16 +#define EMIF_REG_TLEC_MASK (0xffff << 16) +#define EMIF_REG_MT_SHIFT 14 +#define EMIF_REG_MT_MASK (1 << 14) +#define EMIF_REG_ACT_CAP_EN_SHIFT 13 +#define EMIF_REG_ACT_CAP_EN_MASK (1 << 13) +#define EMIF_REG_OPG_LD_SHIFT 12 +#define EMIF_REG_OPG_LD_MASK (1 << 12) +#define EMIF_REG_RESET_PHY_SHIFT 10 +#define EMIF_REG_RESET_PHY_MASK (1 << 10) +#define EMIF_REG_MMS_SHIFT 8 +#define EMIF_REG_MMS_MASK (1 << 8) +#define EMIF_REG_MC_SHIFT 4 +#define EMIF_REG_MC_MASK (0x3 << 4) +#define EMIF_REG_PC_SHIFT 1 +#define EMIF_REG_PC_MASK (0x7 << 1) +#define EMIF_REG_TM_SHIFT 0 +#define EMIF_REG_TM_MASK (1 << 0) + +/* IODFT_CTRL_MISR_RSLT */ +#define EMIF_REG_DQM_TLMR_SHIFT 16 +#define EMIF_REG_DQM_TLMR_MASK (0x3ff << 16) +#define EMIF_REG_CTL_TLMR_SHIFT 0 +#define EMIF_REG_CTL_TLMR_MASK (0x7ff << 0) + +/* IODFT_ADDR_MISR_RSLT */ +#define EMIF_REG_ADDR_TLMR_SHIFT 0 +#define EMIF_REG_ADDR_TLMR_MASK (0x1fffff << 0) + +/* IODFT_DATA_MISR_RSLT_1 */ +#define EMIF_REG_DATA_TLMR_31_0_SHIFT 0 +#define EMIF_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0) + +/* IODFT_DATA_MISR_RSLT_2 */ +#define EMIF_REG_DATA_TLMR_63_32_SHIFT 0 +#define EMIF_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0) + +/* IODFT_DATA_MISR_RSLT_3 */ +#define EMIF_REG_DATA_TLMR_66_64_SHIFT 0 +#define EMIF_REG_DATA_TLMR_66_64_MASK (0x7 << 0) + +/* PERF_CNT_1 */ +#define EMIF_REG_COUNTER1_SHIFT 0 +#define EMIF_REG_COUNTER1_MASK (0xffffffff << 0) + +/* PERF_CNT_2 */ +#define EMIF_REG_COUNTER2_SHIFT 0 +#define EMIF_REG_COUNTER2_MASK (0xffffffff << 0) + +/* PERF_CNT_CFG */ +#define EMIF_REG_CNTR2_MCONNID_EN_SHIFT 31 +#define EMIF_REG_CNTR2_MCONNID_EN_MASK (1 << 31) +#define EMIF_REG_CNTR2_REGION_EN_SHIFT 30 +#define EMIF_REG_CNTR2_REGION_EN_MASK (1 << 30) +#define EMIF_REG_CNTR2_CFG_SHIFT 16 +#define EMIF_REG_CNTR2_CFG_MASK (0xf << 16) +#define EMIF_REG_CNTR1_MCONNID_EN_SHIFT 15 +#define EMIF_REG_CNTR1_MCONNID_EN_MASK (1 << 15) +#define EMIF_REG_CNTR1_REGION_EN_SHIFT 14 +#define EMIF_REG_CNTR1_REGION_EN_MASK (1 << 14) +#define EMIF_REG_CNTR1_CFG_SHIFT 0 +#define EMIF_REG_CNTR1_CFG_MASK (0xf << 0) + +/* PERF_CNT_SEL */ +#define EMIF_REG_MCONNID2_SHIFT 24 +#define EMIF_REG_MCONNID2_MASK (0xff << 24) +#define EMIF_REG_REGION_SEL2_SHIFT 16 +#define EMIF_REG_REGION_SEL2_MASK (0x3 << 16) +#define EMIF_REG_MCONNID1_SHIFT 8 +#define EMIF_REG_MCONNID1_MASK (0xff << 8) +#define EMIF_REG_REGION_SEL1_SHIFT 0 +#define EMIF_REG_REGION_SEL1_MASK (0x3 << 0) + +/* PERF_CNT_TIM */ +#define EMIF_REG_TOTAL_TIME_SHIFT 0 +#define EMIF_REG_TOTAL_TIME_MASK (0xffffffff << 0) + +/* READ_IDLE_CTRL */ +#define EMIF_REG_READ_IDLE_LEN_SHIFT 16 +#define EMIF_REG_READ_IDLE_LEN_MASK (0xf << 16) +#define EMIF_REG_READ_IDLE_INTERVAL_SHIFT 0 +#define EMIF_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0) + +/* READ_IDLE_CTRL_SHDW */ +#define EMIF_REG_READ_IDLE_LEN_SHDW_SHIFT 16 +#define EMIF_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16) +#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0 +#define EMIF_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0) + +/* IRQ_EOI */ +#define EMIF_REG_EOI_SHIFT 0 +#define EMIF_REG_EOI_MASK (1 << 0) + +/* IRQSTATUS_RAW_SYS */ +#define EMIF_REG_DNV_SYS_SHIFT 2 +#define EMIF_REG_DNV_SYS_MASK (1 << 2) +#define EMIF_REG_TA_SYS_SHIFT 1 +#define EMIF_REG_TA_SYS_MASK (1 << 1) +#define EMIF_REG_ERR_SYS_SHIFT 0 +#define EMIF_REG_ERR_SYS_MASK (1 << 0) + +/* IRQSTATUS_RAW_LL */ +#define EMIF_REG_DNV_LL_SHIFT 2 +#define EMIF_REG_DNV_LL_MASK (1 << 2) +#define EMIF_REG_TA_LL_SHIFT 1 +#define EMIF_REG_TA_LL_MASK (1 << 1) +#define EMIF_REG_ERR_LL_SHIFT 0 +#define EMIF_REG_ERR_LL_MASK (1 << 0) + +/* IRQSTATUS_SYS */ + +/* IRQSTATUS_LL */ + +/* IRQENABLE_SET_SYS */ +#define EMIF_REG_EN_DNV_SYS_SHIFT 2 +#define EMIF_REG_EN_DNV_SYS_MASK (1 << 2) +#define EMIF_REG_EN_TA_SYS_SHIFT 1 +#define EMIF_REG_EN_TA_SYS_MASK (1 << 1) +#define EMIF_REG_EN_ERR_SYS_SHIFT 0 +#define EMIF_REG_EN_ERR_SYS_MASK (1 << 0) + +/* IRQENABLE_SET_LL */ +#define EMIF_REG_EN_DNV_LL_SHIFT 2 +#define EMIF_REG_EN_DNV_LL_MASK (1 << 2) +#define EMIF_REG_EN_TA_LL_SHIFT 1 +#define EMIF_REG_EN_TA_LL_MASK (1 << 1) +#define EMIF_REG_EN_ERR_LL_SHIFT 0 +#define EMIF_REG_EN_ERR_LL_MASK (1 << 0) + +/* IRQENABLE_CLR_SYS */ + +/* IRQENABLE_CLR_LL */ + +/* ZQ_CONFIG */ +#define EMIF_REG_ZQ_CS1EN_SHIFT 31 +#define EMIF_REG_ZQ_CS1EN_MASK (1 << 31) +#define EMIF_REG_ZQ_CS0EN_SHIFT 30 +#define EMIF_REG_ZQ_CS0EN_MASK (1 << 30) +#define EMIF_REG_ZQ_DUALCALEN_SHIFT 29 +#define EMIF_REG_ZQ_DUALCALEN_MASK (1 << 29) +#define EMIF_REG_ZQ_SFEXITEN_SHIFT 28 +#define EMIF_REG_ZQ_SFEXITEN_MASK (1 << 28) +#define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT 18 +#define EMIF_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18) +#define EMIF_REG_ZQ_ZQCL_MULT_SHIFT 16 +#define EMIF_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16) +#define EMIF_REG_ZQ_REFINTERVAL_SHIFT 0 +#define EMIF_REG_ZQ_REFINTERVAL_MASK (0xffff << 0) + +/* TEMP_ALERT_CONFIG */ +#define EMIF_REG_TA_CS1EN_SHIFT 31 +#define EMIF_REG_TA_CS1EN_MASK (1 << 31) +#define EMIF_REG_TA_CS0EN_SHIFT 30 +#define EMIF_REG_TA_CS0EN_MASK (1 << 30) +#define EMIF_REG_TA_SFEXITEN_SHIFT 28 +#define EMIF_REG_TA_SFEXITEN_MASK (1 << 28) +#define EMIF_REG_TA_DEVWDT_SHIFT 26 +#define EMIF_REG_TA_DEVWDT_MASK (0x3 << 26) +#define EMIF_REG_TA_DEVCNT_SHIFT 24 +#define EMIF_REG_TA_DEVCNT_MASK (0x3 << 24) +#define EMIF_REG_TA_REFINTERVAL_SHIFT 0 +#define EMIF_REG_TA_REFINTERVAL_MASK (0x3fffff << 0) + +/* OCP_ERR_LOG */ +#define EMIF_REG_MADDRSPACE_SHIFT 14 +#define EMIF_REG_MADDRSPACE_MASK (0x3 << 14) +#define EMIF_REG_MBURSTSEQ_SHIFT 11 +#define EMIF_REG_MBURSTSEQ_MASK (0x7 << 11) +#define EMIF_REG_MCMD_SHIFT 8 +#define EMIF_REG_MCMD_MASK (0x7 << 8) +#define EMIF_REG_MCONNID_SHIFT 0 +#define EMIF_REG_MCONNID_MASK (0xff << 0) + +/* DDR_PHY_CTRL_1 */ +#define EMIF_REG_DDR_PHY_CTRL_1_SHIFT 4 +#define EMIF_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4) +#define EMIF_REG_READ_LATENCY_SHIFT 0 +#define EMIF_REG_READ_LATENCY_MASK (0xf << 0) +#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4 +#define EMIF_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4) +#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12 +#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12) + +/* DDR_PHY_CTRL_1_SHDW */ +#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4 +#define EMIF_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4) +#define EMIF_REG_READ_LATENCY_SHDW_SHIFT 0 +#define EMIF_REG_READ_LATENCY_SHDW_MASK (0xf << 0) +#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4 +#define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) +#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 +#define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) + +/* DDR_PHY_CTRL_2 */ +#define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 +#define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) + +/* DMM */ +#define DMM_BASE 0x4E000040 + +/* Memory Adapter */ +#define MA_BASE 0x482AF040 + +/* DMM_LISA_MAP */ +#define EMIF_SYS_ADDR_SHIFT 24 +#define EMIF_SYS_ADDR_MASK (0xff << 24) +#define EMIF_SYS_SIZE_SHIFT 20 +#define EMIF_SYS_SIZE_MASK (0x7 << 20) +#define EMIF_SDRC_INTL_SHIFT 18 +#define EMIF_SDRC_INTL_MASK (0x3 << 18) +#define EMIF_SDRC_ADDRSPC_SHIFT 16 +#define EMIF_SDRC_ADDRSPC_MASK (0x3 << 16) +#define EMIF_SDRC_MAP_SHIFT 8 +#define EMIF_SDRC_MAP_MASK (0x3 << 8) +#define EMIF_SDRC_ADDR_SHIFT 0 +#define EMIF_SDRC_ADDR_MASK (0xff << 0) + +/* DMM_LISA_MAP fields */ +#define DMM_SDRC_MAP_UNMAPPED 0 +#define DMM_SDRC_MAP_EMIF1_ONLY 1 +#define DMM_SDRC_MAP_EMIF2_ONLY 2 +#define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3 + +#define DMM_SDRC_INTL_NONE 0 +#define DMM_SDRC_INTL_128B 1 +#define DMM_SDRC_INTL_256B 2 +#define DMM_SDRC_INTL_512 3 + +#define DMM_SDRC_ADDR_SPC_SDRAM 0 +#define DMM_SDRC_ADDR_SPC_NVM 1 +#define DMM_SDRC_ADDR_SPC_INVALID 2 + +#define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\ + (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\ + (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\ + (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\ + (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) + +#define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ + (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)) + +#define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\ + (DMM_SDRC_MAP_EMIF2_ONLY << EMIF_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)) + +/* Trap for invalid TILER PAT entries */ +#define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\ + (0 << EMIF_SDRC_ADDR_SHIFT) |\ + (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ + (DMM_SDRC_ADDR_SPC_INVALID << EMIF_SDRC_ADDRSPC_SHIFT)|\ + (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\ + (0xFF << EMIF_SYS_ADDR_SHIFT)) + + +/* Reg mapping structure */ +struct emif_reg_struct { + u32 emif_mod_id_rev; + u32 emif_status; + u32 emif_sdram_config; + u32 emif_lpddr2_nvm_config; + u32 emif_sdram_ref_ctrl; + u32 emif_sdram_ref_ctrl_shdw; + u32 emif_sdram_tim_1; + u32 emif_sdram_tim_1_shdw; + u32 emif_sdram_tim_2; + u32 emif_sdram_tim_2_shdw; + u32 emif_sdram_tim_3; + u32 emif_sdram_tim_3_shdw; + u32 emif_lpddr2_nvm_tim; + u32 emif_lpddr2_nvm_tim_shdw; + u32 emif_pwr_mgmt_ctrl; + u32 emif_pwr_mgmt_ctrl_shdw; + u32 emif_lpddr2_mode_reg_data; + u32 padding1[1]; + u32 emif_lpddr2_mode_reg_data_es2; + u32 padding11[1]; + u32 emif_lpddr2_mode_reg_cfg; + u32 emif_l3_config; + u32 emif_l3_cfg_val_1; + u32 emif_l3_cfg_val_2; + u32 emif_iodft_tlgc; + u32 padding2[7]; + u32 emif_perf_cnt_1; + u32 emif_perf_cnt_2; + u32 emif_perf_cnt_cfg; + u32 emif_perf_cnt_sel; + u32 emif_perf_cnt_tim; + u32 padding3; + u32 emif_read_idlectrl; + u32 emif_read_idlectrl_shdw; + u32 padding4; + u32 emif_irqstatus_raw_sys; + u32 emif_irqstatus_raw_ll; + u32 emif_irqstatus_sys; + u32 emif_irqstatus_ll; + u32 emif_irqenable_set_sys; + u32 emif_irqenable_set_ll; + u32 emif_irqenable_clr_sys; + u32 emif_irqenable_clr_ll; + u32 padding5; + u32 emif_zq_config; + u32 emif_temp_alert_config; + u32 emif_l3_err_log; + u32 padding6[4]; + u32 emif_ddr_phy_ctrl_1; + u32 emif_ddr_phy_ctrl_1_shdw; + u32 emif_ddr_phy_ctrl_2; +}; + +struct dmm_lisa_map_regs { + u32 dmm_lisa_map_0; + u32 dmm_lisa_map_1; + u32 dmm_lisa_map_2; + u32 dmm_lisa_map_3; +}; + +#define CS0 0 +#define CS1 1 +/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ +#define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */ + +/* + * The period of DDR clk is represented as numerator and denominator for + * better accuracy in integer based calculations. However, if the numerator + * and denominator are very huge there may be chances of overflow in + * calculations. So, as a trade-off keep denominator(and consequently + * numerator) within a limit sacrificing some accuracy - but not much + * If denominator and numerator are already small (such as at 400 MHz) + * no adjustment is needed + */ +#define EMIF_PERIOD_DEN_LIMIT 1000 +/* + * Maximum number of different frequencies supported by EMIF driver + * Determines the number of entries in the pointer array for register + * cache + */ +#define EMIF_MAX_NUM_FREQUENCIES 6 +/* + * Indices into the Addressing Table array. + * One entry each for all the different types of devices with different + * addressing schemes + */ +#define ADDR_TABLE_INDEX64M 0 +#define ADDR_TABLE_INDEX128M 1 +#define ADDR_TABLE_INDEX256M 2 +#define ADDR_TABLE_INDEX512M 3 +#define ADDR_TABLE_INDEX1GS4 4 +#define ADDR_TABLE_INDEX2GS4 5 +#define ADDR_TABLE_INDEX4G 6 +#define ADDR_TABLE_INDEX8G 7 +#define ADDR_TABLE_INDEX1GS2 8 +#define ADDR_TABLE_INDEX2GS2 9 +#define ADDR_TABLE_INDEXMAX 10 + +/* Number of Row bits */ +#define ROW_9 0 +#define ROW_10 1 +#define ROW_11 2 +#define ROW_12 3 +#define ROW_13 4 +#define ROW_14 5 +#define ROW_15 6 +#define ROW_16 7 + +/* Number of Column bits */ +#define COL_8 0 +#define COL_9 1 +#define COL_10 2 +#define COL_11 3 +#define COL_7 4 /*Not supported by OMAP included for completeness */ + +/* Number of Banks*/ +#define BANKS1 0 +#define BANKS2 1 +#define BANKS4 2 +#define BANKS8 3 + +/* Refresh rate in micro seconds x 10 */ +#define T_REFI_15_6 156 +#define T_REFI_7_8 78 +#define T_REFI_3_9 39 + +#define EBANK_CS1_DIS 0 +#define EBANK_CS1_EN 1 + +/* Read Latency used by the device at reset */ +#define RL_BOOT 3 +/* Read Latency for the highest frequency you want to use */ +#ifdef CONFIG_OMAP54XX +#define RL_FINAL 8 +#else +#define RL_FINAL 6 +#endif + + +/* Interleaving policies at EMIF level- between banks and Chip Selects */ +#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0 +#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3 + +/* + * Interleaving policy to be used + * Currently set to MAX interleaving for better performance + */ +#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING + +/* State of the core voltage: + * This is important for some parameters such as read idle control and + * ZQ calibration timings. Timings are much stricter when voltage ramp + * is happening compared to when the voltage is stable. + * We need to calculate two sets of values for these parameters and use + * them accordingly + */ +#define LPDDR2_VOLTAGE_STABLE 0 +#define LPDDR2_VOLTAGE_RAMPING 1 + +/* Length of the forced read idle period in terms of cycles */ +#define EMIF_REG_READ_IDLE_LEN_VAL 5 + +/* Interval between forced 'read idles' */ +/* To be used when voltage is changed for DPS/DVFS - 1us */ +#define READ_IDLE_INTERVAL_DVFS (1*1000) +/* + * To be used when voltage is not scaled except by Smart Reflex + * 50us - or maximum value will do + */ +#define READ_IDLE_INTERVAL_NORMAL (50*1000) + + +/* + * Unless voltage is changing due to DVFS one ZQCS command every 50ms should + * be enough. This shoule be enough also in the case when voltage is changing + * due to smart-reflex. + */ +#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000) +/* + * If voltage is changing due to DVFS ZQCS should be performed more + * often(every 50us) + */ +#define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50 + +/* The interval between ZQCL commands as a multiple of ZQCS interval */ +#define REG_ZQ_ZQCL_MULT 4 +/* The interval between ZQINIT commands as a multiple of ZQCL interval */ +#define REG_ZQ_ZQINIT_MULT 3 +/* Enable ZQ Calibration on exiting Self-refresh */ +#define REG_ZQ_SFEXITEN_ENABLE 1 +/* + * ZQ Calibration simultaneously on both chip-selects: + * Needs one calibration resistor per CS + * None of the boards that we know of have this capability + * So disabled by default + */ +#define REG_ZQ_DUALCALEN_DISABLE 0 +/* + * Enable ZQ Calibration by default on CS0. If we are asked to program + * the EMIF there will be something connected to CS0 for sure + */ +#define REG_ZQ_CS0EN_ENABLE 1 + +/* EMIF_PWR_MGMT_CTRL register */ +/* Low power modes */ +#define LP_MODE_DISABLE 0 +#define LP_MODE_CLOCK_STOP 1 +#define LP_MODE_SELF_REFRESH 2 +#define LP_MODE_PWR_DN 3 + +/* REG_DPD_EN */ +#define DPD_DISABLE 0 +#define DPD_ENABLE 1 + +/* Maximum delay before Low Power Modes */ +#define REG_CS_TIM 0xF +#define REG_SR_TIM 0xF +#define REG_PD_TIM 0xF + +/* EMIF_PWR_MGMT_CTRL register */ +#define EMIF_PWR_MGMT_CTRL (\ + ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\ + ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\ + ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\ + ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\ + ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\ + & EMIF_REG_LP_MODE_MASK) |\ + ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\ + & EMIF_REG_DPD_EN_MASK))\ + +#define EMIF_PWR_MGMT_CTRL_SHDW (\ + ((REG_CS_TIM << EMIF_REG_CS_TIM_SHDW_SHIFT)\ + & EMIF_REG_CS_TIM_SHDW_MASK) |\ + ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\ + & EMIF_REG_SR_TIM_SHDW_MASK) |\ + ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\ + & EMIF_REG_PD_TIM_SHDW_MASK) |\ + ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\ + & EMIF_REG_PD_TIM_SHDW_MASK)) + +/* EMIF_L3_CONFIG register value */ +#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF +#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000 +#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0 0x0A300000 + +/* + * Value of bits 12:31 of DDR_PHY_CTRL_1 register: + * All these fields have magic values dependent on frequency and + * determined by PHY and DLL integration with EMIF. Setting the magic + * values suggested by hw team. + */ +#define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF +#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41 +#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80 +#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF + +/* +* MR1 value: +* Burst length : 8 +* Burst type : sequential +* Wrap : enabled +* nWR : 3(default). EMIF does not do pre-charge. +* : So nWR is don't care +*/ +#define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23 + +/* MR2 */ +#define MR2_RL3_WL1 1 +#define MR2_RL4_WL2 2 +#define MR2_RL5_WL2 3 +#define MR2_RL6_WL3 4 + +/* MR10: ZQ calibration codes */ +#define MR10_ZQ_ZQCS 0x56 +#define MR10_ZQ_ZQCL 0xAB +#define MR10_ZQ_ZQINIT 0xFF +#define MR10_ZQ_ZQRESET 0xC3 + +/* TEMP_ALERT_CONFIG */ +#define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */ +#define TEMP_ALERT_CONFIG_DEVCT_1 0 +#define TEMP_ALERT_CONFIG_DEVWDT_32 2 + +/* MR16 value: refresh full array(no partial array self refresh) */ +#define MR16_REF_FULL_ARRAY 0 + +/* + * Maximum number of entries we keep in our array of timing tables + * We need not keep all the speed bins supported by the device + * We need to keep timing tables for only the speed bins that we + * are interested in + */ +#define MAX_NUM_SPEEDBINS 4 + +/* LPDDR2 Densities */ +#define LPDDR2_DENSITY_64Mb 0 +#define LPDDR2_DENSITY_128Mb 1 +#define LPDDR2_DENSITY_256Mb 2 +#define LPDDR2_DENSITY_512Mb 3 +#define LPDDR2_DENSITY_1Gb 4 +#define LPDDR2_DENSITY_2Gb 5 +#define LPDDR2_DENSITY_4Gb 6 +#define LPDDR2_DENSITY_8Gb 7 +#define LPDDR2_DENSITY_16Gb 8 +#define LPDDR2_DENSITY_32Gb 9 + +/* LPDDR2 type */ +#define LPDDR2_TYPE_S4 0 +#define LPDDR2_TYPE_S2 1 +#define LPDDR2_TYPE_NVM 2 + +/* LPDDR2 IO width */ +#define LPDDR2_IO_WIDTH_32 0 +#define LPDDR2_IO_WIDTH_16 1 +#define LPDDR2_IO_WIDTH_8 2 + +/* Mode register numbers */ +#define LPDDR2_MR0 0 +#define LPDDR2_MR1 1 +#define LPDDR2_MR2 2 +#define LPDDR2_MR3 3 +#define LPDDR2_MR4 4 +#define LPDDR2_MR5 5 +#define LPDDR2_MR6 6 +#define LPDDR2_MR7 7 +#define LPDDR2_MR8 8 +#define LPDDR2_MR9 9 +#define LPDDR2_MR10 10 +#define LPDDR2_MR11 11 +#define LPDDR2_MR16 16 +#define LPDDR2_MR17 17 +#define LPDDR2_MR18 18 + +/* MR0 */ +#define LPDDR2_MR0_DAI_SHIFT 0 +#define LPDDR2_MR0_DAI_MASK 1 +#define LPDDR2_MR0_DI_SHIFT 1 +#define LPDDR2_MR0_DI_MASK (1 << 1) +#define LPDDR2_MR0_DNVI_SHIFT 2 +#define LPDDR2_MR0_DNVI_MASK (1 << 2) + +/* MR4 */ +#define MR4_SDRAM_REF_RATE_SHIFT 0 +#define MR4_SDRAM_REF_RATE_MASK 7 +#define MR4_TUF_SHIFT 7 +#define MR4_TUF_MASK (1 << 7) + +/* MR4 SDRAM Refresh Rate field values */ +#define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0 +#define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1 +#define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2 +#define SDRAM_TEMP_NOMINAL 0x3 +#define SDRAM_TEMP_RESERVED_4 0x4 +#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5 +#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6 +#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7 + +#define LPDDR2_MANUFACTURER_SAMSUNG 1 +#define LPDDR2_MANUFACTURER_QIMONDA 2 +#define LPDDR2_MANUFACTURER_ELPIDA 3 +#define LPDDR2_MANUFACTURER_ETRON 4 +#define LPDDR2_MANUFACTURER_NANYA 5 +#define LPDDR2_MANUFACTURER_HYNIX 6 +#define LPDDR2_MANUFACTURER_MOSEL 7 +#define LPDDR2_MANUFACTURER_WINBOND 8 +#define LPDDR2_MANUFACTURER_ESMT 9 +#define LPDDR2_MANUFACTURER_SPANSION 11 +#define LPDDR2_MANUFACTURER_SST 12 +#define LPDDR2_MANUFACTURER_ZMOS 13 +#define LPDDR2_MANUFACTURER_INTEL 14 +#define LPDDR2_MANUFACTURER_NUMONYX 254 +#define LPDDR2_MANUFACTURER_MICRON 255 + +/* MR8 register fields */ +#define MR8_TYPE_SHIFT 0x0 +#define MR8_TYPE_MASK 0x3 +#define MR8_DENSITY_SHIFT 0x2 +#define MR8_DENSITY_MASK (0xF << 0x2) +#define MR8_IO_WIDTH_SHIFT 0x6 +#define MR8_IO_WIDTH_MASK (0x3 << 0x6) + +struct lpddr2_addressing { + u8 num_banks; + u8 t_REFI_us_x10; + u8 row_sz[2]; /* One entry each for x32 and x16 */ + u8 col_sz[2]; /* One entry each for x32 and x16 */ +}; + +/* Structure for timings from the DDR datasheet */ +struct lpddr2_ac_timings { + u32 max_freq; + u8 RL; + u8 tRPab; + u8 tRCD; + u8 tWR; + u8 tRASmin; + u8 tRRD; + u8 tWTRx2; + u8 tXSR; + u8 tXPx2; + u8 tRFCab; + u8 tRTPx2; + u8 tCKE; + u8 tCKESR; + u8 tZQCS; + u32 tZQCL; + u32 tZQINIT; + u8 tDQSCKMAXx2; + u8 tRASmax; + u8 tFAW; + +}; + +/* + * Min tCK values for some of the parameters: + * If the calculated clock cycles for the respective parameter is + * less than the corresponding min tCK value, we need to set the min + * tCK value. This may happen at lower frequencies. + */ +struct lpddr2_min_tck { + u32 tRL; + u32 tRP_AB; + u32 tRCD; + u32 tWR; + u32 tRAS_MIN; + u32 tRRD; + u32 tWTR; + u32 tXP; + u32 tRTP; + u8 tCKE; + u32 tCKESR; + u32 tFAW; +}; + +struct lpddr2_device_details { + u8 type; + u8 density; + u8 io_width; + u8 manufacturer; +}; + +struct lpddr2_device_timings { + const struct lpddr2_ac_timings **ac_timings; + const struct lpddr2_min_tck *min_tck; +}; + +/* Details of the devices connected to each chip-select of an EMIF instance */ +struct emif_device_details { + const struct lpddr2_device_details *cs0_device_details; + const struct lpddr2_device_details *cs1_device_details; + const struct lpddr2_device_timings *cs0_device_timings; + const struct lpddr2_device_timings *cs1_device_timings; +}; + +/* + * Structure containing shadow of important registers in EMIF + * The calculation function fills in this structure to be later used for + * initialization and DVFS + */ +struct emif_regs { + u32 freq; + u32 sdram_config_init; + u32 sdram_config; + u32 ref_ctrl; + u32 sdram_tim1; + u32 sdram_tim2; + u32 sdram_tim3; + u32 read_idle_ctrl; + u32 zq_config; + u32 temp_alert_config; + u32 emif_ddr_phy_ctlr_1_init; + u32 emif_ddr_phy_ctlr_1; +}; + +/* assert macros */ +#if defined(DEBUG) +#define emif_assert(c) ({ if (!(c)) for (;;); }) +#else +#define emif_assert(c) ({ if (0) hang(); }) +#endif + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs); +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs); +#else +struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, + struct lpddr2_device_details *lpddr2_dev_details); +void emif_get_device_timings(u32 emif_nr, + const struct lpddr2_device_timings **cs0_device_timings, + const struct lpddr2_device_timings **cs1_device_timings); +#endif + +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +extern u32 *const T_num; +extern u32 *const T_den; +extern u32 *const emif_sizes; +#endif + + +#endif diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 254905137..2d5c3bc37 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1104,6 +1104,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_THALES_ADC 3492 #define MACH_TYPE_UBISYS_P9D_EVP 3493 #define MACH_TYPE_ATDGP318 3494 +#define MACH_TYPE_OMAP5_SEVM 3777 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -14209,6 +14210,18 @@ extern unsigned int __machine_arch_type; # define machine_is_atdgp318() (0) #endif +#ifdef CONFIG_MACH_OMAP5_SEVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP5_SEVM +# endif +# define machine_is_omap5_sevm() (machine_arch_type == MACH_TYPE_OMAP5_SEVM) +#else +# define machine_is_omap5_sevm() (0) +#endif + /* * These have not yet been registered */ diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 3f2f004af..f1562ea4a 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -37,7 +37,16 @@ void preloader_console_init(void); /* Boot device */ -#ifdef CONFIG_OMAP44XX /* OMAP4 */ +#ifdef CONFIG_OMAP54XX +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_XIP 1 +#define BOOT_DEVICE_XIPWAIT 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_ONE_NAND 4 +#define BOOT_DEVICE_MMC1 5 +#define BOOT_DEVICE_MMC2 6 +#define BOOT_DEVICE_MMC3 7 +#elif defined(CONFIG_OMAP44XX) /* OMAP4 */ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 #define BOOT_DEVICE_XIPWAIT 2 @@ -71,10 +80,10 @@ struct spl_image_info { extern struct spl_image_info spl_image; +extern u32* boot_params_ptr; u32 omap_boot_device(void); u32 omap_boot_mode(void); - /* SPL common function s*/ void spl_parse_image_header(const struct image_header *header); void omap_rev_string(char *omap_rev_string); @@ -85,4 +94,22 @@ void spl_nand_load_image(void); /* MMC SPL functions */ void spl_mmc_load_image(void); +/* + * silicon revisions. + * Moving this to common, so that most of code can be moved to common, + * directories. + */ + +/* omap4 */ +#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF +#define OMAP4430_ES1_0 0x44300100 +#define OMAP4430_ES2_0 0x44300200 +#define OMAP4430_ES2_1 0x44300210 +#define OMAP4430_ES2_2 0x44300220 +#define OMAP4430_ES2_3 0x44300230 +#define OMAP4460_ES1_0 0x44600100 + +/* omap5 */ +#define OMAP5430_SILICON_ID_INVALID 0 +#define OMAP5430_ES1_0 0x54300100 #endif /* _OMAP_COMMON_H_ */ |