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Diffstat (limited to 'arch/arm/include/asm/arch-omap5')
-rw-r--r--arch/arm/include/asm/arch-omap5/clocks.h722
-rw-r--r--arch/arm/include/asm/arch-omap5/cpu.h175
-rw-r--r--arch/arm/include/asm/arch-omap5/gpio.h50
-rw-r--r--arch/arm/include/asm/arch-omap5/i2c.h74
-rw-r--r--arch/arm/include/asm/arch-omap5/mmc_host_def.h174
-rw-r--r--arch/arm/include/asm/arch-omap5/mux_omap5.h344
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h223
-rw-r--r--arch/arm/include/asm/arch-omap5/sys_proto.h122
8 files changed, 1884 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
new file mode 100644
index 000000000..fa99f654b
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -0,0 +1,722 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_OMAP5_H_
+#define _CLOCKS_OMAP5_H_
+#include <common.h>
+
+/*
+ * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
+ * loop, allow for a minimum of 2 ms wait (in reality the wait will be
+ * much more than that)
+ */
+#define LDELAY 1000000
+
+#define CM_CLKMODE_DPLL_CORE (OMAP54XX_L4_CORE_BASE + 0x4120)
+#define CM_CLKMODE_DPLL_PER (OMAP54XX_L4_CORE_BASE + 0x8140)
+#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160)
+#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100)
+
+struct omap5_prcm_regs {
+ /* cm1.ckgen */
+ u32 cm_clksel_core; /* 4a004100 */
+ u32 pad001[1]; /* 4a004104 */
+ u32 cm_clksel_abe; /* 4a004108 */
+ u32 pad002[1]; /* 4a00410c */
+ u32 cm_dll_ctrl; /* 4a004110 */
+ u32 pad003[3]; /* 4a004114 */
+ u32 cm_clkmode_dpll_core; /* 4a004120 */
+ u32 cm_idlest_dpll_core; /* 4a004124 */
+ u32 cm_autoidle_dpll_core; /* 4a004128 */
+ u32 cm_clksel_dpll_core; /* 4a00412c */
+ u32 cm_div_m2_dpll_core; /* 4a004130 */
+ u32 cm_div_m3_dpll_core; /* 4a004134 */
+ u32 cm_div_h11_dpll_core; /* 4a004138 */
+ u32 cm_div_h12_dpll_core; /* 4a00413c */
+ u32 cm_div_h13_dpll_core; /* 4a004140 */
+ u32 cm_div_h14_dpll_core; /* 4a004144 */
+ u32 cm_ssc_deltamstep_dpll_core; /* 4a004148 */
+ u32 cm_ssc_modfreqdiv_dpll_core; /* 4a00414c */
+ u32 cm_emu_override_dpll_core; /* 4a004150 */
+
+ u32 cm_div_h22_dpllcore; /* 4a004154 */
+ u32 cm_div_h23_dpll_core; /* 4a004158 */
+ u32 pad0041[1]; /* 4a00415c */
+ u32 cm_clkmode_dpll_mpu; /* 4a004160 */
+ u32 cm_idlest_dpll_mpu; /* 4a004164 */
+ u32 cm_autoidle_dpll_mpu; /* 4a004168 */
+ u32 cm_clksel_dpll_mpu; /* 4a00416c */
+ u32 cm_div_m2_dpll_mpu; /* 4a004170 */
+ u32 pad005[5]; /* 4a004174 */
+ u32 cm_ssc_deltamstep_dpll_mpu; /* 4a004188 */
+ u32 cm_ssc_modfreqdiv_dpll_mpu; /* 4a00418c */
+ u32 pad006[3]; /* 4a004190 */
+ u32 cm_bypclk_dpll_mpu; /* 4a00419c */
+ u32 cm_clkmode_dpll_iva; /* 4a0041a0 */
+ u32 cm_idlest_dpll_iva; /* 4a0041a4 */
+ u32 cm_autoidle_dpll_iva; /* 4a0041a8 */
+ u32 cm_clksel_dpll_iva; /* 4a0041ac */
+ u32 pad007[2]; /* 4a0041b0 */
+ u32 cm_div_h11_dpll_iva; /* 4a0041b8 */
+ u32 cm_div_h12_dpll_iva; /* 4a0041bc */
+ u32 pad008[2]; /* 4a0041c0 */
+ u32 cm_ssc_deltamstep_dpll_iva; /* 4a0041c8 */
+ u32 cm_ssc_modfreqdiv_dpll_iva; /* 4a0041cc */
+ u32 pad009[3]; /* 4a0041d0 */
+ u32 cm_bypclk_dpll_iva; /* 4a0041dc */
+ u32 cm_clkmode_dpll_abe; /* 4a0041e0 */
+ u32 cm_idlest_dpll_abe; /* 4a0041e4 */
+ u32 cm_autoidle_dpll_abe; /* 4a0041e8 */
+ u32 cm_clksel_dpll_abe; /* 4a0041ec */
+ u32 cm_div_m2_dpll_abe; /* 4a0041f0 */
+ u32 cm_div_m3_dpll_abe; /* 4a0041f4 */
+ u32 pad010[4]; /* 4a0041f8 */
+ u32 cm_ssc_deltamstep_dpll_abe; /* 4a004208 */
+ u32 cm_ssc_modfreqdiv_dpll_abe; /* 4a00420c */
+ u32 pad011[4]; /* 4a004210 */
+ u32 cm_clkmode_dpll_ddrphy; /* 4a004220 */
+ u32 cm_idlest_dpll_ddrphy; /* 4a004224 */
+ u32 cm_autoidle_dpll_ddrphy; /* 4a004228 */
+ u32 cm_clksel_dpll_ddrphy; /* 4a00422c */
+ u32 cm_div_m2_dpll_ddrphy; /* 4a004230 */
+ u32 pad012[1]; /* 4a004234 */
+ u32 cm_div_h11_dpll_ddrphy; /* 4a004238 */
+ u32 cm_div_h12_dpll_ddrphy; /* 4a00423c */
+ u32 cm_div_h13_dpll_ddrphy; /* 4a004240 */
+ u32 pad013[1]; /* 4a004244 */
+ u32 cm_ssc_deltamstep_dpll_ddrphy; /* 4a004248 */
+ u32 pad014[5]; /* 4a00424c */
+ u32 cm_shadow_freq_config1; /* 4a004260 */
+ u32 pad0141[47]; /* 4a004264 */
+ u32 cm_mpu_mpu_clkctrl; /* 4a004320 */
+
+
+ /* cm1.dsp */
+ u32 pad015[55]; /* 4a004324 */
+ u32 cm_dsp_clkstctrl; /* 4a004400 */
+ u32 pad016[7]; /* 4a004404 */
+ u32 cm_dsp_dsp_clkctrl; /* 4a004420 */
+
+ /* cm1.abe */
+ u32 pad017[55]; /* 4a004424 */
+ u32 cm1_abe_clkstctrl; /* 4a004500 */
+ u32 pad018[7]; /* 4a004504 */
+ u32 cm1_abe_l4abe_clkctrl; /* 4a004520 */
+ u32 pad019[1]; /* 4a004524 */
+ u32 cm1_abe_aess_clkctrl; /* 4a004528 */
+ u32 pad020[1]; /* 4a00452c */
+ u32 cm1_abe_pdm_clkctrl; /* 4a004530 */
+ u32 pad021[1]; /* 4a004534 */
+ u32 cm1_abe_dmic_clkctrl; /* 4a004538 */
+ u32 pad022[1]; /* 4a00453c */
+ u32 cm1_abe_mcasp_clkctrl; /* 4a004540 */
+ u32 pad023[1]; /* 4a004544 */
+ u32 cm1_abe_mcbsp1_clkctrl; /* 4a004548 */
+ u32 pad024[1]; /* 4a00454c */
+ u32 cm1_abe_mcbsp2_clkctrl; /* 4a004550 */
+ u32 pad025[1]; /* 4a004554 */
+ u32 cm1_abe_mcbsp3_clkctrl; /* 4a004558 */
+ u32 pad026[1]; /* 4a00455c */
+ u32 cm1_abe_slimbus_clkctrl; /* 4a004560 */
+ u32 pad027[1]; /* 4a004564 */
+ u32 cm1_abe_timer5_clkctrl; /* 4a004568 */
+ u32 pad028[1]; /* 4a00456c */
+ u32 cm1_abe_timer6_clkctrl; /* 4a004570 */
+ u32 pad029[1]; /* 4a004574 */
+ u32 cm1_abe_timer7_clkctrl; /* 4a004578 */
+ u32 pad030[1]; /* 4a00457c */
+ u32 cm1_abe_timer8_clkctrl; /* 4a004580 */
+ u32 pad031[1]; /* 4a004584 */
+ u32 cm1_abe_wdt3_clkctrl; /* 4a004588 */
+
+ /* cm2.ckgen */
+ u32 pad032[3805]; /* 4a00458c */
+ u32 cm_clksel_mpu_m3_iss_root; /* 4a008100 */
+ u32 cm_clksel_usb_60mhz; /* 4a008104 */
+ u32 cm_scale_fclk; /* 4a008108 */
+ u32 pad033[1]; /* 4a00810c */
+ u32 cm_core_dvfs_perf1; /* 4a008110 */
+ u32 cm_core_dvfs_perf2; /* 4a008114 */
+ u32 cm_core_dvfs_perf3; /* 4a008118 */
+ u32 cm_core_dvfs_perf4; /* 4a00811c */
+ u32 pad034[1]; /* 4a008120 */
+ u32 cm_core_dvfs_current; /* 4a008124 */
+ u32 cm_iva_dvfs_perf_tesla; /* 4a008128 */
+ u32 cm_iva_dvfs_perf_ivahd; /* 4a00812c */
+ u32 cm_iva_dvfs_perf_abe; /* 4a008130 */
+ u32 pad035[1]; /* 4a008134 */
+ u32 cm_iva_dvfs_current; /* 4a008138 */
+ u32 pad036[1]; /* 4a00813c */
+ u32 cm_clkmode_dpll_per; /* 4a008140 */
+ u32 cm_idlest_dpll_per; /* 4a008144 */
+ u32 cm_autoidle_dpll_per; /* 4a008148 */
+ u32 cm_clksel_dpll_per; /* 4a00814c */
+ u32 cm_div_m2_dpll_per; /* 4a008150 */
+ u32 cm_div_m3_dpll_per; /* 4a008154 */
+ u32 cm_div_h11_dpll_per; /* 4a008158 */
+ u32 cm_div_h12_dpll_per; /* 4a00815c */
+ u32 pad0361[1]; /* 4a008160 */
+ u32 cm_div_h14_dpll_per; /* 4a008164 */
+ u32 cm_ssc_deltamstep_dpll_per; /* 4a008168 */
+ u32 cm_ssc_modfreqdiv_dpll_per; /* 4a00816c */
+ u32 cm_emu_override_dpll_per; /* 4a008170 */
+ u32 pad037[3]; /* 4a008174 */
+ u32 cm_clkmode_dpll_usb; /* 4a008180 */
+ u32 cm_idlest_dpll_usb; /* 4a008184 */
+ u32 cm_autoidle_dpll_usb; /* 4a008188 */
+ u32 cm_clksel_dpll_usb; /* 4a00818c */
+ u32 cm_div_m2_dpll_usb; /* 4a008190 */
+ u32 pad038[5]; /* 4a008194 */
+ u32 cm_ssc_deltamstep_dpll_usb; /* 4a0081a8 */
+ u32 cm_ssc_modfreqdiv_dpll_usb; /* 4a0081ac */
+ u32 pad039[1]; /* 4a0081b0 */
+ u32 cm_clkdcoldo_dpll_usb; /* 4a0081b4 */
+ u32 pad040[2]; /* 4a0081b8 */
+ u32 cm_clkmode_dpll_unipro; /* 4a0081c0 */
+ u32 cm_idlest_dpll_unipro; /* 4a0081c4 */
+ u32 cm_autoidle_dpll_unipro; /* 4a0081c8 */
+ u32 cm_clksel_dpll_unipro; /* 4a0081cc */
+ u32 cm_div_m2_dpll_unipro; /* 4a0081d0 */
+ u32 pad041[5]; /* 4a0081d4 */
+ u32 cm_ssc_deltamstep_dpll_unipro; /* 4a0081e8 */
+ u32 cm_ssc_modfreqdiv_dpll_unipro; /* 4a0081ec */
+
+ /* cm2.core */
+ u32 pad0411[324]; /* 4a0081f0 */
+ u32 cm_l3_1_clkstctrl; /* 4a008700 */
+ u32 pad042[1]; /* 4a008704 */
+ u32 cm_l3_1_dynamicdep; /* 4a008708 */
+ u32 pad043[5]; /* 4a00870c */
+ u32 cm_l3_1_l3_1_clkctrl; /* 4a008720 */
+ u32 pad044[55]; /* 4a008724 */
+ u32 cm_l3_2_clkstctrl; /* 4a008800 */
+ u32 pad045[1]; /* 4a008804 */
+ u32 cm_l3_2_dynamicdep; /* 4a008808 */
+ u32 pad046[5]; /* 4a00880c */
+ u32 cm_l3_2_l3_2_clkctrl; /* 4a008820 */
+ u32 pad047[1]; /* 4a008824 */
+ u32 cm_l3_2_gpmc_clkctrl; /* 4a008828 */
+ u32 pad048[1]; /* 4a00882c */
+ u32 cm_l3_2_ocmc_ram_clkctrl; /* 4a008830 */
+ u32 pad049[51]; /* 4a008834 */
+ u32 cm_mpu_m3_clkstctrl; /* 4a008900 */
+ u32 cm_mpu_m3_staticdep; /* 4a008904 */
+ u32 cm_mpu_m3_dynamicdep; /* 4a008908 */
+ u32 pad050[5]; /* 4a00890c */
+ u32 cm_mpu_m3_mpu_m3_clkctrl; /* 4a008920 */
+ u32 pad051[55]; /* 4a008924 */
+ u32 cm_sdma_clkstctrl; /* 4a008a00 */
+ u32 cm_sdma_staticdep; /* 4a008a04 */
+ u32 cm_sdma_dynamicdep; /* 4a008a08 */
+ u32 pad052[5]; /* 4a008a0c */
+ u32 cm_sdma_sdma_clkctrl; /* 4a008a20 */
+ u32 pad053[55]; /* 4a008a24 */
+ u32 cm_memif_clkstctrl; /* 4a008b00 */
+ u32 pad054[7]; /* 4a008b04 */
+ u32 cm_memif_dmm_clkctrl; /* 4a008b20 */
+ u32 pad055[1]; /* 4a008b24 */
+ u32 cm_memif_emif_fw_clkctrl; /* 4a008b28 */
+ u32 pad056[1]; /* 4a008b2c */
+ u32 cm_memif_emif_1_clkctrl; /* 4a008b30 */
+ u32 pad057[1]; /* 4a008b34 */
+ u32 cm_memif_emif_2_clkctrl; /* 4a008b38 */
+ u32 pad058[1]; /* 4a008b3c */
+ u32 cm_memif_dll_clkctrl; /* 4a008b40 */
+ u32 pad059[3]; /* 4a008b44 */
+ u32 cm_memif_emif_h1_clkctrl; /* 4a008b50 */
+ u32 pad060[1]; /* 4a008b54 */
+ u32 cm_memif_emif_h2_clkctrl; /* 4a008b58 */
+ u32 pad061[1]; /* 4a008b5c */
+ u32 cm_memif_dll_h_clkctrl; /* 4a008b60 */
+ u32 pad062[39]; /* 4a008b64 */
+ u32 cm_c2c_clkstctrl; /* 4a008c00 */
+ u32 cm_c2c_staticdep; /* 4a008c04 */
+ u32 cm_c2c_dynamicdep; /* 4a008c08 */
+ u32 pad063[5]; /* 4a008c0c */
+ u32 cm_c2c_sad2d_clkctrl; /* 4a008c20 */
+ u32 pad064[1]; /* 4a008c24 */
+ u32 cm_c2c_modem_icr_clkctrl; /* 4a008c28 */
+ u32 pad065[1]; /* 4a008c2c */
+ u32 cm_c2c_sad2d_fw_clkctrl; /* 4a008c30 */
+ u32 pad066[51]; /* 4a008c34 */
+ u32 cm_l4cfg_clkstctrl; /* 4a008d00 */
+ u32 pad067[1]; /* 4a008d04 */
+ u32 cm_l4cfg_dynamicdep; /* 4a008d08 */
+ u32 pad068[5]; /* 4a008d0c */
+ u32 cm_l4cfg_l4_cfg_clkctrl; /* 4a008d20 */
+ u32 pad069[1]; /* 4a008d24 */
+ u32 cm_l4cfg_hw_sem_clkctrl; /* 4a008d28 */
+ u32 pad070[1]; /* 4a008d2c */
+ u32 cm_l4cfg_mailbox_clkctrl; /* 4a008d30 */
+ u32 pad071[1]; /* 4a008d34 */
+ u32 cm_l4cfg_sar_rom_clkctrl; /* 4a008d38 */
+ u32 pad072[49]; /* 4a008d3c */
+ u32 cm_l3instr_clkstctrl; /* 4a008e00 */
+ u32 pad073[7]; /* 4a008e04 */
+ u32 cm_l3instr_l3_3_clkctrl; /* 4a008e20 */
+ u32 pad074[1]; /* 4a008e24 */
+ u32 cm_l3instr_l3_instr_clkctrl; /* 4a008e28 */
+ u32 pad075[5]; /* 4a008e2c */
+ u32 cm_l3instr_intrconn_wp1_clkctrl; /* 4a008e40 */
+
+
+ /* cm2.ivahd */
+ u32 pad076[47]; /* 4a008e44 */
+ u32 cm_ivahd_clkstctrl; /* 4a008f00 */
+ u32 pad077[7]; /* 4a008f04 */
+ u32 cm_ivahd_ivahd_clkctrl; /* 4a008f20 */
+ u32 pad078[1]; /* 4a008f24 */
+ u32 cm_ivahd_sl2_clkctrl; /* 4a008f28 */
+
+ /* cm2.cam */
+ u32 pad079[53]; /* 4a008f2c */
+ u32 cm_cam_clkstctrl; /* 4a009000 */
+ u32 pad080[7]; /* 4a009004 */
+ u32 cm_cam_iss_clkctrl; /* 4a009020 */
+ u32 pad081[1]; /* 4a009024 */
+ u32 cm_cam_fdif_clkctrl; /* 4a009028 */
+
+ /* cm2.dss */
+ u32 pad082[53]; /* 4a00902c */
+ u32 cm_dss_clkstctrl; /* 4a009100 */
+ u32 pad083[7]; /* 4a009104 */
+ u32 cm_dss_dss_clkctrl; /* 4a009120 */
+
+ /* cm2.sgx */
+ u32 pad084[55]; /* 4a009124 */
+ u32 cm_sgx_clkstctrl; /* 4a009200 */
+ u32 pad085[7]; /* 4a009204 */
+ u32 cm_sgx_sgx_clkctrl; /* 4a009220 */
+
+ /* cm2.l3init */
+ u32 pad086[55]; /* 4a009224 */
+ u32 cm_l3init_clkstctrl; /* 4a009300 */
+
+ /* cm2.l3init */
+ u32 pad087[9]; /* 4a009304 */
+ u32 cm_l3init_hsmmc1_clkctrl; /* 4a009328 */
+ u32 pad088[1]; /* 4a00932c */
+ u32 cm_l3init_hsmmc2_clkctrl; /* 4a009330 */
+ u32 pad089[1]; /* 4a009334 */
+ u32 cm_l3init_hsi_clkctrl; /* 4a009338 */
+ u32 pad090[7]; /* 4a00933c */
+ u32 cm_l3init_hsusbhost_clkctrl; /* 4a009358 */
+ u32 pad091[1]; /* 4a00935c */
+ u32 cm_l3init_hsusbotg_clkctrl; /* 4a009360 */
+ u32 pad092[1]; /* 4a009364 */
+ u32 cm_l3init_hsusbtll_clkctrl; /* 4a009368 */
+ u32 pad093[3]; /* 4a00936c */
+ u32 cm_l3init_p1500_clkctrl; /* 4a009378 */
+ u32 pad094[21]; /* 4a00937c */
+ u32 cm_l3init_fsusb_clkctrl; /* 4a0093d0 */
+ u32 pad095[3]; /* 4a0093d4 */
+ u32 cm_l3init_ocp2scp1_clkctrl;
+
+ /* cm2.l4per */
+ u32 pad096[7]; /* 4a0093e4 */
+ u32 cm_l4per_clkstctrl; /* 4a009400 */
+ u32 pad097[1]; /* 4a009404 */
+ u32 cm_l4per_dynamicdep; /* 4a009408 */
+ u32 pad098[5]; /* 4a00940c */
+ u32 cm_l4per_adc_clkctrl; /* 4a009420 */
+ u32 pad100[1]; /* 4a009424 */
+ u32 cm_l4per_gptimer10_clkctrl; /* 4a009428 */
+ u32 pad101[1]; /* 4a00942c */
+ u32 cm_l4per_gptimer11_clkctrl; /* 4a009430 */
+ u32 pad102[1]; /* 4a009434 */
+ u32 cm_l4per_gptimer2_clkctrl; /* 4a009438 */
+ u32 pad103[1]; /* 4a00943c */
+ u32 cm_l4per_gptimer3_clkctrl; /* 4a009440 */
+ u32 pad104[1]; /* 4a009444 */
+ u32 cm_l4per_gptimer4_clkctrl; /* 4a009448 */
+ u32 pad105[1]; /* 4a00944c */
+ u32 cm_l4per_gptimer9_clkctrl; /* 4a009450 */
+ u32 pad106[1]; /* 4a009454 */
+ u32 cm_l4per_elm_clkctrl; /* 4a009458 */
+ u32 pad107[1]; /* 4a00945c */
+ u32 cm_l4per_gpio2_clkctrl; /* 4a009460 */
+ u32 pad108[1]; /* 4a009464 */
+ u32 cm_l4per_gpio3_clkctrl; /* 4a009468 */
+ u32 pad109[1]; /* 4a00946c */
+ u32 cm_l4per_gpio4_clkctrl; /* 4a009470 */
+ u32 pad110[1]; /* 4a009474 */
+ u32 cm_l4per_gpio5_clkctrl; /* 4a009478 */
+ u32 pad111[1]; /* 4a00947c */
+ u32 cm_l4per_gpio6_clkctrl; /* 4a009480 */
+ u32 pad112[1]; /* 4a009484 */
+ u32 cm_l4per_hdq1w_clkctrl; /* 4a009488 */
+ u32 pad113[1]; /* 4a00948c */
+ u32 cm_l4per_hecc1_clkctrl; /* 4a009490 */
+ u32 pad114[1]; /* 4a009494 */
+ u32 cm_l4per_hecc2_clkctrl; /* 4a009498 */
+ u32 pad115[1]; /* 4a00949c */
+ u32 cm_l4per_i2c1_clkctrl; /* 4a0094a0 */
+ u32 pad116[1]; /* 4a0094a4 */
+ u32 cm_l4per_i2c2_clkctrl; /* 4a0094a8 */
+ u32 pad117[1]; /* 4a0094ac */
+ u32 cm_l4per_i2c3_clkctrl; /* 4a0094b0 */
+ u32 pad118[1]; /* 4a0094b4 */
+ u32 cm_l4per_i2c4_clkctrl; /* 4a0094b8 */
+ u32 pad119[1]; /* 4a0094bc */
+ u32 cm_l4per_l4per_clkctrl; /* 4a0094c0 */
+ u32 pad1191[3]; /* 4a0094c4 */
+ u32 cm_l4per_mcasp2_clkctrl; /* 4a0094d0 */
+ u32 pad120[1]; /* 4a0094d4 */
+ u32 cm_l4per_mcasp3_clkctrl; /* 4a0094d8 */
+ u32 pad121[3]; /* 4a0094dc */
+ u32 cm_l4per_mgate_clkctrl; /* 4a0094e8 */
+ u32 pad123[1]; /* 4a0094ec */
+ u32 cm_l4per_mcspi1_clkctrl; /* 4a0094f0 */
+ u32 pad124[1]; /* 4a0094f4 */
+ u32 cm_l4per_mcspi2_clkctrl; /* 4a0094f8 */
+ u32 pad125[1]; /* 4a0094fc */
+ u32 cm_l4per_mcspi3_clkctrl; /* 4a009500 */
+ u32 pad126[1]; /* 4a009504 */
+ u32 cm_l4per_mcspi4_clkctrl; /* 4a009508 */
+ u32 pad127[1]; /* 4a00950c */
+ u32 cm_l4per_gpio7_clkctrl; /* 4a009510 */
+ u32 pad1271[1]; /* 4a009514 */
+ u32 cm_l4per_gpio8_clkctrl; /* 4a009518 */
+ u32 pad1272[1]; /* 4a00951c */
+ u32 cm_l4per_mmcsd3_clkctrl; /* 4a009520 */
+ u32 pad128[1]; /* 4a009524 */
+ u32 cm_l4per_mmcsd4_clkctrl; /* 4a009528 */
+ u32 pad129[1]; /* 4a00952c */
+ u32 cm_l4per_msprohg_clkctrl; /* 4a009530 */
+ u32 pad130[1]; /* 4a009534 */
+ u32 cm_l4per_slimbus2_clkctrl; /* 4a009538 */
+ u32 pad131[1]; /* 4a00953c */
+ u32 cm_l4per_uart1_clkctrl; /* 4a009540 */
+ u32 pad132[1]; /* 4a009544 */
+ u32 cm_l4per_uart2_clkctrl; /* 4a009548 */
+ u32 pad133[1]; /* 4a00954c */
+ u32 cm_l4per_uart3_clkctrl; /* 4a009550 */
+ u32 pad134[1]; /* 4a009554 */
+ u32 cm_l4per_uart4_clkctrl; /* 4a009558 */
+ u32 pad135[1]; /* 4a00955c */
+ u32 cm_l4per_mmcsd5_clkctrl; /* 4a009560 */
+ u32 pad136[1]; /* 4a009564 */
+ u32 cm_l4per_i2c5_clkctrl; /* 4a009568 */
+ u32 pad1371[1]; /* 4a00956c */
+ u32 cm_l4per_uart5_clkctrl; /* 4a009570 */
+ u32 pad1372[1]; /* 4a009574 */
+ u32 cm_l4per_uart6_clkctrl; /* 4a009578 */
+ u32 pad1374[1]; /* 4a00957c */
+ u32 cm_l4sec_clkstctrl; /* 4a009580 */
+ u32 cm_l4sec_staticdep; /* 4a009584 */
+ u32 cm_l4sec_dynamicdep; /* 4a009588 */
+ u32 pad138[5]; /* 4a00958c */
+ u32 cm_l4sec_aes1_clkctrl; /* 4a0095a0 */
+ u32 pad139[1]; /* 4a0095a4 */
+ u32 cm_l4sec_aes2_clkctrl; /* 4a0095a8 */
+ u32 pad140[1]; /* 4a0095ac */
+ u32 cm_l4sec_des3des_clkctrl; /* 4a0095b0 */
+ u32 pad141[1]; /* 4a0095b4 */
+ u32 cm_l4sec_pkaeip29_clkctrl; /* 4a0095b8 */
+ u32 pad142[1]; /* 4a0095bc */
+ u32 cm_l4sec_rng_clkctrl; /* 4a0095c0 */
+ u32 pad143[1]; /* 4a0095c4 */
+ u32 cm_l4sec_sha2md51_clkctrl; /* 4a0095c8 */
+ u32 pad144[3]; /* 4a0095cc */
+ u32 cm_l4sec_cryptodma_clkctrl; /* 4a0095d8 */
+ u32 pad145[3660425]; /* 4a0095dc */
+
+ /* l4 wkup regs */
+ u32 pad201[6211]; /* 4ae00000 */
+ u32 cm_abe_pll_ref_clksel; /* 4ae0610c */
+ u32 cm_sys_clksel; /* 4ae06110 */
+ u32 pad202[1467]; /* 4ae06114 */
+ u32 cm_wkup_clkstctrl; /* 4ae07800 */
+ u32 pad203[7]; /* 4ae07804 */
+ u32 cm_wkup_l4wkup_clkctrl; /* 4ae07820 */
+ u32 pad204; /* 4ae07824 */
+ u32 cm_wkup_wdtimer1_clkctrl; /* 4ae07828 */
+ u32 pad205; /* 4ae0782c */
+ u32 cm_wkup_wdtimer2_clkctrl; /* 4ae07830 */
+ u32 pad206; /* 4ae07834 */
+ u32 cm_wkup_gpio1_clkctrl; /* 4ae07838 */
+ u32 pad207; /* 4ae0783c */
+ u32 cm_wkup_gptimer1_clkctrl; /* 4ae07840 */
+ u32 pad208; /* 4ae07844 */
+ u32 cm_wkup_gptimer12_clkctrl; /* 4ae07848 */
+ u32 pad209; /* 4ae0784c */
+ u32 cm_wkup_synctimer_clkctrl; /* 4ae07850 */
+ u32 pad210; /* 4ae07854 */
+ u32 cm_wkup_usim_clkctrl; /* 4ae07858 */
+ u32 pad211; /* 4ae0785c */
+ u32 cm_wkup_sarram_clkctrl; /* 4ae07860 */
+ u32 pad212[5]; /* 4ae07864 */
+ u32 cm_wkup_keyboard_clkctrl; /* 4ae07878 */
+ u32 pad213; /* 4ae0787c */
+ u32 cm_wkup_rtc_clkctrl; /* 4ae07880 */
+ u32 pad214; /* 4ae07884 */
+ u32 cm_wkup_bandgap_clkctrl; /* 4ae07888 */
+ u32 pad215[197]; /* 4ae0788c */
+ u32 prm_vc_val_bypass; /* 4ae07ba0 */
+ u32 pad216[4];
+ u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */
+ u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */
+};
+
+/* DPLL register offsets */
+#define CM_CLKMODE_DPLL 0
+#define CM_IDLEST_DPLL 0x4
+#define CM_AUTOIDLE_DPLL 0x8
+#define CM_CLKSEL_DPLL 0xC
+
+#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
+
+/* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
+#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
+#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
+#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
+#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
+#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
+#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
+#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
+#define CM_CLKMODE_DPLL_EN_SHIFT 0
+#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
+
+#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
+#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
+
+#define DPLL_EN_STOP 1
+#define DPLL_EN_MN_BYPASS 4
+#define DPLL_EN_LOW_POWER_BYPASS 5
+#define DPLL_EN_FAST_RELOCK_BYPASS 6
+#define DPLL_EN_LOCK 7
+
+/* CM_IDLEST_DPLL fields */
+#define ST_DPLL_CLK_MASK 1
+
+/* CM_CLKSEL_DPLL */
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
+#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
+#define CM_CLKSEL_DPLL_M_SHIFT 8
+#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
+#define CM_CLKSEL_DPLL_N_SHIFT 0
+#define CM_CLKSEL_DPLL_N_MASK 0x7F
+#define CM_CLKSEL_DCC_EN_SHIFT 22
+#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
+
+#define OMAP4_DPLL_MAX_N 127
+
+/* CM_SYS_CLKSEL */
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
+
+/* CM_CLKSEL_CORE */
+#define CLKSEL_CORE_SHIFT 0
+#define CLKSEL_L3_SHIFT 4
+#define CLKSEL_L4_SHIFT 8
+
+#define CLKSEL_CORE_X2_DIV_1 0
+#define CLKSEL_L3_CORE_DIV_2 1
+#define CLKSEL_L4_L3_DIV_2 1
+
+/* CM_ABE_PLL_REF_CLKSEL */
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
+#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
+
+/* CM_BYPCLK_DPLL_IVA */
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
+#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
+
+#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
+
+/* CM_SHADOW_FREQ_CONFIG1 */
+#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
+#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
+#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
+
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
+#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
+
+#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
+#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
+
+/*CM_<clock_domain>__CLKCTRL */
+#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
+#define CD_CLKCTRL_CLKTRCTRL_MASK 3
+
+#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
+#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
+#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
+#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
+
+
+/* CM_<clock_domain>_<module>_CLKCTRL */
+#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
+#define MODULE_CLKCTRL_MODULEMODE_MASK 3
+#define MODULE_CLKCTRL_IDLEST_SHIFT 16
+#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
+
+#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
+#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
+#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
+
+#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
+#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
+#define MODULE_CLKCTRL_IDLEST_IDLE 2
+#define MODULE_CLKCTRL_IDLEST_DISABLED 3
+
+/* CM_L4PER_GPIO4_CLKCTRL */
+#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
+
+/* CM_L3INIT_HSMMCn_CLKCTRL */
+#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
+
+/* CM_WKUP_GPTIMER1_CLKCTRL */
+#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
+
+/* CM_CAM_ISS_CLKCTRL */
+#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
+
+/* CM_DSS_DSS_CLKCTRL */
+#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
+
+/* CM_L3INIT_USBPHY_CLKCTRL */
+#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
+
+/* CM_MPU_MPU_CLKCTRL */
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
+
+/* Clock frequencies */
+#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
+#define OMAP_SYS_CLK_IND_38_4_MHZ 6
+#define OMAP_32K_CLK_FREQ 32768
+
+/* PRM_VC_CFG_I2C_CLK */
+#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0
+#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF
+#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8
+#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8)
+
+/* PRM_VC_VAL_BYPASS */
+#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
+
+#define PRM_VC_VAL_BYPASS_VALID_BIT 0x1000000
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0
+#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F
+#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8
+#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF
+#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16
+#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF
+
+/* SMPS */
+#define SMPS_I2C_SLAVE_ADDR 0x12
+#define SMPS_REG_ADDR_VCORE1 0x55
+#define SMPS_REG_ADDR_VCORE2 0x5B
+#define SMPS_REG_ADDR_VCORE3 0x61
+
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
+#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
+
+/* TPS */
+#define TPS62361_I2C_SLAVE_ADDR 0x60
+#define TPS62361_REG_ADDR_SET0 0x0
+#define TPS62361_REG_ADDR_SET1 0x1
+#define TPS62361_REG_ADDR_SET2 0x2
+#define TPS62361_REG_ADDR_SET3 0x3
+#define TPS62361_REG_ADDR_CTRL 0x4
+#define TPS62361_REG_ADDR_TEMP 0x5
+#define TPS62361_REG_ADDR_RMP_CTRL 0x6
+#define TPS62361_REG_ADDR_CHIP_ID 0x8
+#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
+
+#define TPS62361_BASE_VOLT_MV 500
+#define TPS62361_VSEL0_GPIO 7
+
+/* Defines for DPLL setup */
+#define DPLL_LOCKED_FREQ_TOLERANCE_0 0
+#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
+#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000
+
+#define DPLL_NO_LOCK 0
+#define DPLL_LOCK 1
+
+#define NUM_SYS_CLKS 7
+
+struct dpll_regs {
+ u32 cm_clkmode_dpll;
+ u32 cm_idlest_dpll;
+ u32 cm_autoidle_dpll;
+ u32 cm_clksel_dpll;
+ u32 cm_div_m2_dpll;
+ u32 cm_div_m3_dpll;
+ u32 cm_div_h11_dpll;
+ u32 cm_div_h12_dpll;
+ u32 cm_div_h13_dpll;
+ u32 cm_div_h14_dpll;
+ u32 reserved[2];
+ u32 cm_div_h22_dpll;
+ u32 cm_div_h23_dpll;
+};
+
+/* DPLL parameter table */
+struct dpll_params {
+ u32 m;
+ u32 n;
+ u8 m2;
+ u8 m3;
+ u8 h11;
+ u8 h12;
+ u8 h13;
+ u8 h14;
+ u8 h22;
+ u8 h23;
+};
+
+extern struct omap5_prcm_regs *const prcm;
+extern const u32 sys_clk_array[8];
+
+void scale_vcores(void);
+void do_scale_tps62361(u32 reg, u32 volt_mv);
+u32 omap_ddr_clk(void);
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
+void setup_sri2c(void);
+void setup_post_dividers(u32 *const base, const struct dpll_params *params);
+u32 get_sys_clk_index(void);
+void enable_basic_clocks(void);
+void enable_non_essential_clocks(void);
+void enable_basic_uboot_clocks(void);
+void do_enable_clocks(u32 *const *clk_domains,
+ u32 *const *clk_modules_hw_auto,
+ u32 *const *clk_modules_explicit_en,
+ u8 wait_for_enable);
+const struct dpll_params *get_mpu_dpll_params(void);
+const struct dpll_params *get_core_dpll_params(void);
+const struct dpll_params *get_per_dpll_params(void);
+const struct dpll_params *get_iva_dpll_params(void);
+const struct dpll_params *get_usb_dpll_params(void);
+const struct dpll_params *get_abe_dpll_params(void);
+#endif /* _CLOCKS_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
new file mode 100644
index 000000000..0697a732d
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -0,0 +1,175 @@
+/*
+ * (C) Copyright 2006-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct gpmc_cs {
+ u32 config1; /* 0x00 */
+ u32 config2; /* 0x04 */
+ u32 config3; /* 0x08 */
+ u32 config4; /* 0x0C */
+ u32 config5; /* 0x10 */
+ u32 config6; /* 0x14 */
+ u32 config7; /* 0x18 */
+ u32 nand_cmd; /* 0x1C */
+ u32 nand_adr; /* 0x20 */
+ u32 nand_dat; /* 0x24 */
+ u8 res[8]; /* blow up to 0x30 byte */
+};
+
+struct gpmc {
+ u8 res1[0x10];
+ u32 sysconfig; /* 0x10 */
+ u8 res2[0x4];
+ u32 irqstatus; /* 0x18 */
+ u32 irqenable; /* 0x1C */
+ u8 res3[0x20];
+ u32 timeout_control; /* 0x40 */
+ u8 res4[0xC];
+ u32 config; /* 0x50 */
+ u32 status; /* 0x54 */
+ u8 res5[0x8]; /* 0x58 */
+ struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
+ u8 res6[0x14]; /* 0x1E0 */
+ u32 ecc_config; /* 0x1F4 */
+ u32 ecc_control; /* 0x1F8 */
+ u32 ecc_size_config; /* 0x1FC */
+ u32 ecc1_result; /* 0x200 */
+ u32 ecc2_result; /* 0x204 */
+ u32 ecc3_result; /* 0x208 */
+ u32 ecc4_result; /* 0x20C */
+ u32 ecc5_result; /* 0x210 */
+ u32 ecc6_result; /* 0x214 */
+ u32 ecc7_result; /* 0x218 */
+ u32 ecc8_result; /* 0x21C */
+ u32 ecc9_result; /* 0x220 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
+struct gptimer {
+ u32 tidr; /* 0x00 r */
+ u8 res1[0xc];
+ u32 tiocp_cfg; /* 0x10 rw */
+ u8 res2[0x10];
+ u32 tisr_raw; /* 0x24 r */
+ u32 tisr; /* 0x28 rw */
+ u32 tier; /* 0x2c rw */
+ u32 ticr; /* 0x30 rw */
+ u32 twer; /* 0x34 rw */
+ u32 tclr; /* 0x38 rw */
+ u32 tcrr; /* 0x3c rw */
+ u32 tldr; /* 0x40 rw */
+ u32 ttgr; /* 0x44 rw */
+ u32 twpc; /* 0x48 r */
+ u32 tmar; /* 0x4c rw */
+ u32 tcar1; /* 0x50 r */
+ u32 tcicr; /* 0x54 rw */
+ u32 tcar2; /* 0x58 r */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+/* enable sys_clk NO-prescale /1 */
+#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+
+/* Watchdog */
+#ifndef __KERNEL_STRICT_NAMES
+#ifndef __ASSEMBLY__
+struct watchdog {
+ u8 res1[0x34];
+ u32 wwps; /* 0x34 r */
+ u8 res2[0x10];
+ u32 wspr; /* 0x48 rw */
+};
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
+
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+#define SYSCLKDIV_1 (0x1 << 6)
+#define SYSCLKDIV_2 (0x1 << 7)
+
+#define CLKSEL_GPT1 (0x1 << 0)
+
+#define EN_GPT1 (0x1 << 0)
+#define EN_32KSYNC (0x1 << 2)
+
+#define ST_WDT2 (0x1 << 5)
+
+#define RESETDONE (0x1 << 0)
+
+#define TCLR_ST (0x1 << 0)
+#define TCLR_AR (0x1 << 1)
+#define TCLR_PRE (0x1 << 5)
+
+/* GPMC BASE */
+#define GPMC_BASE (OMAP54XX_GPMC_BASE)
+
+/* I2C base */
+#define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000)
+#define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000)
+#define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000)
+
+/* MUSB base */
+#define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000)
+
+/* OMAP4 GPIO registers */
+#define OMAP_GPIO_REVISION 0x0000
+#define OMAP_GPIO_SYSCONFIG 0x0010
+#define OMAP_GPIO_SYSSTATUS 0x0114
+#define OMAP_GPIO_IRQSTATUS1 0x0118
+#define OMAP_GPIO_IRQSTATUS2 0x0128
+#define OMAP_GPIO_IRQENABLE2 0x012c
+#define OMAP_GPIO_IRQENABLE1 0x011c
+#define OMAP_GPIO_WAKE_EN 0x0120
+#define OMAP_GPIO_CTRL 0x0130
+#define OMAP_GPIO_OE 0x0134
+#define OMAP_GPIO_DATAIN 0x0138
+#define OMAP_GPIO_DATAOUT 0x013c
+#define OMAP_GPIO_LEVELDETECT0 0x0140
+#define OMAP_GPIO_LEVELDETECT1 0x0144
+#define OMAP_GPIO_RISINGDETECT 0x0148
+#define OMAP_GPIO_FALLINGDETECT 0x014c
+#define OMAP_GPIO_DEBOUNCE_EN 0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL 0x0154
+#define OMAP_GPIO_CLEARIRQENABLE1 0x0160
+#define OMAP_GPIO_SETIRQENABLE1 0x0164
+#define OMAP_GPIO_CLEARWKUENA 0x0180
+#define OMAP_GPIO_SETWKUENA 0x0184
+#define OMAP_GPIO_CLEARDATAOUT 0x0190
+#define OMAP_GPIO_SETDATAOUT 0x0194
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap5/gpio.h b/arch/arm/include/asm/arch-omap5/gpio.h
new file mode 100644
index 000000000..c14dff0f3
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/gpio.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ * linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _GPIO_OMAP5_H
+#define _GPIO_OMAP5_H
+
+#include <asm/omap_gpio.h>
+
+#define OMAP54XX_GPIO1_BASE 0x4Ae10000
+#define OMAP54XX_GPIO2_BASE 0x48055000
+#define OMAP54XX_GPIO3_BASE 0x48057000
+#define OMAP54XX_GPIO4_BASE 0x48059000
+#define OMAP54XX_GPIO5_BASE 0x4805B000
+#define OMAP54XX_GPIO6_BASE 0x4805D000
+
+#endif /* _GPIO_OMAP5_H */
diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h
new file mode 100644
index 000000000..68be03be5
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/i2c.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2004-2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _OMAP5_I2C_H_
+#define _OMAP5_I2C_H_
+
+#define I2C_BUS_MAX 3
+#define I2C_DEFAULT_BASE I2C_BASE1
+
+struct i2c {
+ unsigned short revnb_lo; /* 0x00 */
+ unsigned short res1;
+ unsigned short revnb_hi; /* 0x04 */
+ unsigned short res2[13];
+ unsigned short sysc; /* 0x20 */
+ unsigned short res3;
+ unsigned short irqstatus_raw; /* 0x24 */
+ unsigned short res4;
+ unsigned short stat; /* 0x28 */
+ unsigned short res5;
+ unsigned short ie; /* 0x2C */
+ unsigned short res6;
+ unsigned short irqenable_clr; /* 0x30 */
+ unsigned short res7;
+ unsigned short iv; /* 0x34 */
+ unsigned short res8[45];
+ unsigned short syss; /* 0x90 */
+ unsigned short res9;
+ unsigned short buf; /* 0x94 */
+ unsigned short res10;
+ unsigned short cnt; /* 0x98 */
+ unsigned short res11;
+ unsigned short data; /* 0x9C */
+ unsigned short res13;
+ unsigned short res14; /* 0xA0 */
+ unsigned short res15;
+ unsigned short con; /* 0xA4 */
+ unsigned short res16;
+ unsigned short oa; /* 0xA8 */
+ unsigned short res17;
+ unsigned short sa; /* 0xAC */
+ unsigned short res18;
+ unsigned short psc; /* 0xB0 */
+ unsigned short res19;
+ unsigned short scll; /* 0xB4 */
+ unsigned short res20;
+ unsigned short sclh; /* 0xB8 */
+ unsigned short res21;
+ unsigned short systest; /* 0xBC */
+ unsigned short res22;
+ unsigned short bufstat; /* 0xC0 */
+ unsigned short res23;
+};
+
+#endif /* _OMAP5_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
new file mode 100644
index 000000000..74439c9d9
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/*
+ * OMAP HSMMC register definitions
+ */
+
+#define OMAP_HSMMC1_BASE 0x4809C100
+#define OMAP_HSMMC2_BASE 0x480B4100
+#define OMAP_HSMMC3_BASE 0x480AD100
+
+struct hsmmc {
+ unsigned char res1[0x10];
+ unsigned int sysconfig; /* 0x10 */
+ unsigned int sysstatus; /* 0x14 */
+ unsigned char res2[0x14];
+ unsigned int con; /* 0x2C */
+ unsigned char res3[0xD4];
+ unsigned int blk; /* 0x104 */
+ unsigned int arg; /* 0x108 */
+ unsigned int cmd; /* 0x10C */
+ unsigned int rsp10; /* 0x110 */
+ unsigned int rsp32; /* 0x114 */
+ unsigned int rsp54; /* 0x118 */
+ unsigned int rsp76; /* 0x11C */
+ unsigned int data; /* 0x120 */
+ unsigned int pstate; /* 0x124 */
+ unsigned int hctl; /* 0x128 */
+ unsigned int sysctl; /* 0x12C */
+ unsigned int stat; /* 0x130 */
+ unsigned int ie; /* 0x134 */
+ unsigned char res4[0x8];
+ unsigned int capa; /* 0x140 */
+};
+
+/*
+ * OMAP HS MMC Bit definitions
+ */
+#define MMC_SOFTRESET (0x1 << 1)
+#define RESETDONE (0x1 << 0)
+#define NOOPENDRAIN (0x0 << 0)
+#define OPENDRAIN (0x1 << 0)
+#define OD (0x1 << 0)
+#define INIT_NOINIT (0x0 << 1)
+#define INIT_INITSTREAM (0x1 << 1)
+#define HR_NOHOSTRESP (0x0 << 2)
+#define STR_BLOCK (0x0 << 3)
+#define MODE_FUNC (0x0 << 4)
+#define DW8_1_4BITMODE (0x0 << 5)
+#define MIT_CTO (0x0 << 6)
+#define CDP_ACTIVEHIGH (0x0 << 7)
+#define WPP_ACTIVEHIGH (0x0 << 8)
+#define RESERVED_MASK (0x3 << 9)
+#define CTPL_MMC_SD (0x0 << 11)
+#define BLEN_512BYTESLEN (0x200 << 0)
+#define NBLK_STPCNT (0x0 << 16)
+#define DE_DISABLE (0x0 << 0)
+#define BCE_DISABLE (0x0 << 1)
+#define BCE_ENABLE (0x1 << 1)
+#define ACEN_DISABLE (0x0 << 2)
+#define DDIR_OFFSET (4)
+#define DDIR_MASK (0x1 << 4)
+#define DDIR_WRITE (0x0 << 4)
+#define DDIR_READ (0x1 << 4)
+#define MSBS_SGLEBLK (0x0 << 5)
+#define MSBS_MULTIBLK (0x1 << 5)
+#define RSP_TYPE_OFFSET (16)
+#define RSP_TYPE_MASK (0x3 << 16)
+#define RSP_TYPE_NORSP (0x0 << 16)
+#define RSP_TYPE_LGHT136 (0x1 << 16)
+#define RSP_TYPE_LGHT48 (0x2 << 16)
+#define RSP_TYPE_LGHT48B (0x3 << 16)
+#define CCCE_NOCHECK (0x0 << 19)
+#define CCCE_CHECK (0x1 << 19)
+#define CICE_NOCHECK (0x0 << 20)
+#define CICE_CHECK (0x1 << 20)
+#define DP_OFFSET (21)
+#define DP_MASK (0x1 << 21)
+#define DP_NO_DATA (0x0 << 21)
+#define DP_DATA (0x1 << 21)
+#define CMD_TYPE_NORMAL (0x0 << 22)
+#define INDEX_OFFSET (24)
+#define INDEX_MASK (0x3f << 24)
+#define INDEX(i) (i << 24)
+#define DATI_MASK (0x1 << 1)
+#define DATI_CMDDIS (0x1 << 1)
+#define DTW_1_BITMODE (0x0 << 1)
+#define DTW_4_BITMODE (0x1 << 1)
+#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
+#define SDBP_PWROFF (0x0 << 8)
+#define SDBP_PWRON (0x1 << 8)
+#define SDVS_1V8 (0x5 << 9)
+#define SDVS_3V0 (0x6 << 9)
+#define ICE_MASK (0x1 << 0)
+#define ICE_STOP (0x0 << 0)
+#define ICS_MASK (0x1 << 1)
+#define ICS_NOTREADY (0x0 << 1)
+#define ICE_OSCILLATE (0x1 << 0)
+#define CEN_MASK (0x1 << 2)
+#define CEN_DISABLE (0x0 << 2)
+#define CEN_ENABLE (0x1 << 2)
+#define CLKD_OFFSET (6)
+#define CLKD_MASK (0x3FF << 6)
+#define DTO_MASK (0xF << 16)
+#define DTO_15THDTO (0xE << 16)
+#define SOFTRESETALL (0x1 << 24)
+#define CC_MASK (0x1 << 0)
+#define TC_MASK (0x1 << 1)
+#define BWR_MASK (0x1 << 4)
+#define BRR_MASK (0x1 << 5)
+#define ERRI_MASK (0x1 << 15)
+#define IE_CC (0x01 << 0)
+#define IE_TC (0x01 << 1)
+#define IE_BWR (0x01 << 4)
+#define IE_BRR (0x01 << 5)
+#define IE_CTO (0x01 << 16)
+#define IE_CCRC (0x01 << 17)
+#define IE_CEB (0x01 << 18)
+#define IE_CIE (0x01 << 19)
+#define IE_DTO (0x01 << 20)
+#define IE_DCRC (0x01 << 21)
+#define IE_DEB (0x01 << 22)
+#define IE_CERR (0x01 << 28)
+#define IE_BADA (0x01 << 29)
+
+#define VS30_3V0SUP (1 << 25)
+#define VS18_1V8SUP (1 << 26)
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE 512
+#define MMC_CARD 0
+#define SD_CARD 1
+#define BYTE_MODE 0
+#define SECTOR_MODE 1
+#define CLK_INITSEQ 0
+#define CLK_400KHZ 1
+#define CLK_MISC 2
+
+#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
+#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+
+/* Clock Configurations and Macros */
+#define MMC_CLOCK_REFERENCE 96 /* MHz */
+
+#define mmc_reg_out(addr, mask, val)\
+ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+
+int omap_mmc_init(int dev_index);
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h
new file mode 100644
index 000000000..b8c21853f
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/mux_omap5.h
@@ -0,0 +1,344 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments Incorporated
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Aneesh V <aneesh@ti.com>
+ * Balaji Krishnamoorthy <balajitk@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MUX_OMAP5_H_
+#define _MUX_OMAP5_H_
+
+#include <asm/types.h>
+
+struct pad_conf_entry {
+
+ u16 offset;
+
+ u16 val;
+
+} __attribute__ ((__packed__));
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_PD (1 << 12)
+#define OFF_PU (3 << 12)
+#define OFF_OUT_PTD (0 << 10)
+#define OFF_OUT_PTU (2 << 10)
+#define OFF_IN (1 << 10)
+#define OFF_OUT (0 << 10)
+#define OFF_EN (1 << 9)
+#else
+#define OFF_PD (0 << 12)
+#define OFF_PU (0 << 12)
+#define OFF_OUT_PTD (0 << 10)
+#define OFF_OUT_PTU (0 << 10)
+#define OFF_IN (0 << 10)
+#define OFF_OUT (0 << 10)
+#define OFF_EN (0 << 9)
+#endif
+
+#define IEN (1 << 8)
+#define IDIS (0 << 8)
+#define PTU (3 << 3)
+#define PTD (1 << 3)
+#define EN (1 << 3)
+#define DIS (0 << 3)
+
+#define M0 0
+#define M1 1
+#define M2 2
+#define M3 3
+#define M4 4
+#define M5 5
+#define M6 6
+#define M7 7
+
+#define SAFE_MODE M7
+
+#ifdef CONFIG_OFF_PADCONF
+#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN)
+#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN)
+#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN)
+#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN)
+#else
+#define OFF_IN_PD 0
+#define OFF_IN_PU 0
+#define OFF_OUT_PD 0
+#define OFF_OUT_PU 0
+#endif
+
+#define CORE_REVISION 0x0000
+#define CORE_HWINFO 0x0004
+#define CORE_SYSCONFIG 0x0010
+#define GPMC_AD0 0x0040
+#define GPMC_AD1 0x0042
+#define GPMC_AD2 0x0044
+#define GPMC_AD3 0x0046
+#define GPMC_AD4 0x0048
+#define GPMC_AD5 0x004A
+#define GPMC_AD6 0x004C
+#define GPMC_AD7 0x004E
+#define GPMC_AD8 0x0050
+#define GPMC_AD9 0x0052
+#define GPMC_AD10 0x0054
+#define GPMC_AD11 0x0056
+#define GPMC_AD12 0x0058
+#define GPMC_AD13 0x005A
+#define GPMC_AD14 0x005C
+#define GPMC_AD15 0x005E
+#define GPMC_A16 0x0060
+#define GPMC_A17 0x0062
+#define GPMC_A18 0x0064
+#define GPMC_A19 0x0066
+#define GPMC_A20 0x0068
+#define GPMC_A21 0x006A
+#define GPMC_A22 0x006C
+#define GPMC_A23 0x006E
+#define GPMC_A24 0x0070
+#define GPMC_A25 0x0072
+#define GPMC_NCS0 0x0074
+#define GPMC_NCS1 0x0076
+#define GPMC_NCS2 0x0078
+#define GPMC_NCS3 0x007A
+#define GPMC_NWP 0x007C
+#define GPMC_CLK 0x007E
+#define GPMC_NADV_ALE 0x0080
+#define GPMC_NOE 0x0082
+#define GPMC_NWE 0x0084
+#define GPMC_NBE0_CLE 0x0086
+#define GPMC_NBE1 0x0088
+#define GPMC_WAIT0 0x008A
+#define GPMC_WAIT1 0x008C
+#define C2C_DATA11 0x008E
+#define C2C_DATA12 0x0090
+#define C2C_DATA13 0x0092
+#define C2C_DATA14 0x0094
+#define C2C_DATA15 0x0096
+#define HDMI_HPD 0x0098
+#define HDMI_CEC 0x009A
+#define HDMI_DDC_SCL 0x009C
+#define HDMI_DDC_SDA 0x009E
+#define CSI21_DX0 0x00A0
+#define CSI21_DY0 0x00A2
+#define CSI21_DX1 0x00A4
+#define CSI21_DY1 0x00A6
+#define CSI21_DX2 0x00A8
+#define CSI21_DY2 0x00AA
+#define CSI21_DX3 0x00AC
+#define CSI21_DY3 0x00AE
+#define CSI21_DX4 0x00B0
+#define CSI21_DY4 0x00B2
+#define CSI22_DX0 0x00B4
+#define CSI22_DY0 0x00B6
+#define CSI22_DX1 0x00B8
+#define CSI22_DY1 0x00BA
+#define CAM_SHUTTER 0x00BC
+#define CAM_STROBE 0x00BE
+#define CAM_GLOBALRESET 0x00C0
+#define USBB1_ULPITLL_CLK 0x00C2
+#define USBB1_ULPITLL_STP 0x00C4
+#define USBB1_ULPITLL_DIR 0x00C6
+#define USBB1_ULPITLL_NXT 0x00C8
+#define USBB1_ULPITLL_DAT0 0x00CA
+#define USBB1_ULPITLL_DAT1 0x00CC
+#define USBB1_ULPITLL_DAT2 0x00CE
+#define USBB1_ULPITLL_DAT3 0x00D0
+#define USBB1_ULPITLL_DAT4 0x00D2
+#define USBB1_ULPITLL_DAT5 0x00D4
+#define USBB1_ULPITLL_DAT6 0x00D6
+#define USBB1_ULPITLL_DAT7 0x00D8
+#define USBB1_HSIC_DATA 0x00DA
+#define USBB1_HSIC_STROBE 0x00DC
+#define USBC1_ICUSB_DP 0x00DE
+#define USBC1_ICUSB_DM 0x00E0
+#define SDMMC1_CLK 0x00E2
+#define SDMMC1_CMD 0x00E4
+#define SDMMC1_DAT0 0x00E6
+#define SDMMC1_DAT1 0x00E8
+#define SDMMC1_DAT2 0x00EA
+#define SDMMC1_DAT3 0x00EC
+#define SDMMC1_DAT4 0x00EE
+#define SDMMC1_DAT5 0x00F0
+#define SDMMC1_DAT6 0x00F2
+#define SDMMC1_DAT7 0x00F4
+#define ABE_MCBSP2_CLKX 0x00F6
+#define ABE_MCBSP2_DR 0x00F8
+#define ABE_MCBSP2_DX 0x00FA
+#define ABE_MCBSP2_FSX 0x00FC
+#define ABE_MCBSP1_CLKX 0x00FE
+#define ABE_MCBSP1_DR 0x0100
+#define ABE_MCBSP1_DX 0x0102
+#define ABE_MCBSP1_FSX 0x0104
+#define ABE_PDM_UL_DATA 0x0106
+#define ABE_PDM_DL_DATA 0x0108
+#define ABE_PDM_FRAME 0x010A
+#define ABE_PDM_LB_CLK 0x010C
+#define ABE_CLKS 0x010E
+#define ABE_DMIC_CLK1 0x0110
+#define ABE_DMIC_DIN1 0x0112
+#define ABE_DMIC_DIN2 0x0114
+#define ABE_DMIC_DIN3 0x0116
+#define UART2_CTS 0x0118
+#define UART2_RTS 0x011A
+#define UART2_RX 0x011C
+#define UART2_TX 0x011E
+#define HDQ_SIO 0x0120
+#define I2C1_SCL 0x0122
+#define I2C1_SDA 0x0124
+#define I2C2_SCL 0x0126
+#define I2C2_SDA 0x0128
+#define I2C3_SCL 0x012A
+#define I2C3_SDA 0x012C
+#define I2C4_SCL 0x012E
+#define I2C4_SDA 0x0130
+#define MCSPI1_CLK 0x0132
+#define MCSPI1_SOMI 0x0134
+#define MCSPI1_SIMO 0x0136
+#define MCSPI1_CS0 0x0138
+#define MCSPI1_CS1 0x013A
+#define MCSPI1_CS2 0x013C
+#define MCSPI1_CS3 0x013E
+#define UART3_CTS_RCTX 0x0140
+#define UART3_RTS_SD 0x0142
+#define UART3_RX_IRRX 0x0144
+#define UART3_TX_IRTX 0x0146
+#define SDMMC5_CLK 0x0148
+#define SDMMC5_CMD 0x014A
+#define SDMMC5_DAT0 0x014C
+#define SDMMC5_DAT1 0x014E
+#define SDMMC5_DAT2 0x0150
+#define SDMMC5_DAT3 0x0152
+#define MCSPI4_CLK 0x0154
+#define MCSPI4_SIMO 0x0156
+#define MCSPI4_SOMI 0x0158
+#define MCSPI4_CS0 0x015A
+#define UART4_RX 0x015C
+#define UART4_TX 0x015E
+#define USBB2_ULPITLL_CLK 0x0160
+#define USBB2_ULPITLL_STP 0x0162
+#define USBB2_ULPITLL_DIR 0x0164
+#define USBB2_ULPITLL_NXT 0x0166
+#define USBB2_ULPITLL_DAT0 0x0168
+#define USBB2_ULPITLL_DAT1 0x016A
+#define USBB2_ULPITLL_DAT2 0x016C
+#define USBB2_ULPITLL_DAT3 0x016E
+#define USBB2_ULPITLL_DAT4 0x0170
+#define USBB2_ULPITLL_DAT5 0x0172
+#define USBB2_ULPITLL_DAT6 0x0174
+#define USBB2_ULPITLL_DAT7 0x0176
+#define USBB2_HSIC_DATA 0x0178
+#define USBB2_HSIC_STROBE 0x017A
+#define UNIPRO_TX0 0x017C
+#define UNIPRO_TY0 0x017E
+#define UNIPRO_TX1 0x0180
+#define UNIPRO_TY1 0x0182
+#define UNIPRO_TX2 0x0184
+#define UNIPRO_TY2 0x0186
+#define UNIPRO_RX0 0x0188
+#define UNIPRO_RY0 0x018A
+#define UNIPRO_RX1 0x018C
+#define UNIPRO_RY1 0x018E
+#define UNIPRO_RX2 0x0190
+#define UNIPRO_RY2 0x0192
+#define USBA0_OTG_CE 0x0194
+#define USBA0_OTG_DP 0x0196
+#define USBA0_OTG_DM 0x0198
+#define FREF_CLK1_OUT 0x019A
+#define FREF_CLK2_OUT 0x019C
+#define SYS_NIRQ1 0x019E
+#define SYS_NIRQ2 0x01A0
+#define SYS_BOOT0 0x01A2
+#define SYS_BOOT1 0x01A4
+#define SYS_BOOT2 0x01A6
+#define SYS_BOOT3 0x01A8
+#define SYS_BOOT4 0x01AA
+#define SYS_BOOT5 0x01AC
+#define DPM_EMU0 0x01AE
+#define DPM_EMU1 0x01B0
+#define DPM_EMU2 0x01B2
+#define DPM_EMU3 0x01B4
+#define DPM_EMU4 0x01B6
+#define DPM_EMU5 0x01B8
+#define DPM_EMU6 0x01BA
+#define DPM_EMU7 0x01BC
+#define DPM_EMU8 0x01BE
+#define DPM_EMU9 0x01C0
+#define DPM_EMU10 0x01C2
+#define DPM_EMU11 0x01C4
+#define DPM_EMU12 0x01C6
+#define DPM_EMU13 0x01C8
+#define DPM_EMU14 0x01CA
+#define DPM_EMU15 0x01CC
+#define DPM_EMU16 0x01CE
+#define DPM_EMU17 0x01D0
+#define DPM_EMU18 0x01D2
+#define DPM_EMU19 0x01D4
+#define WAKEUPEVENT_0 0x01D8
+#define WAKEUPEVENT_1 0x01DC
+#define WAKEUPEVENT_2 0x01E0
+#define WAKEUPEVENT_3 0x01E4
+#define WAKEUPEVENT_4 0x01E8
+#define WAKEUPEVENT_5 0x01EC
+#define WAKEUPEVENT_6 0x01F0
+
+#define WKUP_REVISION 0x0000
+#define WKUP_HWINFO 0x0004
+#define WKUP_SYSCONFIG 0x0010
+#define PAD0_SIM_IO 0x0040
+#define PAD1_SIM_CLK 0x0042
+#define PAD0_SIM_RESET 0x0044
+#define PAD1_SIM_CD 0x0046
+#define PAD0_SIM_PWRCTRL 0x0048
+#define PAD1_SR_SCL 0x004A
+#define PAD0_SR_SDA 0x004C
+#define PAD1_FREF_XTAL_IN 0x004E
+#define PAD0_FREF_SLICER_IN 0x0050
+#define PAD1_FREF_CLK_IOREQ 0x0052
+#define PAD0_FREF_CLK0_OUT 0x0054
+#define PAD1_FREF_CLK3_REQ 0x0056
+#define PAD0_FREF_CLK3_OUT 0x0058
+#define PAD1_FREF_CLK4_REQ 0x005A
+#define PAD0_FREF_CLK4_OUT 0x005C
+#define PAD1_SYS_32K 0x005E
+#define PAD0_SYS_NRESPWRON 0x0060
+#define PAD1_SYS_NRESWARM 0x0062
+#define PAD0_SYS_PWR_REQ 0x0064
+#define PAD1_SYS_PWRON_RESET 0x0066
+#define PAD0_SYS_BOOT6 0x0068
+#define PAD1_SYS_BOOT7 0x006A
+#define PAD0_JTAG_NTRST 0x006C
+#define PAD1_JTAG_TCK 0x006D
+#define PAD0_JTAG_RTCK 0x0070
+#define PAD1_JTAG_TMS_TMSC 0x0072
+#define PAD0_JTAG_TDI 0x0074
+#define PAD1_JTAG_TDO 0x0076
+#define PADCONF_WAKEUPEVENT_0 0x007C
+#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0
+#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4
+#define PADCONF_MODE 0x05A8
+#define CONTROL_XTAL_OSCILLATOR 0x05AC
+#define CONTROL_CONTROL_I2C_2 0x0604
+#define CONTROL_CONTROL_JTAG 0x0608
+#define CONTROL_CONTROL_SYS 0x060C
+#define CONTROL_SPARE_RW 0x0614
+#define CONTROL_SPARE_R 0x0618
+#define CONTROL_SPARE_R_C0 0x061C
+
+#endif /* _MUX_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
new file mode 100644
index 000000000..d811d6ec2
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -0,0 +1,223 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Authors:
+ * Aneesh V <aneesh@ti.com>
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _OMAP5_H_
+#define _OMAP5_H_
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
+/*
+ * L4 Peripherals - L4 Wakeup and L4 Core now
+ */
+#define OMAP54XX_L4_CORE_BASE 0x4A000000
+#define OMAP54XX_L4_WKUP_BASE 0x4Ae00000
+#define OMAP54XX_L4_PER_BASE 0x48000000
+
+#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
+#define OMAP54XX_DRAM_ADDR_SPACE_END 0xD0000000
+#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
+#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
+
+/* CONTROL */
+#define CTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
+#define CONTROL_PADCONF_CORE (CTRL_BASE + 0x0800)
+#define CONTROL_PADCONF_WKUP (OMAP54XX_L4_WKUP_BASE + 0xc800)
+
+/* LPDDR2 IO regs. To be verified */
+#define LPDDR2_IO_REGS_BASE 0x4A100638
+
+/* CONTROL_ID_CODE */
+#define CONTROL_ID_CODE (CTRL_BASE + 0x204)
+
+/* To be verified */
+#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B85202F
+
+/* STD_FUSE_PROD_ID_1 */
+#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
+#define PROD_ID_1_SILICON_TYPE_SHIFT 16
+#define PROD_ID_1_SILICON_TYPE_MASK (3 << 16)
+
+/* UART */
+#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
+#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
+#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000)
+
+/* General Purpose Timers */
+#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000)
+#define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000)
+#define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000)
+
+/* Watchdog Timer2 - MPU watchdog */
+#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
+
+/* 32KTIMER */
+#define SYNC_32KTIMER_BASE (OMAP54XX_L4_WKUP_BASE + 0x4000)
+
+/* GPMC */
+#define OMAP54XX_GPMC_BASE 0x50000000
+
+/* SYSTEM CONTROL MODULE */
+#define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
+
+/*
+ * Hardware Register Details
+ */
+
+/* Watchdog Timer */
+#define WD_UNLOCK1 0xAAAA
+#define WD_UNLOCK2 0x5555
+
+/* GP Timer */
+#define TCLR_ST (0x1 << 0)
+#define TCLR_AR (0x1 << 1)
+#define TCLR_PRE (0x1 << 5)
+
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE 0x4AE06000
+#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET 0x01
+
+/* Control Module */
+#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
+#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
+#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
+#define CONTROL_EFUSE_2_OVERRIDE 0x00084000
+
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
+#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
+#define LPDDR2IO_GR10_WD_MASK (3 << 17)
+#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
+
+/* CONTROL_EFUSE_2 */
+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
+
+#define MMC1_PWRDNZ (1 << 26)
+#define MMC1_PBIASLITE_PWRDNZ (1 << 22)
+#define MMC1_PBIASLITE_VMODE (1 << 21)
+
+#ifndef __ASSEMBLY__
+
+struct s32ktimer {
+ unsigned char res[0x10];
+ unsigned int s32k_cr; /* 0x10 */
+};
+
+struct omap4_sys_ctrl_regs {
+ unsigned int pad1[129];
+ unsigned int control_id_code; /* 0x4A002204 */
+ unsigned int pad11[22];
+ unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */
+ unsigned int pad2[47];
+ unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */
+ unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */
+ unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
+ unsigned int pad3[260277];
+ unsigned int control_pbiaslite; /* 0x4A100600 */
+ unsigned int pad4[63];
+ unsigned int control_efuse_1; /* 0x4A100700 */
+ unsigned int control_efuse_2; /* 0x4A100704 */
+};
+
+struct control_lpddr2io_regs {
+ unsigned int control_lpddr2io1_0;
+ unsigned int control_lpddr2io1_1;
+ unsigned int control_lpddr2io1_2;
+ unsigned int control_lpddr2io1_3;
+ unsigned int control_lpddr2io2_0;
+ unsigned int control_lpddr2io2_1;
+ unsigned int control_lpddr2io2_2;
+ unsigned int control_lpddr2io2_3;
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Non-secure SRAM Addresses
+ * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
+ * at 0x40304000(EMU base) so that our code works for both EMU and GP
+ */
+#define NON_SECURE_SRAM_START 0x40304000
+#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
+/* base address for indirect vectors (internal boot mode) */
+#define SRAM_ROM_VECT_BASE 0x4031F000
+/* Temporary SRAM stack used while low level init is done */
+#define LOW_LEVEL_SRAM_STACK NON_SECURE_SRAM_END
+
+#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
+/*
+ * SRAM scratch space entries
+ */
+#define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR
+#define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
+#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
+#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
+#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+
+/* Silicon revisions */
+#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
+#define OMAP4430_ES1_0 0x44300100
+#define OMAP4430_ES2_0 0x44300200
+#define OMAP4430_ES2_1 0x44300210
+#define OMAP4430_ES2_2 0x44300220
+#define OMAP4430_ES2_3 0x44300230
+#define OMAP4460_ES1_0 0x44600100
+#define OMAP4460_ES1_1 0x44600110
+
+/* ROM code defines */
+/* Boot device */
+#define BOOT_DEVICE_MASK 0xFF
+#define BOOT_DEVICE_OFFSET 0x8
+#define DEV_DESC_PTR_OFFSET 0x4
+#define DEV_DATA_PTR_OFFSET 0x18
+#define BOOT_MODE_OFFSET 0x8
+#define RESET_REASON_OFFSET 0x9
+#define CH_FLAGS_OFFSET 0xA
+
+#define CH_FLAGS_CHSETTINGS (0x1 << 0)
+#define CH_FLAGS_CHRAM (0x1 << 1)
+#define CH_FLAGS_CHFLASH (0x1 << 2)
+#define CH_FLAGS_CHMMCSD (0x1 << 3)
+
+#ifndef __ASSEMBLY__
+struct omap_boot_parameters {
+ char *boot_message;
+ unsigned int mem_boot_descriptor;
+ unsigned char omap_bootdevice;
+ unsigned char reset_reason;
+ unsigned char ch_flags;
+};
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
new file mode 100644
index 000000000..c31e18ca2
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#include <asm/arch/omap.h>
+#include <asm/io.h>
+#include <asm/arch/clocks.h>
+#include <asm/omap_common.h>
+#include <asm/arch/mux_omap5.h>
+#include <asm/arch/clocks.h>
+
+struct omap_sysinfo {
+ char *board_string;
+};
+extern const struct omap_sysinfo sysinfo;
+
+void gpmc_init(void);
+void watchdog_init(void);
+u32 get_device_type(void);
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_essential(void);
+void set_muxconf_regs_non_essential(void);
+void sr32(void *, u32, u32, u32);
+u32 wait_on_value(u32, u32, void *, u32);
+void sdelay(unsigned long);
+void omap_rev_string(char *omap_rev_string);
+void setup_clocks_for_console(void);
+void prcm_init(void);
+void bypass_dpll(u32 *const base);
+void freq_update_core(void);
+u32 get_sys_clk_freq(void);
+u32 omap5_ddr_clk(void);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
+void sdram_init(void);
+u32 omap_sdram_size(void);
+u32 cortex_rev(void);
+void init_omap_revision(void);
+void do_io_settings(void);
+
+/*
+ * This is used to verify if the configuration header
+ * was executed by Romcode prior to control of transfer
+ * to the bootloader. SPL is responsible for saving and
+ * passing this to the u-boot.
+ */
+extern struct omap_boot_parameters boot_params;
+
+static inline u32 running_from_sdram(void)
+{
+ u32 pc;
+ asm volatile ("mov %0, pc" : "=r" (pc));
+ return ((pc >= OMAP54XX_DRAM_ADDR_SPACE_START) &&
+ (pc < OMAP54XX_DRAM_ADDR_SPACE_END));
+}
+
+static inline u8 uboot_loaded_by_spl(void)
+{
+ /*
+ * u-boot can be running from sdram either because of configuration
+ * Header or by SPL. If because of CH, then the romcode sets the
+ * CHSETTINGS executed bit to true in the boot parameter structure that
+ * it passes to the bootloader.This parameter is stored in the ch_flags
+ * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
+ * mandatory section if CH is present.
+ */
+ if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
+ return 0;
+ else
+ return running_from_sdram();
+}
+/*
+ * The basic hardware init of OMAP(s_init()) can happen in 4
+ * different contexts:
+ * 1. SPL running from SRAM
+ * 2. U-Boot running from FLASH
+ * 3. Non-XIP U-Boot loaded to SDRAM by SPL
+ * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
+ * Configuration Header feature
+ *
+ * This function finds this context.
+ * Defining as inline may help in compiling out unused functions in SPL
+ */
+static inline u32 omap_hw_init_context(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ return OMAP_INIT_CONTEXT_SPL;
+#else
+ if (uboot_loaded_by_spl())
+ return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
+ else if (running_from_sdram())
+ return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
+ else
+ return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
+#endif
+}
+
+static inline u32 omap_revision(void)
+{
+ extern u32 *const omap5_revision;
+ return *omap5_revision;
+}
+
+#endif
generated by cgit v1.2.3-70-g09d2 (git 2.51.2) at 2025-10-31 12:47:43 +0000