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-rw-r--r--arch/arm/cpu/arm920t/s3c24x0/Makefile1
-rw-r--r--arch/arm/cpu/arm920t/s3c24x0/cpu_info.c54
-rw-r--r--arch/arm/cpu/arm926ejs/cache.c5
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/timer.c2
-rw-r--r--arch/arm/cpu/armv7/start.S2
5 files changed, 58 insertions, 6 deletions
diff --git a/arch/arm/cpu/arm920t/s3c24x0/Makefile b/arch/arm/cpu/arm920t/s3c24x0/Makefile
index bd53724b5..0029700e4 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/Makefile
+++ b/arch/arm/cpu/arm920t/s3c24x0/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS-$(CONFIG_USE_IRQ) += interrupts.o
+COBJS-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
COBJS-y += speed.o
COBJS-y += timer.o
COBJS-y += usb.o
diff --git a/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c b/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c
new file mode 100644
index 000000000..14c5c6a00
--- /dev/null
+++ b/arch/arm/cpu/arm920t/s3c24x0/cpu_info.c
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2010
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
+
+typedef ulong (*getfreq)(void);
+
+static const getfreq freq_f[] = {
+ get_FCLK,
+ get_HCLK,
+ get_PCLK,
+};
+
+static const char freq_c[] = { 'F', 'H', 'P' };
+
+int print_cpuinfo(void)
+{
+ int i;
+ char buf[32];
+/* the S3C2400 seems to be lacking a CHIP ID register */
+#ifndef CONFIG_S3C2400
+ ulong cpuid;
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+ cpuid = readl(&gpio->gstatus1);
+ printf("CPUID: %8lX\n", cpuid);
+#endif
+ for (i = 0; i < ARRAY_SIZE(freq_f); i++)
+ printf("%cCLK: %8s MHz\n", freq_c[i], strmhz(buf, freq_f[i]()));
+
+ return 0;
+}
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 441564203..ee90ab719 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -38,11 +38,6 @@ void invalidate_dcache_all(void)
dcache_noop();
}
-void flush_dcache_all(void)
-{
- dcache_noop();
-}
-
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
dcache_noop();
diff --git a/arch/arm/cpu/arm926ejs/davinci/timer.c b/arch/arm/cpu/arm926ejs/davinci/timer.c
index a06d44955..93c9e60b7 100644
--- a/arch/arm/cpu/arm926ejs/davinci/timer.c
+++ b/arch/arm/cpu/arm926ejs/davinci/timer.c
@@ -108,7 +108,7 @@ void __udelay(unsigned long usec)
*/
ulong get_tbclk(void)
{
- return CONFIG_SYS_HZ;
+ return gd->timer_rate_hz;
}
#ifdef CONFIG_HW_WATCHDOG
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 6a77c71e1..ef08a55ab 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -132,6 +132,7 @@ reset:
orr r0, r0, #0xd3
msr cpsr,r0
+#if !defined(CONFIG_TEGRA2)
/*
* Setup vector:
* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
@@ -147,6 +148,7 @@ reset:
ldr r0, =_start
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif
+#endif /* !Tegra2 */
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT