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-rw-r--r--arch/arm/cpu/arm926ejs/mxs/Makefile10
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg4
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg4
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_power_init.c2
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/start.S9
-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c7
-rw-r--r--arch/arm/cpu/armv7/mx5/lowlevel_init.S12
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c56
-rw-r--r--arch/arm/cpu/armv7/omap-common/boot-common.c4
-rw-r--r--arch/arm/cpu/armv7/zynq/cpu.c6
10 files changed, 82 insertions, 32 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile
index 13b5a5452..152546eb4 100644
--- a/arch/arm/cpu/arm926ejs/mxs/Makefile
+++ b/arch/arm/cpu/arm926ejs/mxs/Makefile
@@ -14,11 +14,11 @@ obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
endif
# Specify the target for use in elftosb call
-ELFTOSB_TARGET-$(CONFIG_MX23) = imx23
-ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
+MKIMAGE_TARGET-$(CONFIG_MX23) = mx23
+MKIMAGE_TARGET-$(CONFIG_MX28) = mx28
-$(OBJTREE)/u-boot.bd: $(SRCTREE)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd
+$(OBJTREE)/mxsimage.cfg: $(SRCTREE)/$(CPUDIR)/$(SOC)/mxsimage.$(MKIMAGE_TARGET-y).cfg
sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@
-$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/u-boot.bd
- elftosb -zf $(ELFTOSB_TARGET-y) -c $(OBJTREE)/u-boot.bd -o $(OBJTREE)/u-boot.sb
+$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/mxsimage.cfg
+ $(OBJTREE)/tools/mkimage -n $(OBJTREE)/mxsimage.cfg -T mxsimage $@
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
index 811876736..c9cf4b362 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
+++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
@@ -1,6 +1,6 @@
SECTION 0x0 BOOTABLE
TAG LAST
- LOAD 0x0 spl/u-boot-spl.bin
+ LOAD 0x0 OBJTREE/spl/u-boot-spl.bin
CALL 0x14 0x0
- LOAD 0x40000100 u-boot.bin
+ LOAD 0x40000100 OBJTREE/u-boot.bin
CALL 0x40000100 0x0
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
index ea772f0c8..676f5c8f7 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
+++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
@@ -1,8 +1,8 @@
SECTION 0x0 BOOTABLE
TAG LAST
- LOAD 0x0 spl/u-boot-spl.bin
+ LOAD 0x0 OBJTREE/spl/u-boot-spl.bin
LOAD IVT 0x8000 0x14
CALL HAB 0x8000 0x0
- LOAD 0x40000100 u-boot.bin
+ LOAD 0x40000100 OBJTREE/u-boot.bin
LOAD IVT 0x8000 0x40000100
CALL HAB 0x8000 0x0
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index 8ea45be1d..d25019a51 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -654,6 +654,8 @@ static void mxs_batt_boot(void)
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+
+ mxs_power_enable_4p2();
}
/**
diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S
index 3e454ae1b..5de2bad58 100644
--- a/arch/arm/cpu/arm926ejs/mxs/start.S
+++ b/arch/arm/cpu/arm926ejs/mxs/start.S
@@ -150,6 +150,15 @@ IRQ_STACK_START_IN:
_reset:
/*
+ * If the CPU is configured in "Wait JTAG connection mode", the stack
+ * pointer is not configured and is zero. This will cause crash when
+ * trying to push data onto stack right below here. Load the SP and make
+ * it point to the end of OCRAM if the SP is zero.
+ */
+ cmp sp, #0x00000000
+ ldreq sp, =CONFIG_SYS_INIT_SP_ADDR
+
+ /*
* Store all registers on old stack pointer, this will allow us later to
* return to the BootROM and let the BootROM load U-Boot into RAM.
*
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index a31bf40e5..453effa54 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -32,6 +32,7 @@
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
#include <asm/omap_musb.h>
+#include <asm/davinci_rtc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -150,15 +151,15 @@ __weak void am33xx_spl_board_init(void)
static void rtc32k_enable(void)
{
- struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+ struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
/*
* Unlock the RTC's registers. For more details please see the
* RTC_SS section of the TRM. In order to unlock we need to
* write these specific values (keys) in this order.
*/
- writel(0x83e70b13, &rtc->kick0r);
- writel(0x95a4f1e0, &rtc->kick1r);
+ writel(RTC_KICK0R_WE, &rtc->kick0r);
+ writel(RTC_KICK1R_WE, &rtc->kick1r);
/* Enable the RTC 32K OSC by setting bits 3 and 6. */
writel((1 << 3) | (1 << 6), &rtc->osc);
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 25fadf648..f5bc6728b 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -45,6 +45,12 @@
#endif
mcr 15, 1, r0, c9, c0, 2
+
+ /* enable L2 cache */
+ mrc 15, 0, r0, c1, c0, 1
+ orr r0, r0, #2
+ mcr 15, 0, r0, c1, c0, 1
+
.endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.
@@ -369,12 +375,6 @@ setup_pll_func:
#endif /* CONFIG_MX53 */
.endm
-.macro setup_wdog
- ldr r0, =WDOG1_BASE_ADDR
- mov r1, #0x30
- strh r1, [r0]
-.endm
-
ENTRY(lowlevel_init)
mov r10, lr
mov r4, #0 /* Fix R4 to 0 */
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index cf3a38e81..873d9d0fd 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -100,6 +100,32 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
}
/* NOTREACHED */
}
+static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
+{
+ u32 div;
+ u64 freq;
+
+ switch (pll) {
+ case PLL_BUS:
+ if (pfd_num == 3) {
+ /* No PFD3 on PPL2 */
+ return 0;
+ }
+ div = __raw_readl(&imx_ccm->analog_pfd_528);
+ freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
+ break;
+ case PLL_USBOTG:
+ div = __raw_readl(&imx_ccm->analog_pfd_480);
+ freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
+ break;
+ default:
+ /* No PFD on other PLL */
+ return 0;
+ }
+
+ return (freq * 18) / ((div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
+ ANATOP_PFD_FRAC_SHIFT(pfd_num));
+}
static u32 get_mcu_main_clk(void)
{
@@ -144,13 +170,14 @@ u32 get_periph_clk(void)
freq = decode_pll(PLL_BUS, MXC_HCLK);
break;
case 1:
- freq = PLL2_PFD2_FREQ;
+ freq = mxc_get_pll_pfd(PLL_BUS, 2);
break;
case 2:
- freq = PLL2_PFD0_FREQ;
+ freq = mxc_get_pll_pfd(PLL_BUS, 0);
break;
case 3:
- freq = PLL2_PFD2_DIV_FREQ;
+ /* static / 2 divider */
+ freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
break;
default:
break;
@@ -184,7 +211,7 @@ static u32 get_ipg_per_clk(void)
static u32 get_uart_clk(void)
{
u32 reg, uart_podf;
- u32 freq = PLL3_80M;
+ u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
reg = __raw_readl(&imx_ccm->cscdr1);
#ifdef CONFIG_MX6SL
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
@@ -204,7 +231,7 @@ static u32 get_cspi_clk(void)
reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
- return PLL3_60M / (cspi_podf + 1);
+ return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
}
static u32 get_axi_clk(void)
@@ -217,9 +244,9 @@ static u32 get_axi_clk(void)
if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
- root_freq = PLL2_PFD2_FREQ;
+ root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
else
- root_freq = PLL3_PFD1_FREQ;
+ root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
} else
root_freq = get_periph_clk();
@@ -244,10 +271,10 @@ static u32 get_emi_slow_clk(void)
root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
break;
case 2:
- root_freq = PLL2_PFD2_FREQ;
+ root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
break;
case 3:
- root_freq = PLL2_PFD0_FREQ;
+ root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
break;
}
@@ -270,13 +297,14 @@ static u32 get_mmdc_ch0_clk(void)
freq = decode_pll(PLL_BUS, MXC_HCLK);
break;
case 1:
- freq = PLL2_PFD2_FREQ;
+ freq = mxc_get_pll_pfd(PLL_BUS, 2);
break;
case 2:
- freq = PLL2_PFD0_FREQ;
+ freq = mxc_get_pll_pfd(PLL_BUS, 0);
break;
case 3:
- freq = PLL2_PFD2_DIV_FREQ;
+ /* static / 2 divider */
+ freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
}
return freq / (podf + 1);
@@ -359,9 +387,9 @@ static u32 get_usdhc_clk(u32 port)
}
if (clk_sel)
- root_freq = PLL2_PFD0_FREQ;
+ root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
else
- root_freq = PLL2_PFD2_FREQ;
+ root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
return root_freq / (usdhc_podf + 1);
}
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 0ffa03ac0..69fff323d 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -14,6 +14,7 @@
#include <asm/arch/omap.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
+#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -76,6 +77,9 @@ void spl_board_init(void)
#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
arch_misc_init();
#endif
+#if defined(CONFIG_HW_WATCHDOG)
+ hw_watchdog_init();
+#endif
#ifdef CONFIG_AM33XX
am33xx_spl_board_init();
#endif
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 49149861f..2bb38438a 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -11,6 +11,10 @@
void lowlevel_init(void)
{
+}
+
+int arch_cpu_init(void)
+{
zynq_slcr_unlock();
/* remap DDR to zero, FILTERSTART */
writel(0, &scu_base->filter_start);
@@ -31,6 +35,8 @@ void lowlevel_init(void)
writel(0xC, &slcr_base->ddr_urgent);
zynq_slcr_lock();
+
+ return 0;
}
void reset_cpu(ulong addr)
generated by cgit v1.2.3-70-g09d2 (git 2.51.2) at 2025-10-31 18:12:32 +0000