diff options
Diffstat (limited to 'arch/arm/cpu')
32 files changed, 3280 insertions, 1371 deletions
diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index d11e6f627..46f4b64ff 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -519,7 +519,7 @@ u32 spl_boot_device(void) case RCSR_MEM_TYPE_NOR: return BOOT_DEVICE_NOR; case RCSR_MEM_TYPE_ONENAND: - return BOOT_DEVICE_ONE_NAND; + return BOOT_DEVICE_ONENAND; default: return BOOT_DEVICE_NONE; } diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds index 008ae891c..c19285d21 100644 --- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds +++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds @@ -51,7 +51,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN(4); diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c index 0448c0b13..92185460a 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c @@ -61,20 +61,20 @@ char *get_cpu_name() if (cpu_is_at91sam9x5()) { switch (extension_id) { case ARCH_EXID_AT91SAM9G15: - return CONFIG_SYS_AT91_G15_CPU_NAME; + return "AT91SAM9G15"; case ARCH_EXID_AT91SAM9G25: - return CONFIG_SYS_AT91_G25_CPU_NAME; + return "AT91SAM9G25"; case ARCH_EXID_AT91SAM9G35: - return CONFIG_SYS_AT91_G35_CPU_NAME; + return "AT91SAM9G35"; case ARCH_EXID_AT91SAM9X25: - return CONFIG_SYS_AT91_X25_CPU_NAME; + return "AT91SAM9X25"; case ARCH_EXID_AT91SAM9X35: - return CONFIG_SYS_AT91_X35_CPU_NAME; + return "AT91SAM9X35"; default: - return CONFIG_SYS_AT91_UNKNOWN_CPU; + return "Unknown CPU type"; } } else { - return CONFIG_SYS_AT91_UNKNOWN_CPU; + return "Unknown CPU type"; } } @@ -246,14 +246,14 @@ void at91_macb_hw_init(void) #ifndef CONFIG_RMII /* Only emac0 support MII */ if (has_emac0()) { - at91_set_b_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ - at91_set_b_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ - at91_set_b_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ - at91_set_b_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ - at91_set_b_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ - at91_set_b_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ - at91_set_b_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ - at91_set_b_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ + at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ } #endif } diff --git a/arch/arm/cpu/arm926ejs/davinci/misc.c b/arch/arm/cpu/arm926ejs/davinci/misc.c index c310c69ad..162c1e0ff 100644 --- a/arch/arm/cpu/arm926ejs/davinci/misc.c +++ b/arch/arm/cpu/arm926ejs/davinci/misc.c @@ -104,7 +104,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) int ret; ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); - if (ret) { + if (!ret) { /* * There is no MAC address in the environment, so we * initialize it from the value in the EEPROM. @@ -115,7 +115,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr); } if (!ret) - printf("Failed to set mac address from EEPROM\n"); + printf("Failed to set mac address from EEPROM: %d\n", ret); } #endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index 6dc681a31..0f3222c76 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -51,12 +51,6 @@ SECTIONS . = ALIGN(4); - .u_boot_list : { - #include <u-boot.lst> - } - - . = ALIGN(4); - .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds index f3bd5e736..0af3e0a23 100644 --- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -51,12 +51,6 @@ SECTIONS . = ALIGN(4); - .u_boot_list : { - #include <u-boot.lst> - } - - . = ALIGN(4); - .rel.dyn : { __rel_dyn_start = .; *(.rel*) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index ab313265d..e35a3e3a7 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -56,11 +56,11 @@ int cpu_mmc_init(bd_t *bis) { int ret; - ret = omap_mmc_init(0, 0, 0); + ret = omap_mmc_init(0, 0, 0, -1, -1); if (ret) return ret; - return omap_mmc_init(1, 0, 0); + return omap_mmc_init(1, 0, 0, -1, -1); } #endif diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index fd9fc4a72..448cc4015 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -45,13 +45,19 @@ static struct ddr_cmdtctrl *ioctrl_reg = { */ void config_sdram(const struct emif_regs *regs) { - writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); - writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); - if (regs->zq_config){ + if (regs->zq_config) { + /* + * A value of 0x2800 for the REF CTRL will give us + * about 570us for a delay, which will be long enough + * to configure things. + */ + writel(0x2800, &emif_reg->emif_sdram_ref_ctrl); writel(regs->zq_config, &emif_reg->emif_zq_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); } writel(regs->sdram_config, &emif_reg->emif_sdram_config); + writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); } /** diff --git a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds new file mode 100644 index 000000000..69f6d48da --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } >.sram + + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } >.sdram +} diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 1c8b6177d..24cbe2da0 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -64,11 +64,11 @@ int board_mmc_init(bd_t *bis) { switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: - omap_mmc_init(0, 0, 0); + omap_mmc_init(0, 0, 0, -1, -1); break; case BOOT_DEVICE_MMC2: case BOOT_DEVICE_MMC2_2: - omap_mmc_init(1, 0, 0); + omap_mmc_init(1, 0, 0, -1, -1); break; } return 0; diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index b1fd277d6..9ed18995e 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -36,6 +36,7 @@ #include <asm/arch/sys_proto.h> #include <asm/utils.h> #include <asm/omap_gpio.h> +#include <asm/emif.h> #ifndef CONFIG_SPL_BUILD /* @@ -46,9 +47,20 @@ #define puts(s) #endif +const u32 sys_clk_array[8] = { + 12000000, /* 12 MHz */ + 13000000, /* 13 MHz */ + 16800000, /* 16.8 MHz */ + 19200000, /* 19.2 MHz */ + 26000000, /* 26 MHz */ + 27000000, /* 27 MHz */ + 38400000, /* 38.4 MHz */ + 20000000, /* 20 MHz */ +}; + static inline u32 __get_sys_clk_index(void) { - u32 ind; + s8 ind; /* * For ES1 the ROM code calibration of sys clock is not reliable * due to hw issue. So, use hard-coded value. If this value is not @@ -60,8 +72,15 @@ static inline u32 __get_sys_clk_index(void) ind = OMAP_SYS_CLK_IND_38_4_MHZ; else { /* SYS_CLKSEL - 1 to match the dpll param array indices */ - ind = (readl(&prcm->cm_sys_clksel) & + ind = (readl((*prcm)->cm_sys_clksel) & CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; + /* + * SYS_CLKSEL value for 20MHz is 0. This is introduced newly + * in DRA7XX socs. SYS_CLKSEL -1 will be greater than + * NUM_SYS_CLK. So considering the last 3 bits as the index + * for the dpll param array. + */ + ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK; } return ind; } @@ -75,7 +94,34 @@ u32 get_sys_clk_freq(void) return sys_clk_array[index]; } -static inline void do_bypass_dpll(u32 *const base) +void setup_post_dividers(u32 const base, const struct dpll_params *params) +{ + struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + + /* Setup post-dividers */ + if (params->m2 >= 0) + writel(params->m2, &dpll_regs->cm_div_m2_dpll); + if (params->m3 >= 0) + writel(params->m3, &dpll_regs->cm_div_m3_dpll); + if (params->m4_h11 >= 0) + writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll); + if (params->m5_h12 >= 0) + writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll); + if (params->m6_h13 >= 0) + writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll); + if (params->m7_h14 >= 0) + writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll); + if (params->h21 >= 0) + writel(params->h21, &dpll_regs->cm_div_h21_dpll); + if (params->h22 >= 0) + writel(params->h22, &dpll_regs->cm_div_h22_dpll); + if (params->h23 >= 0) + writel(params->h23, &dpll_regs->cm_div_h23_dpll); + if (params->h24 >= 0) + writel(params->h24, &dpll_regs->cm_div_h24_dpll); +} + +static inline void do_bypass_dpll(u32 const base) { struct dpll_regs *dpll_regs = (struct dpll_regs *)base; @@ -85,17 +131,17 @@ static inline void do_bypass_dpll(u32 *const base) CM_CLKMODE_DPLL_EN_SHIFT); } -static inline void wait_for_bypass(u32 *const base) +static inline void wait_for_bypass(u32 const base) { struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll, LDELAY)) { - printf("Bypassing DPLL failed %p\n", base); + printf("Bypassing DPLL failed %x\n", base); } } -static inline void do_lock_dpll(u32 *const base) +static inline void do_lock_dpll(u32 const base) { struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; @@ -104,18 +150,18 @@ static inline void do_lock_dpll(u32 *const base) DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); } -static inline void wait_for_lock(u32 *const base) +static inline void wait_for_lock(u32 const base) { struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, &dpll_regs->cm_idlest_dpll, LDELAY)) { - printf("DPLL locking failed for %p\n", base); + printf("DPLL locking failed for %x\n", base); hang(); } } -inline u32 check_for_lock(u32 *const base) +inline u32 check_for_lock(u32 const base) { struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK; @@ -123,12 +169,65 @@ inline u32 check_for_lock(u32 *const base) return lock; } -static void do_setup_dpll(u32 *const base, const struct dpll_params *params, +const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->mpu[sysclk_ind]; +} + +const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->core[sysclk_ind]; +} + +const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->per[sysclk_ind]; +} + +const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->iva[sysclk_ind]; +} + +const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->usb[sysclk_ind]; +} + +const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data) +{ +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + u32 sysclk_ind = get_sys_clk_index(); + return &dpll_data->abe[sysclk_ind]; +#else + return dpll_data->abe; +#endif +} + +static const struct dpll_params *get_ddr_dpll_params + (struct dplls const *dpll_data) +{ + u32 sysclk_ind = get_sys_clk_index(); + + if (!dpll_data->ddr) + return NULL; + return &dpll_data->ddr[sysclk_ind]; +} + +static void do_setup_dpll(u32 const base, const struct dpll_params *params, u8 lock, char *dpll) { u32 temp, M, N; struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; + if (!params) + return; + temp = readl(&dpll_regs->cm_clksel_dpll); if (check_for_lock(base)) { @@ -183,7 +282,7 @@ u32 omap_ddr_clk(void) omap_rev = omap_revision(); sys_clk_khz = get_sys_clk_freq() / 1000; - core_dpll_params = get_core_dpll_params(); + core_dpll_params = get_core_dpll_params(*dplls_data); debug("sys_clk %d\n ", sys_clk_khz * 1000); @@ -235,24 +334,19 @@ void configure_mpu_dpll(void) */ if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) { mpu_dpll_regs = - (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu; - bypass_dpll(&prcm->cm_clkmode_dpll_mpu); - clrbits_le32(&prcm->cm_mpu_mpu_clkctrl, + (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu); + bypass_dpll((*prcm)->cm_clkmode_dpll_mpu); + clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl, MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); - setbits_le32(&prcm->cm_mpu_mpu_clkctrl, + setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll, CM_CLKSEL_DCC_EN_MASK); } - setbits_le32(&prcm->cm_mpu_mpu_clkctrl, - MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); - setbits_le32(&prcm->cm_mpu_mpu_clkctrl, - MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); + params = get_mpu_dpll_params(*dplls_data); - params = get_mpu_dpll_params(); - - do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); + do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); debug("MPU DPLL locked\n"); } @@ -271,17 +365,17 @@ static void setup_usb_dpll(void) * Use CLKINP in KHz and adjust the denominator accordingly so * that we have enough accuracy and at the same time no overflow */ - params = get_usb_dpll_params(); + params = get_usb_dpll_params(*dplls_data); num = params->m * sys_clk_khz; den = (params->n + 1) * 250 * 1000; num += den - 1; sd_div = num / den; - clrsetbits_le32(&prcm->cm_clksel_dpll_usb, + clrsetbits_le32((*prcm)->cm_clksel_dpll_usb, CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); /* Now setup the dpll with the regular function */ - do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb"); + do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb"); } #endif @@ -293,28 +387,28 @@ static void setup_dplls(void) debug("setup_dplls\n"); /* CORE dpll */ - params = get_core_dpll_params(); /* default - safest */ + params = get_core_dpll_params(*dplls_data); /* default - safest */ /* * Do not lock the core DPLL now. Just set it up. * Core DPLL will be locked after setting up EMIF * using the FREQ_UPDATE method(freq_update_core()) */ - if (omap_revision() != OMAP5432_ES1_0) - do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) + do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, DPLL_NO_LOCK, "core"); else - do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, + do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, DPLL_LOCK, "core"); /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); - writel(temp, &prcm->cm_clksel_core); + writel(temp, (*prcm)->cm_clksel_core); debug("Core DPLL configured\n"); /* lock PER dpll */ - params = get_per_dpll_params(); - do_setup_dpll(&prcm->cm_clkmode_dpll_per, + params = get_per_dpll_params(*dplls_data); + do_setup_dpll((*prcm)->cm_clkmode_dpll_per, params, DPLL_LOCK, "per"); debug("PER DPLL locked\n"); @@ -324,6 +418,9 @@ static void setup_dplls(void) #ifdef CONFIG_USB_EHCI_OMAP setup_usb_dpll(); #endif + params = get_ddr_dpll_params(*dplls_data); + do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy, + params, DPLL_LOCK, "ddr"); } #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL @@ -333,14 +430,14 @@ static void setup_non_essential_dplls(void) const struct dpll_params *params; /* IVA */ - clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, + clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva, CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); - params = get_iva_dpll_params(); - do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva"); + params = get_iva_dpll_params(*dplls_data); + do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva"); /* Configure ABE dpll */ - params = get_abe_dpll_params(); + params = get_abe_dpll_params(*dplls_data); #ifdef CONFIG_SYS_OMAP_ABE_SYSCK abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; #else @@ -349,64 +446,65 @@ static void setup_non_essential_dplls(void) * We need to enable some additional options to achieve * 196.608MHz from 32768 Hz */ - setbits_le32(&prcm->cm_clkmode_dpll_abe, + setbits_le32((*prcm)->cm_clkmode_dpll_abe, CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| CM_CLKMODE_DPLL_LPMODE_EN_MASK| CM_CLKMODE_DPLL_REGM4XEN_MASK); /* Spend 4 REFCLK cycles at each stage */ - clrsetbits_le32(&prcm->cm_clkmode_dpll_abe, + clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe, CM_CLKMODE_DPLL_RAMP_RATE_MASK, 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); #endif /* Select the right reference clk */ - clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel, + clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel, CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); /* Lock the dpll */ - do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe"); + do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe"); } #endif -void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv) +u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic) { - u32 step; - int ret = 0; - - /* See if we can first get the GPIO if needed */ - if (gpio >= 0) - ret = gpio_request(gpio, "TPS62361_VSEL0_GPIO"); - if (ret < 0) { - printf("%s: gpio %d request failed %d\n", __func__, gpio, ret); - gpio = -1; - } - - /* Pull the GPIO low to select SET0 register, while we program SET1 */ - if (gpio >= 0) - gpio_direction_output(gpio, 0); + u32 offset_code; - step = volt_mv - TPS62361_BASE_VOLT_MV; - step /= 10; + volt_offset -= pmic->base_offset; - debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step); - if (omap_vc_bypass_send_value(TPS62361_I2C_SLAVE_ADDR, reg, step)) - puts("Scaling voltage failed for vdd_mpu from TPS\n"); + offset_code = (volt_offset + pmic->step - 1) / pmic->step; - /* Pull the GPIO high to select SET1 register */ - if (gpio >= 0) - gpio_direction_output(gpio, 1); + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + return offset_code + pmic->start_code; } -void do_scale_vcore(u32 vcore_reg, u32 volt_mv) +void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) { u32 offset_code; u32 offset = volt_mv; + int ret = 0; + + /* See if we can first get the GPIO if needed */ + if (pmic->gpio_en) + ret = gpio_request(pmic->gpio, "PMIC_GPIO"); + + if (ret < 0) { + printf("%s: gpio %d request failed %d\n", __func__, + pmic->gpio, ret); + return; + } + + /* Pull the GPIO low to select SET0 register, while we program SET1 */ + if (pmic->gpio_en) + gpio_direction_output(pmic->gpio, 0); /* convert to uV for better accuracy in the calculations */ offset *= 1000; - offset_code = get_offset_code(offset); + offset_code = get_offset_code(offset, pmic); debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, offset_code); @@ -414,16 +512,46 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv) if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR, vcore_reg, offset_code)) printf("Scaling voltage failed for 0x%x\n", vcore_reg); + + if (pmic->gpio_en) + gpio_direction_output(pmic->gpio, 1); +} + +/* + * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva + * We set the maximum voltages allowed here because Smart-Reflex is not + * enabled in bootloader. Voltage initialization in the kernel will set + * these to the nominal values after enabling Smart-Reflex + */ +void scale_vcores(struct vcores_data const *vcores) +{ + omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); + + do_scale_vcore(vcores->core.addr, vcores->core.value, + vcores->core.pmic); + + do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, + vcores->mpu.pmic); + + do_scale_vcore(vcores->mm.addr, vcores->mm.value, + vcores->mm.pmic); + + if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { + /* Configure LDO SRAM "magic" bits */ + writel(2, (*prcm)->prm_sldo_core_setup); + writel(2, (*prcm)->prm_sldo_mpu_setup); + writel(2, (*prcm)->prm_sldo_mm_setup); + } } -static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) +static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode) { clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); - debug("Enable clock domain - %p\n", clkctrl_reg); + debug("Enable clock domain - %x\n", clkctrl_reg); } -static inline void wait_for_clk_enable(u32 *clkctrl_addr) +static inline void wait_for_clk_enable(u32 clkctrl_addr) { u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; u32 bound = LDELAY; @@ -435,19 +563,19 @@ static inline void wait_for_clk_enable(u32 *clkctrl_addr) idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> MODULE_CLKCTRL_IDLEST_SHIFT; if (--bound == 0) { - printf("Clock enable failed for 0x%p idlest 0x%x\n", + printf("Clock enable failed for 0x%x idlest 0x%x\n", clkctrl_addr, clkctrl); return; } } } -static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode, +static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode, u32 wait_for_enable) { clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); - debug("Enable clock module - %p\n", clkctrl_addr); + debug("Enable clock module - %x\n", clkctrl_addr); if (wait_for_enable) wait_for_clk_enable(clkctrl_addr); } @@ -458,12 +586,12 @@ void freq_update_core(void) const struct dpll_params *core_dpll_params; u32 omap_rev = omap_revision(); - core_dpll_params = get_core_dpll_params(); + core_dpll_params = get_core_dpll_params(*dplls_data); /* Put EMIF clock domain in sw wakeup mode */ - enable_clock_domain(&prcm->cm_memif_clkstctrl, + enable_clock_domain((*prcm)->cm_memif_clkstctrl, CD_CLKCTRL_CLKTRCTRL_SW_WKUP); - wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); - wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); + wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl); + wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl); freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK | SHADOW_FREQ_CONFIG1_DLL_RESET_MASK; @@ -475,9 +603,9 @@ void freq_update_core(void) SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) & SHADOW_FREQ_CONFIG1_M2_DIV_MASK; - writel(freq_config1, &prcm->cm_shadow_freq_config1); + writel(freq_config1, (*prcm)->cm_shadow_freq_config1); if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0, - &prcm->cm_shadow_freq_config1, LDELAY)) { + (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) { puts("FREQ UPDATE procedure failed!!"); hang(); } @@ -489,20 +617,20 @@ void freq_update_core(void) */ if (omap_rev != OMAP5430_ES1_0) { /* Put EMIF clock domain back in hw auto mode */ - enable_clock_domain(&prcm->cm_memif_clkstctrl, + enable_clock_domain((*prcm)->cm_memif_clkstctrl, CD_CLKCTRL_CLKTRCTRL_HW_AUTO); - wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl); - wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl); + wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl); + wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl); } } -void bypass_dpll(u32 *const base) +void bypass_dpll(u32 const base) { do_bypass_dpll(base); wait_for_bypass(base); } -void lock_dpll(u32 *const base) +void lock_dpll(u32 const base) { do_lock_dpll(base); wait_for_lock(base); @@ -511,39 +639,39 @@ void lock_dpll(u32 *const base) void setup_clocks_for_console(void) { /* Do not add any spl_debug prints in this function */ - clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, CD_CLKCTRL_CLKTRCTRL_SW_WKUP << CD_CLKCTRL_CLKTRCTRL_SHIFT); /* Enable all UARTs - console will be on one of them */ - clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl, + clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl, MODULE_CLKCTRL_MODULEMODE_MASK, MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << MODULE_CLKCTRL_MODULEMODE_SHIFT); - clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl, + clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl, MODULE_CLKCTRL_MODULEMODE_MASK, MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << MODULE_CLKCTRL_MODULEMODE_SHIFT); - clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl, + clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl, MODULE_CLKCTRL_MODULEMODE_MASK, MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << MODULE_CLKCTRL_MODULEMODE_SHIFT); - clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl, + clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl, MODULE_CLKCTRL_MODULEMODE_MASK, MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << MODULE_CLKCTRL_MODULEMODE_SHIFT); - clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, + clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, CD_CLKCTRL_CLKTRCTRL_HW_AUTO << CD_CLKCTRL_CLKTRCTRL_SHIFT); } -void do_enable_clocks(u32 *const *clk_domains, - u32 *const *clk_modules_hw_auto, - u32 *const *clk_modules_explicit_en, +void do_enable_clocks(u32 const *clk_domains, + u32 const *clk_modules_hw_auto, + u32 const *clk_modules_explicit_en, u8 wait_for_enable) { u32 i, max = 100; @@ -582,7 +710,7 @@ void prcm_init(void) case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: enable_basic_clocks(); - scale_vcores(); + scale_vcores(*omap_vcores); setup_dplls(); #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL setup_non_essential_dplls(); diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 88253cf8c..9eb1279d4 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -66,6 +66,19 @@ inline u32 emif_num(u32 base) return 0; } +/* + * Get SDRAM type connected to EMIF. + * Assuming similar SDRAM parts are connected to both EMIF's + * which is typically the case. So it is sufficient to get + * SDRAM type from EMIF1. + */ +u32 emif_sdram_type() +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; + + return (readl(&emif->emif_sdram_config) & + EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT; +} static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) { @@ -110,11 +123,13 @@ void emif_reset_phy(u32 base) static void do_lpddr2_init(u32 base, u32 cs) { u32 mr_addr; + const struct lpddr2_mr_regs *mr_regs; + get_lpddr2_mr_regs(&mr_regs); /* Wait till device auto initialization is complete */ while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) ; - set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT); + set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10); /* * tZQINIT = 1 us * Enough loops assuming a maximum of 2GHz @@ -122,22 +137,18 @@ static void do_lpddr2_init(u32 base, u32 cs) sdelay(2000); - if (omap_revision() >= OMAP5430_ES1_0) - set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8); - else - set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3); - - set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY); + set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1); + set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16); /* * Enable refresh along with writing MR2 * Encoding of RL in MR2 is (RL - 2) */ mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; - set_mr(base, cs, mr_addr, RL_FINAL - 2); + set_mr(base, cs, mr_addr, mr_regs->mr2); - if (omap_revision() >= OMAP5430_ES1_0) - set_mr(base, cs, LPDDR2_MR3, 0x1); + if (mr_regs->mr3 > 0) + set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3); } static void lpddr2_init(u32 base, const struct emif_regs *regs) @@ -255,9 +266,6 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs) static void ddr3_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 *ext_phy_ctrl_base = 0; - u32 *emif_ext_phy_ctrl_base = 0; - u32 i = 0; /* * Set SDRAM_CONFIG and PHY control registers to locked frequency @@ -277,27 +285,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); - ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); - emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); - - /* Configure external phy control timing registers */ - for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { - writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); - } - - /* - * external phy 6-24 registers do not change with - * ddr frequency - */ - for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { - writel(ddr3_ext_phy_ctrl_const_base[i], - emif_ext_phy_ctrl_base++); - /* Update shadow registers */ - writel(ddr3_ext_phy_ctrl_const_base[i], - emif_ext_phy_ctrl_base++); - } + do_ext_phy_settings(base, regs); /* enable leveling */ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); @@ -1079,7 +1067,7 @@ static void do_sdram_init(u32 base) * OPP to another) */ if (!(in_sdram || warm_reset())) { - if (omap_revision() != OMAP5432_ES1_0) + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) lpddr2_init(base, regs); else ddr3_init(base, regs); @@ -1096,9 +1084,6 @@ void emif_post_init_config(u32 base) struct emif_reg_struct *emif = (struct emif_reg_struct *)base; u32 omap_rev = omap_revision(); - if (omap_rev == OMAP5430_ES1_0) - return; - /* reset phy on ES2.0 */ if (omap_rev == OMAP4430_ES2_0) emif_reset_phy(base); @@ -1206,7 +1191,7 @@ void dmm_init(u32 base) writel(lisa_map_regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); - if (omap_revision() >= OMAP4460_ES1_0) { + if (lisa_map_regs->is_ma_present) { hw_lisa_map_regs = (struct dmm_lisa_map_regs *)MA_BASE; @@ -1264,7 +1249,7 @@ void dmm_init(u32 base) void sdram_init(void) { u32 in_sdram, size_prog, size_detect; - u32 omap_rev = omap_revision(); + u32 sdram_type = emif_sdram_type(); debug(">>sdram_init()\n"); @@ -1275,10 +1260,10 @@ void sdram_init(void) debug("in_sdram = %d\n", in_sdram); if (!(in_sdram || warm_reset())) { - if (omap_rev != OMAP5432_ES1_0) - bypass_dpll(&prcm->cm_clkmode_dpll_core); + if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) + bypass_dpll((*prcm)->cm_clkmode_dpll_core); else - writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl); + writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); } if (!in_sdram) @@ -1298,7 +1283,7 @@ void sdram_init(void) } /* for the shadow registers to take effect */ - if (omap_rev != OMAP5432_ES1_0) + if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) freq_update_core(); /* Do some testing after the init */ diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 9ef10bdf2..05ff2e868 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -32,6 +32,8 @@ #include <asm/arch/sys_proto.h> #include <asm/sizes.h> #include <asm/emif.h> +#include <asm/omap_common.h> +#include <linux/compiler.h> DECLARE_GLOBAL_DATA_PTR; @@ -79,12 +81,17 @@ u32 cortex_rev(void) void omap_rev_string(void) { u32 omap_rev = omap_revision(); + u32 soc_variant = (omap_rev & 0xF0000000) >> 28; u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16; u32 major_rev = (omap_rev & 0x00000F00) >> 8; u32 minor_rev = (omap_rev & 0x000000F0) >> 4; - printf("OMAP%x ES%x.%x\n", omap_variant, major_rev, - minor_rev); + if (soc_variant) + printf("OMAP"); + else + printf("DRA"); + printf("%x ES%x.%x\n", omap_variant, major_rev, + minor_rev); } #ifdef CONFIG_SPL_BUILD @@ -99,6 +106,10 @@ void spl_display_print(void) } #endif +void __weak srcomp_enable(void) +{ +} + /* * Routine: s_init * Description: Does early system init of watchdog, muxing, andclocks @@ -116,6 +127,8 @@ void spl_display_print(void) void s_init(void) { init_omap_revision(); + hw_data_init(); + #ifdef CONFIG_SPL_BUILD if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0)) force_emif_self_refresh(); @@ -123,6 +136,7 @@ void s_init(void) watchdog_init(); set_mux_conf_regs(); #ifdef CONFIG_SPL_BUILD + srcomp_enable(); setup_clocks_for_console(); gd = &gdata; @@ -235,10 +249,7 @@ int checkboard(void) */ u32 get_device_type(void) { - struct omap_sys_ctrl_regs *ctrl = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; - - return (readl(&ctrl->control_status) & + return (readl((*ctrl)->control_status) & (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT; } diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds index 9979c3085..88f40698b 100644 --- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds @@ -48,10 +48,6 @@ SECTIONS . = ALIGN(4); .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram - .u_boot_list : { - #include <u-boot.lst> - } - . = ALIGN(4); __image_copy_end = .; _end = .; diff --git a/arch/arm/cpu/armv7/omap-common/vc.c b/arch/arm/cpu/armv7/omap-common/vc.c index a045b7718..e6e5f7893 100644 --- a/arch/arm/cpu/armv7/omap-common/vc.c +++ b/arch/arm/cpu/armv7/omap-common/vc.c @@ -81,13 +81,13 @@ void omap_vc_init(u16 speed_khz) cycles_low -= 7; val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); - writel(val, &prcm->prm_vc_cfg_i2c_clk); + writel(val, (*prcm)->prm_vc_cfg_i2c_clk); val = CONFIG_OMAP_VC_I2C_HS_MCODE << PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT; /* No HS mode for now */ val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT; - writel(val, &prcm->prm_vc_cfg_i2c_mode); + writel(val, (*prcm)->prm_vc_cfg_i2c_mode); } /** @@ -113,14 +113,15 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data) reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT | reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT | reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT; - writel(reg_val, &prcm->prm_vc_val_bypass); + writel(reg_val, (*prcm)->prm_vc_val_bypass); /* Signal VC to send data */ - writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, &prcm->prm_vc_val_bypass); + writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, + (*prcm)->prm_vc_val_bypass); /* Wait on VC to complete transmission */ do { - reg_val = readl(&prcm->prm_vc_val_bypass) & + reg_val = readl((*prcm)->prm_vc_val_bypass) & PRM_VC_VAL_BYPASS_VALID_BIT; if (!reg_val) break; diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 89c587e31..c6d9a425a 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -98,11 +98,11 @@ int board_mmc_init(bd_t *bis) { switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: - omap_mmc_init(0, 0, 0); + omap_mmc_init(0, 0, 0, -1, -1); break; case BOOT_DEVICE_MMC2: case BOOT_DEVICE_MMC2_2: - omap_mmc_init(1, 0, 0); + omap_mmc_init(1, 0, 0, -1, -1); break; } return 0; @@ -110,7 +110,7 @@ int board_mmc_init(bd_t *bis) void spl_board_init(void) { -#ifdef CONFIG_SPL_NAND_SUPPORT +#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT) gpmc_init(); #endif #ifdef CONFIG_SPL_I2C_SUPPORT diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile index 83160a28f..40808d18f 100644 --- a/arch/arm/cpu/armv7/omap4/Makefile +++ b/arch/arm/cpu/armv7/omap4/Makefile @@ -27,8 +27,9 @@ LIB = $(obj)lib$(SOC).o COBJS += sdram_elpida.o COBJS += hwinit.o -COBJS += clocks.o COBJS += emif.o +COBJS += prcm-regs.o +COBJS += hw_data.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c deleted file mode 100644 index 12c58033d..000000000 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ /dev/null @@ -1,517 +0,0 @@ -/* - * - * Clock initialization for OMAP4 - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Aneesh V <aneesh@ti.com> - * - * Based on previous work by: - * Santosh Shilimkar <santosh.shilimkar@ti.com> - * Rajendra Nayak <rnayak@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <asm/omap_common.h> -#include <asm/gpio.h> -#include <asm/arch/clocks.h> -#include <asm/arch/sys_proto.h> -#include <asm/utils.h> -#include <asm/omap_gpio.h> - -#ifndef CONFIG_SPL_BUILD -/* - * printing to console doesn't work unless - * this code is executed from SPL - */ -#define printf(fmt, args...) -#define puts(s) -#endif /* !CONFIG_SPL_BUILD */ - -struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100; - -const u32 sys_clk_array[8] = { - 12000000, /* 12 MHz */ - 13000000, /* 13 MHz */ - 16800000, /* 16.8 MHz */ - 19200000, /* 19.2 MHz */ - 26000000, /* 26 MHz */ - 27000000, /* 27 MHz */ - 38400000, /* 38.4 MHz */ -}; - -/* - * The M & N values in the following tables are created using the - * following tool: - * tools/omap/clocks_get_m_n.c - * Please use this tool for creating the table for any new frequency. - */ - -/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */ -static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { - {175, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {700, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {125, 2, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {401, 10, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {350, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {700, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {638, 34, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */ -static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { - {200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* dpll locked at 1200 MHz - MPU clk at 600 MHz */ -static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { - {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { - {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ - {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ - {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ - {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ - {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ - {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ - {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ -}; - -static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { - {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */ - {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */ - {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */ - {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */ - {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */ - {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */ - {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */ -}; - -static const struct dpll_params - core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { - {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */ - {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */ - {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */ - {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */ - {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */ - {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */ - {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */ -}; - -static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { - {64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */ - {768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */ - {320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */ - {40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */ - {384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */ - {256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */ - {20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */ -}; - -static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { - {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */ - {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */ - {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */ - {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */ - {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */ - {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */ - {291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */ -}; - -/* ABE M & N values with sys_clk as source */ -static const struct dpll_params - abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { - {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */ - {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */ - {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */ - {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */ - {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */ - {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */ - {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* ABE M & N values with 32K clock as source */ -static const struct dpll_params abe_dpll_params_32k_196608khz = { - 750, 0, 1, 1, -1, -1, -1, -1 -}; - -static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { - {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */ - {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */ - {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */ - {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */ - {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -void setup_post_dividers(u32 *const base, const struct dpll_params *params) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - /* Setup post-dividers */ - if (params->m2 >= 0) - writel(params->m2, &dpll_regs->cm_div_m2_dpll); - if (params->m3 >= 0) - writel(params->m3, &dpll_regs->cm_div_m3_dpll); - if (params->m4 >= 0) - writel(params->m4, &dpll_regs->cm_div_m4_dpll); - if (params->m5 >= 0) - writel(params->m5, &dpll_regs->cm_div_m5_dpll); - if (params->m6 >= 0) - writel(params->m6, &dpll_regs->cm_div_m6_dpll); - if (params->m7 >= 0) - writel(params->m7, &dpll_regs->cm_div_m7_dpll); -} - -/* - * Lock MPU dpll - * - * Resulting MPU frequencies: - * 4430 ES1.0 : 600 MHz - * 4430 ES2.x : 792 MHz (OPP Turbo) - * 4460 : 920 MHz (OPP Turbo) - DCC disabled - */ -const struct dpll_params *get_mpu_dpll_params(void) -{ - u32 omap_rev, sysclk_ind; - - omap_rev = omap_revision(); - sysclk_ind = get_sys_clk_index(); - - if (omap_rev == OMAP4430_ES1_0) - return &mpu_dpll_params_1200mhz[sysclk_ind]; - else if (omap_rev < OMAP4460_ES1_0) - return &mpu_dpll_params_1600mhz[sysclk_ind]; - else - return &mpu_dpll_params_1400mhz[sysclk_ind]; -} - -const struct dpll_params *get_core_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - - switch (omap_revision()) { - case OMAP4430_ES1_0: - return &core_dpll_params_es1_1524mhz[sysclk_ind]; - case OMAP4430_ES2_0: - case OMAP4430_SILICON_ID_INVALID: - /* safest */ - return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind]; - default: - return &core_dpll_params_1600mhz[sysclk_ind]; - } -} - - -const struct dpll_params *get_per_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &per_dpll_params_1536mhz[sysclk_ind]; -} - -const struct dpll_params *get_iva_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &iva_dpll_params_1862mhz[sysclk_ind]; -} - -const struct dpll_params *get_usb_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &usb_dpll_params_1920mhz[sysclk_ind]; -} - -const struct dpll_params *get_abe_dpll_params(void) -{ -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - u32 sysclk_ind = get_sys_clk_index(); - return &abe_dpll_params_sysclk_196608khz[sysclk_ind]; -#else - return &abe_dpll_params_32k_196608khz; -#endif -} - -/* - * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva - * We set the maximum voltages allowed here because Smart-Reflex is not - * enabled in bootloader. Voltage initialization in the kernel will set - * these to the nominal values after enabling Smart-Reflex - */ -void scale_vcores(void) -{ - u32 volt, omap_rev; - - omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); - - omap_rev = omap_revision(); - - /* - * Scale Voltage rails: - * 1. VDD_CORE - * 3. VDD_MPU - * 3. VDD_IVA - */ - if (omap_rev < OMAP4460_ES1_0) { - /* - * OMAP4430: - * VDD_CORE = TWL6030 VCORE3 - * VDD_MPU = TWL6030 VCORE1 - * VDD_IVA = TWL6030 VCORE2 - */ - volt = 1200; - do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt); - - /* - * note on VDD_MPU: - * Setting a high voltage for Nitro mode as smart reflex is not - * enabled. We use the maximum possible value in the AVS range - * because the next higher voltage in the discrete range - * (code >= 0b111010) is way too high. - */ - volt = 1325; - do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); - volt = 1200; - do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); - - } else { - /* - * OMAP4460: - * VDD_CORE = TWL6030 VCORE1 - * VDD_MPU = TPS62361 - * VDD_IVA = TWL6030 VCORE2 - */ - volt = 1200; - do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt); - /* TPS62361 */ - volt = 1203; - do_scale_tps62361(TPS62361_VSEL0_GPIO, - TPS62361_REG_ADDR_SET1, volt); - /* VCORE 2 - supplies vdd_iva */ - volt = 1200; - do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt); - } -} - -u32 get_offset_code(u32 offset) -{ - u32 offset_code, step = 12660; /* 12.66 mV represented in uV */ - - if (omap_revision() == OMAP4430_ES1_0) - offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV; - else - offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV; - - offset_code = (offset + step - 1) / step; - - /* The code starts at 1 not 0 */ - return ++offset_code; -} - -/* - * Enable essential clock domains, modules and - * do some additional special settings needed - */ -void enable_basic_clocks(void) -{ - u32 *const clk_domains_essential[] = { - &prcm->cm_l4per_clkstctrl, - &prcm->cm_l3init_clkstctrl, - &prcm->cm_memif_clkstctrl, - &prcm->cm_l4cfg_clkstctrl, - 0 - }; - - u32 *const clk_modules_hw_auto_essential[] = { - &prcm->cm_l3_2_gpmc_clkctrl, - &prcm->cm_memif_emif_1_clkctrl, - &prcm->cm_memif_emif_2_clkctrl, - &prcm->cm_l4cfg_l4_cfg_clkctrl, - &prcm->cm_wkup_gpio1_clkctrl, - &prcm->cm_l4per_gpio2_clkctrl, - &prcm->cm_l4per_gpio3_clkctrl, - &prcm->cm_l4per_gpio4_clkctrl, - &prcm->cm_l4per_gpio5_clkctrl, - &prcm->cm_l4per_gpio6_clkctrl, - 0 - }; - - u32 *const clk_modules_explicit_en_essential[] = { - &prcm->cm_wkup_gptimer1_clkctrl, - &prcm->cm_l3init_hsmmc1_clkctrl, - &prcm->cm_l3init_hsmmc2_clkctrl, - &prcm->cm_l4per_gptimer2_clkctrl, - &prcm->cm_wkup_wdtimer2_clkctrl, - &prcm->cm_l4per_uart3_clkctrl, - 0 - }; - - /* Enable optional additional functional clock for GPIO4 */ - setbits_le32(&prcm->cm_l4per_gpio4_clkctrl, - GPIO4_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable 96 MHz clock for MMC1 & MMC2 */ - setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl, - HSMMC_CLKCTRL_CLKSEL_MASK); - setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl, - HSMMC_CLKCTRL_CLKSEL_MASK); - - /* Select 32KHz clock as the source of GPTIMER1 */ - setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl, - GPTIMER1_CLKCTRL_CLKSEL_MASK); - - /* Enable optional 48M functional clock for USB PHY */ - setbits_le32(&prcm->cm_l3init_usbphy_clkctrl, - USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); - - do_enable_clocks(clk_domains_essential, - clk_modules_hw_auto_essential, - clk_modules_explicit_en_essential, - 1); -} - -void enable_basic_uboot_clocks(void) -{ - u32 *const clk_domains_essential[] = { - 0 - }; - - u32 *const clk_modules_hw_auto_essential[] = { - &prcm->cm_l3init_hsusbotg_clkctrl, - &prcm->cm_l3init_usbphy_clkctrl, - &prcm->cm_l3init_usbphy_clkctrl, - &prcm->cm_clksel_usb_60mhz, - &prcm->cm_l3init_hsusbtll_clkctrl, - 0 - }; - - u32 *const clk_modules_explicit_en_essential[] = { - &prcm->cm_l4per_mcspi1_clkctrl, - &prcm->cm_l4per_i2c1_clkctrl, - &prcm->cm_l4per_i2c2_clkctrl, - &prcm->cm_l4per_i2c3_clkctrl, - &prcm->cm_l4per_i2c4_clkctrl, - &prcm->cm_l3init_hsusbhost_clkctrl, - 0 - }; - - do_enable_clocks(clk_domains_essential, - clk_modules_hw_auto_essential, - clk_modules_explicit_en_essential, - 1); -} - -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 *const clk_domains_non_essential[] = { - &prcm->cm_mpu_m3_clkstctrl, - &prcm->cm_ivahd_clkstctrl, - &prcm->cm_dsp_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sgx_clkstctrl, - &prcm->cm1_abe_clkstctrl, - &prcm->cm_c2c_clkstctrl, - &prcm->cm_cam_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sdma_clkstctrl, - 0 - }; - - u32 *const clk_modules_hw_auto_non_essential[] = { - &prcm->cm_l3instr_l3_3_clkctrl, - &prcm->cm_l3instr_l3_instr_clkctrl, - &prcm->cm_l3instr_intrconn_wp1_clkctrl, - &prcm->cm_l3init_hsi_clkctrl, - 0 - }; - - u32 *const clk_modules_explicit_en_non_essential[] = { - &prcm->cm1_abe_aess_clkctrl, - &prcm->cm1_abe_pdm_clkctrl, - &prcm->cm1_abe_dmic_clkctrl, - &prcm->cm1_abe_mcasp_clkctrl, - &prcm->cm1_abe_mcbsp1_clkctrl, - &prcm->cm1_abe_mcbsp2_clkctrl, - &prcm->cm1_abe_mcbsp3_clkctrl, - &prcm->cm1_abe_slimbus_clkctrl, - &prcm->cm1_abe_timer5_clkctrl, - &prcm->cm1_abe_timer6_clkctrl, - &prcm->cm1_abe_timer7_clkctrl, - &prcm->cm1_abe_timer8_clkctrl, - &prcm->cm1_abe_wdt3_clkctrl, - &prcm->cm_l4per_gptimer9_clkctrl, - &prcm->cm_l4per_gptimer10_clkctrl, - &prcm->cm_l4per_gptimer11_clkctrl, - &prcm->cm_l4per_gptimer3_clkctrl, - &prcm->cm_l4per_gptimer4_clkctrl, - &prcm->cm_l4per_hdq1w_clkctrl, - &prcm->cm_l4per_mcbsp4_clkctrl, - &prcm->cm_l4per_mcspi2_clkctrl, - &prcm->cm_l4per_mcspi3_clkctrl, - &prcm->cm_l4per_mcspi4_clkctrl, - &prcm->cm_l4per_mmcsd3_clkctrl, - &prcm->cm_l4per_mmcsd4_clkctrl, - &prcm->cm_l4per_mmcsd5_clkctrl, - &prcm->cm_l4per_uart1_clkctrl, - &prcm->cm_l4per_uart2_clkctrl, - &prcm->cm_l4per_uart4_clkctrl, - &prcm->cm_wkup_keyboard_clkctrl, - &prcm->cm_wkup_wdtimer2_clkctrl, - &prcm->cm_cam_iss_clkctrl, - &prcm->cm_cam_fdif_clkctrl, - &prcm->cm_dss_dss_clkctrl, - &prcm->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c new file mode 100644 index 000000000..7551b9861 --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -0,0 +1,491 @@ +/* + * + * HW data initialization for OMAP4 + * + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * Sricharan R <r.sricharan@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/arch/omap.h> +#include <asm/arch/sys_proto.h> +#include <asm/omap_common.h> +#include <asm/arch/clocks.h> +#include <asm/omap_gpio.h> +#include <asm/io.h> + +struct prcm_regs const **prcm = + (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; +struct dplls const **dplls_data = + (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; +struct vcores_data const **omap_vcores = + (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; +struct omap_sys_ctrl_regs const **ctrl = + (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL; + +/* + * The M & N values in the following tables are created using the + * following tool: + * tools/omap/clocks_get_m_n.c + * Please use this tool for creating the table for any new frequency. + */ + +/* + * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF + * OMAP4460 OPP_NOM frequency + */ +static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { + {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* + * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430) + * OMAP4430 OPP_TURBO frequency + */ +static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { + {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* + * dpll locked at 1200 MHz - MPU clk at 600 MHz + * OMAP4430 OPP_NOM frequency + */ +static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { + {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OMAP4460 OPP_NOM frequency */ +static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { + {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OMAP4430 ES1 OPP_NOM frequency */ +static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { + {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OMAP4430 ES2.X OPP_NOM frequency */ +static const struct dpll_params + core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { + {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { + {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */ + {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */ + {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */ + {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */ + {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { + {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with sys_clk as source */ +static const struct dpll_params + abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { + {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with 32K clock as source */ +static const struct dpll_params abe_dpll_params_32k_196608khz = { + 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 +}; + +static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { + {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +struct dplls omap4430_dplls_es1 = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_es1_1524mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap4430_dplls = { + .mpu = mpu_dpll_params_1200mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap4460_dplls = { + .mpu = mpu_dpll_params_1400mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct pmic_data twl6030_4430es1 = { + .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV, + .step = 12660, /* 10 mV represented in uV */ + /* The code starts at 1 not 0 */ + .start_code = 1, +}; + +struct pmic_data twl6030 = { + .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, + .step = 12660, /* 10 mV represented in uV */ + /* The code starts at 1 not 0 */ + .start_code = 1, +}; + +struct pmic_data tps62361 = { + .base_offset = TPS62361_BASE_VOLT_MV, + .step = 10000, /* 10 mV represented in uV */ + .start_code = 0, + .gpio = TPS62361_VSEL0_GPIO, + .gpio_en = 1 +}; + +struct vcores_data omap4430_volts_es1 = { + .mpu.value = 1325, + .mpu.addr = SMPS_REG_ADDR_VCORE1, + .mpu.pmic = &twl6030_4430es1, + + .core.value = 1200, + .core.addr = SMPS_REG_ADDR_VCORE3, + .core.pmic = &twl6030_4430es1, + + .mm.value = 1200, + .mm.addr = SMPS_REG_ADDR_VCORE2, + .mm.pmic = &twl6030_4430es1, +}; + +struct vcores_data omap4430_volts = { + .mpu.value = 1325, + .mpu.addr = SMPS_REG_ADDR_VCORE1, + .mpu.pmic = &twl6030, + + .core.value = 1200, + .core.addr = SMPS_REG_ADDR_VCORE3, + .core.pmic = &twl6030, + + .mm.value = 1200, + .mm.addr = SMPS_REG_ADDR_VCORE2, + .mm.pmic = &twl6030, +}; + +struct vcores_data omap4460_volts = { + .mpu.value = 1203, + .mpu.addr = TPS62361_REG_ADDR_SET1, + .mpu.pmic = &tps62361, + + .core.value = 1200, + .core.addr = SMPS_REG_ADDR_VCORE1, + .core.pmic = &tps62361, + + .mm.value = 1200, + .mm.addr = SMPS_REG_ADDR_VCORE2, + .mm.pmic = &tps62361, +}; + +/* + * Enable essential clock domains, modules and + * do some additional special settings needed + */ +void enable_basic_clocks(void) +{ + u32 const clk_domains_essential[] = { + (*prcm)->cm_l4per_clkstctrl, + (*prcm)->cm_l3init_clkstctrl, + (*prcm)->cm_memif_clkstctrl, + (*prcm)->cm_l4cfg_clkstctrl, + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3_gpmc_clkctrl, + (*prcm)->cm_memif_emif_1_clkctrl, + (*prcm)->cm_memif_emif_2_clkctrl, + (*prcm)->cm_l4cfg_l4_cfg_clkctrl, + (*prcm)->cm_wkup_gpio1_clkctrl, + (*prcm)->cm_l4per_gpio2_clkctrl, + (*prcm)->cm_l4per_gpio3_clkctrl, + (*prcm)->cm_l4per_gpio4_clkctrl, + (*prcm)->cm_l4per_gpio5_clkctrl, + (*prcm)->cm_l4per_gpio6_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_wkup_gptimer1_clkctrl, + (*prcm)->cm_l3init_hsmmc1_clkctrl, + (*prcm)->cm_l3init_hsmmc2_clkctrl, + (*prcm)->cm_l4per_gptimer2_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_l4per_uart3_clkctrl, + 0 + }; + + /* Enable optional additional functional clock for GPIO4 */ + setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, + GPIO4_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable 96 MHz clock for MMC1 & MMC2 */ + setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + + /* Select 32KHz clock as the source of GPTIMER1 */ + setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, + GPTIMER1_CLKCTRL_CLKSEL_MASK); + + /* Enable optional 48M functional clock for USB PHY */ + setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl, + USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +void enable_basic_uboot_clocks(void) +{ + u32 const clk_domains_essential[] = { + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3init_hsusbotg_clkctrl, + (*prcm)->cm_l3init_usbphy_clkctrl, + (*prcm)->cm_l3init_usbphy_clkctrl, + (*prcm)->cm_clksel_usb_60mhz, + (*prcm)->cm_l3init_hsusbtll_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_l4per_mcspi1_clkctrl, + (*prcm)->cm_l4per_i2c1_clkctrl, + (*prcm)->cm_l4per_i2c2_clkctrl, + (*prcm)->cm_l4per_i2c3_clkctrl, + (*prcm)->cm_l4per_i2c4_clkctrl, + (*prcm)->cm_l3init_hsusbhost_clkctrl, + 0 + }; + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +/* + * Enable non-essential clock domains, modules and + * do some additional special settings needed + */ +void enable_non_essential_clocks(void) +{ + u32 const clk_domains_non_essential[] = { + (*prcm)->cm_mpu_m3_clkstctrl, + (*prcm)->cm_ivahd_clkstctrl, + (*prcm)->cm_dsp_clkstctrl, + (*prcm)->cm_dss_clkstctrl, + (*prcm)->cm_sgx_clkstctrl, + (*prcm)->cm1_abe_clkstctrl, + (*prcm)->cm_c2c_clkstctrl, + (*prcm)->cm_cam_clkstctrl, + (*prcm)->cm_dss_clkstctrl, + (*prcm)->cm_sdma_clkstctrl, + 0 + }; + + u32 const clk_modules_hw_auto_non_essential[] = { + (*prcm)->cm_l3instr_l3_3_clkctrl, + (*prcm)->cm_l3instr_l3_instr_clkctrl, + (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, + (*prcm)->cm_l3init_hsi_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_non_essential[] = { + (*prcm)->cm1_abe_aess_clkctrl, + (*prcm)->cm1_abe_pdm_clkctrl, + (*prcm)->cm1_abe_dmic_clkctrl, + (*prcm)->cm1_abe_mcasp_clkctrl, + (*prcm)->cm1_abe_mcbsp1_clkctrl, + (*prcm)->cm1_abe_mcbsp2_clkctrl, + (*prcm)->cm1_abe_mcbsp3_clkctrl, + (*prcm)->cm1_abe_slimbus_clkctrl, + (*prcm)->cm1_abe_timer5_clkctrl, + (*prcm)->cm1_abe_timer6_clkctrl, + (*prcm)->cm1_abe_timer7_clkctrl, + (*prcm)->cm1_abe_timer8_clkctrl, + (*prcm)->cm1_abe_wdt3_clkctrl, + (*prcm)->cm_l4per_gptimer9_clkctrl, + (*prcm)->cm_l4per_gptimer10_clkctrl, + (*prcm)->cm_l4per_gptimer11_clkctrl, + (*prcm)->cm_l4per_gptimer3_clkctrl, + (*prcm)->cm_l4per_gptimer4_clkctrl, + (*prcm)->cm_l4per_hdq1w_clkctrl, + (*prcm)->cm_l4per_mcbsp4_clkctrl, + (*prcm)->cm_l4per_mcspi2_clkctrl, + (*prcm)->cm_l4per_mcspi3_clkctrl, + (*prcm)->cm_l4per_mcspi4_clkctrl, + (*prcm)->cm_l4per_mmcsd3_clkctrl, + (*prcm)->cm_l4per_mmcsd4_clkctrl, + (*prcm)->cm_l4per_mmcsd5_clkctrl, + (*prcm)->cm_l4per_uart1_clkctrl, + (*prcm)->cm_l4per_uart2_clkctrl, + (*prcm)->cm_l4per_uart4_clkctrl, + (*prcm)->cm_wkup_keyboard_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_cam_iss_clkctrl, + (*prcm)->cm_cam_fdif_clkctrl, + (*prcm)->cm_dss_dss_clkctrl, + (*prcm)->cm_sgx_sgx_clkctrl, + 0 + }; + + /* Enable optional functional clock for ISS */ + setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable all optional functional clocks of DSS */ + setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); + + do_enable_clocks(clk_domains_non_essential, + clk_modules_hw_auto_non_essential, + clk_modules_explicit_en_non_essential, + 0); + + /* Put camera module in no sleep mode */ + clrsetbits_le32((*prcm)->cm_cam_clkstctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << + MODULE_CLKCTRL_MODULEMODE_SHIFT); +} + +void hw_data_init(void) +{ + u32 omap_rev = omap_revision(); + + (*prcm) = &omap4_prcm; + + switch (omap_rev) { + + case OMAP4430_ES1_0: + *dplls_data = &omap4430_dplls_es1; + *omap_vcores = &omap4430_volts_es1; + break; + + case OMAP4430_ES2_0: + case OMAP4430_ES2_1: + case OMAP4430_ES2_2: + case OMAP4430_ES2_3: + *dplls_data = &omap4430_dplls; + *omap_vcores = &omap4430_volts; + break; + + case OMAP4460_ES1_0: + case OMAP4460_ES1_1: + *dplls_data = &omap4460_dplls; + *omap_vcores = &omap4460_volts; + break; + + default: + printf("\n INVALID OMAP REVISION "); + } + + *ctrl = &omap4_ctrl; +} diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index f4123aaff..2db517b1b 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -57,10 +57,6 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx; void do_io_settings(void) { u32 lpddr2io; - struct control_lpddr2io_regs *lpddr2io_regs = - (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE; - struct omap_sys_ctrl_regs *const ctrl = - (struct omap_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE; u32 omap4_rev = omap_revision(); @@ -72,20 +68,20 @@ void do_io_settings(void) lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN; /* EMIF1 */ - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0); - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1); + writel(lpddr2io, (*ctrl)->control_lpddr2io1_0); + writel(lpddr2io, (*ctrl)->control_lpddr2io1_1); /* No pull for GR10 as per hw team's recommendation */ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, - &lpddr2io_regs->control_lpddr2io1_2); - writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3); + (*ctrl)->control_lpddr2io1_2); + writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3); /* EMIF2 */ - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0); - writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1); + writel(lpddr2io, (*ctrl)->control_lpddr2io2_0); + writel(lpddr2io, (*ctrl)->control_lpddr2io2_1); /* No pull for GR10 as per hw team's recommendation */ writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, - &lpddr2io_regs->control_lpddr2io2_2); - writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3); + (*ctrl)->control_lpddr2io2_2); + writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3); /* * Some of these settings (TRIM values) come from eFuse and are @@ -93,16 +89,16 @@ void do_io_settings(void) * calibration of the device. Do the software over-ride only if * the device is not correctly trimmed */ - if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) { + if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) { writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - &ctrl->control_ldosram_iva_voltage_ctrl); + (*ctrl)->control_ldosram_iva_voltage_ctrl); writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - &ctrl->control_ldosram_mpu_voltage_ctrl); + (*ctrl)->control_ldosram_mpu_voltage_ctrl); writel(LDOSRAM_VOLT_CTRL_OVERRIDE, - &ctrl->control_ldosram_core_voltage_ctrl); + (*ctrl)->control_ldosram_core_voltage_ctrl); } /* @@ -110,11 +106,11 @@ void do_io_settings(void) * i. unconditionally for all 4430 * ii. only if un-trimmed for 4460 */ - if (!readl(&ctrl->control_efuse_1)) - writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1); + if (!readl((*ctrl)->control_efuse_1)) + writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1); - if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_2)) - writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2); + if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2)) + writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2); } #endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c new file mode 100644 index 000000000..7225a301b --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c @@ -0,0 +1,315 @@ +/* + * + * HW regs data for OMAP4 + * + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * Sricharan R <r.sricharan@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/omap_common.h> + +struct prcm_regs const omap4_prcm = { + /* cm1.ckgen */ + .cm_clksel_core = 0x4a004100, + .cm_clksel_abe = 0x4a004108, + .cm_dll_ctrl = 0x4a004110, + .cm_clkmode_dpll_core = 0x4a004120, + .cm_idlest_dpll_core = 0x4a004124, + .cm_autoidle_dpll_core = 0x4a004128, + .cm_clksel_dpll_core = 0x4a00412c, + .cm_div_m2_dpll_core = 0x4a004130, + .cm_div_m3_dpll_core = 0x4a004134, + .cm_div_m4_dpll_core = 0x4a004138, + .cm_div_m5_dpll_core = 0x4a00413c, + .cm_div_m6_dpll_core = 0x4a004140, + .cm_div_m7_dpll_core = 0x4a004144, + .cm_ssc_deltamstep_dpll_core = 0x4a004148, + .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, + .cm_emu_override_dpll_core = 0x4a004150, + .cm_clkmode_dpll_mpu = 0x4a004160, + .cm_idlest_dpll_mpu = 0x4a004164, + .cm_autoidle_dpll_mpu = 0x4a004168, + .cm_clksel_dpll_mpu = 0x4a00416c, + .cm_div_m2_dpll_mpu = 0x4a004170, + .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, + .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, + .cm_bypclk_dpll_mpu = 0x4a00419c, + .cm_clkmode_dpll_iva = 0x4a0041a0, + .cm_idlest_dpll_iva = 0x4a0041a4, + .cm_autoidle_dpll_iva = 0x4a0041a8, + .cm_clksel_dpll_iva = 0x4a0041ac, + .cm_div_m4_dpll_iva = 0x4a0041b8, + .cm_div_m5_dpll_iva = 0x4a0041bc, + .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, + .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, + .cm_bypclk_dpll_iva = 0x4a0041dc, + .cm_clkmode_dpll_abe = 0x4a0041e0, + .cm_idlest_dpll_abe = 0x4a0041e4, + .cm_autoidle_dpll_abe = 0x4a0041e8, + .cm_clksel_dpll_abe = 0x4a0041ec, + .cm_div_m2_dpll_abe = 0x4a0041f0, + .cm_div_m3_dpll_abe = 0x4a0041f4, + .cm_ssc_deltamstep_dpll_abe = 0x4a004208, + .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, + .cm_clkmode_dpll_ddrphy = 0x4a004220, + .cm_idlest_dpll_ddrphy = 0x4a004224, + .cm_autoidle_dpll_ddrphy = 0x4a004228, + .cm_clksel_dpll_ddrphy = 0x4a00422c, + .cm_div_m2_dpll_ddrphy = 0x4a004230, + .cm_div_m4_dpll_ddrphy = 0x4a004238, + .cm_div_m5_dpll_ddrphy = 0x4a00423c, + .cm_div_m6_dpll_ddrphy = 0x4a004240, + .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, + .cm_shadow_freq_config1 = 0x4a004260, + .cm_mpu_mpu_clkctrl = 0x4a004320, + + /* cm1.dsp */ + .cm_dsp_clkstctrl = 0x4a004400, + .cm_dsp_dsp_clkctrl = 0x4a004420, + + /* cm1.abe */ + .cm1_abe_clkstctrl = 0x4a004500, + .cm1_abe_l4abe_clkctrl = 0x4a004520, + .cm1_abe_aess_clkctrl = 0x4a004528, + .cm1_abe_pdm_clkctrl = 0x4a004530, + .cm1_abe_dmic_clkctrl = 0x4a004538, + .cm1_abe_mcasp_clkctrl = 0x4a004540, + .cm1_abe_mcbsp1_clkctrl = 0x4a004548, + .cm1_abe_mcbsp2_clkctrl = 0x4a004550, + .cm1_abe_mcbsp3_clkctrl = 0x4a004558, + .cm1_abe_slimbus_clkctrl = 0x4a004560, + .cm1_abe_timer5_clkctrl = 0x4a004568, + .cm1_abe_timer6_clkctrl = 0x4a004570, + .cm1_abe_timer7_clkctrl = 0x4a004578, + .cm1_abe_timer8_clkctrl = 0x4a004580, + .cm1_abe_wdt3_clkctrl = 0x4a004588, + + /* cm2.ckgen */ + .cm_clksel_mpu_m3_iss_root = 0x4a008100, + .cm_clksel_usb_60mhz = 0x4a008104, + .cm_scale_fclk = 0x4a008108, + .cm_core_dvfs_perf1 = 0x4a008110, + .cm_core_dvfs_perf2 = 0x4a008114, + .cm_core_dvfs_perf3 = 0x4a008118, + .cm_core_dvfs_perf4 = 0x4a00811c, + .cm_core_dvfs_current = 0x4a008124, + .cm_iva_dvfs_perf_tesla = 0x4a008128, + .cm_iva_dvfs_perf_ivahd = 0x4a00812c, + .cm_iva_dvfs_perf_abe = 0x4a008130, + .cm_iva_dvfs_current = 0x4a008138, + .cm_clkmode_dpll_per = 0x4a008140, + .cm_idlest_dpll_per = 0x4a008144, + .cm_autoidle_dpll_per = 0x4a008148, + .cm_clksel_dpll_per = 0x4a00814c, + .cm_div_m2_dpll_per = 0x4a008150, + .cm_div_m3_dpll_per = 0x4a008154, + .cm_div_m4_dpll_per = 0x4a008158, + .cm_div_m5_dpll_per = 0x4a00815c, + .cm_div_m6_dpll_per = 0x4a008160, + .cm_div_m7_dpll_per = 0x4a008164, + .cm_ssc_deltamstep_dpll_per = 0x4a008168, + .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, + .cm_emu_override_dpll_per = 0x4a008170, + .cm_clkmode_dpll_usb = 0x4a008180, + .cm_idlest_dpll_usb = 0x4a008184, + .cm_autoidle_dpll_usb = 0x4a008188, + .cm_clksel_dpll_usb = 0x4a00818c, + .cm_div_m2_dpll_usb = 0x4a008190, + .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, + .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, + .cm_clkdcoldo_dpll_usb = 0x4a0081b4, + .cm_clkmode_dpll_unipro = 0x4a0081c0, + .cm_idlest_dpll_unipro = 0x4a0081c4, + .cm_autoidle_dpll_unipro = 0x4a0081c8, + .cm_clksel_dpll_unipro = 0x4a0081cc, + .cm_div_m2_dpll_unipro = 0x4a0081d0, + .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, + .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + + /* cm2.core */ + .cm_l3_1_clkstctrl = 0x4a008700, + .cm_l3_1_dynamicdep = 0x4a008708, + .cm_l3_1_l3_1_clkctrl = 0x4a008720, + .cm_l3_2_clkstctrl = 0x4a008800, + .cm_l3_2_dynamicdep = 0x4a008808, + .cm_l3_2_l3_2_clkctrl = 0x4a008820, + .cm_l3_gpmc_clkctrl = 0x4a008828, + .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, + .cm_mpu_m3_clkstctrl = 0x4a008900, + .cm_mpu_m3_staticdep = 0x4a008904, + .cm_mpu_m3_dynamicdep = 0x4a008908, + .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, + .cm_sdma_clkstctrl = 0x4a008a00, + .cm_sdma_staticdep = 0x4a008a04, + .cm_sdma_dynamicdep = 0x4a008a08, + .cm_sdma_sdma_clkctrl = 0x4a008a20, + .cm_memif_clkstctrl = 0x4a008b00, + .cm_memif_dmm_clkctrl = 0x4a008b20, + .cm_memif_emif_fw_clkctrl = 0x4a008b28, + .cm_memif_emif_1_clkctrl = 0x4a008b30, + .cm_memif_emif_2_clkctrl = 0x4a008b38, + .cm_memif_dll_clkctrl = 0x4a008b40, + .cm_memif_emif_h1_clkctrl = 0x4a008b50, + .cm_memif_emif_h2_clkctrl = 0x4a008b58, + .cm_memif_dll_h_clkctrl = 0x4a008b60, + .cm_c2c_clkstctrl = 0x4a008c00, + .cm_c2c_staticdep = 0x4a008c04, + .cm_c2c_dynamicdep = 0x4a008c08, + .cm_c2c_sad2d_clkctrl = 0x4a008c20, + .cm_c2c_modem_icr_clkctrl = 0x4a008c28, + .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, + .cm_l4cfg_clkstctrl = 0x4a008d00, + .cm_l4cfg_dynamicdep = 0x4a008d08, + .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, + .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, + .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, + .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, + .cm_l3instr_clkstctrl = 0x4a008e00, + .cm_l3instr_l3_3_clkctrl = 0x4a008e20, + .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, + .cm_l3instr_intrconn_wp1_clkct = 0x4a008e40, + .cm_ivahd_clkstctrl = 0x4a008f00, + + /* cm2.ivahd */ + .cm_ivahd_ivahd_clkctrl = 0x4a008f20, + .cm_ivahd_sl2_clkctrl = 0x4a008f28, + + /* cm2.cam */ + .cm_cam_clkstctrl = 0x4a009000, + .cm_cam_iss_clkctrl = 0x4a009020, + .cm_cam_fdif_clkctrl = 0x4a009028, + + /* cm2.dss */ + .cm_dss_clkstctrl = 0x4a009100, + .cm_dss_dss_clkctrl = 0x4a009120, + + /* cm2.sgx */ + .cm_sgx_clkstctrl = 0x4a009200, + .cm_sgx_sgx_clkctrl = 0x4a009220, + + /* cm2.l3init */ + .cm_l3init_clkstctrl = 0x4a009300, + .cm_l3init_hsmmc1_clkctrl = 0x4a009328, + .cm_l3init_hsmmc2_clkctrl = 0x4a009330, + .cm_l3init_hsi_clkctrl = 0x4a009338, + .cm_l3init_hsusbhost_clkctrl = 0x4a009358, + .cm_l3init_hsusbotg_clkctrl = 0x4a009360, + .cm_l3init_hsusbtll_clkctrl = 0x4a009368, + .cm_l3init_p1500_clkctrl = 0x4a009378, + .cm_l3init_fsusb_clkctrl = 0x4a0093d0, + .cm_l3init_usbphy_clkctrl = 0x4a0093e0, + + /* cm2.l4per */ + .cm_l4per_clkstctrl = 0x4a009400, + .cm_l4per_dynamicdep = 0x4a009408, + .cm_l4per_adc_clkctrl = 0x4a009420, + .cm_l4per_gptimer10_clkctrl = 0x4a009428, + .cm_l4per_gptimer11_clkctrl = 0x4a009430, + .cm_l4per_gptimer2_clkctrl = 0x4a009438, + .cm_l4per_gptimer3_clkctrl = 0x4a009440, + .cm_l4per_gptimer4_clkctrl = 0x4a009448, + .cm_l4per_gptimer9_clkctrl = 0x4a009450, + .cm_l4per_elm_clkctrl = 0x4a009458, + .cm_l4per_gpio2_clkctrl = 0x4a009460, + .cm_l4per_gpio3_clkctrl = 0x4a009468, + .cm_l4per_gpio4_clkctrl = 0x4a009470, + .cm_l4per_gpio5_clkctrl = 0x4a009478, + .cm_l4per_gpio6_clkctrl = 0x4a009480, + .cm_l4per_hdq1w_clkctrl = 0x4a009488, + .cm_l4per_hecc1_clkctrl = 0x4a009490, + .cm_l4per_hecc2_clkctrl = 0x4a009498, + .cm_l4per_i2c1_clkctrl = 0x4a0094a0, + .cm_l4per_i2c2_clkctrl = 0x4a0094a8, + .cm_l4per_i2c3_clkctrl = 0x4a0094b0, + .cm_l4per_i2c4_clkctrl = 0x4a0094b8, + .cm_l4per_l4per_clkctrl = 0x4a0094c0, + .cm_l4per_mcasp2_clkctrl = 0x4a0094d0, + .cm_l4per_mcasp3_clkctrl = 0x4a0094d8, + .cm_l4per_mcbsp4_clkctrl = 0x4a0094e0, + .cm_l4per_mgate_clkctrl = 0x4a0094e8, + .cm_l4per_mcspi1_clkctrl = 0x4a0094f0, + .cm_l4per_mcspi2_clkctrl = 0x4a0094f8, + .cm_l4per_mcspi3_clkctrl = 0x4a009500, + .cm_l4per_mcspi4_clkctrl = 0x4a009508, + .cm_l4per_mmcsd3_clkctrl = 0x4a009520, + .cm_l4per_mmcsd4_clkctrl = 0x4a009528, + .cm_l4per_msprohg_clkctrl = 0x4a009530, + .cm_l4per_slimbus2_clkctrl = 0x4a009538, + .cm_l4per_uart1_clkctrl = 0x4a009540, + .cm_l4per_uart2_clkctrl = 0x4a009548, + .cm_l4per_uart3_clkctrl = 0x4a009550, + .cm_l4per_uart4_clkctrl = 0x4a009558, + .cm_l4per_mmcsd5_clkctrl = 0x4a009560, + .cm_l4per_i2c5_clkctrl = 0x4a009568, + .cm_l4sec_clkstctrl = 0x4a009580, + .cm_l4sec_staticdep = 0x4a009584, + .cm_l4sec_dynamicdep = 0x4a009588, + .cm_l4sec_aes1_clkctrl = 0x4a0095a0, + .cm_l4sec_aes2_clkctrl = 0x4a0095a8, + .cm_l4sec_des3des_clkctrl = 0x4a0095b0, + .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8, + .cm_l4sec_rng_clkctrl = 0x4a0095c0, + .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8, + .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8, + + /* l4 wkup regs */ + .cm_abe_pll_ref_clksel = 0x4a30610c, + .cm_sys_clksel = 0x4a306110, + .cm_wkup_clkstctrl = 0x4a307800, + .cm_wkup_l4wkup_clkctrl = 0x4a307820, + .cm_wkup_wdtimer1_clkctrl = 0x4a307828, + .cm_wkup_wdtimer2_clkctrl = 0x4a307830, + .cm_wkup_gpio1_clkctrl = 0x4a307838, + .cm_wkup_gptimer1_clkctrl = 0x4a307840, + .cm_wkup_gptimer12_clkctrl = 0x4a307848, + .cm_wkup_synctimer_clkctrl = 0x4a307850, + .cm_wkup_usim_clkctrl = 0x4a307858, + .cm_wkup_sarram_clkctrl = 0x4a307860, + .cm_wkup_keyboard_clkctrl = 0x4a307878, + .cm_wkup_rtc_clkctrl = 0x4a307880, + .cm_wkup_bandgap_clkctrl = 0x4a307888, + .prm_vc_val_bypass = 0x4a307ba0, + .prm_vc_cfg_channel = 0x4a307ba4, + .prm_vc_cfg_i2c_mode = 0x4a307ba8, + .prm_vc_cfg_i2c_clk = 0x4a307bac, +}; + +struct omap_sys_ctrl_regs const omap4_ctrl = { + .control_id_code = 0x4A002204, + .control_std_fuse_opp_bgap = 0x4a002260, + .control_status = 0x4a0022c4, + .control_ldosram_iva_voltage_ctrl = 0x4A002320, + .control_ldosram_mpu_voltage_ctrl = 0x4A002324, + .control_ldosram_core_voltage_ctrl = 0x4A002328, + .control_pbiaslite = 0x4A100600, + .control_lpddr2io1_0 = 0x4A100638, + .control_lpddr2io1_1 = 0x4A10063C, + .control_lpddr2io1_2 = 0x4A100640, + .control_lpddr2io1_3 = 0x4A100644, + .control_lpddr2io2_0 = 0x4A100648, + .control_lpddr2io2_1 = 0x4A10064C, + .control_lpddr2io2_2 = 0x4A100650, + .control_lpddr2io2_3 = 0x4A100654, + .control_efuse_1 = 0x4A100700, + .control_efuse_2 = 0x4A100704, +}; diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index b9128faa5..20fc55216 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -90,21 +90,28 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = { .emif_ddr_phy_ctlr_1 = 0x049ff418 }; -/* Dummy registers for OMAP44xx */ -const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; - const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0xFF020100, .dmm_lisa_map_1 = 0, .dmm_lisa_map_2 = 0, - .dmm_lisa_map_3 = 0x80540300 + .dmm_lisa_map_3 = 0x80540300, + .is_ma_present = 0x0 }; const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { .dmm_lisa_map_0 = 0xFF020100, .dmm_lisa_map_1 = 0, .dmm_lisa_map_2 = 0, - .dmm_lisa_map_3 = 0x80640300 + .dmm_lisa_map_3 = 0x80640300, + .is_ma_present = 0x0 +}; + +const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80640300, + .is_ma_present = 0x1 }; static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) @@ -129,8 +136,10 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs if (omap_rev == OMAP4430_ES1_0) *dmm_lisa_regs = &lisa_map_2G_x_1_x_2; - else + else if (omap_rev < OMAP4460_ES1_0) *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; + else + *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2; } void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) @@ -284,3 +293,16 @@ void emif_get_device_timings(u32 emif_nr, __attribute__((weak, alias("emif_get_device_timings_sdp"))); #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ + +const struct lpddr2_mr_regs mr_regs = { + .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3, + .mr2 = 0x4, + .mr3 = -1, + .mr10 = MR10_ZQ_ZQINIT, + .mr16 = MR16_REF_FULL_ARRAY +}; + +void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) +{ + *regs = &mr_regs; +} diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile index 9b261c4df..ce00e2c3c 100644 --- a/arch/arm/cpu/armv7/omap5/Makefile +++ b/arch/arm/cpu/armv7/omap5/Makefile @@ -26,9 +26,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o COBJS += hwinit.o -COBJS += clocks.o COBJS += emif.o COBJS += sdram.o +COBJS += prcm-regs.o +COBJS += hw_data.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c deleted file mode 100644 index eecfbade3..000000000 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ /dev/null @@ -1,494 +0,0 @@ -/* - * - * Clock initialization for OMAP5 - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Aneesh V <aneesh@ti.com> - * Sricharan R <r.sricharan@ti.com> - * - * Based on previous work by: - * Santosh Shilimkar <santosh.shilimkar@ti.com> - * Rajendra Nayak <rnayak@ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <asm/omap_common.h> -#include <asm/arch/clocks.h> -#include <asm/arch/sys_proto.h> -#include <asm/utils.h> -#include <asm/omap_gpio.h> - -#ifndef CONFIG_SPL_BUILD -/* - * printing to console doesn't work unless - * this code is executed from SPL - */ -#define printf(fmt, args...) -#define puts(s) -#endif - -struct omap5_prcm_regs *const prcm = (struct omap5_prcm_regs *)0x4A004100; - -const u32 sys_clk_array[8] = { - 12000000, /* 12 MHz */ - 0, /* NA */ - 16800000, /* 16.8 MHz */ - 19200000, /* 19.2 MHz */ - 26000000, /* 26 MHz */ - 0, /* NA */ - 38400000, /* 38.4 MHz */ -}; - -static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { - {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = { - {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = { - {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { - {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = { - {200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = { - {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params - core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { - {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */ - {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */ - {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */ -}; - -static const struct dpll_params - core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { - {266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */ - {665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */ - {532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */ -}; - -static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { - {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */ - {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */ - {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */ -}; - -static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { - {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */ - {1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */ - {1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* ABE M & N values with sys_clk as source */ -static const struct dpll_params - abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { - {49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -/* ABE M & N values with 32K clock as source */ -static const struct dpll_params abe_dpll_params_32k_196608khz = { - 750, 0, 1, 1, -1, -1, -1, -1, -1, -1 -}; - -static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { - {400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ -}; - -void setup_post_dividers(u32 *const base, const struct dpll_params *params) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - /* Setup post-dividers */ - if (params->m2 >= 0) - writel(params->m2, &dpll_regs->cm_div_m2_dpll); - if (params->m3 >= 0) - writel(params->m3, &dpll_regs->cm_div_m3_dpll); - if (params->h11 >= 0) - writel(params->h11, &dpll_regs->cm_div_h11_dpll); - if (params->h12 >= 0) - writel(params->h12, &dpll_regs->cm_div_h12_dpll); - if (params->h13 >= 0) - writel(params->h13, &dpll_regs->cm_div_h13_dpll); - if (params->h14 >= 0) - writel(params->h14, &dpll_regs->cm_div_h14_dpll); - if (params->h22 >= 0) - writel(params->h22, &dpll_regs->cm_div_h22_dpll); - if (params->h23 >= 0) - writel(params->h23, &dpll_regs->cm_div_h23_dpll); -} - -const struct dpll_params *get_mpu_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &mpu_dpll_params_800mhz[sysclk_ind]; -} - -const struct dpll_params *get_core_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - - /* Configuring the DDR to be at 532mhz */ - return &core_dpll_params_2128mhz_ddr532[sysclk_ind]; -} - -const struct dpll_params *get_per_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &per_dpll_params_768mhz[sysclk_ind]; -} - -const struct dpll_params *get_iva_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &iva_dpll_params_2330mhz[sysclk_ind]; -} - -const struct dpll_params *get_usb_dpll_params(void) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &usb_dpll_params_1920mhz[sysclk_ind]; -} - -const struct dpll_params *get_abe_dpll_params(void) -{ -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - u32 sysclk_ind = get_sys_clk_index(); - return &abe_dpll_params_sysclk_196608khz[sysclk_ind]; -#else - return &abe_dpll_params_32k_196608khz; -#endif -} - -/* - * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva - * We set the maximum voltages allowed here because Smart-Reflex is not - * enabled in bootloader. Voltage initialization in the kernel will set - * these to the nominal values after enabling Smart-Reflex - */ -void scale_vcores(void) -{ - u32 volt_core, volt_mpu, volt_mm; - - omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); - - /* Palmas settings */ - if (omap_revision() != OMAP5432_ES1_0) { - volt_core = VDD_CORE; - volt_mpu = VDD_MPU; - volt_mm = VDD_MM; - } else { - volt_core = VDD_CORE_5432; - volt_mpu = VDD_MPU_5432; - volt_mm = VDD_MM_5432; - } - - do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core); - do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu); - do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm); - - if (omap_revision() == OMAP5432_ES1_0) { - /* Configure LDO SRAM "magic" bits */ - writel(2, &prcm->prm_sldo_core_setup); - writel(2, &prcm->prm_sldo_mpu_setup); - writel(2, &prcm->prm_sldo_mm_setup); - } -} - -u32 get_offset_code(u32 volt_offset) -{ - u32 offset_code, step = 10000; /* 10 mV represented in uV */ - - volt_offset -= PALMAS_SMPS_BASE_VOLT_UV; - - offset_code = (volt_offset + step - 1) / step; - - /* - * Offset codes 1-6 all give the base voltage in Palmas - * Offset code 0 switches OFF the SMPS - */ - return offset_code + 6; -} - -/* - * Enable essential clock domains, modules and - * do some additional special settings needed - */ -void enable_basic_clocks(void) -{ - u32 *const clk_domains_essential[] = { - &prcm->cm_l4per_clkstctrl, - &prcm->cm_l3init_clkstctrl, - &prcm->cm_memif_clkstctrl, - &prcm->cm_l4cfg_clkstctrl, - 0 - }; - - u32 *const clk_modules_hw_auto_essential[] = { - &prcm->cm_l3_2_gpmc_clkctrl, - &prcm->cm_memif_emif_1_clkctrl, - &prcm->cm_memif_emif_2_clkctrl, - &prcm->cm_l4cfg_l4_cfg_clkctrl, - &prcm->cm_wkup_gpio1_clkctrl, - &prcm->cm_l4per_gpio2_clkctrl, - &prcm->cm_l4per_gpio3_clkctrl, - &prcm->cm_l4per_gpio4_clkctrl, - &prcm->cm_l4per_gpio5_clkctrl, - &prcm->cm_l4per_gpio6_clkctrl, - 0 - }; - - u32 *const clk_modules_explicit_en_essential[] = { - &prcm->cm_wkup_gptimer1_clkctrl, - &prcm->cm_l3init_hsmmc1_clkctrl, - &prcm->cm_l3init_hsmmc2_clkctrl, - &prcm->cm_l4per_gptimer2_clkctrl, - &prcm->cm_wkup_wdtimer2_clkctrl, - &prcm->cm_l4per_uart3_clkctrl, - &prcm->cm_l4per_i2c1_clkctrl, - 0 - }; - - /* Enable optional additional functional clock for GPIO4 */ - setbits_le32(&prcm->cm_l4per_gpio4_clkctrl, - GPIO4_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable 96 MHz clock for MMC1 & MMC2 */ - setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl, - HSMMC_CLKCTRL_CLKSEL_MASK); - setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl, - HSMMC_CLKCTRL_CLKSEL_MASK); - - /* Set the correct clock dividers for mmc */ - setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl, - HSMMC_CLKCTRL_CLKSEL_DIV_MASK); - setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl, - HSMMC_CLKCTRL_CLKSEL_DIV_MASK); - - /* Select 32KHz clock as the source of GPTIMER1 */ - setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl, - GPTIMER1_CLKCTRL_CLKSEL_MASK); - - do_enable_clocks(clk_domains_essential, - clk_modules_hw_auto_essential, - clk_modules_explicit_en_essential, - 1); - - /* Select 384Mhz for GPU as its the POR for ES1.0 */ - setbits_le32(&prcm->cm_sgx_sgx_clkctrl, - CLKSEL_GPU_HYD_GCLK_MASK); - setbits_le32(&prcm->cm_sgx_sgx_clkctrl, - CLKSEL_GPU_CORE_GCLK_MASK); - - /* Enable SCRM OPT clocks for PER and CORE dpll */ - setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl, - OPTFCLKEN_SCRM_PER_MASK); - setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl, - OPTFCLKEN_SCRM_CORE_MASK); -} - -void enable_basic_uboot_clocks(void) -{ - u32 *const clk_domains_essential[] = { - 0 - }; - - u32 *const clk_modules_hw_auto_essential[] = { - 0 - }; - - u32 *const clk_modules_explicit_en_essential[] = { - &prcm->cm_l4per_mcspi1_clkctrl, - &prcm->cm_l4per_i2c2_clkctrl, - &prcm->cm_l4per_i2c3_clkctrl, - &prcm->cm_l4per_i2c4_clkctrl, - &prcm->cm_l3init_hsusbtll_clkctrl, - &prcm->cm_l3init_hsusbhost_clkctrl, - &prcm->cm_l3init_fsusb_clkctrl, - 0 - }; - - do_enable_clocks(clk_domains_essential, - clk_modules_hw_auto_essential, - clk_modules_explicit_en_essential, - 1); -} - -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 *const clk_domains_non_essential[] = { - &prcm->cm_mpu_m3_clkstctrl, - &prcm->cm_ivahd_clkstctrl, - &prcm->cm_dsp_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sgx_clkstctrl, - &prcm->cm1_abe_clkstctrl, - &prcm->cm_c2c_clkstctrl, - &prcm->cm_cam_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sdma_clkstctrl, - 0 - }; - - u32 *const clk_modules_hw_auto_non_essential[] = { - &prcm->cm_mpu_m3_mpu_m3_clkctrl, - &prcm->cm_ivahd_ivahd_clkctrl, - &prcm->cm_ivahd_sl2_clkctrl, - &prcm->cm_dsp_dsp_clkctrl, - &prcm->cm_l3instr_l3_3_clkctrl, - &prcm->cm_l3instr_l3_instr_clkctrl, - &prcm->cm_l3instr_intrconn_wp1_clkctrl, - &prcm->cm_l3init_hsi_clkctrl, - &prcm->cm_l4per_hdq1w_clkctrl, - 0 - }; - - u32 *const clk_modules_explicit_en_non_essential[] = { - &prcm->cm1_abe_aess_clkctrl, - &prcm->cm1_abe_pdm_clkctrl, - &prcm->cm1_abe_dmic_clkctrl, - &prcm->cm1_abe_mcasp_clkctrl, - &prcm->cm1_abe_mcbsp1_clkctrl, - &prcm->cm1_abe_mcbsp2_clkctrl, - &prcm->cm1_abe_mcbsp3_clkctrl, - &prcm->cm1_abe_slimbus_clkctrl, - &prcm->cm1_abe_timer5_clkctrl, - &prcm->cm1_abe_timer6_clkctrl, - &prcm->cm1_abe_timer7_clkctrl, - &prcm->cm1_abe_timer8_clkctrl, - &prcm->cm1_abe_wdt3_clkctrl, - &prcm->cm_l4per_gptimer9_clkctrl, - &prcm->cm_l4per_gptimer10_clkctrl, - &prcm->cm_l4per_gptimer11_clkctrl, - &prcm->cm_l4per_gptimer3_clkctrl, - &prcm->cm_l4per_gptimer4_clkctrl, - &prcm->cm_l4per_mcspi2_clkctrl, - &prcm->cm_l4per_mcspi3_clkctrl, - &prcm->cm_l4per_mcspi4_clkctrl, - &prcm->cm_l4per_mmcsd3_clkctrl, - &prcm->cm_l4per_mmcsd4_clkctrl, - &prcm->cm_l4per_mmcsd5_clkctrl, - &prcm->cm_l4per_uart1_clkctrl, - &prcm->cm_l4per_uart2_clkctrl, - &prcm->cm_l4per_uart4_clkctrl, - &prcm->cm_wkup_keyboard_clkctrl, - &prcm->cm_wkup_wdtimer2_clkctrl, - &prcm->cm_cam_iss_clkctrl, - &prcm->cm_cam_fdif_clkctrl, - &prcm->cm_dss_dss_clkctrl, - &prcm->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c new file mode 100644 index 000000000..ced274e4d --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -0,0 +1,596 @@ +/* + * + * HW data initialization for OMAP5 + * + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * Sricharan R <r.sricharan@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/arch/omap.h> +#include <asm/arch/sys_proto.h> +#include <asm/omap_common.h> +#include <asm/arch/clocks.h> +#include <asm/omap_gpio.h> +#include <asm/io.h> +#include <asm/emif.h> + +struct prcm_regs const **prcm = + (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; +struct dplls const **dplls_data = + (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; +struct vcores_data const **omap_vcores = + (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; +struct omap_sys_ctrl_regs const **ctrl = + (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL; + +/* OPP HIGH FREQUENCY for ES2.0 */ +static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { + {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */ +static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = { + {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OPP NOM FREQUENCY for ES1.0 */ +static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { + {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OPP LOW FREQUENCY for ES1.0 */ +static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = { + {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* OPP LOW FREQUENCY for ES2.0 */ +static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { + {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { + {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ + {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { + {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */ + {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */ + {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = { + {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */ + {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */ + {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = { + {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */ + {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */ + {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */ + {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { + {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */ + {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */ + {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = { + {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */ + {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */ + {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { + {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { + {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { + {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ + {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */ +}; + +static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { + {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with sys_clk as source */ +static const struct dpll_params + abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { + {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +/* ABE M & N values with 32K clock as source */ +static const struct dpll_params abe_dpll_params_32k_196608khz = { + 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 +}; + +static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { + {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ + {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ +}; + +static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = { + {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ + {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ +}; + +struct dplls omap5_dplls_es1 = { + .mpu = mpu_dpll_params_800mhz, + .core = core_dpll_params_2128mhz_ddr532, + .per = per_dpll_params_768mhz, + .iva = iva_dpll_params_2330mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls omap5_dplls_es2 = { + .mpu = mpu_dpll_params_1100mhz, + .core = core_dpll_params_2128mhz_ddr532_es2, + .per = per_dpll_params_768mhz_es2, + .iva = iva_dpll_params_2330mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + +struct dplls dra7xx_dplls = { + .mpu = mpu_dpll_params_1ghz, + .core = core_dpll_params_2128mhz_ddr532_dra7xx, + .per = per_dpll_params_768mhz_dra7xx, + .usb = usb_dpll_params_1920mhz, + .ddr = ddr_dpll_params_1066mhz, +}; + +struct pmic_data palmas = { + .base_offset = PALMAS_SMPS_BASE_VOLT_UV, + .step = 10000, /* 10 mV represented in uV */ + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + .start_code = 6, +}; + +struct vcores_data omap5430_volts = { + .mpu.value = VDD_MPU, + .mpu.addr = SMPS_REG_ADDR_12_MPU, + .mpu.pmic = &palmas, + + .core.value = VDD_CORE, + .core.addr = SMPS_REG_ADDR_8_CORE, + .core.pmic = &palmas, + + .mm.value = VDD_MM, + .mm.addr = SMPS_REG_ADDR_45_IVA, + .mm.pmic = &palmas, +}; + +struct vcores_data omap5430_volts_es2 = { + .mpu.value = VDD_MPU_ES2, + .mpu.addr = SMPS_REG_ADDR_12_MPU, + .mpu.pmic = &palmas, + + .core.value = VDD_CORE_ES2, + .core.addr = SMPS_REG_ADDR_8_CORE, + .core.pmic = &palmas, + + .mm.value = VDD_MM_ES2, + .mm.addr = SMPS_REG_ADDR_45_IVA, + .mm.pmic = &palmas, +}; + +/* + * Enable essential clock domains, modules and + * do some additional special settings needed + */ +void enable_basic_clocks(void) +{ + u32 const clk_domains_essential[] = { + (*prcm)->cm_l4per_clkstctrl, + (*prcm)->cm_l3init_clkstctrl, + (*prcm)->cm_memif_clkstctrl, + (*prcm)->cm_l4cfg_clkstctrl, + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + (*prcm)->cm_l3_gpmc_clkctrl, + (*prcm)->cm_memif_emif_1_clkctrl, + (*prcm)->cm_memif_emif_2_clkctrl, + (*prcm)->cm_l4cfg_l4_cfg_clkctrl, + (*prcm)->cm_wkup_gpio1_clkctrl, + (*prcm)->cm_l4per_gpio2_clkctrl, + (*prcm)->cm_l4per_gpio3_clkctrl, + (*prcm)->cm_l4per_gpio4_clkctrl, + (*prcm)->cm_l4per_gpio5_clkctrl, + (*prcm)->cm_l4per_gpio6_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_wkup_gptimer1_clkctrl, + (*prcm)->cm_l3init_hsmmc1_clkctrl, + (*prcm)->cm_l3init_hsmmc2_clkctrl, + (*prcm)->cm_l4per_gptimer2_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_l4per_uart3_clkctrl, + (*prcm)->cm_l4per_i2c1_clkctrl, + 0 + }; + + /* Enable optional additional functional clock for GPIO4 */ + setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, + GPIO4_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable 96 MHz clock for MMC1 & MMC2 */ + setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_MASK); + + /* Set the correct clock dividers for mmc */ + setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + + /* Select 32KHz clock as the source of GPTIMER1 */ + setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, + GPTIMER1_CLKCTRL_CLKSEL_MASK); + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); + + /* Select 384Mhz for GPU as its the POR for ES1.0 */ + setbits_le32((*prcm)->cm_sgx_sgx_clkctrl, + CLKSEL_GPU_HYD_GCLK_MASK); + setbits_le32((*prcm)->cm_sgx_sgx_clkctrl, + CLKSEL_GPU_CORE_GCLK_MASK); + + /* Enable SCRM OPT clocks for PER and CORE dpll */ + setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, + OPTFCLKEN_SCRM_PER_MASK); + setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, + OPTFCLKEN_SCRM_CORE_MASK); +} + +void enable_basic_uboot_clocks(void) +{ + u32 const clk_domains_essential[] = { + 0 + }; + + u32 const clk_modules_hw_auto_essential[] = { + 0 + }; + + u32 const clk_modules_explicit_en_essential[] = { + (*prcm)->cm_l4per_mcspi1_clkctrl, + (*prcm)->cm_l4per_i2c2_clkctrl, + (*prcm)->cm_l4per_i2c3_clkctrl, + (*prcm)->cm_l4per_i2c4_clkctrl, + (*prcm)->cm_l3init_hsusbtll_clkctrl, + (*prcm)->cm_l3init_hsusbhost_clkctrl, + (*prcm)->cm_l3init_fsusb_clkctrl, + 0 + }; + + do_enable_clocks(clk_domains_essential, + clk_modules_hw_auto_essential, + clk_modules_explicit_en_essential, + 1); +} + +/* + * Enable non-essential clock domains, modules and + * do some additional special settings needed + */ +void enable_non_essential_clocks(void) +{ + u32 const clk_domains_non_essential[] = { + (*prcm)->cm_mpu_m3_clkstctrl, + (*prcm)->cm_ivahd_clkstctrl, + (*prcm)->cm_dsp_clkstctrl, + (*prcm)->cm_dss_clkstctrl, + (*prcm)->cm_sgx_clkstctrl, + (*prcm)->cm1_abe_clkstctrl, + (*prcm)->cm_c2c_clkstctrl, + (*prcm)->cm_cam_clkstctrl, + (*prcm)->cm_dss_clkstctrl, + (*prcm)->cm_sdma_clkstctrl, + 0 + }; + + u32 const clk_modules_hw_auto_non_essential[] = { + (*prcm)->cm_mpu_m3_mpu_m3_clkctrl, + (*prcm)->cm_ivahd_ivahd_clkctrl, + (*prcm)->cm_ivahd_sl2_clkctrl, + (*prcm)->cm_dsp_dsp_clkctrl, + (*prcm)->cm_l3instr_l3_3_clkctrl, + (*prcm)->cm_l3instr_l3_instr_clkctrl, + (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, + (*prcm)->cm_l3init_hsi_clkctrl, + (*prcm)->cm_l4per_hdq1w_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_non_essential[] = { + (*prcm)->cm1_abe_aess_clkctrl, + (*prcm)->cm1_abe_pdm_clkctrl, + (*prcm)->cm1_abe_dmic_clkctrl, + (*prcm)->cm1_abe_mcasp_clkctrl, + (*prcm)->cm1_abe_mcbsp1_clkctrl, + (*prcm)->cm1_abe_mcbsp2_clkctrl, + (*prcm)->cm1_abe_mcbsp3_clkctrl, + (*prcm)->cm1_abe_slimbus_clkctrl, + (*prcm)->cm1_abe_timer5_clkctrl, + (*prcm)->cm1_abe_timer6_clkctrl, + (*prcm)->cm1_abe_timer7_clkctrl, + (*prcm)->cm1_abe_timer8_clkctrl, + (*prcm)->cm1_abe_wdt3_clkctrl, + (*prcm)->cm_l4per_gptimer9_clkctrl, + (*prcm)->cm_l4per_gptimer10_clkctrl, + (*prcm)->cm_l4per_gptimer11_clkctrl, + (*prcm)->cm_l4per_gptimer3_clkctrl, + (*prcm)->cm_l4per_gptimer4_clkctrl, + (*prcm)->cm_l4per_mcspi2_clkctrl, + (*prcm)->cm_l4per_mcspi3_clkctrl, + (*prcm)->cm_l4per_mcspi4_clkctrl, + (*prcm)->cm_l4per_mmcsd3_clkctrl, + (*prcm)->cm_l4per_mmcsd4_clkctrl, + (*prcm)->cm_l4per_mmcsd5_clkctrl, + (*prcm)->cm_l4per_uart1_clkctrl, + (*prcm)->cm_l4per_uart2_clkctrl, + (*prcm)->cm_l4per_uart4_clkctrl, + (*prcm)->cm_wkup_keyboard_clkctrl, + (*prcm)->cm_wkup_wdtimer2_clkctrl, + (*prcm)->cm_cam_iss_clkctrl, + (*prcm)->cm_cam_fdif_clkctrl, + (*prcm)->cm_dss_dss_clkctrl, + (*prcm)->cm_sgx_sgx_clkctrl, + 0 + }; + + /* Enable optional functional clock for ISS */ + setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); + + /* Enable all optional functional clocks of DSS */ + setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); + + do_enable_clocks(clk_domains_non_essential, + clk_modules_hw_auto_non_essential, + clk_modules_explicit_en_non_essential, + 0); + + /* Put camera module in no sleep mode */ + clrsetbits_le32((*prcm)->cm_cam_clkstctrl, + MODULE_CLKCTRL_MODULEMODE_MASK, + CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << + MODULE_CLKCTRL_MODULEMODE_SHIFT); +} + +const struct ctrl_ioregs ioregs_omap5430 = { + .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, + .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, + .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, + .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, +}; + +const struct ctrl_ioregs ioregs_omap5432_es1 = { + .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, + .ctrl_lpddr2ch = 0x0, + .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, + .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE, + .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE, + .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE, + .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, +}; + +const struct ctrl_ioregs ioregs_omap5432_es2 = { + .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, + .ctrl_lpddr2ch = 0x0, + .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, + .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2, + .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, + .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, + .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, +}; + +void hw_data_init(void) +{ + u32 omap_rev = omap_revision(); + + switch (omap_rev) { + + case OMAP5430_ES1_0: + case OMAP5432_ES1_0: + *prcm = &omap5_es1_prcm; + *dplls_data = &omap5_dplls_es1; + *omap_vcores = &omap5430_volts; + *ctrl = &omap5_ctrl; + break; + + case OMAP5430_ES2_0: + case OMAP5432_ES2_0: + *prcm = &omap5_es2_prcm; + *dplls_data = &omap5_dplls_es2; + *omap_vcores = &omap5430_volts_es2; + *ctrl = &omap5_ctrl; + break; + + case DRA752_ES1_0: + *prcm = &dra7xx_prcm; + *dplls_data = &dra7xx_dplls; + *omap_vcores = &omap5430_volts_es2; + *ctrl = &dra7xx_ctrl; + break; + + default: + printf("\n INVALID OMAP REVISION "); + } +} + +void get_ioregs(const struct ctrl_ioregs **regs) +{ + u32 omap_rev = omap_revision(); + + switch (omap_rev) { + case OMAP5430_ES1_0: + case OMAP5430_ES2_0: + *regs = &ioregs_omap5430; + break; + case OMAP5432_ES1_0: + *regs = &ioregs_omap5432_es1; + break; + case OMAP5432_ES2_0: + case DRA752_ES1_0: + *regs = &ioregs_omap5432_es2; + break; + + default: + printf("\n INVALID OMAP REVISION "); + } +} diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index d0c3ff702..2f4b24752 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -32,6 +32,7 @@ #include <asm/armv7.h> #include <asm/arch/cpu.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/clocks.h> #include <asm/sizes.h> #include <asm/utils.h> #include <asm/arch/gpio.h> @@ -56,76 +57,58 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx; /* LPDDR2 specific IO settings */ static void io_settings_lpddr2(void) { - struct omap_sys_ctrl_regs *ioregs_base = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; + const struct ctrl_ioregs *ioregs; - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch1_0)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch1_1)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch2_0)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch2_1)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, - &(ioregs_base->control_lpddr2ch1_0)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, - &(ioregs_base->control_lpddr2ch1_1)); - writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, - &(ioregs_base->control_ddrio_0)); - writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, - &(ioregs_base->control_ddrio_1)); - writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, - &(ioregs_base->control_ddrio_2)); + get_ioregs(&ioregs); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); + writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); + writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); + writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); + writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); + writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); } /* DDR3 specific IO settings */ static void io_settings_ddr3(void) { u32 io_settings = 0; - struct omap_sys_ctrl_regs *ioregs_base = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; + const struct ctrl_ioregs *ioregs; - writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddr3ch1_0)); - writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddrch1_0)); - writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddrch1_1)); + get_ioregs(&ioregs); + writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); - writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddr3ch2_0)); - writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddrch2_0)); - writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, - &(ioregs_base->control_ddrch2_1)); + writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); + writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); - writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE, - &(ioregs_base->control_ddrio_0)); - writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE, - &(ioregs_base->control_ddrio_1)); - writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE, - &(ioregs_base->control_ddrio_2)); + writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); + writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); + writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); /* omap5432 does not use lpddr2 */ - writel(0x0, &(ioregs_base->control_lpddr2ch1_0)); - writel(0x0, &(ioregs_base->control_lpddr2ch1_1)); + writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); + writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); - writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, - &(ioregs_base->control_emif1_sdram_config_ext)); - writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, - &(ioregs_base->control_emif2_sdram_config_ext)); + writel(ioregs->ctrl_emif_sdram_config_ext, + (*ctrl)->control_emif1_sdram_config_ext); + writel(ioregs->ctrl_emif_sdram_config_ext, + (*ctrl)->control_emif2_sdram_config_ext); /* Disable DLL select */ - io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config)) + io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) & 0xFFEFFFFF); writel(io_settings, - &(ioregs_base->control_port_emif1_sdram_config)); + (*ctrl)->control_port_emif1_sdram_config); - io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config)) + io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) & 0xFFEFFFFF); writel(io_settings, - &(ioregs_base->control_port_emif2_sdram_config)); + (*ctrl)->control_port_emif2_sdram_config); } /* @@ -134,88 +117,198 @@ static void io_settings_ddr3(void) void do_io_settings(void) { u32 io_settings = 0, mask = 0; - struct omap_sys_ctrl_regs *ioregs_base = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; /* Impedance settings EMMC, C2C 1,2, hsi2 */ mask = (ds_mask << 2) | (ds_mask << 8) | (ds_mask << 16) | (ds_mask << 18); - io_settings = readl(&(ioregs_base->control_smart1io_padconf_0)) & + io_settings = readl((*ctrl)->control_smart1io_padconf_0) & (~mask); io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) | (ds_45_ohm << 18) | (ds_60_ohm << 2); - writel(io_settings, &(ioregs_base->control_smart1io_padconf_0)); + writel(io_settings, (*ctrl)->control_smart1io_padconf_0); /* Impedance settings Mcspi2 */ mask = (ds_mask << 30); - io_settings = readl(&(ioregs_base->control_smart1io_padconf_1)) & + io_settings = readl((*ctrl)->control_smart1io_padconf_1) & (~mask); io_settings |= (ds_60_ohm << 30); - writel(io_settings, &(ioregs_base->control_smart1io_padconf_1)); + writel(io_settings, (*ctrl)->control_smart1io_padconf_1); /* Impedance settings C2C 3,4 */ mask = (ds_mask << 14) | (ds_mask << 16); - io_settings = readl(&(ioregs_base->control_smart1io_padconf_2)) & + io_settings = readl((*ctrl)->control_smart1io_padconf_2) & (~mask); io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16); - writel(io_settings, &(ioregs_base->control_smart1io_padconf_2)); + writel(io_settings, (*ctrl)->control_smart1io_padconf_2); /* Slew rate settings EMMC, C2C 1,2 */ mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18); - io_settings = readl(&(ioregs_base->control_smart2io_padconf_0)) & + io_settings = readl((*ctrl)->control_smart2io_padconf_0) & (~mask); io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18); - writel(io_settings, &(ioregs_base->control_smart2io_padconf_0)); + writel(io_settings, (*ctrl)->control_smart2io_padconf_0); /* Slew rate settings hsi2, Mcspi2 */ mask = (sc_mask << 24) | (sc_mask << 28); - io_settings = readl(&(ioregs_base->control_smart2io_padconf_1)) & + io_settings = readl((*ctrl)->control_smart2io_padconf_1) & (~mask); io_settings |= (sc_fast << 28) | (sc_fast << 24); - writel(io_settings, &(ioregs_base->control_smart2io_padconf_1)); + writel(io_settings, (*ctrl)->control_smart2io_padconf_1); /* Slew rate settings C2C 3,4 */ mask = (sc_mask << 16) | (sc_mask << 18); - io_settings = readl(&(ioregs_base->control_smart2io_padconf_2)) & + io_settings = readl((*ctrl)->control_smart2io_padconf_2) & (~mask); io_settings |= (sc_na << 16) | (sc_na << 18); - writel(io_settings, &(ioregs_base->control_smart2io_padconf_2)); + writel(io_settings, (*ctrl)->control_smart2io_padconf_2); /* impedance and slew rate settings for usb */ mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) | (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14); - io_settings = readl(&(ioregs_base->control_smart3io_padconf_1)) & + io_settings = readl((*ctrl)->control_smart3io_padconf_1) & (~mask); io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) | (ds_60_ohm << 23) | (sc_fast << 20) | (sc_fast << 17) | (sc_fast << 14); - writel(io_settings, &(ioregs_base->control_smart3io_padconf_1)); + writel(io_settings, (*ctrl)->control_smart3io_padconf_1); - if (omap_revision() <= OMAP5430_ES1_0) + if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) io_settings_lpddr2(); else io_settings_ddr3(); /* Efuse settings */ - writel(EFUSE_1, &(ioregs_base->control_efuse_1)); - writel(EFUSE_2, &(ioregs_base->control_efuse_2)); - writel(EFUSE_3, &(ioregs_base->control_efuse_3)); - writel(EFUSE_4, &(ioregs_base->control_efuse_4)); + writel(EFUSE_1, (*ctrl)->control_efuse_1); + writel(EFUSE_2, (*ctrl)->control_efuse_2); + writel(EFUSE_3, (*ctrl)->control_efuse_3); + writel(EFUSE_4, (*ctrl)->control_efuse_4); +} + +static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = { + {0x45, 0x1}, /* 12 MHz */ + {-1, -1}, /* 13 MHz */ + {0x63, 0x2}, /* 16.8 MHz */ + {0x57, 0x2}, /* 19.2 MHz */ + {0x20, 0x1}, /* 26 MHz */ + {-1, -1}, /* 27 MHz */ + {0x41, 0x3} /* 38.4 MHz */ +}; + +void srcomp_enable(void) +{ + u32 srcomp_value, mul_factor, div_factor, clk_val, i; + u32 sysclk_ind = get_sys_clk_index(); + u32 omap_rev = omap_revision(); + + mul_factor = srcomp_parameters[sysclk_ind].multiply_factor; + div_factor = srcomp_parameters[sysclk_ind].divide_factor; + + for (i = 0; i < 4; i++) { + srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= + ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK); + srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | + (div_factor << DIVIDE_FACTOR_XS_SHIFT); + writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4); + } + + if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) { + clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); + clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; + writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); + + for (i = 0; i < 4; i++) { + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~PWRDWN_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + + while (((readl((*ctrl)->control_srcomp_north_side + i*4) + & SRCODE_READ_XS_MASK) >> + SRCODE_READ_XS_SHIFT) == 0) + ; + + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~OVERRIDE_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + } + } else { + srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK | + DIVIDE_FACTOR_XS_MASK); + srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | + (div_factor << DIVIDE_FACTOR_XS_SHIFT); + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + + for (i = 0; i < 4; i++) { + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~OVERRIDE_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + } + + srcomp_value = + readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + + srcomp_value = + readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value &= ~OVERRIDE_XS_MASK; + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + + clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); + clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; + writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); + + clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl); + clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; + writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl); + + for (i = 0; i < 4; i++) { + while (((readl((*ctrl)->control_srcomp_north_side + i*4) + & SRCODE_READ_XS_MASK) >> + SRCODE_READ_XS_SHIFT) == 0) + ; + + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + } + + while (((readl((*ctrl)->control_srcomp_east_side_wkup) & + SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0) + ; + + srcomp_value = + readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + } } #endif void config_data_eye_leveling_samples(u32 emif_base) { - struct omap_sys_ctrl_regs *ioregs_base = - (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; - /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/ if (emif_base == EMIF1_BASE) writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, - &(ioregs_base->control_emif1_sdram_config_ext)); + (*ctrl)->control_emif1_sdram_config_ext); else if (emif_base == EMIF2_BASE) writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, - &(ioregs_base->control_emif2_sdram_config_ext)); + (*ctrl)->control_emif2_sdram_config_ext); } void init_omap_revision(void) @@ -227,17 +320,25 @@ void init_omap_revision(void) */ unsigned int rev = cortex_rev(); - switch (rev) { - case MIDR_CORTEX_A15_R0P0: - switch (readl(CONTROL_ID_CODE)) { - case OMAP5430_CONTROL_ID_CODE_ES1_0: - *omap_si_rev = OMAP5430_ES1_0; - break; - case OMAP5432_CONTROL_ID_CODE_ES1_0: - default: - *omap_si_rev = OMAP5432_ES1_0; - break; - } + switch (readl(CONTROL_ID_CODE)) { + case OMAP5430_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP5430_ES1_0; + if (rev == MIDR_CORTEX_A15_R2P2) + *omap_si_rev = OMAP5430_ES2_0; + break; + case OMAP5432_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP5432_ES1_0; + if (rev == MIDR_CORTEX_A15_R2P2) + *omap_si_rev = OMAP5432_ES2_0; + break; + case OMAP5430_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = OMAP5430_ES2_0; + break; + case OMAP5432_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = OMAP5432_ES2_0; + break; + case DRA752_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = DRA752_ES1_0; break; default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; @@ -253,7 +354,12 @@ void reset_cpu(ulong ignored) * So use cold reset in case instead. */ if (omap_rev == OMAP5430_ES1_0) - writel(PRM_RSTCTRL_RESET << 0x1, PRM_RSTCTRL); + writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl); else - writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); + writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl); +} + +u32 warm_reset(void) +{ + return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK; } diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c new file mode 100644 index 000000000..b8a61fe88 --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -0,0 +1,958 @@ +/* + * + * HW regs data for OMAP5 Soc + * + * (C) Copyright 2013 + * Texas Instruments, <www.ti.com> + * + * Sricharan R <r.sricharan@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/omap_common.h> + +struct prcm_regs const omap5_es1_prcm = { + /* cm1.ckgen */ + .cm_clksel_core = 0x4a004100, + .cm_clksel_abe = 0x4a004108, + .cm_dll_ctrl = 0x4a004110, + .cm_clkmode_dpll_core = 0x4a004120, + .cm_idlest_dpll_core = 0x4a004124, + .cm_autoidle_dpll_core = 0x4a004128, + .cm_clksel_dpll_core = 0x4a00412c, + .cm_div_m2_dpll_core = 0x4a004130, + .cm_div_m3_dpll_core = 0x4a004134, + .cm_div_h11_dpll_core = 0x4a004138, + .cm_div_h12_dpll_core = 0x4a00413c, + .cm_div_h13_dpll_core = 0x4a004140, + .cm_div_h14_dpll_core = 0x4a004144, + .cm_ssc_deltamstep_dpll_core = 0x4a004148, + .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, + .cm_emu_override_dpll_core = 0x4a004150, + .cm_div_h22_dpllcore = 0x4a004154, + .cm_div_h23_dpll_core = 0x4a004158, + .cm_clkmode_dpll_mpu = 0x4a004160, + .cm_idlest_dpll_mpu = 0x4a004164, + .cm_autoidle_dpll_mpu = 0x4a004168, + .cm_clksel_dpll_mpu = 0x4a00416c, + .cm_div_m2_dpll_mpu = 0x4a004170, + .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, + .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, + .cm_bypclk_dpll_mpu = 0x4a00419c, + .cm_clkmode_dpll_iva = 0x4a0041a0, + .cm_idlest_dpll_iva = 0x4a0041a4, + .cm_autoidle_dpll_iva = 0x4a0041a8, + .cm_clksel_dpll_iva = 0x4a0041ac, + .cm_div_h11_dpll_iva = 0x4a0041b8, + .cm_div_h12_dpll_iva = 0x4a0041bc, + .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, + .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, + .cm_bypclk_dpll_iva = 0x4a0041dc, + .cm_clkmode_dpll_abe = 0x4a0041e0, + .cm_idlest_dpll_abe = 0x4a0041e4, + .cm_autoidle_dpll_abe = 0x4a0041e8, + .cm_clksel_dpll_abe = 0x4a0041ec, + .cm_div_m2_dpll_abe = 0x4a0041f0, + .cm_div_m3_dpll_abe = 0x4a0041f4, + .cm_ssc_deltamstep_dpll_abe = 0x4a004208, + .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, + .cm_clkmode_dpll_ddrphy = 0x4a004220, + .cm_idlest_dpll_ddrphy = 0x4a004224, + .cm_autoidle_dpll_ddrphy = 0x4a004228, + .cm_clksel_dpll_ddrphy = 0x4a00422c, + .cm_div_m2_dpll_ddrphy = 0x4a004230, + .cm_div_h11_dpll_ddrphy = 0x4a004238, + .cm_div_h12_dpll_ddrphy = 0x4a00423c, + .cm_div_h13_dpll_ddrphy = 0x4a004240, + .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, + .cm_shadow_freq_config1 = 0x4a004260, + .cm_mpu_mpu_clkctrl = 0x4a004320, + + /* cm1.dsp */ + .cm_dsp_clkstctrl = 0x4a004400, + .cm_dsp_dsp_clkctrl = 0x4a004420, + + /* cm1.abe */ + .cm1_abe_clkstctrl = 0x4a004500, + .cm1_abe_l4abe_clkctrl = 0x4a004520, + .cm1_abe_aess_clkctrl = 0x4a004528, + .cm1_abe_pdm_clkctrl = 0x4a004530, + .cm1_abe_dmic_clkctrl = 0x4a004538, + .cm1_abe_mcasp_clkctrl = 0x4a004540, + .cm1_abe_mcbsp1_clkctrl = 0x4a004548, + .cm1_abe_mcbsp2_clkctrl = 0x4a004550, + .cm1_abe_mcbsp3_clkctrl = 0x4a004558, + .cm1_abe_slimbus_clkctrl = 0x4a004560, + .cm1_abe_timer5_clkctrl = 0x4a004568, + .cm1_abe_timer6_clkctrl = 0x4a004570, + .cm1_abe_timer7_clkctrl = 0x4a004578, + .cm1_abe_timer8_clkctrl = 0x4a004580, + .cm1_abe_wdt3_clkctrl = 0x4a004588, + + /* cm2.ckgen */ + .cm_clksel_mpu_m3_iss_root = 0x4a008100, + .cm_clksel_usb_60mhz = 0x4a008104, + .cm_scale_fclk = 0x4a008108, + .cm_core_dvfs_perf1 = 0x4a008110, + .cm_core_dvfs_perf2 = 0x4a008114, + .cm_core_dvfs_perf3 = 0x4a008118, + .cm_core_dvfs_perf4 = 0x4a00811c, + .cm_core_dvfs_current = 0x4a008124, + .cm_iva_dvfs_perf_tesla = 0x4a008128, + .cm_iva_dvfs_perf_ivahd = 0x4a00812c, + .cm_iva_dvfs_perf_abe = 0x4a008130, + .cm_iva_dvfs_current = 0x4a008138, + .cm_clkmode_dpll_per = 0x4a008140, + .cm_idlest_dpll_per = 0x4a008144, + .cm_autoidle_dpll_per = 0x4a008148, + .cm_clksel_dpll_per = 0x4a00814c, + .cm_div_m2_dpll_per = 0x4a008150, + .cm_div_m3_dpll_per = 0x4a008154, + .cm_div_h11_dpll_per = 0x4a008158, + .cm_div_h12_dpll_per = 0x4a00815c, + .cm_div_h14_dpll_per = 0x4a008164, + .cm_ssc_deltamstep_dpll_per = 0x4a008168, + .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, + .cm_emu_override_dpll_per = 0x4a008170, + .cm_clkmode_dpll_usb = 0x4a008180, + .cm_idlest_dpll_usb = 0x4a008184, + .cm_autoidle_dpll_usb = 0x4a008188, + .cm_clksel_dpll_usb = 0x4a00818c, + .cm_div_m2_dpll_usb = 0x4a008190, + .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, + .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, + .cm_clkdcoldo_dpll_usb = 0x4a0081b4, + .cm_clkmode_dpll_unipro = 0x4a0081c0, + .cm_idlest_dpll_unipro = 0x4a0081c4, + .cm_autoidle_dpll_unipro = 0x4a0081c8, + .cm_clksel_dpll_unipro = 0x4a0081cc, + .cm_div_m2_dpll_unipro = 0x4a0081d0, + .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, + .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + + /* cm2.core */ + .cm_coreaon_bandgap_clkctrl = 0x4a008648, + .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, + .cm_l3_1_clkstctrl = 0x4a008700, + .cm_l3_1_dynamicdep = 0x4a008708, + .cm_l3_1_l3_1_clkctrl = 0x4a008720, + .cm_l3_2_clkstctrl = 0x4a008800, + .cm_l3_2_dynamicdep = 0x4a008808, + .cm_l3_2_l3_2_clkctrl = 0x4a008820, + .cm_l3_gpmc_clkctrl = 0x4a008828, + .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, + .cm_mpu_m3_clkstctrl = 0x4a008900, + .cm_mpu_m3_staticdep = 0x4a008904, + .cm_mpu_m3_dynamicdep = 0x4a008908, + .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, + .cm_sdma_clkstctrl = 0x4a008a00, + .cm_sdma_staticdep = 0x4a008a04, + .cm_sdma_dynamicdep = 0x4a008a08, + .cm_sdma_sdma_clkctrl = 0x4a008a20, + .cm_memif_clkstctrl = 0x4a008b00, + .cm_memif_dmm_clkctrl = 0x4a008b20, + .cm_memif_emif_fw_clkctrl = 0x4a008b28, + .cm_memif_emif_1_clkctrl = 0x4a008b30, + .cm_memif_emif_2_clkctrl = 0x4a008b38, + .cm_memif_dll_clkctrl = 0x4a008b40, + .cm_memif_emif_h1_clkctrl = 0x4a008b50, + .cm_memif_emif_h2_clkctrl = 0x4a008b58, + .cm_memif_dll_h_clkctrl = 0x4a008b60, + .cm_c2c_clkstctrl = 0x4a008c00, + .cm_c2c_staticdep = 0x4a008c04, + .cm_c2c_dynamicdep = 0x4a008c08, + .cm_c2c_sad2d_clkctrl = 0x4a008c20, + .cm_c2c_modem_icr_clkctrl = 0x4a008c28, + .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, + .cm_l4cfg_clkstctrl = 0x4a008d00, + .cm_l4cfg_dynamicdep = 0x4a008d08, + .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, + .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, + .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, + .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, + .cm_l3instr_clkstctrl = 0x4a008e00, + .cm_l3instr_l3_3_clkctrl = 0x4a008e20, + .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, + .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, + + /* cm2.ivahd */ + .cm_ivahd_clkstctrl = 0x4a008f00, + .cm_ivahd_ivahd_clkctrl = 0x4a008f20, + .cm_ivahd_sl2_clkctrl = 0x4a008f28, + + /* cm2.cam */ + .cm_cam_clkstctrl = 0x4a009000, + .cm_cam_iss_clkctrl = 0x4a009020, + .cm_cam_fdif_clkctrl = 0x4a009028, + + /* cm2.dss */ + .cm_dss_clkstctrl = 0x4a009100, + .cm_dss_dss_clkctrl = 0x4a009120, + + /* cm2.sgx */ + .cm_sgx_clkstctrl = 0x4a009200, + .cm_sgx_sgx_clkctrl = 0x4a009220, + + /* cm2.l3init */ + .cm_l3init_clkstctrl = 0x4a009300, + .cm_l3init_hsmmc1_clkctrl = 0x4a009328, + .cm_l3init_hsmmc2_clkctrl = 0x4a009330, + .cm_l3init_hsi_clkctrl = 0x4a009338, + .cm_l3init_hsusbhost_clkctrl = 0x4a009358, + .cm_l3init_hsusbotg_clkctrl = 0x4a009360, + .cm_l3init_hsusbtll_clkctrl = 0x4a009368, + .cm_l3init_p1500_clkctrl = 0x4a009378, + .cm_l3init_fsusb_clkctrl = 0x4a0093d0, + .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, + + /* cm2.l4per */ + .cm_l4per_clkstctrl = 0x4a009400, + .cm_l4per_dynamicdep = 0x4a009408, + .cm_l4per_adc_clkctrl = 0x4a009420, + .cm_l4per_gptimer10_clkctrl = 0x4a009428, + .cm_l4per_gptimer11_clkctrl = 0x4a009430, + .cm_l4per_gptimer2_clkctrl = 0x4a009438, + .cm_l4per_gptimer3_clkctrl = 0x4a009440, + .cm_l4per_gptimer4_clkctrl = 0x4a009448, + .cm_l4per_gptimer9_clkctrl = 0x4a009450, + .cm_l4per_elm_clkctrl = 0x4a009458, + .cm_l4per_gpio2_clkctrl = 0x4a009460, + .cm_l4per_gpio3_clkctrl = 0x4a009468, + .cm_l4per_gpio4_clkctrl = 0x4a009470, + .cm_l4per_gpio5_clkctrl = 0x4a009478, + .cm_l4per_gpio6_clkctrl = 0x4a009480, + .cm_l4per_hdq1w_clkctrl = 0x4a009488, + .cm_l4per_hecc1_clkctrl = 0x4a009490, + .cm_l4per_hecc2_clkctrl = 0x4a009498, + .cm_l4per_i2c1_clkctrl = 0x4a0094a0, + .cm_l4per_i2c2_clkctrl = 0x4a0094a8, + .cm_l4per_i2c3_clkctrl = 0x4a0094b0, + .cm_l4per_i2c4_clkctrl = 0x4a0094b8, + .cm_l4per_l4per_clkctrl = 0x4a0094c0, + .cm_l4per_mcasp2_clkctrl = 0x4a0094d0, + .cm_l4per_mcasp3_clkctrl = 0x4a0094d8, + .cm_l4per_mgate_clkctrl = 0x4a0094e8, + .cm_l4per_mcspi1_clkctrl = 0x4a0094f0, + .cm_l4per_mcspi2_clkctrl = 0x4a0094f8, + .cm_l4per_mcspi3_clkctrl = 0x4a009500, + .cm_l4per_mcspi4_clkctrl = 0x4a009508, + .cm_l4per_gpio7_clkctrl = 0x4a009510, + .cm_l4per_gpio8_clkctrl = 0x4a009518, + .cm_l4per_mmcsd3_clkctrl = 0x4a009520, + .cm_l4per_mmcsd4_clkctrl = 0x4a009528, + .cm_l4per_msprohg_clkctrl = 0x4a009530, + .cm_l4per_slimbus2_clkctrl = 0x4a009538, + .cm_l4per_uart1_clkctrl = 0x4a009540, + .cm_l4per_uart2_clkctrl = 0x4a009548, + .cm_l4per_uart3_clkctrl = 0x4a009550, + .cm_l4per_uart4_clkctrl = 0x4a009558, + .cm_l4per_mmcsd5_clkctrl = 0x4a009560, + .cm_l4per_i2c5_clkctrl = 0x4a009568, + .cm_l4per_uart5_clkctrl = 0x4a009570, + .cm_l4per_uart6_clkctrl = 0x4a009578, + .cm_l4sec_clkstctrl = 0x4a009580, + .cm_l4sec_staticdep = 0x4a009584, + .cm_l4sec_dynamicdep = 0x4a009588, + .cm_l4sec_aes1_clkctrl = 0x4a0095a0, + .cm_l4sec_aes2_clkctrl = 0x4a0095a8, + .cm_l4sec_des3des_clkctrl = 0x4a0095b0, + .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8, + .cm_l4sec_rng_clkctrl = 0x4a0095c0, + .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8, + .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8, + + /* l4 wkup regs */ + .cm_abe_pll_ref_clksel = 0x4ae0610c, + .cm_sys_clksel = 0x4ae06110, + .cm_wkup_clkstctrl = 0x4ae07800, + .cm_wkup_l4wkup_clkctrl = 0x4ae07820, + .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, + .cm_wkup_wdtimer2_clkctrl = 0x4ae07830, + .cm_wkup_gpio1_clkctrl = 0x4ae07838, + .cm_wkup_gptimer1_clkctrl = 0x4ae07840, + .cm_wkup_gptimer12_clkctrl = 0x4ae07848, + .cm_wkup_synctimer_clkctrl = 0x4ae07850, + .cm_wkup_usim_clkctrl = 0x4ae07858, + .cm_wkup_sarram_clkctrl = 0x4ae07860, + .cm_wkup_keyboard_clkctrl = 0x4ae07878, + .cm_wkup_rtc_clkctrl = 0x4ae07880, + .cm_wkup_bandgap_clkctrl = 0x4ae07888, + .cm_wkupaon_scrm_clkctrl = 0x4ae07890, + .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898, + .prm_rstctrl = 0x4ae07b00, + .prm_rstst = 0x4ae07b04, + .prm_vc_val_bypass = 0x4ae07ba0, + .prm_vc_cfg_i2c_mode = 0x4ae07bb4, + .prm_vc_cfg_i2c_clk = 0x4ae07bb8, + .prm_sldo_core_setup = 0x4ae07bc4, + .prm_sldo_core_ctrl = 0x4ae07bc8, + .prm_sldo_mpu_setup = 0x4ae07bcc, + .prm_sldo_mpu_ctrl = 0x4ae07bd0, + .prm_sldo_mm_setup = 0x4ae07bd4, + .prm_sldo_mm_ctrl = 0x4ae07bd8, +}; + +struct omap_sys_ctrl_regs const omap5_ctrl = { + .control_status = 0x4A002134, + .control_paconf_global = 0x4A002DA0, + .control_paconf_mode = 0x4A002DA4, + .control_smart1io_padconf_0 = 0x4A002DA8, + .control_smart1io_padconf_1 = 0x4A002DAC, + .control_smart1io_padconf_2 = 0x4A002DB0, + .control_smart2io_padconf_0 = 0x4A002DB4, + .control_smart2io_padconf_1 = 0x4A002DB8, + .control_smart2io_padconf_2 = 0x4A002DBC, + .control_smart3io_padconf_0 = 0x4A002DC0, + .control_smart3io_padconf_1 = 0x4A002DC4, + .control_pbias = 0x4A002E00, + .control_i2c_0 = 0x4A002E04, + .control_camera_rx = 0x4A002E08, + .control_hdmi_tx_phy = 0x4A002E0C, + .control_uniportm = 0x4A002E10, + .control_dsiphy = 0x4A002E14, + .control_mcbsplp = 0x4A002E18, + .control_usb2phycore = 0x4A002E1C, + .control_hdmi_1 = 0x4A002E20, + .control_hsi = 0x4A002E24, + .control_ddr3ch1_0 = 0x4A002E30, + .control_ddr3ch2_0 = 0x4A002E34, + .control_ddrch1_0 = 0x4A002E38, + .control_ddrch1_1 = 0x4A002E3C, + .control_ddrch2_0 = 0x4A002E40, + .control_ddrch2_1 = 0x4A002E44, + .control_lpddr2ch1_0 = 0x4A002E48, + .control_lpddr2ch1_1 = 0x4A002E4C, + .control_ddrio_0 = 0x4A002E50, + .control_ddrio_1 = 0x4A002E54, + .control_ddrio_2 = 0x4A002E58, + .control_hyst_1 = 0x4A002E5C, + .control_usbb_hsic_control = 0x4A002E60, + .control_c2c = 0x4A002E64, + .control_core_control_spare_rw = 0x4A002E68, + .control_core_control_spare_r = 0x4A002E6C, + .control_core_control_spare_r_c0 = 0x4A002E70, + .control_srcomp_north_side = 0x4A002E74, + .control_srcomp_south_side = 0x4A002E78, + .control_srcomp_east_side = 0x4A002E7C, + .control_srcomp_west_side = 0x4A002E80, + .control_srcomp_code_latch = 0x4A002E84, + .control_port_emif1_sdram_config = 0x4AE0C110, + .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, + .control_port_emif2_sdram_config = 0x4AE0C118, + .control_emif1_sdram_config_ext = 0x4AE0C144, + .control_emif2_sdram_config_ext = 0x4AE0C148, + .control_smart1nopmio_padconf_0 = 0x4AE0CDA0, + .control_smart1nopmio_padconf_1 = 0x4AE0CDA4, + .control_padconf_mode = 0x4AE0CDA8, + .control_xtal_oscillator = 0x4AE0CDAC, + .control_i2c_2 = 0x4AE0CDB0, + .control_ckobuffer = 0x4AE0CDB4, + .control_wkup_control_spare_rw = 0x4AE0CDB8, + .control_wkup_control_spare_r = 0x4AE0CDBC, + .control_wkup_control_spare_r_c0 = 0x4AE0CDC0, + .control_srcomp_east_side_wkup = 0x4AE0CDC4, + .control_efuse_1 = 0x4AE0CDC8, + .control_efuse_2 = 0x4AE0CDCC, + .control_efuse_3 = 0x4AE0CDD0, + .control_efuse_4 = 0x4AE0CDD4, + .control_efuse_5 = 0x4AE0CDD8, + .control_efuse_6 = 0x4AE0CDDC, + .control_efuse_7 = 0x4AE0CDE0, + .control_efuse_8 = 0x4AE0CDE4, + .control_efuse_9 = 0x4AE0CDE8, + .control_efuse_10 = 0x4AE0CDEC, + .control_efuse_11 = 0x4AE0CDF0, + .control_efuse_12 = 0x4AE0CDF4, + .control_efuse_13 = 0x4AE0CDF8, +}; + +struct omap_sys_ctrl_regs const dra7xx_ctrl = { + .control_status = 0x4A002134, + .control_core_mmr_lock1 = 0x4A002540, + .control_core_mmr_lock2 = 0x4A002544, + .control_core_mmr_lock3 = 0x4A002548, + .control_core_mmr_lock4 = 0x4A00254C, + .control_core_mmr_lock5 = 0x4A002550, + .control_core_control_io1 = 0x4A002554, + .control_core_control_io2 = 0x4A002558, + .control_paconf_global = 0x4A002DA0, + .control_paconf_mode = 0x4A002DA4, + .control_smart1io_padconf_0 = 0x4A002DA8, + .control_smart1io_padconf_1 = 0x4A002DAC, + .control_smart1io_padconf_2 = 0x4A002DB0, + .control_smart2io_padconf_0 = 0x4A002DB4, + .control_smart2io_padconf_1 = 0x4A002DB8, + .control_smart2io_padconf_2 = 0x4A002DBC, + .control_smart3io_padconf_0 = 0x4A002DC0, + .control_smart3io_padconf_1 = 0x4A002DC4, + .control_pbias = 0x4A002E00, + .control_i2c_0 = 0x4A002E04, + .control_camera_rx = 0x4A002E08, + .control_hdmi_tx_phy = 0x4A002E0C, + .control_uniportm = 0x4A002E10, + .control_dsiphy = 0x4A002E14, + .control_mcbsplp = 0x4A002E18, + .control_usb2phycore = 0x4A002E1C, + .control_hdmi_1 = 0x4A002E20, + .control_hsi = 0x4A002E24, + .control_ddr3ch1_0 = 0x4A002E30, + .control_ddr3ch2_0 = 0x4A002E34, + .control_ddrch1_0 = 0x4A002E38, + .control_ddrch1_1 = 0x4A002E3C, + .control_ddrch2_0 = 0x4A002E40, + .control_ddrch2_1 = 0x4A002E44, + .control_lpddr2ch1_0 = 0x4A002E48, + .control_lpddr2ch1_1 = 0x4A002E4C, + .control_ddrio_0 = 0x4A002E50, + .control_ddrio_1 = 0x4A002E54, + .control_ddrio_2 = 0x4A002E58, + .control_hyst_1 = 0x4A002E5C, + .control_usbb_hsic_control = 0x4A002E60, + .control_c2c = 0x4A002E64, + .control_core_control_spare_rw = 0x4A002E68, + .control_core_control_spare_r = 0x4A002E6C, + .control_core_control_spare_r_c0 = 0x4A002E70, + .control_srcomp_north_side = 0x4A002E74, + .control_srcomp_south_side = 0x4A002E78, + .control_srcomp_east_side = 0x4A002E7C, + .control_srcomp_west_side = 0x4A002E80, + .control_srcomp_code_latch = 0x4A002E84, + .control_padconf_core_base = 0x4A003400, + .control_port_emif1_sdram_config = 0x4AE0C110, + .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, + .control_port_emif2_sdram_config = 0x4AE0C118, + .control_emif1_sdram_config_ext = 0x4AE0C144, + .control_emif2_sdram_config_ext = 0x4AE0C148, + .control_padconf_mode = 0x4AE0C5A0, + .control_xtal_oscillator = 0x4AE0C5A4, + .control_i2c_2 = 0x4AE0C5A8, + .control_ckobuffer = 0x4AE0C5AC, + .control_wkup_control_spare_rw = 0x4AE0C5B0, + .control_wkup_control_spare_r = 0x4AE0C5B4, + .control_wkup_control_spare_r_c0 = 0x4AE0C5B8, + .control_srcomp_east_side_wkup = 0x4AE0C5BC, + .control_efuse_1 = 0x4AE0C5C0, + .control_efuse_2 = 0x4AE0C5C4, + .control_efuse_3 = 0x4AE0C5C8, + .control_efuse_4 = 0x4AE0C5CC, + .control_efuse_13 = 0x4AE0C5F0, +}; + +struct prcm_regs const omap5_es2_prcm = { + /* cm1.ckgen */ + .cm_clksel_core = 0x4a004100, + .cm_clksel_abe = 0x4a004108, + .cm_dll_ctrl = 0x4a004110, + .cm_clkmode_dpll_core = 0x4a004120, + .cm_idlest_dpll_core = 0x4a004124, + .cm_autoidle_dpll_core = 0x4a004128, + .cm_clksel_dpll_core = 0x4a00412c, + .cm_div_m2_dpll_core = 0x4a004130, + .cm_div_m3_dpll_core = 0x4a004134, + .cm_div_h11_dpll_core = 0x4a004138, + .cm_div_h12_dpll_core = 0x4a00413c, + .cm_div_h13_dpll_core = 0x4a004140, + .cm_div_h14_dpll_core = 0x4a004144, + .cm_ssc_deltamstep_dpll_core = 0x4a004148, + .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, + .cm_div_h21_dpll_core = 0x4a004150, + .cm_div_h22_dpllcore = 0x4a004154, + .cm_div_h23_dpll_core = 0x4a004158, + .cm_div_h24_dpll_core = 0x4a00415c, + .cm_clkmode_dpll_mpu = 0x4a004160, + .cm_idlest_dpll_mpu = 0x4a004164, + .cm_autoidle_dpll_mpu = 0x4a004168, + .cm_clksel_dpll_mpu = 0x4a00416c, + .cm_div_m2_dpll_mpu = 0x4a004170, + .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, + .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, + .cm_bypclk_dpll_mpu = 0x4a00419c, + .cm_clkmode_dpll_iva = 0x4a0041a0, + .cm_idlest_dpll_iva = 0x4a0041a4, + .cm_autoidle_dpll_iva = 0x4a0041a8, + .cm_clksel_dpll_iva = 0x4a0041ac, + .cm_div_h11_dpll_iva = 0x4a0041b8, + .cm_div_h12_dpll_iva = 0x4a0041bc, + .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, + .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, + .cm_bypclk_dpll_iva = 0x4a0041dc, + .cm_clkmode_dpll_abe = 0x4a0041e0, + .cm_idlest_dpll_abe = 0x4a0041e4, + .cm_autoidle_dpll_abe = 0x4a0041e8, + .cm_clksel_dpll_abe = 0x4a0041ec, + .cm_div_m2_dpll_abe = 0x4a0041f0, + .cm_div_m3_dpll_abe = 0x4a0041f4, + .cm_ssc_deltamstep_dpll_abe = 0x4a004208, + .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, + .cm_clkmode_dpll_ddrphy = 0x4a004220, + .cm_idlest_dpll_ddrphy = 0x4a004224, + .cm_autoidle_dpll_ddrphy = 0x4a004228, + .cm_clksel_dpll_ddrphy = 0x4a00422c, + .cm_div_m2_dpll_ddrphy = 0x4a004230, + .cm_div_h11_dpll_ddrphy = 0x4a004238, + .cm_div_h12_dpll_ddrphy = 0x4a00423c, + .cm_div_h13_dpll_ddrphy = 0x4a004240, + .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, + .cm_shadow_freq_config1 = 0x4a004260, + .cm_mpu_mpu_clkctrl = 0x4a004320, + + /* cm1.dsp */ + .cm_dsp_clkstctrl = 0x4a004400, + .cm_dsp_dsp_clkctrl = 0x4a004420, + + /* cm1.abe */ + .cm1_abe_clkstctrl = 0x4a004500, + .cm1_abe_l4abe_clkctrl = 0x4a004520, + .cm1_abe_aess_clkctrl = 0x4a004528, + .cm1_abe_pdm_clkctrl = 0x4a004530, + .cm1_abe_dmic_clkctrl = 0x4a004538, + .cm1_abe_mcasp_clkctrl = 0x4a004540, + .cm1_abe_mcbsp1_clkctrl = 0x4a004548, + .cm1_abe_mcbsp2_clkctrl = 0x4a004550, + .cm1_abe_mcbsp3_clkctrl = 0x4a004558, + .cm1_abe_slimbus_clkctrl = 0x4a004560, + .cm1_abe_timer5_clkctrl = 0x4a004568, + .cm1_abe_timer6_clkctrl = 0x4a004570, + .cm1_abe_timer7_clkctrl = 0x4a004578, + .cm1_abe_timer8_clkctrl = 0x4a004580, + .cm1_abe_wdt3_clkctrl = 0x4a004588, + + + + /* cm2.ckgen */ + .cm_clksel_mpu_m3_iss_root = 0x4a008100, + .cm_clksel_usb_60mhz = 0x4a008104, + .cm_scale_fclk = 0x4a008108, + .cm_core_dvfs_perf1 = 0x4a008110, + .cm_core_dvfs_perf2 = 0x4a008114, + .cm_core_dvfs_perf3 = 0x4a008118, + .cm_core_dvfs_perf4 = 0x4a00811c, + .cm_core_dvfs_current = 0x4a008124, + .cm_iva_dvfs_perf_tesla = 0x4a008128, + .cm_iva_dvfs_perf_ivahd = 0x4a00812c, + .cm_iva_dvfs_perf_abe = 0x4a008130, + .cm_iva_dvfs_current = 0x4a008138, + .cm_clkmode_dpll_per = 0x4a008140, + .cm_idlest_dpll_per = 0x4a008144, + .cm_autoidle_dpll_per = 0x4a008148, + .cm_clksel_dpll_per = 0x4a00814c, + .cm_div_m2_dpll_per = 0x4a008150, + .cm_div_m3_dpll_per = 0x4a008154, + .cm_div_h11_dpll_per = 0x4a008158, + .cm_div_h12_dpll_per = 0x4a00815c, + .cm_div_h13_dpll_per = 0x4a008160, + .cm_div_h14_dpll_per = 0x4a008164, + .cm_ssc_deltamstep_dpll_per = 0x4a008168, + .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, + .cm_emu_override_dpll_per = 0x4a008170, + .cm_clkmode_dpll_usb = 0x4a008180, + .cm_idlest_dpll_usb = 0x4a008184, + .cm_autoidle_dpll_usb = 0x4a008188, + .cm_clksel_dpll_usb = 0x4a00818c, + .cm_div_m2_dpll_usb = 0x4a008190, + .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, + .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, + .cm_clkdcoldo_dpll_usb = 0x4a0081b4, + .cm_clkmode_dpll_unipro = 0x4a0081c0, + .cm_idlest_dpll_unipro = 0x4a0081c4, + .cm_autoidle_dpll_unipro = 0x4a0081c8, + .cm_clksel_dpll_unipro = 0x4a0081cc, + .cm_div_m2_dpll_unipro = 0x4a0081d0, + .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, + .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + .cm_coreaon_bandgap_clkctrl = 0x4a008648, + .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, + + /* cm2.core */ + .cm_l3_1_clkstctrl = 0x4a008700, + .cm_l3_1_dynamicdep = 0x4a008708, + .cm_l3_1_l3_1_clkctrl = 0x4a008720, + .cm_l3_2_clkstctrl = 0x4a008800, + .cm_l3_2_dynamicdep = 0x4a008808, + .cm_l3_2_l3_2_clkctrl = 0x4a008820, + .cm_l3_gpmc_clkctrl = 0x4a008828, + .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, + .cm_mpu_m3_clkstctrl = 0x4a008900, + .cm_mpu_m3_staticdep = 0x4a008904, + .cm_mpu_m3_dynamicdep = 0x4a008908, + .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, + .cm_sdma_clkstctrl = 0x4a008a00, + .cm_sdma_staticdep = 0x4a008a04, + .cm_sdma_dynamicdep = 0x4a008a08, + .cm_sdma_sdma_clkctrl = 0x4a008a20, + .cm_memif_clkstctrl = 0x4a008b00, + .cm_memif_dmm_clkctrl = 0x4a008b20, + .cm_memif_emif_fw_clkctrl = 0x4a008b28, + .cm_memif_emif_1_clkctrl = 0x4a008b30, + .cm_memif_emif_2_clkctrl = 0x4a008b38, + .cm_memif_dll_clkctrl = 0x4a008b40, + .cm_memif_emif_h1_clkctrl = 0x4a008b50, + .cm_memif_emif_h2_clkctrl = 0x4a008b58, + .cm_memif_dll_h_clkctrl = 0x4a008b60, + .cm_c2c_clkstctrl = 0x4a008c00, + .cm_c2c_staticdep = 0x4a008c04, + .cm_c2c_dynamicdep = 0x4a008c08, + .cm_c2c_sad2d_clkctrl = 0x4a008c20, + .cm_c2c_modem_icr_clkctrl = 0x4a008c28, + .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, + .cm_l4cfg_clkstctrl = 0x4a008d00, + .cm_l4cfg_dynamicdep = 0x4a008d08, + .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, + .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, + .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, + .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, + .cm_l3instr_clkstctrl = 0x4a008e00, + .cm_l3instr_l3_3_clkctrl = 0x4a008e20, + .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, + .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, + .cm_l4per_clkstctrl = 0x4a009000, + .cm_l4per_dynamicdep = 0x4a009008, + .cm_l4per_adc_clkctrl = 0x4a009020, + .cm_l4per_gptimer10_clkctrl = 0x4a009028, + .cm_l4per_gptimer11_clkctrl = 0x4a009030, + .cm_l4per_gptimer2_clkctrl = 0x4a009038, + .cm_l4per_gptimer3_clkctrl = 0x4a009040, + .cm_l4per_gptimer4_clkctrl = 0x4a009048, + .cm_l4per_gptimer9_clkctrl = 0x4a009050, + .cm_l4per_elm_clkctrl = 0x4a009058, + .cm_l4per_gpio2_clkctrl = 0x4a009060, + .cm_l4per_gpio3_clkctrl = 0x4a009068, + .cm_l4per_gpio4_clkctrl = 0x4a009070, + .cm_l4per_gpio5_clkctrl = 0x4a009078, + .cm_l4per_gpio6_clkctrl = 0x4a009080, + .cm_l4per_hdq1w_clkctrl = 0x4a009088, + .cm_l4per_hecc1_clkctrl = 0x4a009090, + .cm_l4per_hecc2_clkctrl = 0x4a009098, + .cm_l4per_i2c1_clkctrl = 0x4a0090a0, + .cm_l4per_i2c2_clkctrl = 0x4a0090a8, + .cm_l4per_i2c3_clkctrl = 0x4a0090b0, + .cm_l4per_i2c4_clkctrl = 0x4a0090b8, + .cm_l4per_l4per_clkctrl = 0x4a0090c0, + .cm_l4per_mcasp2_clkctrl = 0x4a0090d0, + .cm_l4per_mcasp3_clkctrl = 0x4a0090d8, + .cm_l4per_mgate_clkctrl = 0x4a0090e8, + .cm_l4per_mcspi1_clkctrl = 0x4a0090f0, + .cm_l4per_mcspi2_clkctrl = 0x4a0090f8, + .cm_l4per_mcspi3_clkctrl = 0x4a009100, + .cm_l4per_mcspi4_clkctrl = 0x4a009108, + .cm_l4per_gpio7_clkctrl = 0x4a009110, + .cm_l4per_gpio8_clkctrl = 0x4a009118, + .cm_l4per_mmcsd3_clkctrl = 0x4a009120, + .cm_l4per_mmcsd4_clkctrl = 0x4a009128, + .cm_l4per_msprohg_clkctrl = 0x4a009130, + .cm_l4per_slimbus2_clkctrl = 0x4a009138, + .cm_l4per_uart1_clkctrl = 0x4a009140, + .cm_l4per_uart2_clkctrl = 0x4a009148, + .cm_l4per_uart3_clkctrl = 0x4a009150, + .cm_l4per_uart4_clkctrl = 0x4a009158, + .cm_l4per_mmcsd5_clkctrl = 0x4a009160, + .cm_l4per_i2c5_clkctrl = 0x4a009168, + .cm_l4per_uart5_clkctrl = 0x4a009170, + .cm_l4per_uart6_clkctrl = 0x4a009178, + .cm_l4sec_clkstctrl = 0x4a009180, + .cm_l4sec_staticdep = 0x4a009184, + .cm_l4sec_dynamicdep = 0x4a009188, + .cm_l4sec_aes1_clkctrl = 0x4a0091a0, + .cm_l4sec_aes2_clkctrl = 0x4a0091a8, + .cm_l4sec_des3des_clkctrl = 0x4a0091b0, + .cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8, + .cm_l4sec_rng_clkctrl = 0x4a0091c0, + .cm_l4sec_sha2md51_clkctrl = 0x4a0091c8, + .cm_l4sec_cryptodma_clkctrl = 0x4a0091d8, + + /* cm2.ivahd */ + .cm_ivahd_clkstctrl = 0x4a009200, + .cm_ivahd_ivahd_clkctrl = 0x4a009220, + .cm_ivahd_sl2_clkctrl = 0x4a009228, + + /* cm2.cam */ + .cm_cam_clkstctrl = 0x4a009300, + .cm_cam_iss_clkctrl = 0x4a009320, + .cm_cam_fdif_clkctrl = 0x4a009328, + + /* cm2.dss */ + .cm_dss_clkstctrl = 0x4a009400, + .cm_dss_dss_clkctrl = 0x4a009420, + + /* cm2.sgx */ + .cm_sgx_clkstctrl = 0x4a009500, + .cm_sgx_sgx_clkctrl = 0x4a009520, + + /* cm2.l3init */ + .cm_l3init_clkstctrl = 0x4a009600, + + /* cm2.l3init */ + .cm_l3init_hsmmc1_clkctrl = 0x4a009628, + .cm_l3init_hsmmc2_clkctrl = 0x4a009630, + .cm_l3init_hsi_clkctrl = 0x4a009638, + .cm_l3init_hsusbhost_clkctrl = 0x4a009658, + .cm_l3init_hsusbotg_clkctrl = 0x4a009660, + .cm_l3init_hsusbtll_clkctrl = 0x4a009668, + .cm_l3init_p1500_clkctrl = 0x4a009678, + .cm_l3init_fsusb_clkctrl = 0x4a0096d0, + .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, + + /* l4 wkup regs */ + .cm_abe_pll_ref_clksel = 0x4ae0610c, + .cm_sys_clksel = 0x4ae06110, + .cm_wkup_clkstctrl = 0x4ae07900, + .cm_wkup_l4wkup_clkctrl = 0x4ae07920, + .cm_wkup_wdtimer1_clkctrl = 0x4ae07928, + .cm_wkup_wdtimer2_clkctrl = 0x4ae07930, + .cm_wkup_gpio1_clkctrl = 0x4ae07938, + .cm_wkup_gptimer1_clkctrl = 0x4ae07940, + .cm_wkup_gptimer12_clkctrl = 0x4ae07948, + .cm_wkup_synctimer_clkctrl = 0x4ae07950, + .cm_wkup_usim_clkctrl = 0x4ae07958, + .cm_wkup_sarram_clkctrl = 0x4ae07960, + .cm_wkup_keyboard_clkctrl = 0x4ae07978, + .cm_wkup_rtc_clkctrl = 0x4ae07980, + .cm_wkup_bandgap_clkctrl = 0x4ae07988, + .cm_wkupaon_scrm_clkctrl = 0x4ae07990, + .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998, + .prm_rstctrl = 0x4ae07c00, + .prm_rstst = 0x4ae07c04, + .prm_vc_val_bypass = 0x4ae07ca0, + .prm_vc_cfg_i2c_mode = 0x4ae07cb4, + .prm_vc_cfg_i2c_clk = 0x4ae07cb8, + + .prm_sldo_core_setup = 0x4ae07cc4, + .prm_sldo_core_ctrl = 0x4ae07cc8, + .prm_sldo_mpu_setup = 0x4ae07ccc, + .prm_sldo_mpu_ctrl = 0x4ae07cd0, + .prm_sldo_mm_setup = 0x4ae07cd4, + .prm_sldo_mm_ctrl = 0x4ae07cd8, +}; + +struct prcm_regs const dra7xx_prcm = { + /* cm1.ckgen */ + .cm_clksel_core = 0x4a005100, + .cm_clksel_abe = 0x4a005108, + .cm_dll_ctrl = 0x4a005110, + .cm_clkmode_dpll_core = 0x4a005120, + .cm_idlest_dpll_core = 0x4a005124, + .cm_autoidle_dpll_core = 0x4a005128, + .cm_clksel_dpll_core = 0x4a00512c, + .cm_div_m2_dpll_core = 0x4a005130, + .cm_div_m3_dpll_core = 0x4a005134, + .cm_div_h11_dpll_core = 0x4a005138, + .cm_div_h12_dpll_core = 0x4a00513c, + .cm_div_h13_dpll_core = 0x4a005140, + .cm_div_h14_dpll_core = 0x4a005144, + .cm_ssc_deltamstep_dpll_core = 0x4a005148, + .cm_ssc_modfreqdiv_dpll_core = 0x4a00514c, + .cm_div_h21_dpll_core = 0x4a005150, + .cm_div_h22_dpllcore = 0x4a005154, + .cm_div_h23_dpll_core = 0x4a005158, + .cm_div_h24_dpll_core = 0x4a00515c, + .cm_clkmode_dpll_mpu = 0x4a005160, + .cm_idlest_dpll_mpu = 0x4a005164, + .cm_autoidle_dpll_mpu = 0x4a005168, + .cm_clksel_dpll_mpu = 0x4a00516c, + .cm_div_m2_dpll_mpu = 0x4a005170, + .cm_ssc_deltamstep_dpll_mpu = 0x4a005188, + .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00518c, + .cm_bypclk_dpll_mpu = 0x4a00519c, + .cm_clkmode_dpll_iva = 0x4a0051a0, + .cm_idlest_dpll_iva = 0x4a0051a4, + .cm_autoidle_dpll_iva = 0x4a0051a8, + .cm_clksel_dpll_iva = 0x4a0051ac, + .cm_ssc_deltamstep_dpll_iva = 0x4a0051c8, + .cm_ssc_modfreqdiv_dpll_iva = 0x4a0051cc, + .cm_bypclk_dpll_iva = 0x4a0051dc, + .cm_clkmode_dpll_abe = 0x4a0051e0, + .cm_idlest_dpll_abe = 0x4a0051e4, + .cm_autoidle_dpll_abe = 0x4a0051e8, + .cm_clksel_dpll_abe = 0x4a0051ec, + .cm_div_m2_dpll_abe = 0x4a0051f0, + .cm_div_m3_dpll_abe = 0x4a0051f4, + .cm_ssc_deltamstep_dpll_abe = 0x4a005208, + .cm_ssc_modfreqdiv_dpll_abe = 0x4a00520c, + .cm_clkmode_dpll_ddrphy = 0x4a005210, + .cm_idlest_dpll_ddrphy = 0x4a005214, + .cm_autoidle_dpll_ddrphy = 0x4a005218, + .cm_clksel_dpll_ddrphy = 0x4a00521c, + .cm_div_m2_dpll_ddrphy = 0x4a005220, + .cm_div_h11_dpll_ddrphy = 0x4a005228, + .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c, + .cm_clkmode_dpll_dsp = 0x4a005234, + .cm_shadow_freq_config1 = 0x4a005260, + + /* cm1.mpu */ + .cm_mpu_mpu_clkctrl = 0x4a005320, + + /* cm1.dsp */ + .cm_dsp_clkstctrl = 0x4a005400, + .cm_dsp_dsp_clkctrl = 0x4a005420, + + /* cm2.ckgen */ + .cm_clksel_usb_60mhz = 0x4a008104, + .cm_clkmode_dpll_per = 0x4a008140, + .cm_idlest_dpll_per = 0x4a008144, + .cm_autoidle_dpll_per = 0x4a008148, + .cm_clksel_dpll_per = 0x4a00814c, + .cm_div_m2_dpll_per = 0x4a008150, + .cm_div_m3_dpll_per = 0x4a008154, + .cm_div_h11_dpll_per = 0x4a008158, + .cm_div_h12_dpll_per = 0x4a00815c, + .cm_div_h13_dpll_per = 0x4a008160, + .cm_div_h14_dpll_per = 0x4a008164, + .cm_ssc_deltamstep_dpll_per = 0x4a008168, + .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, + .cm_clkmode_dpll_usb = 0x4a008180, + .cm_idlest_dpll_usb = 0x4a008184, + .cm_autoidle_dpll_usb = 0x4a008188, + .cm_clksel_dpll_usb = 0x4a00818c, + .cm_div_m2_dpll_usb = 0x4a008190, + .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, + .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, + .cm_clkdcoldo_dpll_usb = 0x4a0081b4, + .cm_clkmode_dpll_pcie_ref = 0x4a008200, + .cm_clkmode_apll_pcie = 0x4a00821c, + .cm_idlest_apll_pcie = 0x4a008220, + .cm_div_m2_apll_pcie = 0x4a008224, + .cm_clkvcoldo_apll_pcie = 0x4a008228, + + /* cm2.core */ + .cm_l3_1_clkstctrl = 0x4a008700, + .cm_l3_1_dynamicdep = 0x4a008708, + .cm_l3_1_l3_1_clkctrl = 0x4a008720, + .cm_l3_gpmc_clkctrl = 0x4a008728, + .cm_mpu_m3_clkstctrl = 0x4a008900, + .cm_mpu_m3_staticdep = 0x4a008904, + .cm_mpu_m3_dynamicdep = 0x4a008908, + .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, + .cm_sdma_clkstctrl = 0x4a008a00, + .cm_sdma_staticdep = 0x4a008a04, + .cm_sdma_dynamicdep = 0x4a008a08, + .cm_sdma_sdma_clkctrl = 0x4a008a20, + .cm_memif_clkstctrl = 0x4a008b00, + .cm_memif_dmm_clkctrl = 0x4a008b20, + .cm_memif_emif_fw_clkctrl = 0x4a008b28, + .cm_memif_emif_1_clkctrl = 0x4a008b30, + .cm_memif_emif_2_clkctrl = 0x4a008b38, + .cm_memif_dll_clkctrl = 0x4a008b40, + .cm_l4cfg_clkstctrl = 0x4a008d00, + .cm_l4cfg_dynamicdep = 0x4a008d08, + .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, + .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, + .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, + .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, + .cm_l3instr_clkstctrl = 0x4a008e00, + .cm_l3instr_l3_3_clkctrl = 0x4a008e20, + .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, + .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, + + /* cm2.ivahd */ + .cm_ivahd_clkstctrl = 0x4a008f00, + .cm_ivahd_ivahd_clkctrl = 0x4a008f20, + .cm_ivahd_sl2_clkctrl = 0x4a008f28, + + /* cm2.cam */ + .cm_cam_clkstctrl = 0x4a009000, + .cm_cam_vip1_clkctrl = 0x4a009020, + .cm_cam_vip2_clkctrl = 0x4a009028, + .cm_cam_vip3_clkctrl = 0x4a009030, + .cm_cam_lvdsrx_clkctrl = 0x4a009038, + .cm_cam_csi1_clkctrl = 0x4a009040, + .cm_cam_csi2_clkctrl = 0x4a009048, + + /* cm2.dss */ + .cm_dss_clkstctrl = 0x4a009100, + .cm_dss_dss_clkctrl = 0x4a009120, + + /* cm2.sgx */ + .cm_sgx_clkstctrl = 0x4a009200, + .cm_sgx_sgx_clkctrl = 0x4a009220, + + /* cm2.l3init */ + .cm_l3init_clkstctrl = 0x4a009300, + + /* cm2.l3init */ + .cm_l3init_hsmmc1_clkctrl = 0x4a009328, + .cm_l3init_hsmmc2_clkctrl = 0x4a009330, + .cm_l3init_hsusbhost_clkctrl = 0x4a009340, + .cm_l3init_hsusbotg_clkctrl = 0x4a009348, + .cm_l3init_hsusbtll_clkctrl = 0x4a009350, + .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, + + /* cm2.l4per */ + .cm_l4per_clkstctrl = 0x4a009700, + .cm_l4per_dynamicdep = 0x4a009708, + .cm_l4per_gptimer10_clkctrl = 0x4a009728, + .cm_l4per_gptimer11_clkctrl = 0x4a009730, + .cm_l4per_gptimer2_clkctrl = 0x4a009738, + .cm_l4per_gptimer3_clkctrl = 0x4a009740, + .cm_l4per_gptimer4_clkctrl = 0x4a009748, + .cm_l4per_gptimer9_clkctrl = 0x4a009750, + .cm_l4per_elm_clkctrl = 0x4a009758, + .cm_l4per_gpio2_clkctrl = 0x4a009760, + .cm_l4per_gpio3_clkctrl = 0x4a009768, + .cm_l4per_gpio4_clkctrl = 0x4a009770, + .cm_l4per_gpio5_clkctrl = 0x4a009778, + .cm_l4per_gpio6_clkctrl = 0x4a009780, + .cm_l4per_hdq1w_clkctrl = 0x4a009788, + .cm_l4per_i2c1_clkctrl = 0x4a0097a0, + .cm_l4per_i2c2_clkctrl = 0x4a0097a8, + .cm_l4per_i2c3_clkctrl = 0x4a0097b0, + .cm_l4per_i2c4_clkctrl = 0x4a0097b8, + .cm_l4per_l4per_clkctrl = 0x4a0097c0, + .cm_l4per_mcspi1_clkctrl = 0x4a0097f0, + .cm_l4per_mcspi2_clkctrl = 0x4a0097f8, + .cm_l4per_mcspi3_clkctrl = 0x4a009800, + .cm_l4per_mcspi4_clkctrl = 0x4a009808, + .cm_l4per_gpio7_clkctrl = 0x4a009810, + .cm_l4per_gpio8_clkctrl = 0x4a009818, + .cm_l4per_mmcsd3_clkctrl = 0x4a009820, + .cm_l4per_mmcsd4_clkctrl = 0x4a009828, + .cm_l4per_uart1_clkctrl = 0x4a009840, + .cm_l4per_uart2_clkctrl = 0x4a009848, + .cm_l4per_uart3_clkctrl = 0x4a009850, + .cm_l4per_uart4_clkctrl = 0x4a009858, + .cm_l4per_uart5_clkctrl = 0x4a009870, + .cm_l4sec_clkstctrl = 0x4a009880, + .cm_l4sec_staticdep = 0x4a009884, + .cm_l4sec_dynamicdep = 0x4a009888, + .cm_l4sec_aes1_clkctrl = 0x4a0098a0, + .cm_l4sec_aes2_clkctrl = 0x4a0098a8, + .cm_l4sec_des3des_clkctrl = 0x4a0098b0, + .cm_l4sec_rng_clkctrl = 0x4a0098c0, + .cm_l4sec_sha2md51_clkctrl = 0x4a0098c8, + .cm_l4sec_cryptodma_clkctrl = 0x4a0098d8, + + /* l4 wkup regs */ + .cm_abe_pll_ref_clksel = 0x4ae0610c, + .cm_sys_clksel = 0x4ae06110, + .cm_wkup_clkstctrl = 0x4ae07800, + .cm_wkup_l4wkup_clkctrl = 0x4ae07820, + .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, + .cm_wkup_wdtimer2_clkctrl = 0x4ae07830, + .cm_wkup_gpio1_clkctrl = 0x4ae07838, + .cm_wkup_gptimer1_clkctrl = 0x4ae07840, + .cm_wkup_gptimer12_clkctrl = 0x4ae07848, + .cm_wkup_sarram_clkctrl = 0x4ae07860, + .cm_wkup_keyboard_clkctrl = 0x4ae07878, + .cm_wkupaon_scrm_clkctrl = 0x4ae07890, + .prm_rstctrl = 0x4ae07d00, + .prm_rstst = 0x4ae07d04, + .prm_vc_val_bypass = 0x4ae07da0, + .prm_vc_cfg_i2c_mode = 0x4ae07db4, + .prm_vc_cfg_i2c_clk = 0x4ae07db8, +}; diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 6ebdf5fbf..6b461e484 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -67,6 +67,25 @@ const struct emif_regs emif_regs_532_mhz_2cs = { .emif_ddr_ext_phy_ctrl_5 = 0x04010040 }; +const struct emif_regs emif_regs_532_mhz_2cs_es2 = { + .sdram_config_init = 0x80800EBA, + .sdram_config = 0x808022BA, + .ref_ctrl = 0x0000081A, + .sdram_tim1 = 0x772F6873, + .sdram_tim2 = 0x304a129a, + .sdram_tim3 = 0x02f7e45f, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x100b3215, + .temp_alert_config = 0x08000a05, + .emif_ddr_phy_ctlr_1_init = 0x0E30400d, + .emif_ddr_phy_ctlr_1 = 0x0E30400d, + .emif_ddr_ext_phy_ctrl_1 = 0x04020080, + .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3, + .emif_ddr_ext_phy_ctrl_3 = 0x518A3146, + .emif_ddr_ext_phy_ctrl_4 = 0x0014628C, + .emif_ddr_ext_phy_ctrl_5 = 0xC330CC33, +}; + const struct emif_regs emif_regs_266_mhz_2cs = { .sdram_config_init = 0x80800EBA, .sdram_config = 0x808022BA, @@ -109,13 +128,111 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { .emif_rd_wr_exec_thresh = 0x00000305 }; +const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x1007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0030400A, + .emif_ddr_phy_ctlr_1 = 0x0034400A, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00000000, + .emif_ddr_ext_phy_ctrl_3 = 0x00000000, + .emif_ddr_ext_phy_ctrl_4 = 0x00000000, + .emif_ddr_ext_phy_ctrl_5 = 0x4350D435, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x40000305 +}; + const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, .dmm_lisa_map_2 = 0x80740300, - .dmm_lisa_map_3 = 0xFF020100 + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + +const struct dmm_lisa_map_regs lisa_map_512M_x_1 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x0, + .dmm_lisa_map_3 = 0x80500100, + .is_ma_present = 0x1 +}; + +static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) +{ + switch (omap_revision()) { + case OMAP5430_ES1_0: + *regs = &emif_regs_532_mhz_2cs; + break; + case OMAP5432_ES1_0: + *regs = &emif_regs_ddr3_532_mhz_1cs; + break; + case OMAP5430_ES2_0: + *regs = &emif_regs_532_mhz_2cs_es2; + break; + case OMAP5432_ES2_0: + case DRA752_ES1_0: + default: + *regs = &emif_regs_ddr3_532_mhz_1cs_es2; + } +} + +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) + __attribute__((weak, alias("emif_get_reg_dump_sdp"))); + +static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs + **dmm_lisa_regs) +{ + switch (omap_revision()) { + case OMAP5430_ES1_0: + case OMAP5430_ES2_0: + case OMAP5432_ES1_0: + case OMAP5432_ES2_0: + *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; + break; + case DRA752_ES1_0: + default: + *dmm_lisa_regs = &lisa_map_512M_x_1; + } + +} + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) + __attribute__((weak, alias("emif_get_dmm_regs_sdp"))); +#else + +static const struct lpddr2_device_details dev_4G_S4_details = { + .type = LPDDR2_TYPE_S4, + .density = LPDDR2_DENSITY_4Gb, + .io_width = LPDDR2_IO_WIDTH_32, + .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG }; +static void emif_get_device_details_sdp(u32 emif_nr, + struct lpddr2_device_details *cs0_device_details, + struct lpddr2_device_details *cs1_device_details) +{ + /* EMIF1 & EMIF2 have identical configuration */ + *cs0_device_details = dev_4G_S4_details; + *cs1_device_details = dev_4G_S4_details; +} + +void emif_get_device_details(u32 emif_nr, + struct lpddr2_device_details *cs0_device_details, + struct lpddr2_device_details *cs1_device_details) + __attribute__((weak, alias("emif_get_device_details_sdp"))); + +#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ + const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x01004010, 0x00001004, @@ -138,7 +255,7 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000077 }; -const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { +const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x01004010, 0x00001004, 0x04010040, @@ -160,54 +277,64 @@ const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000057 }; -static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) -{ - if (omap_revision() == OMAP5432_ES1_0) - *regs = &emif_regs_ddr3_532_mhz_1cs; - else - *regs = &emif_regs_532_mhz_2cs; -} -void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) - __attribute__((weak, alias("emif_get_reg_dump_sdp"))); - -static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs - **dmm_lisa_regs) -{ - *dmm_lisa_regs = &lisa_map_4G_x_2_x_2; -} - -void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) - __attribute__((weak, alias("emif_get_dmm_regs_sdp"))); - -#else +const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { + 0x50D4350D, + 0x00000D43, + 0x04010040, + 0x01004010, + 0x00001004, + 0x00000000, + 0x00000000, + 0x00000000, + 0x80080080, + 0x00800800, + 0x08102040, + 0x00000002, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000057 +}; -static const struct lpddr2_device_details dev_4G_S4_details = { - .type = LPDDR2_TYPE_S4, - .density = LPDDR2_DENSITY_4Gb, - .io_width = LPDDR2_IO_WIDTH_32, - .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG +const struct lpddr2_mr_regs mr_regs = { + .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8, + .mr2 = 0x6, + .mr3 = 0x1, + .mr10 = MR10_ZQ_ZQINIT, + .mr16 = MR16_REF_FULL_ARRAY }; -static void emif_get_device_details_sdp(u32 emif_nr, - struct lpddr2_device_details *cs0_device_details, - struct lpddr2_device_details *cs1_device_details) +static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs) { - /* EMIF1 & EMIF2 have identical configuration */ - *cs0_device_details = dev_4G_S4_details; - *cs1_device_details = dev_4G_S4_details; -} + switch (omap_revision()) { + case OMAP5430_ES1_0: + case OMAP5430_ES2_0: + *regs = ext_phy_ctrl_const_base; + break; + case OMAP5432_ES1_0: + *regs = ddr3_ext_phy_ctrl_const_base_es1; + break; + case OMAP5432_ES2_0: + case DRA752_ES1_0: + default: + *regs = ddr3_ext_phy_ctrl_const_base_es2; -void emif_get_device_details(u32 emif_nr, - struct lpddr2_device_details *cs0_device_details, - struct lpddr2_device_details *cs1_device_details) - __attribute__((weak, alias("emif_get_device_details_sdp"))); + } +} -#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ +void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs) +{ + *regs = &mr_regs; +} void do_ext_phy_settings(u32 base, const struct emif_regs *regs) { u32 *ext_phy_ctrl_base = 0; u32 *emif_ext_phy_ctrl_base = 0; + const u32 *ext_phy_ctrl_const_regs; u32 i = 0; struct emif_reg_struct *emif = (struct emif_reg_struct *)base; @@ -226,12 +353,13 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) * external phy 6-24 registers do not change with * ddr frequency */ + emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs); for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { - writel(ext_phy_ctrl_const_base[i], - emif_ext_phy_ctrl_base++); + writel(ext_phy_ctrl_const_regs[i], + emif_ext_phy_ctrl_base++); /* Update shadow registers */ - writel(ext_phy_ctrl_const_base[i], - emif_ext_phy_ctrl_base++); + writel(ext_phy_ctrl_const_regs[i], + emif_ext_phy_ctrl_base++); } } diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 6b59529d5..30f02d394 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -309,6 +309,25 @@ ENTRY(cpu_init_cp15) orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache #endif mcr p15, 0, r0, c1, c0, 0 + +#ifdef CONFIG_ARM_ERRATA_742230 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 4 @ set bit #4 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + +#ifdef CONFIG_ARM_ERRATA_743622 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 6 @ set bit #6 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + +#ifdef CONFIG_ARM_ERRATA_751472 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 11 @ set bit #11 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif + mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15) diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds index 81d954f2d..5e66dd142 100644 --- a/arch/arm/cpu/ixp/u-boot.lds +++ b/arch/arm/cpu/ixp/u-boot.lds @@ -49,7 +49,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN(4); @@ -67,11 +67,17 @@ SECTIONS _end = .; - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + } + + .bss __bss_start (OVERLAY) : { *(.bss*) . = ALIGN(4); - __bss_end__ = .; + ___bssend___ = .; + } + .bss_end ___bssend___ (OVERLAY) : { + KEEP(*(.__bss_end__)); } /DISCARD/ : { *(.dynstr*) } diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds new file mode 100644 index 000000000..8321afb95 --- /dev/null +++ b/arch/arm/cpu/u-boot-spl.lds @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + __image_copy_start = .; + CPUDIR/start.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + __image_copy_end = .; + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + _end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} + +#if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE) +ASSERT(__bss_end__ < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big"); +#endif diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index e6b202bd1..d4ad3529b 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -52,7 +52,7 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - #include <u-boot.lst> + KEEP(*(SORT(.u_boot_list*))); } . = ALIGN(4); @@ -81,11 +81,17 @@ SECTIONS *(.mmutable) } - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + } + + .bss __bss_start (OVERLAY) : { *(.bss*) . = ALIGN(4); - __bss_end__ = .; + ___bssend___ = .; + } + .bss_end ___bssend___ (OVERLAY) : { + KEEP(*(.__bss_end__)); } /DISCARD/ : { *(.dynstr*) } |